From 9ba1e6a2f9b0a9774c600522c6b8d2cffcddf35f Mon Sep 17 00:00:00 2001 From: "BITDEFENDER\\vlutas" Date: Tue, 4 Oct 2022 12:22:59 +0300 Subject: [PATCH] Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script. --- bddisasm/bddisasm.c | 41 +- bddisasm/include/instructions.h | 12013 +++++++++------- bddisasm/include/mnemonics.h | 171 +- bddisasm/include/table_evex.h | 1520 +- bddisasm/include/table_root.h | 3763 ++--- bddisasm/include/table_vex.h | 2413 +++- bddisasm/include/table_xop.h | 175 +- bddisasm/include/tabledefs.h | 27 +- bddisasm_test/test_all.py | 127 +- bddisasm_test/{ => x86}/amx/amx1_64.asm | 2 + bddisasm_test/{ => x86}/amx/amx1_64.result | 18 + .../{amx/amx1_64 => x86/amx/amx1_64.test} | Bin 98 -> 103 bytes bddisasm_test/{ => x86}/avx/avx2_64.asm | 0 bddisasm_test/{ => x86}/avx/avx2_64.result | 0 .../{avx/avx2_64 => x86/avx/avx2_64.test} | Bin bddisasm_test/{ => x86}/avx/avx2gather_64.asm | 0 .../{ => x86}/avx/avx2gather_64.result | 0 .../avx/avx2gather_64.test} | Bin bddisasm_test/{ => x86}/avx/avx_64.asm | 0 bddisasm_test/{ => x86}/avx/avx_64.result | 144 +- .../{avx/avx_64 => x86/avx/avx_64.test} | Bin bddisasm_test/x86/avx/avxifma_64.asm | 11 + bddisasm_test/x86/avx/avxifma_64.result | 148 + bddisasm_test/x86/avx/avxifma_64.test | Bin 0 -> 40 bytes bddisasm_test/x86/avx/avxneconvert_64.asm | 20 + bddisasm_test/x86/avx/avxneconvert_64.result | 286 + bddisasm_test/x86/avx/avxneconvert_64.test | Bin 0 -> 80 bytes bddisasm_test/{ => x86}/avx/avxvnni_64.asm | 0 bddisasm_test/{ => x86}/avx/avxvnni_64.result | 0 .../avxvnni_64 => x86/avx/avxvnni_64.test} | 0 bddisasm_test/x86/avx/avxvnniint8_64.asm | 31 + bddisasm_test/x86/avx/avxvnniint8_64.result | 444 + bddisasm_test/x86/avx/avxvnniint8_64.test | Bin 0 -> 120 bytes bddisasm_test/{ => x86}/avx/f16c_64.asm | 0 bddisasm_test/{ => x86}/avx/f16c_64.result | 0 .../{avx/f16c_64 => x86/avx/f16c_64.test} | 0 bddisasm_test/{ => x86}/avx/fma4_64.asm | 0 bddisasm_test/{ => x86}/avx/fma4_64.result | 0 .../{avx/fma4_64 => x86/avx/fma4_64.test} | 0 bddisasm_test/{ => x86}/avx/fma_64.asm | 0 bddisasm_test/{ => x86}/avx/fma_64.result | 0 .../{avx/fma_64 => x86/avx/fma_64.test} | 0 .../{ => x86}/avx512/avx512bitalg_64.asm | 0 .../{ => x86}/avx512/avx512bitalg_64.result | 0 .../avx512/avx512bitalg_64.test} | 0 .../{ => x86}/avx512/avx512bw_64.asm | 0 .../{ => x86}/avx512/avx512bw_64.result | 60 +- .../avx512/avx512bw_64.test} | Bin .../{ => x86}/avx512/avx512cd_64.asm | 0 .../{ => x86}/avx512/avx512cd_64.result | 0 .../avx512/avx512cd_64.test} | 0 .../{ => x86}/avx512/avx512dq_64.asm | 0 .../{ => x86}/avx512/avx512dq_64.result | 12 +- .../avx512/avx512dq_64.test} | Bin .../{ => x86}/avx512/avx512er_64.asm | 0 .../{ => x86}/avx512/avx512er_64.result | 0 .../avx512/avx512er_64.test} | 0 bddisasm_test/{ => x86}/avx512/avx512f_64.asm | 0 .../{ => x86}/avx512/avx512f_64.result | 0 .../avx512f_64 => x86/avx512/avx512f_64.test} | Bin .../{ => x86}/avx512/avx512fma_64.asm | 0 .../{ => x86}/avx512/avx512fma_64.result | 0 .../avx512/avx512fma_64.test} | 0 .../{ => x86}/avx512/avx512fp16_32.result | 0 .../avx512/avx512fp16_32.test} | 0 .../{ => x86}/avx512/avx512fp16_64.result | 0 .../avx512/avx512fp16_64.test} | 0 .../{ => x86}/avx512/avx512pf_64.asm | 0 .../{ => x86}/avx512/avx512pf_64.result | 0 .../avx512/avx512pf_64.test} | Bin .../{ => x86}/avx512/avx512vbmi_64.asm | 0 .../{ => x86}/avx512/avx512vbmi_64.result | 0 .../avx512/avx512vbmi_64.test} | 0 .../{ => x86}/avx512/avx512vnni_64.asm | 0 .../{ => x86}/avx512/avx512vnni_64.result | 0 .../avx512/avx512vnni_64.test} | 0 bddisasm_test/{ => x86}/basic/address_16.asm | 0 .../{ => x86}/basic/address_16.result | 0 .../address_16 => x86/basic/address_16.test} | Bin bddisasm_test/{ => x86}/basic/address_32.asm | 0 .../{ => x86}/basic/address_32.result | 0 .../address_32 => x86/basic/address_32.test} | Bin bddisasm_test/{ => x86}/basic/address_64.asm | 0 .../{ => x86}/basic/address_64.result | 0 .../address_64 => x86/basic/address_64.test} | Bin bddisasm_test/{ => x86}/basic/aes_64.asm | 0 bddisasm_test/{ => x86}/basic/aes_64.result | 0 .../{basic/aes_64 => x86/basic/aes_64.test} | 0 bddisasm_test/{ => x86}/basic/basic1_64.asm | 0 .../{ => x86}/basic/basic1_64.result | 0 .../basic1_64 => x86/basic/basic1_64.test} | Bin bddisasm_test/{ => x86}/basic/basic2_64.asm | 0 .../{ => x86}/basic/basic2_64.result | 0 .../basic2_64 => x86/basic/basic2_64.test} | 0 bddisasm_test/{ => x86}/basic/bmi_64.asm | 0 bddisasm_test/{ => x86}/basic/bmi_64.result | 0 .../{basic/bmi_64 => x86/basic/bmi_64.test} | 0 bddisasm_test/{ => x86}/basic/branch_16.asm | 0 .../{ => x86}/basic/branch_16.result | 0 .../branch_16 => x86/basic/branch_16.test} | Bin bddisasm_test/{ => x86}/basic/branch_32.asm | 0 .../{ => x86}/basic/branch_32.result | 0 .../branch_32 => x86/basic/branch_32.test} | Bin bddisasm_test/{ => x86}/basic/branch_64.asm | 0 .../{ => x86}/basic/branch_64.result | 0 .../branch_64 => x86/basic/branch_64.test} | Bin bddisasm_test/{ => x86}/basic/cet_64.asm | 0 bddisasm_test/{ => x86}/basic/cet_64.result | 0 .../{basic/cet_64 => x86/basic/cet_64.test} | Bin bddisasm_test/{ => x86}/basic/enqcmd_64.asm | 0 .../{ => x86}/basic/enqcmd_64.result | 0 .../enqcmd_64 => x86/basic/enqcmd_64.test} | Bin bddisasm_test/{ => x86}/basic/fpu_64.asm | 0 bddisasm_test/{ => x86}/basic/fpu_64.result | 0 .../{basic/fpu_64 => x86/basic/fpu_64.test} | 0 bddisasm_test/{ => x86}/basic/gfni_64.asm | 0 bddisasm_test/{ => x86}/basic/gfni_64.result | 0 .../{basic/gfni_64 => x86/basic/gfni_64.test} | 0 bddisasm_test/{ => x86}/basic/invlpgb_64.asm | 0 .../{ => x86}/basic/invlpgb_64.result | 0 .../invlpgb_64 => x86/basic/invlpgb_64.test} | 0 bddisasm_test/{ => x86}/basic/misc_16.asm | 0 bddisasm_test/{ => x86}/basic/misc_16.result | 0 .../{basic/misc_16 => x86/basic/misc_16.test} | Bin bddisasm_test/{ => x86}/basic/misc_32.asm | 0 bddisasm_test/{ => x86}/basic/misc_32.result | 0 .../{basic/misc_32 => x86/basic/misc_32.test} | Bin bddisasm_test/{ => x86}/basic/misc_64.asm | 0 bddisasm_test/{ => x86}/basic/misc_64.result | 0 .../{basic/misc_64 => x86/basic/misc_64.test} | 0 bddisasm_test/{ => x86}/basic/mpx_64.asm | 0 bddisasm_test/{ => x86}/basic/mpx_64.result | 0 .../{basic/mpx_64 => x86/basic/mpx_64.test} | 0 bddisasm_test/{ => x86}/basic/prefixes_64.asm | 0 .../{ => x86}/basic/prefixes_64.result | 0 .../basic/prefixes_64.test} | Bin bddisasm_test/{ => x86}/basic/sha_64.asm | 0 bddisasm_test/{ => x86}/basic/sha_64.result | 0 .../{basic/sha_64 => x86/basic/sha_64.test} | 0 bddisasm_test/{ => x86}/basic/snp_64.asm | 0 bddisasm_test/{ => x86}/basic/snp_64.result | 0 .../{basic/snp_64 => x86/basic/snp_64.test} | 0 bddisasm_test/{ => x86}/basic/stack_16.asm | 0 bddisasm_test/{ => x86}/basic/stack_16.result | 0 .../stack_16 => x86/basic/stack_16.test} | Bin bddisasm_test/{ => x86}/basic/stack_32.asm | 0 bddisasm_test/{ => x86}/basic/stack_32.result | 0 .../stack_32 => x86/basic/stack_32.test} | Bin bddisasm_test/{ => x86}/basic/stack_64.asm | 0 bddisasm_test/{ => x86}/basic/stack_64.result | 0 .../stack_64 => x86/basic/stack_64.test} | Bin bddisasm_test/{ => x86}/basic/svm_64.asm | 0 bddisasm_test/{ => x86}/basic/svm_64.result | 0 .../{basic/svm_64 => x86/basic/svm_64.test} | 0 bddisasm_test/{ => x86}/basic/system_16.asm | 0 .../{ => x86}/basic/system_16.result | 0 .../system_16 => x86/basic/system_16.test} | Bin bddisasm_test/{ => x86}/basic/system_32.asm | 0 .../{ => x86}/basic/system_32.result | 0 .../system_32 => x86/basic/system_32.test} | Bin bddisasm_test/{ => x86}/basic/system_64.asm | 0 .../{ => x86}/basic/system_64.result | 0 .../system_64 => x86/basic/system_64.test} | Bin bddisasm_test/{ => x86}/basic/tsx_64.asm | 0 bddisasm_test/{ => x86}/basic/tsx_64.result | 0 .../{basic/tsx_64 => x86/basic/tsx_64.test} | Bin bddisasm_test/{ => x86}/basic/vmx_64.asm | 0 bddisasm_test/{ => x86}/basic/vmx_64.result | 0 .../{basic/vmx_64 => x86/basic/vmx_64.test} | Bin bddisasm_test/{ => x86}/cet/cet_32.asm | 0 bddisasm_test/{ => x86}/cet/cet_32.result | 0 .../{cet/cet_32 => x86/cet/cet_32.test} | Bin bddisasm_test/{ => x86}/cet/cet_64.asm | 0 bddisasm_test/{ => x86}/cet/cet_64.result | 0 .../{cet/cet_64 => x86/cet/cet_64.test} | Bin bddisasm_test/{ => x86}/cet/dnt_32.asm | 0 bddisasm_test/{ => x86}/cet/dnt_32.result | 0 .../{cet/dnt_32 => x86/cet/dnt_32.test} | 0 bddisasm_test/{ => x86}/cet/dnt_64.asm | 0 bddisasm_test/{ => x86}/cet/dnt_64.result | 0 .../{cet/dnt_64 => x86/cet/dnt_64.test} | 0 bddisasm_test/x86/cmpccxadd/cmpccxadd_64.asm | 49 + .../x86/cmpccxadd/cmpccxadd_64.result | 704 + bddisasm_test/x86/cmpccxadd/cmpccxadd_64.test | Bin 0 -> 160 bytes bddisasm_test/{ => x86}/fred/fred_64.asm | 0 bddisasm_test/{ => x86}/fred/fred_64.result | 0 .../{fred/fred_64 => x86/fred/fred_64.test} | Bin bddisasm_test/{ => x86}/kl/kl_64.asm | 0 bddisasm_test/{ => x86}/kl/kl_64.result | 0 bddisasm_test/{kl/kl_64 => x86/kl/kl_64.test} | Bin bddisasm_test/x86/msr/msr_64.asm | 5 + bddisasm_test/x86/msr/msr_64.result | 56 + bddisasm_test/x86/msr/msr_64.test | 1 + .../x86/prefetchit/prefetchit_32.asm | 4 + .../x86/prefetchit/prefetchit_32.result | 30 + .../x86/prefetchit/prefetchit_32.test | 1 + .../x86/prefetchit/prefetchit_64.asm | 11 + .../x86/prefetchit/prefetchit_64.result | 122 + .../x86/prefetchit/prefetchit_64.test | 1 + bddisasm_test/x86/rao-int/raoint_64.asm | 29 + bddisasm_test/x86/rao-int/raoint_64.result | 408 + bddisasm_test/x86/rao-int/raoint_64.test | Bin 0 -> 166 bytes bddisasm_test/{ => x86}/simd/3dnow_64.asm | 0 bddisasm_test/{ => x86}/simd/3dnow_64.result | 0 .../{simd/3dnow_64 => x86/simd/3dnow_64.test} | 0 bddisasm_test/{ => x86}/simd/mmx_64.asm | 0 bddisasm_test/{ => x86}/simd/mmx_64.result | 0 .../{simd/mmx_64 => x86/simd/mmx_64.test} | Bin bddisasm_test/{ => x86}/simd/sse2_64.asm | 0 bddisasm_test/{ => x86}/simd/sse2_64.result | 36 +- .../{simd/sse2_64 => x86/simd/sse2_64.test} | 0 bddisasm_test/{ => x86}/simd/sse3_64.asm | 0 bddisasm_test/{ => x86}/simd/sse3_64.result | 0 .../{simd/sse3_64 => x86/simd/sse3_64.test} | Bin bddisasm_test/{ => x86}/simd/sse4_64.asm | 0 bddisasm_test/{ => x86}/simd/sse4_64.result | 36 +- .../{simd/sse4_64 => x86/simd/sse4_64.test} | 0 .../{ => x86}/special/amx_64_skip.asm | 0 .../{ => x86}/special/amx_64_skip.result | 0 .../special/amx_64_skip.test} | Bin .../special/avx2gather_1_64_skip.asm | 0 .../special/avx2gather_1_64_skip.result | 0 .../special/avx2gather_1_64_skip.test} | Bin .../special/avx2gather_2_64_skip.asm | 0 .../special/avx2gather_2_64_skip.result | 0 .../special/avx2gather_2_64_skip.test} | Bin .../special/avx2gather_3_64_skip.asm | 0 .../special/avx2gather_3_64_skip.result | 0 .../special/avx2gather_3_64_skip.test} | Bin bddisasm_test/{ => x86}/special/cr8_32.asm | 0 bddisasm_test/{ => x86}/special/cr8_32.result | 0 .../cr8_32 => x86/special/cr8_32.test} | 0 .../{ => x86}/special/ignorew_evex_32.result | 0 .../special/ignorew_evex_32.test} | 0 .../{ => x86}/special/ignorew_evex_64.result | 0 .../special/ignorew_evex_64.test} | 0 .../{ => x86}/special/invalid_32_skip.asm | 0 .../{ => x86}/special/invalid_32_skip.result | 0 .../special/invalid_32_skip.test} | 0 .../{ => x86}/special/invalid_64_skip.asm | 0 .../{ => x86}/special/invalid_64_skip.result | 0 .../special/invalid_64_skip.test} | 0 .../special/invalid_evex_64_skip.asm | 0 .../special/invalid_evex_64_skip.result | 0 .../special/invalid_evex_64_skip.test} | 0 bddisasm_test/{ => x86}/special/long_64.asm | 0 .../{ => x86}/special/long_64.result | 0 .../long_64 => x86/special/long_64.test} | 0 .../{ => x86}/special/movcrdr_64.asm | 0 .../{ => x86}/special/movcrdr_64.result | 0 .../special/movcrdr_64.test} | Bin bddisasm_test/{ => x86}/special/only_32.asm | 0 .../{ => x86}/special/only_32.result | 2 +- .../only_32 => x86/special/only_32.test} | 0 bddisasm_test/{ => x86}/special/only_64.asm | 0 .../{ => x86}/special/only_64.result | 0 .../only_64 => x86/special/only_64.test} | 0 .../{ => x86}/special/regressions_32.asm | 0 .../{ => x86}/special/regressions_32.result | 0 .../special/regressions_32.test} | 0 .../{ => x86}/special/regressions_64.asm | 0 .../{ => x86}/special/regressions_64.result | 0 .../special/regressions_64.test} | Bin bddisasm_test/{ => x86}/tdx/tdx_64.asm | 0 bddisasm_test/{ => x86}/tdx/tdx_64.result | 0 .../{tdx/tdx_64 => x86/tdx/tdx_64.test} | 0 bddisasm_test/{ => x86}/uintr/uintr_64.asm | 0 bddisasm_test/{ => x86}/uintr/uintr_64.result | 0 .../uintr_64 => x86/uintr/uintr_64.test} | 0 bindings/pybddisasm/setup.py | 2 +- disasmtool/disasmtool.c | 25 +- disasmtool_lix/dumpers.cpp | 52 + disasmtool_lix/dumpers.cpp.bak | 1933 +++ inc/bddisasm.h | 2 + inc/constants.h | 56 +- inc/cpuidflags.h | 14 + inc/version.h | 4 +- isagenerator/disasmlib.py | 15 +- isagenerator/generate_tables.py | 13 +- isagenerator/instructions/cpuid.dat | 17 + isagenerator/instructions/table_0F.dat | 37 +- isagenerator/instructions/table_0F_38.dat | 5 + isagenerator/instructions/table_0F_3A.dat | 10 +- isagenerator/instructions/table_base.dat | 2 +- isagenerator/instructions/table_evex3.dat | 10 +- isagenerator/instructions/table_vex1.dat | 8 +- isagenerator/instructions/table_vex2.dat | 36 + isagenerator/instructions/table_vex3.dat | 10 +- 288 files changed, 16159 insertions(+), 9013 deletions(-) rename bddisasm_test/{ => x86}/amx/amx1_64.asm (94%) rename bddisasm_test/{ => x86}/amx/amx1_64.result (93%) rename bddisasm_test/{amx/amx1_64 => x86/amx/amx1_64.test} (62%) rename bddisasm_test/{ => x86}/avx/avx2_64.asm (100%) rename bddisasm_test/{ => x86}/avx/avx2_64.result (100%) rename bddisasm_test/{avx/avx2_64 => x86/avx/avx2_64.test} (100%) rename bddisasm_test/{ => x86}/avx/avx2gather_64.asm (100%) rename bddisasm_test/{ => x86}/avx/avx2gather_64.result (100%) rename bddisasm_test/{avx/avx2gather_64 => x86/avx/avx2gather_64.test} (100%) rename bddisasm_test/{ => x86}/avx/avx_64.asm (100%) rename bddisasm_test/{ => x86}/avx/avx_64.result (99%) rename bddisasm_test/{avx/avx_64 => x86/avx/avx_64.test} (100%) create mode 100644 bddisasm_test/x86/avx/avxifma_64.asm create mode 100644 bddisasm_test/x86/avx/avxifma_64.result create mode 100644 bddisasm_test/x86/avx/avxifma_64.test create mode 100644 bddisasm_test/x86/avx/avxneconvert_64.asm create mode 100644 bddisasm_test/x86/avx/avxneconvert_64.result create mode 100644 bddisasm_test/x86/avx/avxneconvert_64.test rename bddisasm_test/{ => x86}/avx/avxvnni_64.asm (100%) rename bddisasm_test/{ => x86}/avx/avxvnni_64.result (100%) rename bddisasm_test/{avx/avxvnni_64 => x86/avx/avxvnni_64.test} (100%) create mode 100644 bddisasm_test/x86/avx/avxvnniint8_64.asm create mode 100644 bddisasm_test/x86/avx/avxvnniint8_64.result create mode 100644 bddisasm_test/x86/avx/avxvnniint8_64.test rename bddisasm_test/{ => x86}/avx/f16c_64.asm (100%) rename bddisasm_test/{ => x86}/avx/f16c_64.result (100%) rename bddisasm_test/{avx/f16c_64 => x86/avx/f16c_64.test} (100%) rename bddisasm_test/{ => x86}/avx/fma4_64.asm (100%) rename bddisasm_test/{ => x86}/avx/fma4_64.result (100%) rename bddisasm_test/{avx/fma4_64 => x86/avx/fma4_64.test} (100%) rename bddisasm_test/{ => x86}/avx/fma_64.asm (100%) rename bddisasm_test/{ => x86}/avx/fma_64.result (100%) rename bddisasm_test/{avx/fma_64 => x86/avx/fma_64.test} (100%) rename bddisasm_test/{ => x86}/avx512/avx512bitalg_64.asm (100%) rename bddisasm_test/{ => x86}/avx512/avx512bitalg_64.result (100%) rename bddisasm_test/{avx512/avx512bitalg_64 => x86/avx512/avx512bitalg_64.test} (100%) rename bddisasm_test/{ => x86}/avx512/avx512bw_64.asm (100%) rename bddisasm_test/{ => x86}/avx512/avx512bw_64.result (99%) rename bddisasm_test/{avx512/avx512bw_64 => x86/avx512/avx512bw_64.test} (100%) rename bddisasm_test/{ => x86}/avx512/avx512cd_64.asm (100%) rename bddisasm_test/{ => x86}/avx512/avx512cd_64.result (100%) rename bddisasm_test/{avx512/avx512cd_64 => x86/avx512/avx512cd_64.test} (100%) rename bddisasm_test/{ => x86}/avx512/avx512dq_64.asm (100%) rename bddisasm_test/{ => x86}/avx512/avx512dq_64.result (99%) rename bddisasm_test/{avx512/avx512dq_64 => x86/avx512/avx512dq_64.test} (100%) rename bddisasm_test/{ => x86}/avx512/avx512er_64.asm (100%) rename bddisasm_test/{ => x86}/avx512/avx512er_64.result (100%) rename bddisasm_test/{avx512/avx512er_64 => x86/avx512/avx512er_64.test} (100%) rename bddisasm_test/{ => x86}/avx512/avx512f_64.asm (100%) rename bddisasm_test/{ => x86}/avx512/avx512f_64.result (100%) rename bddisasm_test/{avx512/avx512f_64 => x86/avx512/avx512f_64.test} (100%) rename bddisasm_test/{ => x86}/avx512/avx512fma_64.asm (100%) rename bddisasm_test/{ => x86}/avx512/avx512fma_64.result (100%) rename bddisasm_test/{avx512/avx512fma_64 => x86/avx512/avx512fma_64.test} (100%) rename bddisasm_test/{ => x86}/avx512/avx512fp16_32.result (100%) rename bddisasm_test/{avx512/avx512fp16_32 => x86/avx512/avx512fp16_32.test} (100%) rename bddisasm_test/{ => x86}/avx512/avx512fp16_64.result (100%) rename bddisasm_test/{avx512/avx512fp16_64 => x86/avx512/avx512fp16_64.test} (100%) rename bddisasm_test/{ => x86}/avx512/avx512pf_64.asm (100%) rename bddisasm_test/{ => x86}/avx512/avx512pf_64.result (100%) rename bddisasm_test/{avx512/avx512pf_64 => x86/avx512/avx512pf_64.test} (100%) rename bddisasm_test/{ => x86}/avx512/avx512vbmi_64.asm (100%) rename bddisasm_test/{ => x86}/avx512/avx512vbmi_64.result (100%) rename bddisasm_test/{avx512/avx512vbmi_64 => x86/avx512/avx512vbmi_64.test} (100%) rename bddisasm_test/{ => x86}/avx512/avx512vnni_64.asm (100%) rename bddisasm_test/{ => x86}/avx512/avx512vnni_64.result (100%) rename bddisasm_test/{avx512/avx512vnni_64 => x86/avx512/avx512vnni_64.test} (100%) rename bddisasm_test/{ => x86}/basic/address_16.asm (100%) rename bddisasm_test/{ => x86}/basic/address_16.result (100%) rename bddisasm_test/{basic/address_16 => x86/basic/address_16.test} (100%) rename bddisasm_test/{ => x86}/basic/address_32.asm (100%) rename bddisasm_test/{ => x86}/basic/address_32.result (100%) rename bddisasm_test/{basic/address_32 => x86/basic/address_32.test} (100%) rename bddisasm_test/{ => x86}/basic/address_64.asm (100%) rename bddisasm_test/{ => x86}/basic/address_64.result (100%) rename bddisasm_test/{basic/address_64 => x86/basic/address_64.test} (100%) rename bddisasm_test/{ => x86}/basic/aes_64.asm (100%) rename bddisasm_test/{ => x86}/basic/aes_64.result (100%) rename bddisasm_test/{basic/aes_64 => x86/basic/aes_64.test} (100%) rename bddisasm_test/{ => x86}/basic/basic1_64.asm (100%) rename bddisasm_test/{ => x86}/basic/basic1_64.result (100%) rename bddisasm_test/{basic/basic1_64 => x86/basic/basic1_64.test} (100%) rename bddisasm_test/{ => x86}/basic/basic2_64.asm (100%) rename bddisasm_test/{ => x86}/basic/basic2_64.result (100%) rename bddisasm_test/{basic/basic2_64 => x86/basic/basic2_64.test} (100%) rename bddisasm_test/{ => x86}/basic/bmi_64.asm (100%) rename bddisasm_test/{ => x86}/basic/bmi_64.result (100%) rename bddisasm_test/{basic/bmi_64 => x86/basic/bmi_64.test} (100%) rename bddisasm_test/{ => x86}/basic/branch_16.asm (100%) rename bddisasm_test/{ => x86}/basic/branch_16.result (100%) rename bddisasm_test/{basic/branch_16 => x86/basic/branch_16.test} (100%) rename bddisasm_test/{ => x86}/basic/branch_32.asm (100%) rename bddisasm_test/{ => x86}/basic/branch_32.result (100%) rename bddisasm_test/{basic/branch_32 => x86/basic/branch_32.test} (100%) rename bddisasm_test/{ => x86}/basic/branch_64.asm (100%) rename bddisasm_test/{ => x86}/basic/branch_64.result (100%) rename bddisasm_test/{basic/branch_64 => x86/basic/branch_64.test} (100%) rename bddisasm_test/{ => x86}/basic/cet_64.asm (100%) rename bddisasm_test/{ => x86}/basic/cet_64.result (100%) rename bddisasm_test/{basic/cet_64 => x86/basic/cet_64.test} (100%) rename bddisasm_test/{ => x86}/basic/enqcmd_64.asm (100%) rename bddisasm_test/{ => x86}/basic/enqcmd_64.result (100%) rename bddisasm_test/{basic/enqcmd_64 => x86/basic/enqcmd_64.test} (100%) rename bddisasm_test/{ => x86}/basic/fpu_64.asm (100%) rename bddisasm_test/{ => x86}/basic/fpu_64.result (100%) rename bddisasm_test/{basic/fpu_64 => x86/basic/fpu_64.test} (100%) rename bddisasm_test/{ => x86}/basic/gfni_64.asm (100%) rename bddisasm_test/{ => x86}/basic/gfni_64.result (100%) rename bddisasm_test/{basic/gfni_64 => x86/basic/gfni_64.test} (100%) rename bddisasm_test/{ => x86}/basic/invlpgb_64.asm (100%) rename bddisasm_test/{ => x86}/basic/invlpgb_64.result (100%) rename bddisasm_test/{basic/invlpgb_64 => x86/basic/invlpgb_64.test} (100%) rename bddisasm_test/{ => x86}/basic/misc_16.asm (100%) rename bddisasm_test/{ => x86}/basic/misc_16.result (100%) rename bddisasm_test/{basic/misc_16 => x86/basic/misc_16.test} (100%) rename bddisasm_test/{ => x86}/basic/misc_32.asm (100%) rename bddisasm_test/{ => x86}/basic/misc_32.result (100%) rename bddisasm_test/{basic/misc_32 => x86/basic/misc_32.test} (100%) rename bddisasm_test/{ => x86}/basic/misc_64.asm (100%) rename bddisasm_test/{ => x86}/basic/misc_64.result (100%) rename bddisasm_test/{basic/misc_64 => x86/basic/misc_64.test} (100%) rename bddisasm_test/{ => x86}/basic/mpx_64.asm (100%) rename bddisasm_test/{ => x86}/basic/mpx_64.result (100%) rename bddisasm_test/{basic/mpx_64 => x86/basic/mpx_64.test} (100%) rename bddisasm_test/{ => x86}/basic/prefixes_64.asm (100%) rename bddisasm_test/{ => x86}/basic/prefixes_64.result (100%) rename bddisasm_test/{basic/prefixes_64 => x86/basic/prefixes_64.test} (100%) rename bddisasm_test/{ => x86}/basic/sha_64.asm (100%) rename bddisasm_test/{ => x86}/basic/sha_64.result (100%) rename bddisasm_test/{basic/sha_64 => x86/basic/sha_64.test} (100%) rename bddisasm_test/{ => x86}/basic/snp_64.asm (100%) rename bddisasm_test/{ => x86}/basic/snp_64.result (100%) rename bddisasm_test/{basic/snp_64 => x86/basic/snp_64.test} (100%) rename bddisasm_test/{ => x86}/basic/stack_16.asm (100%) rename bddisasm_test/{ => x86}/basic/stack_16.result (100%) rename bddisasm_test/{basic/stack_16 => x86/basic/stack_16.test} (100%) rename bddisasm_test/{ => x86}/basic/stack_32.asm (100%) rename bddisasm_test/{ => x86}/basic/stack_32.result (100%) rename bddisasm_test/{basic/stack_32 => x86/basic/stack_32.test} (100%) rename bddisasm_test/{ => x86}/basic/stack_64.asm (100%) rename bddisasm_test/{ => x86}/basic/stack_64.result (100%) rename bddisasm_test/{basic/stack_64 => x86/basic/stack_64.test} (100%) rename bddisasm_test/{ => x86}/basic/svm_64.asm (100%) rename bddisasm_test/{ => x86}/basic/svm_64.result (100%) rename bddisasm_test/{basic/svm_64 => x86/basic/svm_64.test} (100%) rename bddisasm_test/{ => x86}/basic/system_16.asm (100%) rename bddisasm_test/{ => x86}/basic/system_16.result (100%) rename bddisasm_test/{basic/system_16 => x86/basic/system_16.test} (100%) rename bddisasm_test/{ => x86}/basic/system_32.asm (100%) rename bddisasm_test/{ => x86}/basic/system_32.result (100%) rename bddisasm_test/{basic/system_32 => x86/basic/system_32.test} (100%) rename bddisasm_test/{ => x86}/basic/system_64.asm (100%) rename bddisasm_test/{ => x86}/basic/system_64.result (100%) rename bddisasm_test/{basic/system_64 => x86/basic/system_64.test} (100%) rename bddisasm_test/{ => x86}/basic/tsx_64.asm (100%) rename bddisasm_test/{ => x86}/basic/tsx_64.result (100%) rename bddisasm_test/{basic/tsx_64 => x86/basic/tsx_64.test} (100%) rename bddisasm_test/{ => x86}/basic/vmx_64.asm (100%) rename bddisasm_test/{ => x86}/basic/vmx_64.result (100%) rename bddisasm_test/{basic/vmx_64 => x86/basic/vmx_64.test} (100%) rename bddisasm_test/{ => x86}/cet/cet_32.asm (100%) rename bddisasm_test/{ => x86}/cet/cet_32.result (100%) rename bddisasm_test/{cet/cet_32 => x86/cet/cet_32.test} (100%) rename bddisasm_test/{ => x86}/cet/cet_64.asm (100%) rename bddisasm_test/{ => x86}/cet/cet_64.result (100%) rename bddisasm_test/{cet/cet_64 => x86/cet/cet_64.test} (100%) rename bddisasm_test/{ => x86}/cet/dnt_32.asm (100%) rename bddisasm_test/{ => x86}/cet/dnt_32.result (100%) rename bddisasm_test/{cet/dnt_32 => x86/cet/dnt_32.test} (100%) rename bddisasm_test/{ => x86}/cet/dnt_64.asm (100%) rename bddisasm_test/{ => x86}/cet/dnt_64.result (100%) rename bddisasm_test/{cet/dnt_64 => x86/cet/dnt_64.test} (100%) create mode 100644 bddisasm_test/x86/cmpccxadd/cmpccxadd_64.asm create mode 100644 bddisasm_test/x86/cmpccxadd/cmpccxadd_64.result create mode 100644 bddisasm_test/x86/cmpccxadd/cmpccxadd_64.test rename bddisasm_test/{ => x86}/fred/fred_64.asm (100%) rename bddisasm_test/{ => x86}/fred/fred_64.result (100%) rename bddisasm_test/{fred/fred_64 => x86/fred/fred_64.test} (100%) rename bddisasm_test/{ => x86}/kl/kl_64.asm (100%) rename bddisasm_test/{ => x86}/kl/kl_64.result (100%) rename bddisasm_test/{kl/kl_64 => x86/kl/kl_64.test} (100%) create mode 100644 bddisasm_test/x86/msr/msr_64.asm create mode 100644 bddisasm_test/x86/msr/msr_64.result create mode 100644 bddisasm_test/x86/msr/msr_64.test create mode 100644 bddisasm_test/x86/prefetchit/prefetchit_32.asm create mode 100644 bddisasm_test/x86/prefetchit/prefetchit_32.result create mode 100644 bddisasm_test/x86/prefetchit/prefetchit_32.test create mode 100644 bddisasm_test/x86/prefetchit/prefetchit_64.asm create mode 100644 bddisasm_test/x86/prefetchit/prefetchit_64.result create mode 100644 bddisasm_test/x86/prefetchit/prefetchit_64.test create mode 100644 bddisasm_test/x86/rao-int/raoint_64.asm create mode 100644 bddisasm_test/x86/rao-int/raoint_64.result create mode 100644 bddisasm_test/x86/rao-int/raoint_64.test rename bddisasm_test/{ => x86}/simd/3dnow_64.asm (100%) rename bddisasm_test/{ => x86}/simd/3dnow_64.result (100%) rename bddisasm_test/{simd/3dnow_64 => x86/simd/3dnow_64.test} (100%) rename bddisasm_test/{ => x86}/simd/mmx_64.asm (100%) rename bddisasm_test/{ => x86}/simd/mmx_64.result (100%) rename bddisasm_test/{simd/mmx_64 => x86/simd/mmx_64.test} (100%) rename bddisasm_test/{ => x86}/simd/sse2_64.asm (100%) rename bddisasm_test/{ => x86}/simd/sse2_64.result (99%) rename bddisasm_test/{simd/sse2_64 => x86/simd/sse2_64.test} (100%) rename bddisasm_test/{ => x86}/simd/sse3_64.asm (100%) rename bddisasm_test/{ => x86}/simd/sse3_64.result (100%) rename bddisasm_test/{simd/sse3_64 => x86/simd/sse3_64.test} (100%) rename bddisasm_test/{ => x86}/simd/sse4_64.asm (100%) rename bddisasm_test/{ => x86}/simd/sse4_64.result (99%) rename bddisasm_test/{simd/sse4_64 => x86/simd/sse4_64.test} (100%) rename bddisasm_test/{ => x86}/special/amx_64_skip.asm (100%) rename bddisasm_test/{ => x86}/special/amx_64_skip.result (100%) rename bddisasm_test/{special/amx_64_skip => x86/special/amx_64_skip.test} (100%) rename bddisasm_test/{ => x86}/special/avx2gather_1_64_skip.asm (100%) rename bddisasm_test/{ => x86}/special/avx2gather_1_64_skip.result (100%) rename bddisasm_test/{special/avx2gather_1_64_skip => x86/special/avx2gather_1_64_skip.test} (100%) rename bddisasm_test/{ => x86}/special/avx2gather_2_64_skip.asm (100%) rename bddisasm_test/{ => x86}/special/avx2gather_2_64_skip.result (100%) rename bddisasm_test/{special/avx2gather_2_64_skip => x86/special/avx2gather_2_64_skip.test} (100%) rename bddisasm_test/{ => x86}/special/avx2gather_3_64_skip.asm (100%) rename bddisasm_test/{ => x86}/special/avx2gather_3_64_skip.result (100%) rename bddisasm_test/{special/avx2gather_3_64_skip => x86/special/avx2gather_3_64_skip.test} (100%) rename bddisasm_test/{ => x86}/special/cr8_32.asm (100%) rename bddisasm_test/{ => x86}/special/cr8_32.result (100%) rename bddisasm_test/{special/cr8_32 => x86/special/cr8_32.test} (100%) rename bddisasm_test/{ => x86}/special/ignorew_evex_32.result (100%) rename bddisasm_test/{special/ignorew_evex_32 => x86/special/ignorew_evex_32.test} (100%) rename bddisasm_test/{ => x86}/special/ignorew_evex_64.result (100%) rename bddisasm_test/{special/ignorew_evex_64 => x86/special/ignorew_evex_64.test} (100%) rename bddisasm_test/{ => x86}/special/invalid_32_skip.asm (100%) rename bddisasm_test/{ => x86}/special/invalid_32_skip.result (100%) rename bddisasm_test/{special/invalid_32_skip => x86/special/invalid_32_skip.test} (100%) rename bddisasm_test/{ => x86}/special/invalid_64_skip.asm (100%) rename bddisasm_test/{ => x86}/special/invalid_64_skip.result (100%) rename bddisasm_test/{special/invalid_64_skip => x86/special/invalid_64_skip.test} (100%) rename bddisasm_test/{ => x86}/special/invalid_evex_64_skip.asm (100%) rename bddisasm_test/{ => x86}/special/invalid_evex_64_skip.result (100%) rename bddisasm_test/{special/invalid_evex_64_skip => x86/special/invalid_evex_64_skip.test} (100%) rename bddisasm_test/{ => x86}/special/long_64.asm (100%) rename bddisasm_test/{ => x86}/special/long_64.result (100%) rename bddisasm_test/{special/long_64 => x86/special/long_64.test} (100%) rename bddisasm_test/{ => x86}/special/movcrdr_64.asm (100%) rename bddisasm_test/{ => x86}/special/movcrdr_64.result (100%) rename bddisasm_test/{special/movcrdr_64 => x86/special/movcrdr_64.test} (100%) rename bddisasm_test/{ => x86}/special/only_32.asm (100%) rename bddisasm_test/{ => x86}/special/only_32.result (99%) rename bddisasm_test/{special/only_32 => x86/special/only_32.test} (100%) rename bddisasm_test/{ => x86}/special/only_64.asm (100%) rename bddisasm_test/{ => x86}/special/only_64.result (100%) rename bddisasm_test/{special/only_64 => x86/special/only_64.test} (100%) rename bddisasm_test/{ => x86}/special/regressions_32.asm (100%) rename bddisasm_test/{ => x86}/special/regressions_32.result (100%) rename bddisasm_test/{special/regressions_32 => x86/special/regressions_32.test} (100%) rename bddisasm_test/{ => x86}/special/regressions_64.asm (100%) rename bddisasm_test/{ => x86}/special/regressions_64.result (100%) rename bddisasm_test/{special/regressions_64 => x86/special/regressions_64.test} (100%) rename bddisasm_test/{ => x86}/tdx/tdx_64.asm (100%) rename bddisasm_test/{ => x86}/tdx/tdx_64.result (100%) rename bddisasm_test/{tdx/tdx_64 => x86/tdx/tdx_64.test} (100%) rename bddisasm_test/{ => x86}/uintr/uintr_64.asm (100%) rename bddisasm_test/{ => x86}/uintr/uintr_64.result (100%) rename bddisasm_test/{uintr/uintr_64 => x86/uintr/uintr_64.test} (100%) create mode 100644 disasmtool_lix/dumpers.cpp.bak diff --git a/bddisasm/bddisasm.c b/bddisasm/bddisasm.c index 3099ef6..7abf723 100644 --- a/bddisasm/bddisasm.c +++ b/bddisasm/bddisasm.c @@ -99,6 +99,8 @@ static const ND_UINT16 gOperandMap[] = ND_OPE_S, // ND_OPT_MEM_SHS ND_OPE_S, // ND_OPT_MEM_SHSP ND_OPE_S, // ND_OPT_MEM_SHS0 + ND_OPE_S, // ND_OPT_MEM_SMSRT + ND_OPE_S, // ND_OPT_MEM_DMSRT ND_OPE_L, // ND_OPT_Im2z @@ -182,12 +184,12 @@ NdGetVersion( if (ND_NULL != BuildDate) { - *BuildDate = ND_NULL; + *BuildDate = (char *)ND_NULL; } if (ND_NULL != BuildTime) { - *BuildTime = ND_NULL; + *BuildTime = (char *)ND_NULL; } #else @@ -1585,6 +1587,11 @@ NdParseOperand( size = ND_SIZE_512BIT; break; + case ND_OPS_4096: + // 64 entries x 64 bit per entry = 4096 bit MSR address/value list. + size = ND_SIZE_4096BIT; + break; + case ND_OPS_unknown: size = ND_SIZE_UNKNOWN; break; @@ -2792,6 +2799,26 @@ memory: operand->Info.Memory.ShStkType = ND_SHSTK_PL0_SSP; break; + case ND_OPT_MEM_SMSRT: + // Table of MSR addresses, encoded in [RSI]. + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasBase = ND_TRUE; + operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; + operand->Info.Memory.Base = NDR_RSI; // Always rSI. + operand->Info.Memory.HasSeg = ND_FALSE; // Linear Address directly, only useable in 64 bit mode. + break; + + case ND_OPT_MEM_DMSRT: + // Table of MSR addresses, encoded in [RDI]. + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasBase = ND_TRUE; + operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; + operand->Info.Memory.Base = NDR_RDI; // Always rDI. + operand->Info.Memory.HasSeg = ND_FALSE; // Linear Address directly, only useable in 64 bit mode. + break; + case ND_OPT_MEM_SHSP: // Shadow stack push/pop access. Instrux->MemoryAccess |= operand->Access.Access; @@ -3325,6 +3352,12 @@ NdFindInstruction( { nextIndex = ND_ILUT_INDEX_AUX_REP; } + else if (Instrux->DefCode == ND_CODE_64 && Instrux->HasModRm && + Instrux->ModRm.mod == 0 && Instrux->ModRm.rm == NDR_RBP && + ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_RIPREL]) + { + nextIndex = ND_ILUT_INDEX_AUX_RIPREL; + } else { nextIndex = ND_ILUT_INDEX_AUX_NONE; @@ -3358,6 +3391,10 @@ NdFindInstruction( { pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_FEATURE_CLDEMOTE]; } + else if ((ND_NULL != pTable->Table[ND_ILUT_FEATURE_PITI]) && !!(Instrux->FeatMode & ND_FEAT_PITI)) + { + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_FEATURE_PITI]; + } else { pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_FEATURE_NONE]; diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h index d36b1cb..b54ea69 100644 --- a/bddisasm/include/instructions.h +++ b/bddisasm/include/instructions.h @@ -2,15 +2,15 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ - + // -// This file was auto-generated by generate_tables.py from defs.dat. DO NOT MODIFY! +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! // #ifndef INSTRUCTIONS_H #define INSTRUCTIONS_H -const ND_INSTRUCTION gInstructions[2701] = +const ND_INSTRUCTION gInstructions[2762] = { // Pos:0 Instruction:"AAA" Encoding:"0x37"/"" { @@ -47,9 +47,25 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2 Instruction:"AAM Ib" Encoding:"0xD4 ib"/"I" + // Pos:2 Instruction:"AADD My,Gy" Encoding:"NP 0x0F 0x38 0xFC /r:mem"/"MR" { - ND_INS_AAM, ND_CAT_DECIMAL, ND_SET_I86, 2, + ND_INS_AADD, ND_CAT_RAOINT, ND_SET_RAOINT, 2, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RAOINT, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3 Instruction:"AAM Ib" Encoding:"0xD4 ib"/"I" + { + ND_INS_AAM, ND_CAT_DECIMAL, ND_SET_I86, 3, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -65,9 +81,25 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:3 Instruction:"AAS" Encoding:"0x3F"/"" + // Pos:4 Instruction:"AAND My,Gy" Encoding:"0x66 0x0F 0x38 0xFC /r:mem"/"MR" + { + ND_INS_AAND, ND_CAT_RAOINT, ND_SET_RAOINT, 4, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RAOINT, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:5 Instruction:"AAS" Encoding:"0x3F"/"" { - ND_INS_AAS, ND_CAT_DECIMAL, ND_SET_I86, 3, + ND_INS_AAS, ND_CAT_DECIMAL, ND_SET_I86, 5, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -82,9 +114,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:4 Instruction:"ADC Eb,Gb" Encoding:"0x10 /r"/"MR" + // Pos:6 Instruction:"ADC Eb,Gb" Encoding:"0x10 /r"/"MR" { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -99,9 +131,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:5 Instruction:"ADC Ev,Gv" Encoding:"0x11 /r"/"MR" + // Pos:7 Instruction:"ADC Ev,Gv" Encoding:"0x11 /r"/"MR" { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -116,9 +148,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:6 Instruction:"ADC Gb,Eb" Encoding:"0x12 /r"/"RM" + // Pos:8 Instruction:"ADC Gb,Eb" Encoding:"0x12 /r"/"RM" { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -133,9 +165,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:7 Instruction:"ADC Gv,Ev" Encoding:"0x13 /r"/"RM" + // Pos:9 Instruction:"ADC Gv,Ev" Encoding:"0x13 /r"/"RM" { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -150,9 +182,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:8 Instruction:"ADC AL,Ib" Encoding:"0x14 ib"/"I" + // Pos:10 Instruction:"ADC AL,Ib" Encoding:"0x14 ib"/"I" { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -167,9 +199,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:9 Instruction:"ADC rAX,Iz" Encoding:"0x15 iz"/"I" + // Pos:11 Instruction:"ADC rAX,Iz" Encoding:"0x15 iz"/"I" { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -184,9 +216,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:10 Instruction:"ADC Eb,Ib" Encoding:"0x80 /2 ib"/"MI" + // Pos:12 Instruction:"ADC Eb,Ib" Encoding:"0x80 /2 ib"/"MI" { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -201,9 +233,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:11 Instruction:"ADC Ev,Iz" Encoding:"0x81 /2 iz"/"MI" + // Pos:13 Instruction:"ADC Ev,Iz" Encoding:"0x81 /2 iz"/"MI" { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -218,9 +250,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:12 Instruction:"ADC Eb,Ib" Encoding:"0x82 /2 iz"/"MI" + // Pos:14 Instruction:"ADC Eb,Ib" Encoding:"0x82 /2 iz"/"MI" { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -235,9 +267,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:13 Instruction:"ADC Ev,Ib" Encoding:"0x83 /2 ib"/"MI" + // Pos:15 Instruction:"ADC Ev,Ib" Encoding:"0x83 /2 ib"/"MI" { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -252,9 +284,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:14 Instruction:"ADCX Gy,Ey" Encoding:"0x66 0x0F 0x38 0xF6 /r"/"RM" + // Pos:16 Instruction:"ADCX Gy,Ey" Encoding:"0x66 0x0F 0x38 0xF6 /r"/"RM" { - ND_INS_ADCX, ND_CAT_ARITH, ND_SET_ADX, 5, + ND_INS_ADCX, ND_CAT_ARITH, ND_SET_ADX, 7, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, @@ -269,9 +301,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:15 Instruction:"ADD Eb,Gb" Encoding:"0x00 /r"/"MR" + // Pos:17 Instruction:"ADD Eb,Gb" Encoding:"0x00 /r"/"MR" { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -286,9 +318,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:16 Instruction:"ADD Ev,Gv" Encoding:"0x01 /r"/"MR" + // Pos:18 Instruction:"ADD Ev,Gv" Encoding:"0x01 /r"/"MR" { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -303,9 +335,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:17 Instruction:"ADD Gb,Eb" Encoding:"0x02 /r"/"RM" + // Pos:19 Instruction:"ADD Gb,Eb" Encoding:"0x02 /r"/"RM" { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -320,9 +352,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:18 Instruction:"ADD Gv,Ev" Encoding:"0x03 /r"/"RM" + // Pos:20 Instruction:"ADD Gv,Ev" Encoding:"0x03 /r"/"RM" { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -337,9 +369,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:19 Instruction:"ADD AL,Ib" Encoding:"0x04 ib"/"I" + // Pos:21 Instruction:"ADD AL,Ib" Encoding:"0x04 ib"/"I" { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -354,9 +386,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:20 Instruction:"ADD rAX,Iz" Encoding:"0x05 iz"/"I" + // Pos:22 Instruction:"ADD rAX,Iz" Encoding:"0x05 iz"/"I" { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -371,9 +403,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:21 Instruction:"ADD Eb,Ib" Encoding:"0x80 /0 ib"/"MI" + // Pos:23 Instruction:"ADD Eb,Ib" Encoding:"0x80 /0 ib"/"MI" { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -388,9 +420,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:22 Instruction:"ADD Ev,Iz" Encoding:"0x81 /0 iz"/"MI" + // Pos:24 Instruction:"ADD Ev,Iz" Encoding:"0x81 /0 iz"/"MI" { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -405,9 +437,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:23 Instruction:"ADD Eb,Ib" Encoding:"0x82 /0 iz"/"MI" + // Pos:25 Instruction:"ADD Eb,Ib" Encoding:"0x82 /0 iz"/"MI" { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -422,9 +454,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:24 Instruction:"ADD Ev,Ib" Encoding:"0x83 /0 ib"/"MI" + // Pos:26 Instruction:"ADD Ev,Ib" Encoding:"0x83 /0 ib"/"MI" { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -439,9 +471,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:25 Instruction:"ADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x58 /r"/"RM" + // Pos:27 Instruction:"ADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x58 /r"/"RM" { - ND_INS_ADDPD, ND_CAT_SSE, ND_SET_SSE2, 7, + ND_INS_ADDPD, ND_CAT_SSE, ND_SET_SSE2, 9, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -455,9 +487,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:26 Instruction:"ADDPS Vps,Wps" Encoding:"NP 0x0F 0x58 /r"/"RM" + // Pos:28 Instruction:"ADDPS Vps,Wps" Encoding:"NP 0x0F 0x58 /r"/"RM" { - ND_INS_ADDPS, ND_CAT_SSE, ND_SET_SSE, 8, + ND_INS_ADDPS, ND_CAT_SSE, ND_SET_SSE, 10, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -471,9 +503,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:27 Instruction:"ADDSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x58 /r"/"RM" + // Pos:29 Instruction:"ADDSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x58 /r"/"RM" { - ND_INS_ADDSD, ND_CAT_SSE, ND_SET_SSE2, 9, + ND_INS_ADDSD, ND_CAT_SSE, ND_SET_SSE2, 11, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -487,9 +519,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:28 Instruction:"ADDSS Vss,Wss" Encoding:"0xF3 0x0F 0x58 /r"/"RM" + // Pos:30 Instruction:"ADDSS Vss,Wss" Encoding:"0xF3 0x0F 0x58 /r"/"RM" { - ND_INS_ADDSS, ND_CAT_SSE, ND_SET_SSE, 10, + ND_INS_ADDSS, ND_CAT_SSE, ND_SET_SSE, 12, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -503,9 +535,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:29 Instruction:"ADDSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0xD0 /r"/"RM" + // Pos:31 Instruction:"ADDSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0xD0 /r"/"RM" { - ND_INS_ADDSUBPD, ND_CAT_SSE, ND_SET_SSE3, 11, + ND_INS_ADDSUBPD, ND_CAT_SSE, ND_SET_SSE3, 13, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -519,9 +551,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:30 Instruction:"ADDSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0xD0 /r"/"RM" + // Pos:32 Instruction:"ADDSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0xD0 /r"/"RM" { - ND_INS_ADDSUBPS, ND_CAT_SSE, ND_SET_SSE3, 12, + ND_INS_ADDSUBPS, ND_CAT_SSE, ND_SET_SSE3, 14, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -535,9 +567,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:31 Instruction:"ADOX Gy,Ey" Encoding:"0xF3 0x0F 0x38 0xF6 /r"/"RM" + // Pos:33 Instruction:"ADOX Gy,Ey" Encoding:"0xF3 0x0F 0x38 0xF6 /r"/"RM" { - ND_INS_ADOX, ND_CAT_ARITH, ND_SET_ADX, 13, + ND_INS_ADOX, ND_CAT_ARITH, ND_SET_ADX, 15, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, @@ -552,9 +584,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:32 Instruction:"AESDEC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDE /r"/"RM" + // Pos:34 Instruction:"AESDEC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDE /r"/"RM" { - ND_INS_AESDEC, ND_CAT_AES, ND_SET_AES, 14, + ND_INS_AESDEC, ND_CAT_AES, ND_SET_AES, 16, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -568,9 +600,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:33 Instruction:"AESDEC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDD /r:mem"/"RM" + // Pos:35 Instruction:"AESDEC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDD /r:mem"/"RM" { - ND_INS_AESDEC128KL, ND_CAT_AESKL, ND_SET_KL, 15, + ND_INS_AESDEC128KL, ND_CAT_AESKL, ND_SET_KL, 17, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, @@ -585,9 +617,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:34 Instruction:"AESDEC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDF /r:mem"/"RM" + // Pos:36 Instruction:"AESDEC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDF /r:mem"/"RM" { - ND_INS_AESDEC256KL, ND_CAT_AESKL, ND_SET_KL, 16, + ND_INS_AESDEC256KL, ND_CAT_AESKL, ND_SET_KL, 18, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, @@ -602,9 +634,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:35 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM" + // Pos:37 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM" { - ND_INS_AESDECLAST, ND_CAT_AES, ND_SET_AES, 17, + ND_INS_AESDECLAST, ND_CAT_AES, ND_SET_AES, 19, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -618,9 +650,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:36 Instruction:"AESDECWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /1:mem"/"M" + // Pos:38 Instruction:"AESDECWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /1:mem"/"M" { - ND_INS_AESDECWIDE128KL, ND_CAT_WIDE_KL, ND_SET_KL, 18, + ND_INS_AESDECWIDE128KL, ND_CAT_WIDE_KL, ND_SET_KL, 20, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, @@ -635,9 +667,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:37 Instruction:"AESDECWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /3:mem"/"M" + // Pos:39 Instruction:"AESDECWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /3:mem"/"M" { - ND_INS_AESDECWIDE256KL, ND_CAT_WIDE_KL, ND_SET_KL, 19, + ND_INS_AESDECWIDE256KL, ND_CAT_WIDE_KL, ND_SET_KL, 21, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, @@ -652,9 +684,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:38 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM" + // Pos:40 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM" { - ND_INS_AESENC, ND_CAT_AES, ND_SET_AES, 20, + ND_INS_AESENC, ND_CAT_AES, ND_SET_AES, 22, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -668,9 +700,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:39 Instruction:"AESENC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDC /r:mem"/"RM" + // Pos:41 Instruction:"AESENC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDC /r:mem"/"RM" { - ND_INS_AESENC128KL, ND_CAT_AESKL, ND_SET_KL, 21, + ND_INS_AESENC128KL, ND_CAT_AESKL, ND_SET_KL, 23, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, @@ -685,9 +717,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:40 Instruction:"AESENC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDE /r:mem"/"RM" + // Pos:42 Instruction:"AESENC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDE /r:mem"/"RM" { - ND_INS_AESENC256KL, ND_CAT_AESKL, ND_SET_KL, 22, + ND_INS_AESENC256KL, ND_CAT_AESKL, ND_SET_KL, 24, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, @@ -702,9 +734,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:41 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM" + // Pos:43 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM" { - ND_INS_AESENCLAST, ND_CAT_AES, ND_SET_AES, 23, + ND_INS_AESENCLAST, ND_CAT_AES, ND_SET_AES, 25, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -718,9 +750,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:42 Instruction:"AESENCWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /0:mem"/"M" + // Pos:44 Instruction:"AESENCWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /0:mem"/"M" { - ND_INS_AESENCWIDE128KL, ND_CAT_WIDE_KL, ND_SET_KL, 24, + ND_INS_AESENCWIDE128KL, ND_CAT_WIDE_KL, ND_SET_KL, 26, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, @@ -735,9 +767,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:43 Instruction:"AESENCWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /2:mem"/"M" + // Pos:45 Instruction:"AESENCWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /2:mem"/"M" { - ND_INS_AESENCWIDE256KL, ND_CAT_WIDE_KL, ND_SET_KL, 25, + ND_INS_AESENCWIDE256KL, ND_CAT_WIDE_KL, ND_SET_KL, 27, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, @@ -752,9 +784,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:44 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM" + // Pos:46 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM" { - ND_INS_AESIMC, ND_CAT_AES, ND_SET_AES, 26, + ND_INS_AESIMC, ND_CAT_AES, ND_SET_AES, 28, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -768,9 +800,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:45 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI" + // Pos:47 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI" { - ND_INS_AESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 27, + ND_INS_AESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 29, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -785,9 +817,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:46 Instruction:"ALTINST" Encoding:"0x0F 0x3F"/"" + // Pos:48 Instruction:"ALTINST" Encoding:"0x0F 0x3F"/"" { - ND_INS_ALTINST, ND_CAT_SYSTEM, ND_SET_CYRIX, 28, + ND_INS_ALTINST, ND_CAT_SYSTEM, ND_SET_CYRIX, 30, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -800,9 +832,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:47 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR" + // Pos:49 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR" { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -817,9 +849,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:48 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR" + // Pos:50 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR" { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -834,9 +866,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:49 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM" + // Pos:51 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM" { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -851,9 +883,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:50 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM" + // Pos:52 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM" { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -868,9 +900,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:51 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I" + // Pos:53 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I" { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -885,9 +917,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:52 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I" + // Pos:54 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I" { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -902,9 +934,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:53 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI" + // Pos:55 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI" { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -919,9 +951,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:54 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI" + // Pos:56 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI" { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -936,9 +968,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:55 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI" + // Pos:57 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI" { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -953,9 +985,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:56 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI" + // Pos:58 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI" { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -970,9 +1002,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:57 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM" + // Pos:59 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM" { - ND_INS_ANDN, ND_CAT_BMI1, ND_SET_BMI1, 30, + ND_INS_ANDN, ND_CAT_BMI1, ND_SET_BMI1, 32, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, @@ -988,9 +1020,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:58 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM" + // Pos:60 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM" { - ND_INS_ANDNPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 31, + ND_INS_ANDNPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 33, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -1004,9 +1036,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:59 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM" + // Pos:61 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM" { - ND_INS_ANDNPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 32, + ND_INS_ANDNPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 34, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -1020,9 +1052,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:60 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM" + // Pos:62 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM" { - ND_INS_ANDPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 33, + ND_INS_ANDPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 35, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -1036,9 +1068,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:61 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM" + // Pos:63 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM" { - ND_INS_ANDPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 34, + ND_INS_ANDPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 36, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -1052,9 +1084,25 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:62 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR" + // Pos:64 Instruction:"AOR My,Gy" Encoding:"0xF2 0x0F 0x38 0xFC /r:mem"/"MR" + { + ND_INS_AOR, ND_CAT_RAOINT, ND_SET_RAOINT, 37, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RAOINT, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:65 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR" { - ND_INS_ARPL, ND_CAT_SYSTEM, ND_SET_I286PROT, 35, + ND_INS_ARPL, ND_CAT_SYSTEM, ND_SET_I286PROT, 38, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -1069,9 +1117,25 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:63 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV" + // Pos:66 Instruction:"AXOR My,Gy" Encoding:"0xF3 0x0F 0x38 0xFC /r:mem"/"MR" { - ND_INS_BEXTR, ND_CAT_BMI1, ND_SET_BMI1, 36, + ND_INS_AXOR, ND_CAT_RAOINT, ND_SET_RAOINT, 39, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RAOINT, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:67 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV" + { + ND_INS_BEXTR, ND_CAT_BMI1, ND_SET_BMI1, 40, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, @@ -1087,9 +1151,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:64 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI" + // Pos:68 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI" { - ND_INS_BEXTR, ND_CAT_BITBYTE, ND_SET_TBM, 36, + ND_INS_BEXTR, ND_CAT_BITBYTE, ND_SET_TBM, 40, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -1104,9 +1168,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:65 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM" + // Pos:69 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM" { - ND_INS_BLCFILL, ND_CAT_BITBYTE, ND_SET_TBM, 37, + ND_INS_BLCFILL, ND_CAT_BITBYTE, ND_SET_TBM, 41, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -1120,9 +1184,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:66 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM" + // Pos:70 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM" { - ND_INS_BLCI, ND_CAT_BITBYTE, ND_SET_TBM, 38, + ND_INS_BLCI, ND_CAT_BITBYTE, ND_SET_TBM, 42, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -1136,9 +1200,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:67 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM" + // Pos:71 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM" { - ND_INS_BLCIC, ND_CAT_BITBYTE, ND_SET_TBM, 39, + ND_INS_BLCIC, ND_CAT_BITBYTE, ND_SET_TBM, 43, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -1152,9 +1216,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:68 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM" + // Pos:72 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM" { - ND_INS_BLCMSK, ND_CAT_BITBYTE, ND_SET_TBM, 40, + ND_INS_BLCMSK, ND_CAT_BITBYTE, ND_SET_TBM, 44, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -1168,9 +1232,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:69 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM" + // Pos:73 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM" { - ND_INS_BLCS, ND_CAT_BITBYTE, ND_SET_TBM, 41, + ND_INS_BLCS, ND_CAT_BITBYTE, ND_SET_TBM, 45, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -1184,9 +1248,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:70 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI" + // Pos:74 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI" { - ND_INS_BLENDPD, ND_CAT_SSE, ND_SET_SSE4, 42, + ND_INS_BLENDPD, ND_CAT_SSE, ND_SET_SSE4, 46, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -1201,9 +1265,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:71 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI" + // Pos:75 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI" { - ND_INS_BLENDPS, ND_CAT_SSE, ND_SET_SSE4, 43, + ND_INS_BLENDPS, ND_CAT_SSE, ND_SET_SSE4, 47, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -1218,9 +1282,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:72 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM" + // Pos:76 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM" { - ND_INS_BLENDVPD, ND_CAT_SSE, ND_SET_SSE4, 44, + ND_INS_BLENDVPD, ND_CAT_SSE, ND_SET_SSE4, 48, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -1235,9 +1299,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:73 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM" + // Pos:77 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM" { - ND_INS_BLENDVPS, ND_CAT_SSE, ND_SET_SSE4, 45, + ND_INS_BLENDVPS, ND_CAT_SSE, ND_SET_SSE4, 49, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -1252,9 +1316,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:74 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM" + // Pos:78 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM" { - ND_INS_BLSFILL, ND_CAT_BITBYTE, ND_SET_TBM, 46, + ND_INS_BLSFILL, ND_CAT_BITBYTE, ND_SET_TBM, 50, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -1268,9 +1332,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:75 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM" + // Pos:79 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM" { - ND_INS_BLSI, ND_CAT_BMI1, ND_SET_BMI1, 47, + ND_INS_BLSI, ND_CAT_BMI1, ND_SET_BMI1, 51, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, @@ -1285,9 +1349,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:76 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM" + // Pos:80 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM" { - ND_INS_BLSIC, ND_CAT_BITBYTE, ND_SET_TBM, 48, + ND_INS_BLSIC, ND_CAT_BITBYTE, ND_SET_TBM, 52, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -1301,9 +1365,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:77 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM" + // Pos:81 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM" { - ND_INS_BLSMSK, ND_CAT_BMI1, ND_SET_BMI1, 49, + ND_INS_BLSMSK, ND_CAT_BMI1, ND_SET_BMI1, 53, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, @@ -1318,9 +1382,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:78 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM" + // Pos:82 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM" { - ND_INS_BLSR, ND_CAT_BMI1, ND_SET_BMI1, 50, + ND_INS_BLSR, ND_CAT_BMI1, ND_SET_BMI1, 54, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, @@ -1335,9 +1399,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:79 Instruction:"BNDCL rBl,Ey" Encoding:"mpx 0xF3 0x0F 0x1A /r"/"RM" + // Pos:83 Instruction:"BNDCL rBl,Ey" Encoding:"mpx 0xF3 0x0F 0x1A /r"/"RM" { - ND_INS_BNDCL, ND_CAT_MPX, ND_SET_MPX, 51, + ND_INS_BNDCL, ND_CAT_MPX, ND_SET_MPX, 55, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, @@ -1351,9 +1415,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:80 Instruction:"BNDCN rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1B /r"/"RM" + // Pos:84 Instruction:"BNDCN rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1B /r"/"RM" { - ND_INS_BNDCN, ND_CAT_MPX, ND_SET_MPX, 52, + ND_INS_BNDCN, ND_CAT_MPX, ND_SET_MPX, 56, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, @@ -1367,9 +1431,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:81 Instruction:"BNDCU rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1A /r"/"RM" + // Pos:85 Instruction:"BNDCU rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1A /r"/"RM" { - ND_INS_BNDCU, ND_CAT_MPX, ND_SET_MPX, 53, + ND_INS_BNDCU, ND_CAT_MPX, ND_SET_MPX, 57, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, @@ -1383,9 +1447,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:82 Instruction:"BNDLDX rBl,Mmib" Encoding:"mpx 0x0F 0x1A /r:mem mib"/"RM" + // Pos:86 Instruction:"BNDLDX rBl,Mmib" Encoding:"mpx 0x0F 0x1A /r:mem mib"/"RM" { - ND_INS_BNDLDX, ND_CAT_MPX, ND_SET_MPX, 54, + ND_INS_BNDLDX, ND_CAT_MPX, ND_SET_MPX, 58, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, @@ -1399,9 +1463,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:83 Instruction:"BNDMK rBl,My" Encoding:"mpx 0xF3 0x0F 0x1B /r:mem"/"RM" + // Pos:87 Instruction:"BNDMK rBl,My" Encoding:"mpx 0xF3 0x0F 0x1B /r:mem"/"RM" { - ND_INS_BNDMK, ND_CAT_MPX, ND_SET_MPX, 55, + ND_INS_BNDMK, ND_CAT_MPX, ND_SET_MPX, 59, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, @@ -1415,9 +1479,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:84 Instruction:"BNDMOV rBl,mBl" Encoding:"mpx 0x66 0x0F 0x1A /r"/"RM" + // Pos:88 Instruction:"BNDMOV rBl,mBl" Encoding:"mpx 0x66 0x0F 0x1A /r"/"RM" { - ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 56, + ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 60, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, @@ -1431,9 +1495,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:85 Instruction:"BNDMOV mBl,rBl" Encoding:"mpx 0x66 0x0F 0x1B /r"/"MR" + // Pos:89 Instruction:"BNDMOV mBl,rBl" Encoding:"mpx 0x66 0x0F 0x1B /r"/"MR" { - ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 56, + ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 60, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, @@ -1447,9 +1511,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:86 Instruction:"BNDSTX Mmib,rBl" Encoding:"mpx 0x0F 0x1B /r:mem mib"/"MR" + // Pos:90 Instruction:"BNDSTX Mmib,rBl" Encoding:"mpx 0x0F 0x1B /r:mem mib"/"MR" { - ND_INS_BNDSTX, ND_CAT_MPX, ND_SET_MPX, 57, + ND_INS_BNDSTX, ND_CAT_MPX, ND_SET_MPX, 61, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, @@ -1463,9 +1527,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:87 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM" + // Pos:91 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM" { - ND_INS_BOUND, ND_CAT_INTERRUPT, ND_SET_I186, 58, + ND_INS_BOUND, ND_CAT_INTERRUPT, ND_SET_I186, 62, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -1479,9 +1543,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:88 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM" + // Pos:92 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM" { - ND_INS_BSF, ND_CAT_I386, ND_SET_I386, 59, + ND_INS_BSF, ND_CAT_I386, ND_SET_I386, 63, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -1496,9 +1560,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:89 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM" + // Pos:93 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM" { - ND_INS_BSR, ND_CAT_BITBYTE, ND_SET_I386, 60, + ND_INS_BSR, ND_CAT_BITBYTE, ND_SET_I386, 64, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -1513,9 +1577,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:90 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O" + // Pos:94 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O" { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1528,9 +1592,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:91 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O" + // Pos:95 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O" { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1543,9 +1607,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:92 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O" + // Pos:96 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O" { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1558,9 +1622,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:93 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O" + // Pos:97 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O" { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1573,9 +1637,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:94 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O" + // Pos:98 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O" { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1588,9 +1652,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:95 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O" + // Pos:99 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O" { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1603,9 +1667,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:96 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O" + // Pos:100 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O" { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1618,9 +1682,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:97 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O" + // Pos:101 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O" { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1633,9 +1697,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:98 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR" + // Pos:102 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR" { - ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 62, + ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 66, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, @@ -1650,9 +1714,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:99 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI" + // Pos:103 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI" { - ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 62, + ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 66, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -1667,9 +1731,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:100 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI" + // Pos:104 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI" { - ND_INS_BTC, ND_CAT_BITBYTE, ND_SET_I386, 63, + ND_INS_BTC, ND_CAT_BITBYTE, ND_SET_I386, 67, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -1684,9 +1748,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:101 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR" + // Pos:105 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR" { - ND_INS_BTC, ND_CAT_I386, ND_SET_I386, 63, + ND_INS_BTC, ND_CAT_I386, ND_SET_I386, 67, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, @@ -1701,9 +1765,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:102 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR" + // Pos:106 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR" { - ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 64, + ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 68, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, @@ -1718,9 +1782,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:103 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI" + // Pos:107 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI" { - ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 64, + ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 68, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -1735,9 +1799,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:104 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR" + // Pos:108 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR" { - ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 65, + ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 69, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, @@ -1752,9 +1816,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:105 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI" + // Pos:109 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI" { - ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 65, + ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 69, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -1769,9 +1833,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:106 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV" + // Pos:110 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV" { - ND_INS_BZHI, ND_CAT_BMI2, ND_SET_BMI2, 66, + ND_INS_BZHI, ND_CAT_BMI2, ND_SET_BMI2, 70, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -1787,9 +1851,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:107 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D" + // Pos:111 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D" { - ND_INS_CALLNR, ND_CAT_CALL, ND_SET_I86, 67, + ND_INS_CALLNR, ND_CAT_CALL, ND_SET_I86, 71, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -1805,9 +1869,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:108 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M" + // Pos:112 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M" { - ND_INS_CALLNI, ND_CAT_CALL, ND_SET_I86, 67, + ND_INS_CALLNI, ND_CAT_CALL, ND_SET_I86, 71, ND_PREF_BND|ND_PREF_DNT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, @@ -1823,9 +1887,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:109 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D" + // Pos:113 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D" { - ND_INS_CALLFD, ND_CAT_CALL, ND_SET_I86, 68, + ND_INS_CALLFD, ND_CAT_CALL, ND_SET_I86, 72, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -1842,9 +1906,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:110 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M" + // Pos:114 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M" { - ND_INS_CALLFI, ND_CAT_CALL, ND_SET_I86, 68, + ND_INS_CALLFI, ND_CAT_CALL, ND_SET_I86, 72, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, @@ -1861,9 +1925,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:111 Instruction:"CBW" Encoding:"ds16 0x98"/"" + // Pos:115 Instruction:"CBW" Encoding:"ds16 0x98"/"" { - ND_INS_CBW, ND_CAT_CONVERT, ND_SET_I386, 69, + ND_INS_CBW, ND_CAT_CONVERT, ND_SET_I386, 73, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1877,9 +1941,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:112 Instruction:"CDQ" Encoding:"ds32 0x99"/"" + // Pos:116 Instruction:"CDQ" Encoding:"ds32 0x99"/"" { - ND_INS_CDQ, ND_CAT_CONVERT, ND_SET_I386, 70, + ND_INS_CDQ, ND_CAT_CONVERT, ND_SET_I386, 74, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1893,9 +1957,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:113 Instruction:"CDQE" Encoding:"ds64 0x98"/"" + // Pos:117 Instruction:"CDQE" Encoding:"ds64 0x98"/"" { - ND_INS_CDQE, ND_CAT_CONVERT, ND_SET_I386, 71, + ND_INS_CDQE, ND_CAT_CONVERT, ND_SET_I386, 75, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1909,9 +1973,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:114 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/"" + // Pos:118 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/"" { - ND_INS_CLAC, ND_CAT_SMAP, ND_SET_SMAP, 72, + ND_INS_CLAC, ND_CAT_SMAP, ND_SET_SMAP, 76, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, @@ -1924,9 +1988,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:115 Instruction:"CLC" Encoding:"0xF8"/"" + // Pos:119 Instruction:"CLC" Encoding:"0xF8"/"" { - ND_INS_CLC, ND_CAT_FLAGOP, ND_SET_I86, 73, + ND_INS_CLC, ND_CAT_FLAGOP, ND_SET_I86, 77, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1939,9 +2003,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:116 Instruction:"CLD" Encoding:"0xFC"/"" + // Pos:120 Instruction:"CLD" Encoding:"0xFC"/"" { - ND_INS_CLD, ND_CAT_FLAGOP, ND_SET_I86, 74, + ND_INS_CLD, ND_CAT_FLAGOP, ND_SET_I86, 78, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -1954,9 +2018,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:117 Instruction:"CLDEMOTE Mb" Encoding:"cldm NP 0x0F 0x1C /0:mem"/"M" + // Pos:121 Instruction:"CLDEMOTE Mb" Encoding:"cldm NP 0x0F 0x1C /0:mem"/"M" { - ND_INS_CLDEMOTE, ND_CAT_CLDEMOTE, ND_SET_CLDEMOTE, 75, + ND_INS_CLDEMOTE, ND_CAT_CLDEMOTE, ND_SET_CLDEMOTE, 79, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLDEMOTE, @@ -1969,9 +2033,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:118 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M" + // Pos:122 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M" { - ND_INS_CLEVICT0, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 76, + ND_INS_CLEVICT0, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 80, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -1984,9 +2048,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:119 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M" + // Pos:123 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M" { - ND_INS_CLEVICT1, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 77, + ND_INS_CLEVICT1, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 81, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -1999,9 +2063,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:120 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M" + // Pos:124 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M" { - ND_INS_CLFLUSH, ND_CAT_MISC, ND_SET_CLFSH, 78, + ND_INS_CLFLUSH, ND_CAT_MISC, ND_SET_CLFSH, 82, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSH, @@ -2014,9 +2078,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:121 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M" + // Pos:125 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M" { - ND_INS_CLFLUSHOPT, ND_CAT_MISC, ND_SET_CLFSHOPT, 79, + ND_INS_CLFLUSHOPT, ND_CAT_MISC, ND_SET_CLFSHOPT, 83, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSHOPT, @@ -2029,9 +2093,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:122 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/"" + // Pos:126 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/"" { - ND_INS_CLGI, ND_CAT_SYSTEM, ND_SET_SVM, 80, + ND_INS_CLGI, ND_CAT_SYSTEM, ND_SET_SVM, 84, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -2044,9 +2108,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:123 Instruction:"CLI" Encoding:"0xFA"/"" + // Pos:127 Instruction:"CLI" Encoding:"0xFA"/"" { - ND_INS_CLI, ND_CAT_FLAGOP, ND_SET_I86, 81, + ND_INS_CLI, ND_CAT_FLAGOP, ND_SET_I86, 85, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2059,9 +2123,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:124 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M" + // Pos:128 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M" { - ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET_SS, 82, + ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET_SS, 86, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -2075,9 +2139,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:125 Instruction:"CLTS" Encoding:"0x0F 0x06"/"" + // Pos:129 Instruction:"CLTS" Encoding:"0x0F 0x06"/"" { - ND_INS_CLTS, ND_CAT_SYSTEM, ND_SET_I286REAL, 83, + ND_INS_CLTS, ND_CAT_SYSTEM, ND_SET_I286REAL, 87, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2090,9 +2154,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:126 Instruction:"CLUI" Encoding:"0xF3 0x0F 0x01 /0xEE"/"" + // Pos:130 Instruction:"CLUI" Encoding:"0xF3 0x0F 0x01 /0xEE"/"" { - ND_INS_CLUI, ND_CAT_UINTR, ND_SET_UINTR, 84, + ND_INS_CLUI, ND_CAT_UINTR, ND_SET_UINTR, 88, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, @@ -2105,9 +2169,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:127 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M" + // Pos:131 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M" { - ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 85, + ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 89, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLWB, @@ -2120,9 +2184,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:128 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/"" + // Pos:132 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/"" { - ND_INS_CLZERO, ND_CAT_MISC, ND_SET_CLZERO, 86, + ND_INS_CLZERO, ND_CAT_MISC, ND_SET_CLZERO, 90, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2135,9 +2199,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:129 Instruction:"CMC" Encoding:"0xF5"/"" + // Pos:133 Instruction:"CMC" Encoding:"0xF5"/"" { - ND_INS_CMC, ND_CAT_FLAGOP, ND_SET_I86, 87, + ND_INS_CMC, ND_CAT_FLAGOP, ND_SET_I86, 91, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2150,9 +2214,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:130 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM" + // Pos:134 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 88, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 92, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2167,9 +2231,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:131 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM" + // Pos:135 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 89, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 93, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2184,9 +2248,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:132 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM" + // Pos:136 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 90, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 94, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2201,9 +2265,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:133 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM" + // Pos:137 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 91, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 95, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2218,9 +2282,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:134 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM" + // Pos:138 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 92, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 96, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2235,9 +2299,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:135 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM" + // Pos:139 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 93, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 97, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2252,9 +2316,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:136 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM" + // Pos:140 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 94, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 98, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2269,9 +2333,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:137 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM" + // Pos:141 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 95, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 99, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2286,9 +2350,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:138 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM" + // Pos:142 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 96, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 100, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2303,9 +2367,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:139 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM" + // Pos:143 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 97, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 101, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2320,9 +2384,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:140 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM" + // Pos:144 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 98, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 102, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2337,9 +2401,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:141 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM" + // Pos:145 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 99, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 103, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2354,9 +2418,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:142 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM" + // Pos:146 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 100, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 104, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2371,9 +2435,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:143 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM" + // Pos:147 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 101, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 105, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2388,9 +2452,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:144 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM" + // Pos:148 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 102, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 106, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2405,9 +2469,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:145 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM" + // Pos:149 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 103, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 107, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2422,9 +2486,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:146 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR" + // Pos:150 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2439,9 +2503,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:147 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR" + // Pos:151 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2456,9 +2520,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:148 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM" + // Pos:152 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2473,9 +2537,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:149 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM" + // Pos:153 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2490,9 +2554,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:150 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I" + // Pos:154 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2507,9 +2571,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:151 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I" + // Pos:155 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2524,9 +2588,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:152 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI" + // Pos:156 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2541,9 +2605,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:153 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI" + // Pos:157 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2558,9 +2622,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:154 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI" + // Pos:158 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -2575,9 +2639,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:155 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI" + // Pos:159 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2592,9 +2656,243 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:156 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI" + // Pos:160 Instruction:"CMPBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE6 /r:mem"/"MRV" + { + ND_INS_CMPBEXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 109, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:161 Instruction:"CMPCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE2 /r:mem"/"MRV" { - ND_INS_CMPPD, ND_CAT_SSE, ND_SET_SSE2, 105, + ND_INS_CMPCXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 110, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:162 Instruction:"CMPLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEE /r:mem"/"MRV" + { + ND_INS_CMPLEXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 111, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:163 Instruction:"CMPLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEC /r:mem"/"MRV" + { + ND_INS_CMPLXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 112, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:164 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE7 /r:mem"/"MRV" + { + ND_INS_CMPNBEXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 113, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:165 Instruction:"CMPNCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE3 /r:mem"/"MRV" + { + ND_INS_CMPNCXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 114, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:166 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEF /r:mem"/"MRV" + { + ND_INS_CMPNLEXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 115, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:167 Instruction:"CMPNLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xED /r:mem"/"MRV" + { + ND_INS_CMPNLXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 116, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:168 Instruction:"CMPNOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE1 /r:mem"/"MRV" + { + ND_INS_CMPNOXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 117, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:169 Instruction:"CMPNPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEB /r:mem"/"MRV" + { + ND_INS_CMPNPXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 118, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:170 Instruction:"CMPNSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE9 /r:mem"/"MRV" + { + ND_INS_CMPNSXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 119, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:171 Instruction:"CMPNZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE5 /r:mem"/"MRV" + { + ND_INS_CMPNZXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 120, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:172 Instruction:"CMPOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE0 /r:mem"/"MRV" + { + ND_INS_CMPOXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 121, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:173 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI" + { + ND_INS_CMPPD, ND_CAT_SSE, ND_SET_SSE2, 122, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -2609,9 +2907,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:157 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI" + // Pos:174 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI" { - ND_INS_CMPPS, ND_CAT_SSE, ND_SET_SSE, 106, + ND_INS_CMPPS, ND_CAT_SSE, ND_SET_SSE, 123, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -2626,9 +2924,27 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:158 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/"" + // Pos:175 Instruction:"CMPPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEA /r:mem"/"MRV" + { + ND_INS_CMPPXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 124, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:176 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 107, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 125, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2645,9 +2961,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:159 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/"" + // Pos:177 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 107, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 125, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2665,9 +2981,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:160 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI" + // Pos:178 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI" { - ND_INS_CMPSD, ND_CAT_SSE, ND_SET_SSE2, 108, + ND_INS_CMPSD, ND_CAT_SSE, ND_SET_SSE2, 126, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -2682,9 +2998,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:161 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/"" + // Pos:179 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 108, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 126, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2701,9 +3017,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:162 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/"" + // Pos:180 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 108, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 126, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2721,9 +3037,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:163 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/"" + // Pos:181 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 109, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 127, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2740,9 +3056,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:164 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/"" + // Pos:182 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 109, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 127, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2760,9 +3076,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:165 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI" + // Pos:183 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI" { - ND_INS_CMPSS, ND_CAT_SSE, ND_SET_SSE, 110, + ND_INS_CMPSS, ND_CAT_SSE, ND_SET_SSE, 128, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -2777,9 +3093,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:166 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/"" + // Pos:184 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 111, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 129, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2796,9 +3112,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:167 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/"" + // Pos:185 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 111, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 129, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2816,9 +3132,27 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:168 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR" + // Pos:186 Instruction:"CMPSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE8 /r:mem"/"MRV" { - ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 112, + ND_INS_CMPSXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 130, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:187 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR" + { + ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 131, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2834,9 +3168,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:169 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR" + // Pos:188 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR" { - ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 112, + ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 131, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2852,9 +3186,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:170 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M" + // Pos:189 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M" { - ND_INS_CMPXCHG16B, ND_CAT_SEMAPHORE, ND_SET_CMPXCHG16B, 113, + ND_INS_CMPXCHG16B, ND_CAT_SEMAPHORE, ND_SET_CMPXCHG16B, 132, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, @@ -2872,9 +3206,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:171 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M" + // Pos:190 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M" { - ND_INS_CMPXCHG8B, ND_CAT_SEMAPHORE, ND_SET_PENTIUMREAL, 114, + ND_INS_CMPXCHG8B, ND_CAT_SEMAPHORE, ND_SET_PENTIUMREAL, 133, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, @@ -2892,9 +3226,27 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:172 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM" + // Pos:191 Instruction:"CMPZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE4 /r:mem"/"MRV" + { + ND_INS_CMPZXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 134, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:192 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM" { - ND_INS_COMISD, ND_CAT_SSE2, ND_SET_SSE2, 115, + ND_INS_COMISD, ND_CAT_SSE2, ND_SET_SSE2, 135, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -2909,9 +3261,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:173 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM" + // Pos:193 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM" { - ND_INS_COMISS, ND_CAT_SSE, ND_SET_SSE, 116, + ND_INS_COMISS, ND_CAT_SSE, ND_SET_SSE, 136, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -2926,9 +3278,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:174 Instruction:"CPUID" Encoding:"0x0F 0xA2"/"" + // Pos:194 Instruction:"CPUID" Encoding:"0x0F 0xA2"/"" { - ND_INS_CPUID, ND_CAT_MISC, ND_SET_I486REAL, 117, + ND_INS_CPUID, ND_CAT_MISC, ND_SET_I486REAL, 137, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -2944,9 +3296,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:175 Instruction:"CPU_READ" Encoding:"0x0F 0x3D"/"" + // Pos:195 Instruction:"CPU_READ" Encoding:"0x0F 0x3D"/"" { - ND_INS_CPU_READ, ND_CAT_SYSTEM, ND_SET_CYRIX, 118, + ND_INS_CPU_READ, ND_CAT_SYSTEM, ND_SET_CYRIX, 138, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2959,9 +3311,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:176 Instruction:"CPU_WRITE" Encoding:"0x0F 0x3C"/"" + // Pos:196 Instruction:"CPU_WRITE" Encoding:"0x0F 0x3C"/"" { - ND_INS_CPU_WRITE, ND_CAT_SYSTEM, ND_SET_CYRIX, 119, + ND_INS_CPU_WRITE, ND_CAT_SYSTEM, ND_SET_CYRIX, 139, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2974,9 +3326,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:177 Instruction:"CQO" Encoding:"ds64 0x99"/"" + // Pos:197 Instruction:"CQO" Encoding:"ds64 0x99"/"" { - ND_INS_CQO, ND_CAT_CONVERT, ND_SET_I386, 120, + ND_INS_CQO, ND_CAT_CONVERT, ND_SET_I386, 140, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2990,9 +3342,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:178 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM" + // Pos:198 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM" { - ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 121, + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 141, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, @@ -3006,9 +3358,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:179 Instruction:"CRC32 Gy,Eb" Encoding:"0x66 0xF2 0x0F 0x38 0xF0 /r"/"RM" + // Pos:199 Instruction:"CRC32 Gy,Eb" Encoding:"0x66 0xF2 0x0F 0x38 0xF0 /r"/"RM" { - ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 121, + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 141, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, @@ -3022,9 +3374,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:180 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM" + // Pos:200 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM" { - ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 121, + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 141, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, @@ -3038,9 +3390,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:181 Instruction:"CRC32 Gy,Ev" Encoding:"0x66 0xF2 0x0F 0x38 0xF1 /r"/"RM" + // Pos:201 Instruction:"CRC32 Gy,Ev" Encoding:"0x66 0xF2 0x0F 0x38 0xF1 /r"/"RM" { - ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 121, + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 141, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, @@ -3054,9 +3406,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:182 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM" + // Pos:202 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM" { - ND_INS_CVTDQ2PD, ND_CAT_CONVERT, ND_SET_SSE2, 122, + ND_INS_CVTDQ2PD, ND_CAT_CONVERT, ND_SET_SSE2, 142, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3070,9 +3422,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:183 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM" + // Pos:203 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM" { - ND_INS_CVTDQ2PS, ND_CAT_CONVERT, ND_SET_SSE2, 123, + ND_INS_CVTDQ2PS, ND_CAT_CONVERT, ND_SET_SSE2, 143, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3086,9 +3438,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:184 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM" + // Pos:204 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM" { - ND_INS_CVTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 124, + ND_INS_CVTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 144, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3102,9 +3454,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:185 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM" + // Pos:205 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM" { - ND_INS_CVTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 125, + ND_INS_CVTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 145, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3118,9 +3470,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:186 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM" + // Pos:206 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM" { - ND_INS_CVTPD2PS, ND_CAT_CONVERT, ND_SET_SSE2, 126, + ND_INS_CVTPD2PS, ND_CAT_CONVERT, ND_SET_SSE2, 146, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3134,9 +3486,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:187 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM" + // Pos:207 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM" { - ND_INS_CVTPI2PD, ND_CAT_CONVERT, ND_SET_SSE2, 127, + ND_INS_CVTPI2PD, ND_CAT_CONVERT, ND_SET_SSE2, 147, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3150,9 +3502,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:188 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM" + // Pos:208 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM" { - ND_INS_CVTPI2PS, ND_CAT_CONVERT, ND_SET_SSE, 128, + ND_INS_CVTPI2PS, ND_CAT_CONVERT, ND_SET_SSE, 148, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3166,9 +3518,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:189 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM" + // Pos:209 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM" { - ND_INS_CVTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 129, + ND_INS_CVTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 149, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3182,9 +3534,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:190 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM" + // Pos:210 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM" { - ND_INS_CVTPS2PD, ND_CAT_CONVERT, ND_SET_SSE2, 130, + ND_INS_CVTPS2PD, ND_CAT_CONVERT, ND_SET_SSE2, 150, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3198,9 +3550,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:191 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM" + // Pos:211 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM" { - ND_INS_CVTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 131, + ND_INS_CVTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 151, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3214,9 +3566,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:192 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM" + // Pos:212 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM" { - ND_INS_CVTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 132, + ND_INS_CVTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 152, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3230,9 +3582,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:193 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM" + // Pos:213 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM" { - ND_INS_CVTSD2SS, ND_CAT_CONVERT, ND_SET_SSE2, 133, + ND_INS_CVTSD2SS, ND_CAT_CONVERT, ND_SET_SSE2, 153, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3246,9 +3598,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:194 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM" + // Pos:214 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM" { - ND_INS_CVTSI2SD, ND_CAT_CONVERT, ND_SET_SSE2, 134, + ND_INS_CVTSI2SD, ND_CAT_CONVERT, ND_SET_SSE2, 154, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3262,9 +3614,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:195 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM" + // Pos:215 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM" { - ND_INS_CVTSI2SS, ND_CAT_CONVERT, ND_SET_SSE, 135, + ND_INS_CVTSI2SS, ND_CAT_CONVERT, ND_SET_SSE, 155, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3278,9 +3630,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:196 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM" + // Pos:216 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM" { - ND_INS_CVTSS2SD, ND_CAT_CONVERT, ND_SET_SSE2, 136, + ND_INS_CVTSS2SD, ND_CAT_CONVERT, ND_SET_SSE2, 156, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3294,9 +3646,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:197 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM" + // Pos:217 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM" { - ND_INS_CVTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 137, + ND_INS_CVTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 157, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3310,9 +3662,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:198 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM" + // Pos:218 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM" { - ND_INS_CVTTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 138, + ND_INS_CVTTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 158, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3326,9 +3678,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:199 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM" + // Pos:219 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM" { - ND_INS_CVTTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 139, + ND_INS_CVTTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 159, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3342,9 +3694,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:200 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM" + // Pos:220 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM" { - ND_INS_CVTTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 140, + ND_INS_CVTTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 160, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3358,9 +3710,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:201 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM" + // Pos:221 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM" { - ND_INS_CVTTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 141, + ND_INS_CVTTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 161, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3374,9 +3726,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:202 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM" + // Pos:222 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM" { - ND_INS_CVTTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 142, + ND_INS_CVTTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 162, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3390,9 +3742,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:203 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM" + // Pos:223 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM" { - ND_INS_CVTTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 143, + ND_INS_CVTTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 163, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3406,9 +3758,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:204 Instruction:"CWD" Encoding:"ds16 0x99"/"" + // Pos:224 Instruction:"CWD" Encoding:"ds16 0x99"/"" { - ND_INS_CWD, ND_CAT_CONVERT, ND_SET_I386, 144, + ND_INS_CWD, ND_CAT_CONVERT, ND_SET_I386, 164, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -3422,9 +3774,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:205 Instruction:"CWDE" Encoding:"ds32 0x98"/"" + // Pos:225 Instruction:"CWDE" Encoding:"ds32 0x98"/"" { - ND_INS_CWDE, ND_CAT_CONVERT, ND_SET_I386, 145, + ND_INS_CWDE, ND_CAT_CONVERT, ND_SET_I386, 165, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -3438,9 +3790,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:206 Instruction:"DAA" Encoding:"0x27"/"" + // Pos:226 Instruction:"DAA" Encoding:"0x27"/"" { - ND_INS_DAA, ND_CAT_DECIMAL, ND_SET_I86, 146, + ND_INS_DAA, ND_CAT_DECIMAL, ND_SET_I86, 166, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3454,9 +3806,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:207 Instruction:"DAS" Encoding:"0x2F"/"" + // Pos:227 Instruction:"DAS" Encoding:"0x2F"/"" { - ND_INS_DAS, ND_CAT_DECIMAL, ND_SET_I86, 147, + ND_INS_DAS, ND_CAT_DECIMAL, ND_SET_I86, 167, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3470,9 +3822,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:208 Instruction:"DEC Zv" Encoding:"0x48"/"O" + // Pos:228 Instruction:"DEC Zv" Encoding:"0x48"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3486,9 +3838,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:209 Instruction:"DEC Zv" Encoding:"0x49"/"O" + // Pos:229 Instruction:"DEC Zv" Encoding:"0x49"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3502,9 +3854,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:210 Instruction:"DEC Zv" Encoding:"0x4A"/"O" + // Pos:230 Instruction:"DEC Zv" Encoding:"0x4A"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3518,9 +3870,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:211 Instruction:"DEC Zv" Encoding:"0x4B"/"O" + // Pos:231 Instruction:"DEC Zv" Encoding:"0x4B"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3534,9 +3886,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:212 Instruction:"DEC Zv" Encoding:"0x4C"/"O" + // Pos:232 Instruction:"DEC Zv" Encoding:"0x4C"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3550,9 +3902,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:213 Instruction:"DEC Zv" Encoding:"0x4D"/"O" + // Pos:233 Instruction:"DEC Zv" Encoding:"0x4D"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3566,9 +3918,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:214 Instruction:"DEC Zv" Encoding:"0x4E"/"O" + // Pos:234 Instruction:"DEC Zv" Encoding:"0x4E"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3582,9 +3934,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:215 Instruction:"DEC Zv" Encoding:"0x4F"/"O" + // Pos:235 Instruction:"DEC Zv" Encoding:"0x4F"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3598,9 +3950,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:216 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M" + // Pos:236 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -3614,9 +3966,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:217 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M" + // Pos:237 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -3630,9 +3982,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:218 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M" + // Pos:238 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M" { - ND_INS_DELAY, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 149, + ND_INS_DELAY, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 169, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -3645,9 +3997,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:219 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M" + // Pos:239 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M" { - ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 150, + ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 170, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -3664,9 +4016,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:220 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M" + // Pos:240 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M" { - ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 150, + ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 170, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -3682,9 +4034,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:221 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM" + // Pos:241 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM" { - ND_INS_DIVPD, ND_CAT_SSE, ND_SET_SSE2, 151, + ND_INS_DIVPD, ND_CAT_SSE, ND_SET_SSE2, 171, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3698,9 +4050,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:222 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM" + // Pos:242 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM" { - ND_INS_DIVPS, ND_CAT_SSE, ND_SET_SSE, 152, + ND_INS_DIVPS, ND_CAT_SSE, ND_SET_SSE, 172, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3714,9 +4066,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:223 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM" + // Pos:243 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM" { - ND_INS_DIVSD, ND_CAT_SSE, ND_SET_SSE2, 153, + ND_INS_DIVSD, ND_CAT_SSE, ND_SET_SSE2, 173, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3730,9 +4082,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:224 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM" + // Pos:244 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM" { - ND_INS_DIVSS, ND_CAT_SSE, ND_SET_SSE, 154, + ND_INS_DIVSS, ND_CAT_SSE, ND_SET_SSE, 174, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3746,9 +4098,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:225 Instruction:"DMINT" Encoding:"0x0F 0x39"/"" + // Pos:245 Instruction:"DMINT" Encoding:"0x0F 0x39"/"" { - ND_INS_DMINT, ND_CAT_SYSTEM, ND_SET_CYRIX, 155, + ND_INS_DMINT, ND_CAT_SYSTEM, ND_SET_CYRIX, 175, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3761,9 +4113,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:226 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI" + // Pos:246 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI" { - ND_INS_DPPD, ND_CAT_SSE, ND_SET_SSE4, 156, + ND_INS_DPPD, ND_CAT_SSE, ND_SET_SSE4, 176, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -3778,9 +4130,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:227 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI" + // Pos:247 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI" { - ND_INS_DPPS, ND_CAT_SSE, ND_SET_SSE4, 157, + ND_INS_DPPS, ND_CAT_SSE, ND_SET_SSE4, 177, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -3795,9 +4147,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:228 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/"" + // Pos:248 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/"" { - ND_INS_EMMS, ND_CAT_MMX, ND_SET_MMX, 158, + ND_INS_EMMS, ND_CAT_MMX, ND_SET_MMX, 178, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MMX, @@ -3810,9 +4162,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:229 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/"" + // Pos:249 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/"" { - ND_INS_ENCLS, ND_CAT_SGX, ND_SET_SGX, 159, + ND_INS_ENCLS, ND_CAT_SGX, ND_SET_SGX, 179, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, @@ -3828,9 +4180,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:230 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/"" + // Pos:250 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/"" { - ND_INS_ENCLU, ND_CAT_SGX, ND_SET_SGX, 160, + ND_INS_ENCLU, ND_CAT_SGX, ND_SET_SGX, 180, 0, ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, @@ -3846,9 +4198,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:231 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/"" + // Pos:251 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/"" { - ND_INS_ENCLV, ND_CAT_SGX, ND_SET_SGX, 161, + ND_INS_ENCLV, ND_CAT_SGX, ND_SET_SGX, 181, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, @@ -3864,9 +4216,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:232 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFA /r:reg"/"RM" + // Pos:252 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFA /r:reg"/"RM" { - ND_INS_ENCODEKEY128, ND_CAT_AESKL, ND_SET_KL, 162, + ND_INS_ENCODEKEY128, ND_CAT_AESKL, ND_SET_KL, 182, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, @@ -3884,9 +4236,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:233 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFB /r:reg"/"RM" + // Pos:253 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFB /r:reg"/"RM" { - ND_INS_ENCODEKEY256, ND_CAT_AESKL, ND_SET_KL, 163, + ND_INS_ENCODEKEY256, ND_CAT_AESKL, ND_SET_KL, 183, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, @@ -3903,9 +4255,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:234 Instruction:"ENDBR32" Encoding:"cet a0xF3 0x0F 0x1E /0xFB"/"" + // Pos:254 Instruction:"ENDBR32" Encoding:"cet a0xF3 0x0F 0x1E /0xFB"/"" { - ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 164, + ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 184, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, @@ -3918,9 +4270,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:235 Instruction:"ENDBR64" Encoding:"cet a0xF3 0x0F 0x1E /0xFA"/"" + // Pos:255 Instruction:"ENDBR64" Encoding:"cet a0xF3 0x0F 0x1E /0xFA"/"" { - ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 165, + ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 185, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, @@ -3933,9 +4285,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:236 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M" + // Pos:256 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M" { - ND_INS_ENQCMD, ND_CAT_ENQCMD, ND_SET_ENQCMD, 166, + ND_INS_ENQCMD, ND_CAT_ENQCMD, ND_SET_ENQCMD, 186, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, @@ -3950,9 +4302,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:237 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M" + // Pos:257 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M" { - ND_INS_ENQCMDS, ND_CAT_ENQCMD, ND_SET_ENQCMD, 167, + ND_INS_ENQCMDS, ND_CAT_ENQCMD, ND_SET_ENQCMD, 187, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, @@ -3967,9 +4319,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:238 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II" + // Pos:258 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II" { - ND_INS_ENTER, ND_CAT_MISC, ND_SET_I186, 168, + ND_INS_ENTER, ND_CAT_MISC, ND_SET_I186, 188, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -3986,9 +4338,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:239 Instruction:"ERETS" Encoding:"0xF2 0x0F 0x01 /0xCA"/"" + // Pos:259 Instruction:"ERETS" Encoding:"0xF2 0x0F 0x01 /0xCA"/"" { - ND_INS_ERETS, ND_CAT_RET, ND_SET_FRED, 169, + ND_INS_ERETS, ND_CAT_RET, ND_SET_FRED, 189, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_FRED, @@ -4005,9 +4357,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:240 Instruction:"ERETU" Encoding:"0xF3 0x0F 0x01 /0xCA"/"" + // Pos:260 Instruction:"ERETU" Encoding:"0xF3 0x0F 0x01 /0xCA"/"" { - ND_INS_ERETU, ND_CAT_RET, ND_SET_FRED, 170, + ND_INS_ERETU, ND_CAT_RET, ND_SET_FRED, 190, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_FRED, @@ -4028,9 +4380,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:241 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI" + // Pos:261 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI" { - ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 171, + ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 191, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -4045,9 +4397,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:242 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII" + // Pos:262 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII" { - ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 172, + ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 192, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, @@ -4062,9 +4414,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:243 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM" + // Pos:263 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM" { - ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 172, + ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 192, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, @@ -4078,9 +4430,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:244 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/"" + // Pos:264 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/"" { - ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 173, + ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 193, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4093,9 +4445,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:245 Instruction:"FABS" Encoding:"0xD9 /0xE1"/"" + // Pos:265 Instruction:"FABS" Encoding:"0xD9 /0xE1"/"" { - ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 174, + ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 194, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -4108,9 +4460,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:246 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M" + // Pos:266 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M" { - ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 175, + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 195, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4125,9 +4477,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:247 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M" + // Pos:267 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M" { - ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 175, + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 195, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4142,9 +4494,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:248 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M" + // Pos:268 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M" { - ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 175, + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 195, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4159,9 +4511,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:249 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M" + // Pos:269 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M" { - ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 175, + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 195, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4176,9 +4528,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:250 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M" + // Pos:270 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M" { - ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 176, + ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 196, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4193,9 +4545,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:251 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M" + // Pos:271 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M" { - ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 177, + ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 197, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4210,9 +4562,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:252 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M" + // Pos:272 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M" { - ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 178, + ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 198, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4227,9 +4579,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:253 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/"" + // Pos:273 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/"" { - ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 179, + ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 199, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -4242,9 +4594,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:254 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M" + // Pos:274 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M" { - ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 180, + ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 200, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4260,9 +4612,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:255 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M" + // Pos:275 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M" { - ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 181, + ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 201, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4278,9 +4630,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:256 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M" + // Pos:276 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M" { - ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 182, + ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 202, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4296,9 +4648,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:257 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M" + // Pos:277 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M" { - ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 183, + ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 203, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4314,9 +4666,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:258 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M" + // Pos:278 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M" { - ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 184, + ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 204, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4332,9 +4684,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:259 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M" + // Pos:279 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M" { - ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 185, + ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 205, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4350,9 +4702,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:260 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M" + // Pos:280 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M" { - ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 186, + ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 206, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4368,9 +4720,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:261 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M" + // Pos:281 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M" { - ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 187, + ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 207, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4386,9 +4738,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:262 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M" + // Pos:282 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M" { - ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 188, + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 208, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4403,9 +4755,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:263 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M" + // Pos:283 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M" { - ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 188, + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 208, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4420,9 +4772,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:264 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M" + // Pos:284 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M" { - ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 188, + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 208, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4437,9 +4789,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:265 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M" + // Pos:285 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M" { - ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 188, + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 208, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4454,9 +4806,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:266 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M" + // Pos:286 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M" { - ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 189, + ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 209, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4472,9 +4824,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:267 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M" + // Pos:287 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M" { - ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 190, + ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 210, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4490,9 +4842,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:268 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M" + // Pos:288 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M" { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 191, + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4507,9 +4859,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:269 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M" + // Pos:289 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M" { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 191, + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4524,9 +4876,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:270 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M" + // Pos:290 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M" { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 191, + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4541,9 +4893,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:271 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M" + // Pos:291 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M" { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 191, + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4558,9 +4910,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:272 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M" + // Pos:292 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M" { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 191, + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4575,9 +4927,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:273 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/"" + // Pos:293 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/"" { - ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 192, + ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 212, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4590,9 +4942,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:274 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/"" + // Pos:294 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/"" { - ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 193, + ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 213, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, @@ -4605,9 +4957,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:275 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/"" + // Pos:295 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/"" { - ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 194, + ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 214, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -4620,9 +4972,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:276 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M" + // Pos:296 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M" { - ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 215, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4637,9 +4989,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:277 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M" + // Pos:297 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M" { - ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 215, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4654,9 +5006,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:278 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M" + // Pos:298 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M" { - ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 215, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4671,9 +5023,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:279 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M" + // Pos:299 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M" { - ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 215, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4688,9 +5040,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:280 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M" + // Pos:300 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M" { - ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 196, + ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 216, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4705,9 +5057,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:281 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M" + // Pos:301 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M" { - ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 197, + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 217, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4722,9 +5074,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:282 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M" + // Pos:302 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M" { - ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 197, + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 217, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4739,9 +5091,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:283 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M" + // Pos:303 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M" { - ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 197, + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 217, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4756,9 +5108,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:284 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M" + // Pos:304 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M" { - ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 197, + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 217, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4773,9 +5125,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:285 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M" + // Pos:305 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M" { - ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 198, + ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 218, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4790,9 +5142,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:286 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/"" + // Pos:306 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/"" { - ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 199, + ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 219, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_3DNOW, @@ -4805,9 +5157,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:287 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M" + // Pos:307 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M" { - ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 200, + ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 220, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -4821,9 +5173,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:288 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M" + // Pos:308 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M" { - ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 201, + ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 221, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -4837,9 +5189,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:289 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M" + // Pos:309 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M" { - ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 202, + ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 222, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4854,9 +5206,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:290 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M" + // Pos:310 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M" { - ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 202, + ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 222, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4871,9 +5223,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:291 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M" + // Pos:311 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M" { - ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 203, + ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 223, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -4888,9 +5240,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:292 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M" + // Pos:312 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M" { - ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 203, + ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 223, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -4905,9 +5257,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:293 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M" + // Pos:313 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M" { - ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 204, + ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 224, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -4922,9 +5274,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:294 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M" + // Pos:314 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M" { - ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 204, + ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 224, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -4939,9 +5291,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:295 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M" + // Pos:315 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M" { - ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 205, + ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 225, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4956,9 +5308,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:296 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M" + // Pos:316 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M" { - ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 205, + ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 225, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4973,9 +5325,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:297 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M" + // Pos:317 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M" { - ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 206, + ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 226, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4990,9 +5342,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:298 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M" + // Pos:318 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M" { - ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 206, + ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 226, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5007,9 +5359,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:299 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M" + // Pos:319 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M" { - ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 207, + ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 227, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5024,9 +5376,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:300 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M" + // Pos:320 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M" { - ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 207, + ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 227, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5041,9 +5393,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:301 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M" + // Pos:321 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M" { - ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 207, + ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 227, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5058,9 +5410,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:302 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M" + // Pos:322 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M" { - ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 208, + ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 228, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5075,9 +5427,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:303 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M" + // Pos:323 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M" { - ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 208, + ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 228, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5092,9 +5444,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:304 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/"" + // Pos:324 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/"" { - ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 209, + ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 229, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -5107,9 +5459,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:305 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M" + // Pos:325 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M" { - ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 210, + ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 230, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5124,9 +5476,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:306 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M" + // Pos:326 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M" { - ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 210, + ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 230, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5141,9 +5493,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:307 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M" + // Pos:327 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M" { - ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 211, + ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 231, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5158,9 +5510,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:308 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M" + // Pos:328 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M" { - ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 211, + ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 231, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5175,9 +5527,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:309 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M" + // Pos:329 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M" { - ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 211, + ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 231, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5192,9 +5544,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:310 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M" + // Pos:330 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M" { - ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 212, + ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 232, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -5209,9 +5561,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:311 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M" + // Pos:331 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M" { - ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 212, + ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 232, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -5226,9 +5578,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:312 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M" + // Pos:332 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M" { - ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 212, + ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 232, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -5243,9 +5595,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:313 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M" + // Pos:333 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M" { - ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 233, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5260,9 +5612,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:314 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M" + // Pos:334 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M" { - ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 233, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5277,9 +5629,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:315 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M" + // Pos:335 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M" { - ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 214, + ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 234, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5294,9 +5646,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:316 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M" + // Pos:336 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M" { - ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 214, + ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 234, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5311,9 +5663,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:317 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M" + // Pos:337 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M" { - ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 215, + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 235, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5328,9 +5680,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:318 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M" + // Pos:338 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M" { - ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 215, + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 235, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5345,9 +5697,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:319 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M" + // Pos:339 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M" { - ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 215, + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 235, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5362,9 +5714,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:320 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M" + // Pos:340 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M" { - ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 215, + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 235, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5379,9 +5731,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:321 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/"" + // Pos:341 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/"" { - ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 216, + ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 236, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5394,9 +5746,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:322 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M" + // Pos:342 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M" { - ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 217, + ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 237, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5411,9 +5763,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:323 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M" + // Pos:343 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M" { - ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 218, + ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 238, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -5427,9 +5779,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:324 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/"" + // Pos:344 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/"" { - ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 219, + ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 239, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5442,9 +5794,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:325 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/"" + // Pos:345 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/"" { - ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 220, + ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 240, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5457,9 +5809,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:326 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/"" + // Pos:346 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/"" { - ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 221, + ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 241, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5472,9 +5824,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:327 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/"" + // Pos:347 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/"" { - ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 222, + ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 242, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5487,9 +5839,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:328 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/"" + // Pos:348 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/"" { - ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 223, + ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 243, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5502,9 +5854,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:329 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/"" + // Pos:349 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/"" { - ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 224, + ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 244, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5517,9 +5869,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:330 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M" + // Pos:350 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M" { - ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 225, + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 245, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5534,9 +5886,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:331 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M" + // Pos:351 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M" { - ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 225, + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 245, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5551,9 +5903,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:332 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M" + // Pos:352 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M" { - ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 225, + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 245, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5568,9 +5920,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:333 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M" + // Pos:353 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M" { - ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 225, + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 245, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5585,9 +5937,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:334 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M" + // Pos:354 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M" { - ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 226, + ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 246, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5602,9 +5954,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:335 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/"" + // Pos:355 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/"" { - ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 227, + ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 247, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5617,9 +5969,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:336 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/"" + // Pos:356 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/"" { - ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 228, + ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 248, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5632,9 +5984,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:337 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/"" + // Pos:357 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/"" { - ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 229, + ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 249, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, @@ -5649,9 +6001,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:338 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/"" + // Pos:358 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/"" { - ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 230, + ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 250, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5664,9 +6016,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:339 Instruction:"FNOP" Encoding:"0xDB /0xE0"/"" + // Pos:359 Instruction:"FNOP" Encoding:"0xDB /0xE0"/"" { - ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 230, + ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 250, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5679,9 +6031,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:340 Instruction:"FNOP" Encoding:"0xDB /0xE4"/"" + // Pos:360 Instruction:"FNOP" Encoding:"0xDB /0xE4"/"" { - ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 230, + ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 250, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5694,9 +6046,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:341 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M" + // Pos:361 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M" { - ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 231, + ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 251, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, @@ -5712,9 +6064,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:342 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M" + // Pos:362 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M" { - ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 232, + ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 252, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5729,9 +6081,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:343 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M" + // Pos:363 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M" { - ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 233, + ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 253, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5745,9 +6097,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:344 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M" + // Pos:364 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M" { - ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 234, + ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 254, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5761,9 +6113,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:345 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/"" + // Pos:365 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/"" { - ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 234, + ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 254, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5777,9 +6129,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:346 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/"" + // Pos:366 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/"" { - ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 235, + ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 255, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5792,9 +6144,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:347 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/"" + // Pos:367 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/"" { - ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 256, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -5807,9 +6159,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:348 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/"" + // Pos:368 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/"" { - ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 237, + ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 257, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -5822,9 +6174,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:349 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/"" + // Pos:369 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/"" { - ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 238, + ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 258, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, @@ -5837,9 +6189,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:350 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/"" + // Pos:370 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/"" { - ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 239, + ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 259, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5852,9 +6204,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:351 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/"" + // Pos:371 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/"" { - ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 240, + ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 260, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5867,9 +6219,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:352 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M" + // Pos:372 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M" { - ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 241, + ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 261, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -5883,9 +6235,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:353 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/"" + // Pos:373 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/"" { - ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 242, + ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 262, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5898,9 +6250,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:354 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/"" + // Pos:374 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/"" { - ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 243, + ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 263, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, @@ -5913,9 +6265,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:355 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/"" + // Pos:375 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/"" { - ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 244, + ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 264, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, @@ -5928,9 +6280,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:356 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/"" + // Pos:376 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/"" { - ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 245, + ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 265, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5943,9 +6295,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:357 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M" + // Pos:377 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M" { - ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 246, + ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 266, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5960,9 +6312,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:358 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M" + // Pos:378 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M" { - ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 246, + ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 266, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5977,9 +6329,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:359 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M" + // Pos:379 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M" { - ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 246, + ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 266, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5994,9 +6346,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:360 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/"" + // Pos:380 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/"" { - ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 247, + ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 267, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -6009,9 +6361,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:361 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M" + // Pos:381 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M" { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 248, + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6026,9 +6378,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:362 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M" + // Pos:382 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M" { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 248, + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6043,9 +6395,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:363 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M" + // Pos:383 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M" { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 248, + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6060,9 +6412,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:364 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M" + // Pos:384 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M" { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 248, + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6077,9 +6429,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:365 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M" + // Pos:385 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M" { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 248, + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6094,9 +6446,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:366 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M" + // Pos:386 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M" { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 248, + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6111,9 +6463,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:367 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M" + // Pos:387 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M" { - ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 249, + ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 269, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -6128,9 +6480,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:368 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/"" + // Pos:388 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/"" { - ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 250, + ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 270, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -6143,9 +6495,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:369 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M" + // Pos:389 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M" { - ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 251, + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 271, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6160,9 +6512,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:370 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M" + // Pos:390 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M" { - ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 251, + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 271, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6177,9 +6529,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:371 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M" + // Pos:391 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M" { - ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 251, + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 271, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6194,9 +6546,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:372 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M" + // Pos:392 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M" { - ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 251, + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 271, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6211,9 +6563,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:373 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M" + // Pos:393 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M" { - ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 252, + ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 272, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6228,9 +6580,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:374 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M" + // Pos:394 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M" { - ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 253, + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 273, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6245,9 +6597,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:375 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M" + // Pos:395 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M" { - ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 253, + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 273, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6262,9 +6614,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:376 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M" + // Pos:396 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M" { - ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 253, + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 273, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6279,9 +6631,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:377 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M" + // Pos:397 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M" { - ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 253, + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 273, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6296,9 +6648,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:378 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M" + // Pos:398 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M" { - ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 254, + ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 274, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6313,9 +6665,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:379 Instruction:"FTST" Encoding:"0xD9 /0xE4"/"" + // Pos:399 Instruction:"FTST" Encoding:"0xD9 /0xE4"/"" { - ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 255, + ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 275, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -6328,9 +6680,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:380 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M" + // Pos:400 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M" { - ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 256, + ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 276, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -6345,9 +6697,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:381 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M" + // Pos:401 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M" { - ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 257, + ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 277, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -6363,9 +6715,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:382 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M" + // Pos:402 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M" { - ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 258, + ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 278, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -6381,9 +6733,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:383 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M" + // Pos:403 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M" { - ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 259, + ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 279, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -6398,9 +6750,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:384 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/"" + // Pos:404 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/"" { - ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 260, + ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 280, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -6413,9 +6765,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:385 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/"" + // Pos:405 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/"" { - ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 261, + ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 281, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -6428,9 +6780,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:386 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M" + // Pos:406 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M" { - ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 262, + ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 282, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -6445,9 +6797,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:387 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M" + // Pos:407 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M" { - ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 262, + ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 282, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -6462,9 +6814,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:388 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M" + // Pos:408 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M" { - ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 262, + ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 282, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -6479,9 +6831,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:389 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M" + // Pos:409 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M" { - ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 263, + ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 283, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, @@ -6495,9 +6847,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:390 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M" + // Pos:410 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M" { - ND_INS_FXRSTOR64, ND_CAT_SSE, ND_SET_FXSAVE, 264, + ND_INS_FXRSTOR64, ND_CAT_SSE, ND_SET_FXSAVE, 284, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, @@ -6511,9 +6863,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:391 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M" + // Pos:411 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M" { - ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 265, + ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 285, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, @@ -6527,9 +6879,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:392 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M" + // Pos:412 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M" { - ND_INS_FXSAVE64, ND_CAT_SSE, ND_SET_FXSAVE, 266, + ND_INS_FXSAVE64, ND_CAT_SSE, ND_SET_FXSAVE, 286, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, @@ -6543,9 +6895,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:393 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/"" + // Pos:413 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/"" { - ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 267, + ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 287, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6558,9 +6910,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:394 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/"" + // Pos:414 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/"" { - ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 268, + ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 288, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6573,9 +6925,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:395 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/"" + // Pos:415 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/"" { - ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 269, + ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 289, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6588,9 +6940,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:396 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/"" + // Pos:416 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/"" { - ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 270, + ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 290, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SMX, @@ -6604,9 +6956,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:397 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI" + // Pos:417 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI" { - ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 271, + ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 291, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -6621,9 +6973,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:398 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI" + // Pos:418 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI" { - ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 272, + ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 292, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -6638,9 +6990,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:399 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM" + // Pos:419 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM" { - ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 273, + ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 293, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -6654,9 +7006,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:400 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM" + // Pos:420 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM" { - ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 274, + ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 294, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -6670,9 +7022,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:401 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM" + // Pos:421 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM" { - ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 275, + ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 295, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -6686,9 +7038,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:402 Instruction:"HLT" Encoding:"0xF4"/"" + // Pos:422 Instruction:"HLT" Encoding:"0xF4"/"" { - ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 276, + ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 296, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -6701,9 +7053,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:403 Instruction:"HRESET Ib" Encoding:"0xF3 0x0F 0x3A 0xF0 /0xC0 ib"/"I" + // Pos:423 Instruction:"HRESET Ib" Encoding:"0xF3 0x0F 0x3A 0xF0 /0xC0 ib"/"I" { - ND_INS_HRESET, ND_CAT_HRESET, ND_SET_HRESET, 277, + ND_INS_HRESET, ND_CAT_HRESET, ND_SET_HRESET, 297, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_HRESET, @@ -6717,9 +7069,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:404 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM" + // Pos:424 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM" { - ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 278, + ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 298, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -6733,9 +7085,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:405 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM" + // Pos:425 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM" { - ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 279, + ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 299, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -6749,9 +7101,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:406 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M" + // Pos:426 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M" { - ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 280, + ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 300, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6768,9 +7120,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:407 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M" + // Pos:427 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M" { - ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 280, + ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 300, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6786,9 +7138,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:408 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM" + // Pos:428 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM" { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 281, + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6803,9 +7155,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:409 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI" + // Pos:429 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI" { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 281, + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6821,9 +7173,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:410 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI" + // Pos:430 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI" { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 281, + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6839,9 +7191,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:411 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M" + // Pos:431 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M" { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 281, + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6857,9 +7209,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:412 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M" + // Pos:432 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M" { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 281, + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6875,9 +7227,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:413 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I" + // Pos:433 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I" { - ND_INS_IN, ND_CAT_IO, ND_SET_I86, 282, + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -6892,9 +7244,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:414 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I" + // Pos:434 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I" { - ND_INS_IN, ND_CAT_IO, ND_SET_I86, 282, + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -6909,9 +7261,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:415 Instruction:"IN AL,DX" Encoding:"0xEC"/"" + // Pos:435 Instruction:"IN AL,DX" Encoding:"0xEC"/"" { - ND_INS_IN, ND_CAT_IO, ND_SET_I86, 282, + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -6926,9 +7278,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:416 Instruction:"IN eAX,DX" Encoding:"0xED"/"" + // Pos:436 Instruction:"IN eAX,DX" Encoding:"0xED"/"" { - ND_INS_IN, ND_CAT_IO, ND_SET_I86, 282, + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -6943,9 +7295,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:417 Instruction:"INC Zv" Encoding:"0x40"/"O" + // Pos:437 Instruction:"INC Zv" Encoding:"0x40"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -6959,9 +7311,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:418 Instruction:"INC Zv" Encoding:"0x41"/"O" + // Pos:438 Instruction:"INC Zv" Encoding:"0x41"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -6975,9 +7327,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:419 Instruction:"INC Zv" Encoding:"0x42"/"O" + // Pos:439 Instruction:"INC Zv" Encoding:"0x42"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -6991,9 +7343,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:420 Instruction:"INC Zv" Encoding:"0x43"/"O" + // Pos:440 Instruction:"INC Zv" Encoding:"0x43"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -7007,9 +7359,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:421 Instruction:"INC Zv" Encoding:"0x44"/"O" + // Pos:441 Instruction:"INC Zv" Encoding:"0x44"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -7023,9 +7375,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:422 Instruction:"INC Zv" Encoding:"0x45"/"O" + // Pos:442 Instruction:"INC Zv" Encoding:"0x45"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -7039,9 +7391,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:423 Instruction:"INC Zv" Encoding:"0x46"/"O" + // Pos:443 Instruction:"INC Zv" Encoding:"0x46"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -7055,9 +7407,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:424 Instruction:"INC Zv" Encoding:"0x47"/"O" + // Pos:444 Instruction:"INC Zv" Encoding:"0x47"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -7071,9 +7423,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:425 Instruction:"INC Eb" Encoding:"0xFE /0"/"M" + // Pos:445 Instruction:"INC Eb" Encoding:"0xFE /0"/"M" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -7087,9 +7439,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:426 Instruction:"INC Ev" Encoding:"0xFF /0"/"M" + // Pos:446 Instruction:"INC Ev" Encoding:"0xFF /0"/"M" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 283, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -7103,9 +7455,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:427 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M" + // Pos:447 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M" { - ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 284, + ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 304, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -7120,9 +7472,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:428 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M" + // Pos:448 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M" { - ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 285, + ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 305, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -7137,9 +7489,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:429 Instruction:"INSB Yb,DX" Encoding:"0x6C"/"" + // Pos:449 Instruction:"INSB Yb,DX" Encoding:"0x6C"/"" { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 286, + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 306, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7155,9 +7507,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:430 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/"" + // Pos:450 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/"" { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 286, + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 306, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7174,9 +7526,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:431 Instruction:"INSD Yz,DX" Encoding:"0x6D"/"" + // Pos:451 Instruction:"INSD Yz,DX" Encoding:"0x6D"/"" { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 287, + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 307, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7192,9 +7544,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:432 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/"" + // Pos:452 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/"" { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 287, + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 307, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7211,9 +7563,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:433 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI" + // Pos:453 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI" { - ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 288, + ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 308, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -7228,9 +7580,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:434 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI" + // Pos:454 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI" { - ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 288, + ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 308, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -7245,9 +7597,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:435 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII" + // Pos:455 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII" { - ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 289, + ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 309, 0, ND_MOD_ANY, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, @@ -7263,9 +7615,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:436 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM" + // Pos:456 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM" { - ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 289, + ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 309, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, @@ -7279,9 +7631,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:437 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/"" + // Pos:457 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/"" { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 290, + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 310, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7297,9 +7649,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:438 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/"" + // Pos:458 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/"" { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 290, + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 310, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7316,9 +7668,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:439 Instruction:"INT Ib" Encoding:"0xCD ib"/"I" + // Pos:459 Instruction:"INT Ib" Encoding:"0xCD ib"/"I" { - ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 291, + ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 311, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT, 0, @@ -7336,9 +7688,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:440 Instruction:"INT1" Encoding:"0xF1"/"" + // Pos:460 Instruction:"INT1" Encoding:"0xF1"/"" { - ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 292, + ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 312, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7354,9 +7706,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:441 Instruction:"INT3" Encoding:"0xCC"/"" + // Pos:461 Instruction:"INT3" Encoding:"0xCC"/"" { - ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 293, + ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 313, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT, 0, @@ -7373,9 +7725,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:442 Instruction:"INTO" Encoding:"0xCE"/"" + // Pos:462 Instruction:"INTO" Encoding:"0xCE"/"" { - ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 294, + ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 314, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_I64, 0, @@ -7392,9 +7744,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:443 Instruction:"INVD" Encoding:"0x0F 0x08"/"" + // Pos:463 Instruction:"INVD" Encoding:"0x0F 0x08"/"" { - ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 295, + ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 315, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -7407,9 +7759,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:444 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM" + // Pos:464 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM" { - ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 296, + ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 316, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, @@ -7424,9 +7776,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:445 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M" + // Pos:465 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M" { - ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 297, + ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 317, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, @@ -7439,9 +7791,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:446 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/"" + // Pos:466 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/"" { - ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 298, + ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 318, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -7455,9 +7807,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:447 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/"" + // Pos:467 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/"" { - ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 299, + ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 319, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, @@ -7472,9 +7824,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:448 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM" + // Pos:468 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM" { - ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 300, + ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 320, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_INVPCID, @@ -7488,9 +7840,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:449 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM" + // Pos:469 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM" { - ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 301, + ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 321, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, @@ -7505,9 +7857,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:450 Instruction:"IRETD" Encoding:"ds32 0xCF"/"" + // Pos:470 Instruction:"IRETD" Encoding:"ds32 0xCF"/"" { - ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 302, + ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 322, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -7524,9 +7876,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:451 Instruction:"IRETQ" Encoding:"ds64 0xCF"/"" + // Pos:471 Instruction:"IRETQ" Encoding:"ds64 0xCF"/"" { - ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 303, + ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 323, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -7543,9 +7895,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:452 Instruction:"IRETW" Encoding:"ds16 0xCF"/"" + // Pos:472 Instruction:"IRETW" Encoding:"ds16 0xCF"/"" { - ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 304, + ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 324, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -7562,9 +7914,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:453 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D" + // Pos:473 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 325, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7579,9 +7931,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:454 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D" + // Pos:474 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 325, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7596,9 +7948,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:455 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D" + // Pos:475 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 326, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7613,9 +7965,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:456 Instruction:"JC Jb" Encoding:"0x72 cb"/"D" + // Pos:476 Instruction:"JC Jb" Encoding:"0x72 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 326, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7630,9 +7982,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:457 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D" + // Pos:477 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D" { - ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 307, + ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 327, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -7647,9 +7999,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:458 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D" + // Pos:478 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D" { - ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 308, + ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 328, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -7664,9 +8016,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:459 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D" + // Pos:479 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 329, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7681,9 +8033,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:460 Instruction:"JL Jb" Encoding:"0x7C cb"/"D" + // Pos:480 Instruction:"JL Jb" Encoding:"0x7C cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 329, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7698,9 +8050,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:461 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D" + // Pos:481 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 330, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7715,9 +8067,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:462 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D" + // Pos:482 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 330, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7732,9 +8084,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:463 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D" + // Pos:483 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D" { - ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 311, + ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 331, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -7748,9 +8100,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:464 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D" + // Pos:484 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D" { - ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 311, + ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 331, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -7764,9 +8116,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:465 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M" + // Pos:485 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M" { - ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 311, + ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 331, ND_PREF_BND|ND_PREF_DNT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, @@ -7780,9 +8132,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:466 Instruction:"JMPE Ev" Encoding:"NP 0x0F 0x00 /6"/"M" + // Pos:486 Instruction:"JMPE Ev" Encoding:"NP 0x0F 0x00 /6"/"M" { - ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 312, + ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 332, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -7796,9 +8148,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:467 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D" + // Pos:487 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D" { - ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 312, + ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 332, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -7812,9 +8164,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:468 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D" + // Pos:488 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D" { - ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 313, + ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 333, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -7829,9 +8181,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:469 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M" + // Pos:489 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M" { - ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 313, + ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 333, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, @@ -7846,9 +8198,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:470 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D" + // Pos:490 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 314, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 334, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7863,9 +8215,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:471 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D" + // Pos:491 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 314, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 334, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7880,9 +8232,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:472 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D" + // Pos:492 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 315, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 335, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7897,9 +8249,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:473 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D" + // Pos:493 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 315, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 335, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7914,9 +8266,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:474 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D" + // Pos:494 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 316, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 336, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7931,9 +8283,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:475 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D" + // Pos:495 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 316, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 336, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7948,9 +8300,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:476 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D" + // Pos:496 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 317, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 337, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7965,9 +8317,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:477 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D" + // Pos:497 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 317, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 337, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7982,9 +8334,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:478 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D" + // Pos:498 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 318, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 338, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7999,9 +8351,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:479 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D" + // Pos:499 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 318, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 338, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8016,9 +8368,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:480 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D" + // Pos:500 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 319, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 339, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8033,9 +8385,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:481 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D" + // Pos:501 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 319, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 339, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8050,9 +8402,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:482 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D" + // Pos:502 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 320, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 340, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8067,9 +8419,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:483 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D" + // Pos:503 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 320, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 340, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8084,9 +8436,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:484 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D" + // Pos:504 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 321, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 341, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8101,9 +8453,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:485 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D" + // Pos:505 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 321, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 341, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8118,9 +8470,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:486 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D" + // Pos:506 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 322, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 342, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8135,9 +8487,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:487 Instruction:"JO Jb" Encoding:"0x70 cb"/"D" + // Pos:507 Instruction:"JO Jb" Encoding:"0x70 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 322, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 342, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8152,9 +8504,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:488 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D" + // Pos:508 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 323, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 343, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8169,9 +8521,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:489 Instruction:"JP Jb" Encoding:"0x7A cb"/"D" + // Pos:509 Instruction:"JP Jb" Encoding:"0x7A cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 323, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 343, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8186,9 +8538,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:490 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D" + // Pos:510 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D" { - ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 324, + ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 344, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -8203,9 +8555,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:491 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D" + // Pos:511 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 325, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 345, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8220,9 +8572,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:492 Instruction:"JS Jb" Encoding:"0x78 cb"/"D" + // Pos:512 Instruction:"JS Jb" Encoding:"0x78 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 325, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 345, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8237,9 +8589,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:493 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D" + // Pos:513 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 326, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 346, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8254,9 +8606,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:494 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D" + // Pos:514 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 326, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 346, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8271,9 +8623,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:495 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM" + // Pos:515 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM" { - ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 327, + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 347, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8288,9 +8640,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:496 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM" + // Pos:516 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM" { - ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 328, + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 348, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8305,9 +8657,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:497 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM" + // Pos:517 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM" { - ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 329, + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 349, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8322,9 +8674,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:498 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM" + // Pos:518 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM" { - ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 330, + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 350, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8339,9 +8691,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:499 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM" + // Pos:519 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM" { - ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 331, + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 351, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8356,9 +8708,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:500 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM" + // Pos:520 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM" { - ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 332, + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 352, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8373,9 +8725,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:501 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM" + // Pos:521 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM" { - ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 333, + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 353, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8390,9 +8742,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:502 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM" + // Pos:522 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM" { - ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 334, + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 354, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8407,9 +8759,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:503 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM" + // Pos:523 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM" { - ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 335, + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8424,9 +8776,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:504 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM" + // Pos:524 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM" { - ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 336, + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8441,9 +8793,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:505 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM" + // Pos:525 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM" { - ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 337, + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8458,9 +8810,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:506 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM" + // Pos:526 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM" { - ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 338, + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 358, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8475,9 +8827,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:507 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM" + // Pos:527 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM" { - ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 339, + ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 359, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -8491,9 +8843,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:508 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM" + // Pos:528 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM" { - ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 340, + ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 360, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -8507,9 +8859,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:509 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM" + // Pos:529 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 341, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8523,9 +8875,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:510 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM" + // Pos:530 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 341, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8539,9 +8891,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:511 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR" + // Pos:531 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 341, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8555,9 +8907,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:512 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM" + // Pos:532 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 341, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8571,9 +8923,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:513 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM" + // Pos:533 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 341, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8587,9 +8939,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:514 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM" + // Pos:534 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8603,9 +8955,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:515 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM" + // Pos:535 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8619,9 +8971,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:516 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR" + // Pos:536 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8635,9 +8987,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:517 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM" + // Pos:537 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8651,9 +9003,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:518 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM" + // Pos:538 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8667,9 +9019,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:519 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM" + // Pos:539 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 343, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8683,9 +9035,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:520 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM" + // Pos:540 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 343, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8699,9 +9051,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:521 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR" + // Pos:541 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 343, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8715,9 +9067,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:522 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM" + // Pos:542 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 343, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8731,9 +9083,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:523 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM" + // Pos:543 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 343, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8747,9 +9099,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:524 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM" + // Pos:544 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 344, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8763,9 +9115,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:525 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM" + // Pos:545 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 344, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8779,9 +9131,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:526 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR" + // Pos:546 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 344, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8795,9 +9147,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:527 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM" + // Pos:547 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 344, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8811,9 +9163,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:528 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM" + // Pos:548 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 344, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8827,9 +9179,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:529 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM" + // Pos:549 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM" { - ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 345, + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 365, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8843,9 +9195,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:530 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM" + // Pos:550 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM" { - ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 346, + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 366, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8859,9 +9211,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:531 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM" + // Pos:551 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM" { - ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 347, + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 367, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8875,9 +9227,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:532 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM" + // Pos:552 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM" { - ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 348, + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 368, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8891,9 +9243,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:533 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM" + // Pos:553 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM" { - ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 349, + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 369, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8908,9 +9260,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:534 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM" + // Pos:554 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM" { - ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 350, + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 370, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8925,9 +9277,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:535 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM" + // Pos:555 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM" { - ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 351, + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 371, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8942,9 +9294,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:536 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM" + // Pos:556 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM" { - ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 352, + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 372, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8959,9 +9311,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:537 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM" + // Pos:557 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM" { - ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 353, + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8976,9 +9328,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:538 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM" + // Pos:558 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM" { - ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 354, + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8993,9 +9345,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:539 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM" + // Pos:559 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM" { - ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 355, + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 375, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -9010,9 +9362,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:540 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM" + // Pos:560 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM" { - ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 356, + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 376, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -9027,9 +9379,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:541 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI" + // Pos:561 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI" { - ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 357, + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 377, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -9044,9 +9396,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:542 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI" + // Pos:562 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI" { - ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 358, + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 378, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9061,9 +9413,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:543 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI" + // Pos:563 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI" { - ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 359, + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 379, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9078,9 +9430,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:544 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI" + // Pos:564 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI" { - ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 360, + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 380, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -9095,9 +9447,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:545 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI" + // Pos:565 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI" { - ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 381, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -9112,9 +9464,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:546 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI" + // Pos:566 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI" { - ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 362, + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 382, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9129,9 +9481,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:547 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI" + // Pos:567 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI" { - ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 363, + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 383, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9146,9 +9498,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:548 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI" + // Pos:568 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI" { - ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 364, + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 384, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -9163,9 +9515,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:549 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM" + // Pos:569 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM" { - ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 365, + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 385, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -9179,9 +9531,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:550 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM" + // Pos:570 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM" { - ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 366, + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 386, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9195,9 +9547,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:551 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM" + // Pos:571 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM" { - ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 367, + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 387, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9211,9 +9563,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:552 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM" + // Pos:572 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM" { - ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 368, + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 388, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -9227,9 +9579,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:553 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM" + // Pos:573 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM" { - ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 369, + ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 389, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -9244,9 +9596,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:554 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM" + // Pos:574 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM" { - ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 370, + ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 390, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9261,9 +9613,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:555 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM" + // Pos:575 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM" { - ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 371, + ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 391, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9278,9 +9630,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:556 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM" + // Pos:576 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM" { - ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 372, + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 392, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -9295,9 +9647,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:557 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM" + // Pos:577 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM" { - ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 373, + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 393, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9312,9 +9664,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:558 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM" + // Pos:578 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM" { - ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 374, + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 394, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9329,9 +9681,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:559 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM" + // Pos:579 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM" { - ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 375, + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 395, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -9346,9 +9698,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:560 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM" + // Pos:580 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM" { - ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 376, + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 396, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -9363,9 +9715,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:561 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM" + // Pos:581 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM" { - ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 377, + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 397, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9380,9 +9732,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:562 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM" + // Pos:582 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM" { - ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 378, + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 398, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9397,9 +9749,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:563 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM" + // Pos:583 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM" { - ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 379, + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 399, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -9414,9 +9766,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:564 Instruction:"LAHF" Encoding:"0x9F"/"" + // Pos:584 Instruction:"LAHF" Encoding:"0x9F"/"" { - ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 380, + ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 400, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9430,9 +9782,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:565 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM" + // Pos:585 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM" { - ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 381, + ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 401, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9447,9 +9799,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:566 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM" + // Pos:586 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM" { - ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 381, + ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 401, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9464,9 +9816,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:567 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM" + // Pos:587 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM" { - ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 382, + ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 402, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -9480,9 +9832,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:568 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M" + // Pos:588 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M" { - ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 383, + ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 403, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -9496,9 +9848,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:569 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM" + // Pos:589 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM" { - ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 384, + ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 404, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -9513,9 +9865,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:570 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M" + // Pos:590 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M" { - ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 385, + ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 405, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E1, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -9528,9 +9880,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:571 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM" + // Pos:591 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM" { - ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 386, + ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 406, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, @@ -9544,9 +9896,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:572 Instruction:"LEAVE" Encoding:"0xC9"/"" + // Pos:592 Instruction:"LEAVE" Encoding:"0xC9"/"" { - ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 387, + ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 407, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -9562,9 +9914,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:573 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM" + // Pos:593 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM" { - ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 388, + ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 408, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -9579,9 +9931,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:574 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/"" + // Pos:594 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/"" { - ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 389, + ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 409, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -9594,9 +9946,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:575 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM" + // Pos:595 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM" { - ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 390, + ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 410, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9611,9 +9963,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:576 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M" + // Pos:596 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M" { - ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 391, + ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 411, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -9627,9 +9979,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:577 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM" + // Pos:597 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM" { - ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 392, + ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 412, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9644,9 +9996,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:578 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M" + // Pos:598 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M" { - ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 393, + ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 413, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -9660,9 +10012,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:579 Instruction:"LKGS Mw" Encoding:"0xF2 0x0F 0x00 /6:mem"/"M" + // Pos:599 Instruction:"LKGS Mw" Encoding:"0xF2 0x0F 0x00 /6:mem"/"M" { - ND_INS_LKGS, ND_CAT_LKGS, ND_SET_LKGS, 394, + ND_INS_LKGS, ND_CAT_LKGS, ND_SET_LKGS, 414, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_LKGS, @@ -9676,9 +10028,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:580 Instruction:"LKGS Rv" Encoding:"0xF2 0x0F 0x00 /6:reg"/"M" + // Pos:600 Instruction:"LKGS Rv" Encoding:"0xF2 0x0F 0x00 /6:reg"/"M" { - ND_INS_LKGS, ND_CAT_LKGS, ND_SET_LKGS, 394, + ND_INS_LKGS, ND_CAT_LKGS, ND_SET_LKGS, 414, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_LKGS, @@ -9692,9 +10044,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:581 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M" + // Pos:601 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M" { - ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 395, + ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 415, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -9708,9 +10060,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:582 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M" + // Pos:602 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M" { - ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 396, + ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 416, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, @@ -9723,9 +10075,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:583 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M" + // Pos:603 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M" { - ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 397, + ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 417, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -9739,9 +10091,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:584 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM" + // Pos:604 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM" { - ND_INS_LOADIWKEY, ND_CAT_KL, ND_SET_KL, 398, + ND_INS_LOADIWKEY, ND_CAT_KL, ND_SET_KL, 418, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, @@ -9758,9 +10110,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:585 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/"" + // Pos:605 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 399, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 419, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9776,9 +10128,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:586 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/"" + // Pos:606 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 399, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 419, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9795,9 +10147,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:587 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/"" + // Pos:607 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 400, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 420, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9813,9 +10165,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:588 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/"" + // Pos:608 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 400, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 420, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9832,9 +10184,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:589 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/"" + // Pos:609 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 401, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 421, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9850,9 +10202,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:590 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/"" + // Pos:610 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 401, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 421, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9869,9 +10221,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:591 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/"" + // Pos:611 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 402, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 422, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9887,9 +10239,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:592 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/"" + // Pos:612 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 402, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 422, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9906,9 +10258,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:593 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D" + // Pos:613 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D" { - ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 403, + ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 423, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -9924,9 +10276,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:594 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D" + // Pos:614 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D" { - ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 404, + ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 424, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -9942,9 +10294,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:595 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D" + // Pos:615 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D" { - ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 405, + ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -9960,9 +10312,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:596 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM" + // Pos:616 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM" { - ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 406, + ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 426, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9977,9 +10329,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:597 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM" + // Pos:617 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM" { - ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 406, + ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 426, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9994,9 +10346,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:598 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM" + // Pos:618 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM" { - ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 407, + ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 427, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10011,9 +10363,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:599 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M" + // Pos:619 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M" { - ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 408, + ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 428, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -10027,9 +10379,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:600 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI" + // Pos:620 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI" { - ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 409, + ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 429, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, @@ -10044,9 +10396,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:601 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI" + // Pos:621 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI" { - ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 410, + ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 430, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, @@ -10061,9 +10413,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:602 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM" + // Pos:622 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM" { - ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 411, + ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 431, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LZCNT, @@ -10078,9 +10430,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:603 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM" + // Pos:623 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM" { - ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 412, + ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 432, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10095,9 +10447,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:604 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM" + // Pos:624 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM" { - ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 413, + ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 433, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -10112,9 +10464,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:605 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM" + // Pos:625 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM" { - ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 414, + ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 434, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10128,9 +10480,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:606 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM" + // Pos:626 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM" { - ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 415, + ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 435, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -10144,9 +10496,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:607 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM" + // Pos:627 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM" { - ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 416, + ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 436, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10160,9 +10512,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:608 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM" + // Pos:628 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM" { - ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 417, + ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 437, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -10176,9 +10528,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:609 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/"" + // Pos:629 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/"" { - ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 418, + ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 438, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MCOMMIT, @@ -10191,9 +10543,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:610 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/"" + // Pos:630 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/"" { - ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 419, + ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 439, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -10206,9 +10558,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:611 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM" + // Pos:631 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM" { - ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 420, + ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 440, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10222,9 +10574,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:612 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM" + // Pos:632 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM" { - ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 421, + ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 441, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -10238,9 +10590,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:613 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM" + // Pos:633 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM" { - ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 422, + ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 442, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10254,9 +10606,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:614 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM" + // Pos:634 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM" { - ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 423, + ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 443, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -10270,9 +10622,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:615 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/"" + // Pos:635 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/"" { - ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 424, + ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 444, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, @@ -10287,9 +10639,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:616 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/"" + // Pos:636 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/"" { - ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 425, + ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 445, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10304,9 +10656,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:617 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/"" + // Pos:637 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/"" { - ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 426, + ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 446, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10319,9 +10671,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:618 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR" + // Pos:638 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR" { - ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, @@ -10335,9 +10687,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:619 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR" + // Pos:639 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR" { - ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, @@ -10351,9 +10703,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:620 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM" + // Pos:640 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM" { - ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -10367,9 +10719,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:621 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM" + // Pos:641 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM" { - ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -10383,9 +10735,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:622 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR" + // Pos:642 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR" { - ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -10399,9 +10751,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:623 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM" + // Pos:643 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM" { - ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -10415,9 +10767,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:624 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR" + // Pos:644 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10431,9 +10783,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:625 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR" + // Pos:645 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10447,9 +10799,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:626 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM" + // Pos:646 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10463,9 +10815,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:627 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM" + // Pos:647 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10479,9 +10831,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:628 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR" + // Pos:648 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10495,9 +10847,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:629 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR" + // Pos:649 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10511,9 +10863,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:630 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM" + // Pos:650 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10527,9 +10879,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:631 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM" + // Pos:651 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10543,9 +10895,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:632 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D" + // Pos:652 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10559,9 +10911,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:633 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D" + // Pos:653 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10575,9 +10927,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:634 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D" + // Pos:654 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10591,9 +10943,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:635 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D" + // Pos:655 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10607,9 +10959,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:636 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI" + // Pos:656 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10623,9 +10975,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:637 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI" + // Pos:657 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10639,9 +10991,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:638 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI" + // Pos:658 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10655,9 +11007,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:639 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI" + // Pos:659 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10671,9 +11023,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:640 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI" + // Pos:660 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10687,9 +11039,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:641 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI" + // Pos:661 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10703,9 +11055,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:642 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI" + // Pos:662 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10719,9 +11071,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:643 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI" + // Pos:663 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10735,9 +11087,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:644 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI" + // Pos:664 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10751,9 +11103,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:645 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI" + // Pos:665 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10767,9 +11119,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:646 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI" + // Pos:666 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10783,9 +11135,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:647 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI" + // Pos:667 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10799,9 +11151,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:648 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI" + // Pos:668 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10815,9 +11167,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:649 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI" + // Pos:669 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10831,9 +11183,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:650 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI" + // Pos:670 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10847,9 +11199,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:651 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI" + // Pos:671 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10863,9 +11215,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:652 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI" + // Pos:672 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10879,9 +11231,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:653 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI" + // Pos:673 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 427, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10895,9 +11247,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:654 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM" + // Pos:674 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM" { - ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 428, + ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 448, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10911,9 +11263,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:655 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR" + // Pos:675 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR" { - ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 428, + ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 448, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10927,9 +11279,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:656 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM" + // Pos:676 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM" { - ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 429, + ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 449, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -10943,9 +11295,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:657 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR" + // Pos:677 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR" { - ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 429, + ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 449, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -10959,9 +11311,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:658 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM" + // Pos:678 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM" { - ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 430, + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 450, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, @@ -10975,9 +11327,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:659 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM" + // Pos:679 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM" { - ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 430, + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 450, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, @@ -10991,9 +11343,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:660 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR" + // Pos:680 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR" { - ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 430, + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 450, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, @@ -11007,9 +11359,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:661 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR" + // Pos:681 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR" { - ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 430, + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 450, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, @@ -11023,9 +11375,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:662 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM" + // Pos:682 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM" { - ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 431, + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 451, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -11039,9 +11391,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:663 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM" + // Pos:683 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM" { - ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 431, + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 451, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11055,9 +11407,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:664 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR" + // Pos:684 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR" { - ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 431, + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 451, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -11071,9 +11423,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:665 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR" + // Pos:685 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR" { - ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 431, + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 451, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11087,9 +11439,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:666 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM" + // Pos:686 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM" { - ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 432, + ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 452, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -11103,9 +11455,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:667 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M" + // Pos:687 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M" { - ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 433, + ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 453, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIR64B, @@ -11119,9 +11471,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:668 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR" + // Pos:688 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR" { - ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 434, + ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 454, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIRI, @@ -11135,9 +11487,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:669 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM" + // Pos:689 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM" { - ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 435, + ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 455, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11151,9 +11503,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:670 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM" + // Pos:690 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM" { - ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 436, + ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 456, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11167,9 +11519,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:671 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR" + // Pos:691 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR" { - ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 436, + ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 456, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11183,9 +11535,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:672 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM" + // Pos:692 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM" { - ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 437, + ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 457, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11199,9 +11551,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:673 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR" + // Pos:693 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR" { - ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 437, + ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 457, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11215,9 +11567,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:674 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM" + // Pos:694 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM" { - ND_INS_MOVHLPS, ND_CAT_DATAXFER, ND_SET_SSE, 438, + ND_INS_MOVHLPS, ND_CAT_DATAXFER, ND_SET_SSE, 458, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11231,9 +11583,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:675 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM" + // Pos:695 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM" { - ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 439, + ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 459, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11247,9 +11599,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:676 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR" + // Pos:696 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR" { - ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 439, + ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 459, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11263,9 +11615,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:677 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM" + // Pos:697 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM" { - ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 440, + ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 460, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11279,9 +11631,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:678 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR" + // Pos:698 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR" { - ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 440, + ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 460, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11295,9 +11647,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:679 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM" + // Pos:699 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM" { - ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 441, + ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 461, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11311,9 +11663,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:680 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM" + // Pos:700 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM" { - ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 442, + ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 462, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11327,9 +11679,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:681 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR" + // Pos:701 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR" { - ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 442, + ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 462, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11343,9 +11695,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:682 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR" + // Pos:702 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR" { - ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 443, + ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 463, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11359,41 +11711,41 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:683 Instruction:"MOVMSKPD Gd,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM" + // Pos:703 Instruction:"MOVMSKPD Gy,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM" { - ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 444, + ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 464, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { - OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, - // Pos:684 Instruction:"MOVMSKPS Gd,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM" + // Pos:704 Instruction:"MOVMSKPS Gy,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM" { - ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 445, + ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 465, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { - OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, - // Pos:685 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR" + // Pos:705 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR" { - ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 446, + ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 466, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11407,9 +11759,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:686 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM" + // Pos:706 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM" { - ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 447, + ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 467, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -11423,9 +11775,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:687 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR" + // Pos:707 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR" { - ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 448, + ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 468, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -11439,9 +11791,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:688 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR" + // Pos:708 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR" { - ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 449, + ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 469, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11455,9 +11807,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:689 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR" + // Pos:709 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR" { - ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 450, + ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 470, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11471,9 +11823,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:690 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR" + // Pos:710 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR" { - ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 451, + ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 471, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -11487,9 +11839,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:691 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR" + // Pos:711 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR" { - ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 452, + ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 472, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, @@ -11503,9 +11855,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:692 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR" + // Pos:712 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR" { - ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 453, + ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 473, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, @@ -11519,9 +11871,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:693 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM" + // Pos:713 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 454, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -11535,9 +11887,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:694 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM" + // Pos:714 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 454, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11551,9 +11903,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:695 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM" + // Pos:715 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 454, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -11567,9 +11919,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:696 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR" + // Pos:716 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 454, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -11583,9 +11935,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:697 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR" + // Pos:717 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 454, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11599,9 +11951,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:698 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM" + // Pos:718 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 454, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11615,9 +11967,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:699 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR" + // Pos:719 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 454, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -11631,9 +11983,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:700 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR" + // Pos:720 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 454, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11647,9 +11999,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:701 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM" + // Pos:721 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM" { - ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 455, + ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 475, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11663,9 +12015,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:702 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" + // Pos:722 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 456, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 476, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11682,9 +12034,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:703 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" + // Pos:723 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 456, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 476, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11702,9 +12054,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:704 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" + // Pos:724 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" { - ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 457, + ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 477, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11718,9 +12070,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:705 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" + // Pos:725 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" { - ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 457, + ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 477, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11734,9 +12086,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:706 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" + // Pos:726 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 457, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 477, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11753,9 +12105,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:707 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" + // Pos:727 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 457, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 477, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11773,9 +12125,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:708 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" + // Pos:728 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" { - ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 458, + ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 478, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -11789,9 +12141,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:709 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" + // Pos:729 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" { - ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 459, + ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 479, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -11805,9 +12157,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:710 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" + // Pos:730 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 460, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 480, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11824,9 +12176,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:711 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" + // Pos:731 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 460, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 480, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11844,9 +12196,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:712 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" + // Pos:732 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" { - ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 461, + ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 481, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11860,9 +12212,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:713 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" + // Pos:733 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" { - ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 461, + ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 481, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11876,9 +12228,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:714 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" + // Pos:734 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 462, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 482, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11895,9 +12247,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:715 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" + // Pos:735 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 462, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 482, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11915,9 +12267,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:716 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" + // Pos:736 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" { - ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 463, + ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 483, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -11931,9 +12283,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:717 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" + // Pos:737 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" { - ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 463, + ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 483, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -11947,9 +12299,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:718 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM" + // Pos:738 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM" { - ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 464, + ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 484, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -11963,9 +12315,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:719 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" + // Pos:739 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" { - ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 465, + ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 485, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11979,9 +12331,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:720 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" + // Pos:740 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" { - ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 465, + ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 485, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11995,9 +12347,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:721 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" + // Pos:741 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" { - ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 466, + ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 486, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -12011,9 +12363,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:722 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" + // Pos:742 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" { - ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 466, + ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 486, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -12027,9 +12379,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:723 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" + // Pos:743 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" { - ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 467, + ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 487, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12043,9 +12395,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:724 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" + // Pos:744 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" { - ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 467, + ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 487, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12059,9 +12411,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:725 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" + // Pos:745 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" { - ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 468, + ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 488, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -12076,9 +12428,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:726 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" + // Pos:746 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" { - ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 469, + ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 489, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12094,9 +12446,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:727 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" + // Pos:747 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" { - ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 469, + ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 489, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12112,9 +12464,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:728 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" + // Pos:748 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" { - ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 470, + ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 490, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -12128,9 +12480,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:729 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" + // Pos:749 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" { - ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 471, + ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 491, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -12144,9 +12496,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:730 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" + // Pos:750 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" { - ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 472, + ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 492, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -12160,9 +12512,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:731 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" + // Pos:751 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" { - ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 473, + ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 493, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -12176,9 +12528,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:732 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" + // Pos:752 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" { - ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 474, + ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 494, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -12194,9 +12546,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:733 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" + // Pos:753 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" { - ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 475, + ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 495, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, @@ -12210,9 +12562,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:734 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" + // Pos:754 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" { - ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 476, + ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 496, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12227,9 +12579,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:735 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" + // Pos:755 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" { - ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 477, + ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 497, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12243,9 +12595,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:736 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" + // Pos:756 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" { - ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 477, + ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 497, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12259,9 +12611,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:737 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" + // Pos:757 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12275,9 +12627,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:738 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" + // Pos:758 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12291,9 +12643,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:739 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" + // Pos:759 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12307,9 +12659,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:740 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" + // Pos:760 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12323,9 +12675,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:741 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" + // Pos:761 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12339,9 +12691,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:742 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" + // Pos:762 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12355,9 +12707,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:743 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" + // Pos:763 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12371,9 +12723,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:744 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" + // Pos:764 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12387,9 +12739,69 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:745 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" + // Pos:765 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:766 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:767 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:768 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:769 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12402,9 +12814,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:746 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" + // Pos:770 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12417,9 +12829,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:747 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" + // Pos:771 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12432,9 +12844,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:748 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" + // Pos:772 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12447,9 +12859,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:749 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" + // Pos:773 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12462,9 +12874,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:750 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" + // Pos:774 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /0:reg"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12477,9 +12889,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:751 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" + // Pos:775 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /1:reg"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12492,9 +12904,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:752 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" + // Pos:776 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /2:reg"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12507,9 +12919,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:753 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" + // Pos:777 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /3:reg"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12522,9 +12934,99 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:754 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1A /r"/"MR" + // Pos:778 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /4"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:779 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /5"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:780 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:mem"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:781 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:782 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:mem"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:783 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:784 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1A /r"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12538,9 +13040,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:755 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM" + // Pos:785 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12554,9 +13056,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:756 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR" + // Pos:786 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12570,9 +13072,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:757 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" + // Pos:787 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12586,9 +13088,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:758 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR" + // Pos:788 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12602,9 +13104,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:759 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" + // Pos:789 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12618,9 +13120,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:760 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1A /r:reg"/"RM" + // Pos:790 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1A /r:reg"/"RM" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12634,9 +13136,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:761 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1B /r:reg"/"RM" + // Pos:791 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1B /r:reg"/"RM" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12650,9 +13152,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:762 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM" + // Pos:792 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12666,9 +13168,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:763 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR" + // Pos:793 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12682,9 +13184,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:764 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR" + // Pos:794 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12698,9 +13200,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:765 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR" + // Pos:795 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12714,9 +13216,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:766 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR" + // Pos:796 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12730,9 +13232,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:767 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR" + // Pos:797 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12746,9 +13248,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:768 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR" + // Pos:798 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12762,9 +13264,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:769 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR" + // Pos:799 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12778,9 +13280,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:770 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR" + // Pos:800 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12794,9 +13296,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:771 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR" + // Pos:801 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12810,9 +13312,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:772 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR" + // Pos:802 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12826,9 +13328,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:773 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR" + // Pos:803 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12842,9 +13344,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:774 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /r:mem"/"MR" + // Pos:804 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /r:mem"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12858,9 +13360,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:775 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR" + // Pos:805 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12874,9 +13376,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:776 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR" + // Pos:806 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12890,9 +13392,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:777 Instruction:"NOP Rv,Gv" Encoding:"cet rexw 0x0F 0x1E /1:reg"/"MR" + // Pos:807 Instruction:"NOP Rv,Gv" Encoding:"cet rexw 0x0F 0x1E /1:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12906,9 +13408,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:778 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR" + // Pos:808 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12922,9 +13424,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:779 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR" + // Pos:809 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12938,9 +13440,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:780 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR" + // Pos:810 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12954,9 +13456,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:781 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR" + // Pos:811 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12970,9 +13472,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:782 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR" + // Pos:812 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12986,9 +13488,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:783 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR" + // Pos:813 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13002,9 +13504,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:784 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR" + // Pos:814 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13018,9 +13520,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:785 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR" + // Pos:815 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13034,9 +13536,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:786 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR" + // Pos:816 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13050,9 +13552,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:787 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR" + // Pos:817 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13066,9 +13568,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:788 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR" + // Pos:818 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13082,9 +13584,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:789 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR" + // Pos:819 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13098,9 +13600,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:790 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR" + // Pos:820 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 478, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13114,9 +13616,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:791 Instruction:"NOP" Encoding:"0x90"/"" + // Pos:821 Instruction:"NOP" Encoding:"0x90"/"" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 478, + ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -13129,9 +13631,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:792 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" + // Pos:822 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" { - ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 479, + ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 499, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13144,9 +13646,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:793 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" + // Pos:823 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" { - ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 479, + ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 499, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13159,9 +13661,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:794 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" + // Pos:824 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13176,9 +13678,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:795 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" + // Pos:825 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13193,9 +13695,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:796 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" + // Pos:826 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13210,9 +13712,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:797 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" + // Pos:827 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13227,9 +13729,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:798 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" + // Pos:828 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -13244,9 +13746,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:799 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" + // Pos:829 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -13261,9 +13763,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:800 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" + // Pos:830 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13278,9 +13780,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:801 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" + // Pos:831 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13295,9 +13797,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:802 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI" + // Pos:832 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -13312,9 +13814,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:803 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" + // Pos:833 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 480, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13329,9 +13831,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:804 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" + // Pos:834 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" { - ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 481, + ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 501, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13345,9 +13847,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:805 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" + // Pos:835 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" { - ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 482, + ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 502, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -13361,9 +13863,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:806 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" + // Pos:836 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" { - ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 483, + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13378,9 +13880,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:807 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" + // Pos:837 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" { - ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 483, + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13395,9 +13897,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:808 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" + // Pos:838 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" { - ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 483, + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13412,9 +13914,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:809 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" + // Pos:839 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" { - ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 483, + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13429,9 +13931,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:810 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" + // Pos:840 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 484, + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 504, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13447,9 +13949,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:811 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" + // Pos:841 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 484, + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 504, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13466,9 +13968,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:812 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" + // Pos:842 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 485, + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 505, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13484,9 +13986,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:813 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" + // Pos:843 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 485, + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 505, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13503,9 +14005,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:814 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" + // Pos:844 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 486, + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 506, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13521,9 +14023,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:815 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" + // Pos:845 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 486, + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 506, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13540,9 +14042,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:816 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" + // Pos:846 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" { - ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 487, + ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 507, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -13556,9 +14058,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:817 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" + // Pos:847 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" { - ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 487, + ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 507, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -13572,9 +14074,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:818 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" + // Pos:848 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" { - ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 488, + ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 508, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -13588,9 +14090,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:819 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" + // Pos:849 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" { - ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 488, + ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 508, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -13604,9 +14106,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:820 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" + // Pos:850 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" { - ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 489, + ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 509, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -13620,9 +14122,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:821 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" + // Pos:851 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" { - ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 489, + ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 509, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -13636,9 +14138,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:822 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" + // Pos:852 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" { - ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 490, + ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 510, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13652,9 +14154,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:823 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" + // Pos:853 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" { - ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 490, + ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 510, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13668,9 +14170,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:824 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" + // Pos:854 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" { - ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 491, + ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 511, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13684,9 +14186,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:825 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" + // Pos:855 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" { - ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 491, + ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 511, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13700,9 +14202,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:826 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" + // Pos:856 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" { - ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 492, + ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 512, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -13716,9 +14218,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:827 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" + // Pos:857 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" { - ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 493, + ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 513, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13732,9 +14234,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:828 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" + // Pos:858 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" { - ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 493, + ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 513, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13748,9 +14250,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:829 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" + // Pos:859 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" { - ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 494, + ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 514, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13764,9 +14266,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:830 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" + // Pos:860 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" { - ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 494, + ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 514, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13780,9 +14282,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:831 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" + // Pos:861 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" { - ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 495, + ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 515, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13796,9 +14298,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:832 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" + // Pos:862 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" { - ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 495, + ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 515, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13812,9 +14314,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:833 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" + // Pos:863 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" { - ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 496, + ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 516, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -13828,9 +14330,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:834 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" + // Pos:864 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" { - ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 496, + ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 516, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13844,9 +14346,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:835 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" + // Pos:865 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" { - ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 497, + ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 517, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13860,9 +14362,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:836 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" + // Pos:866 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" { - ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 497, + ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 517, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13876,9 +14378,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:837 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" + // Pos:867 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" { - ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 498, + ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 518, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13892,9 +14394,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:838 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" + // Pos:868 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" { - ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 498, + ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 518, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13908,9 +14410,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:839 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" + // Pos:869 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" { - ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 499, + ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 519, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13924,9 +14426,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:840 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" + // Pos:870 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" { - ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 499, + ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 519, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13940,9 +14442,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:841 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" + // Pos:871 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" { - ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 500, + ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 520, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13956,9 +14458,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:842 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" + // Pos:872 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" { - ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 500, + ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 520, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13972,9 +14474,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:843 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" + // Pos:873 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" { - ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 501, + ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 521, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13988,9 +14490,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:844 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" + // Pos:874 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" { - ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 501, + ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 521, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14004,9 +14506,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:845 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" + // Pos:875 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" { - ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 502, + ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 522, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -14021,9 +14523,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:846 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" + // Pos:876 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" { - ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 502, + ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 522, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -14038,9 +14540,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:847 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" + // Pos:877 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" { - ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 503, + ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 523, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14054,9 +14556,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:848 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" + // Pos:878 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" { - ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 503, + ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 523, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14070,9 +14572,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:849 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" + // Pos:879 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" { - ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 504, + ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 524, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14086,9 +14588,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:850 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" + // Pos:880 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" { - ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 504, + ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 524, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14102,9 +14604,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:851 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/"" + // Pos:881 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/"" { - ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 505, + ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 525, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -14117,9 +14619,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:852 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" + // Pos:882 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" { - ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 506, + ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 526, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14133,9 +14635,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:853 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" + // Pos:883 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" { - ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 506, + ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 526, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14149,9 +14651,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:854 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" + // Pos:884 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" { - ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 507, + ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 527, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14165,9 +14667,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:855 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" + // Pos:885 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" { - ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 508, + ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 528, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14181,9 +14683,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:856 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" + // Pos:886 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" { - ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 508, + ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 528, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14197,9 +14699,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:857 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" + // Pos:887 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" { - ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 509, + ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 529, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14214,9 +14716,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:858 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" + // Pos:888 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" { - ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 510, + ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 530, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14231,9 +14733,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:859 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" + // Pos:889 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" { - ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 511, + ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 531, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_PCLMULQDQ, @@ -14248,9 +14750,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:860 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" + // Pos:890 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" { - ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 512, + ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 532, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14264,9 +14766,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:861 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" + // Pos:891 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" { - ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 512, + ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 532, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14280,9 +14782,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:862 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" + // Pos:892 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" { - ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 513, + ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 533, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14296,9 +14798,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:863 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" + // Pos:893 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" { - ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 513, + ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 533, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14312,9 +14814,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:864 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" + // Pos:894 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" { - ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 514, + ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 534, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14328,9 +14830,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:865 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" + // Pos:895 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" { - ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 515, + ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 535, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14344,9 +14846,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:866 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" + // Pos:896 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" { - ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 515, + ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 535, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14360,9 +14862,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:867 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" + // Pos:897 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" { - ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 516, + ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 536, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, @@ -14381,9 +14883,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:868 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" + // Pos:898 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" { - ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 517, + ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 537, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, @@ -14402,9 +14904,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:869 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" + // Pos:899 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" { - ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 518, + ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 538, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14418,9 +14920,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:870 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" + // Pos:900 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" { - ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 518, + ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 538, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14434,9 +14936,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:871 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" + // Pos:901 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" { - ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 519, + ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 539, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14450,9 +14952,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:872 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" + // Pos:902 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" { - ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 519, + ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 539, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14466,9 +14968,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:873 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" + // Pos:903 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" { - ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 520, + ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 540, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, @@ -14482,9 +14984,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:874 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" + // Pos:904 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" { - ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 521, + ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 541, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14498,9 +15000,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:875 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" + // Pos:905 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" { - ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 521, + ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 541, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14514,9 +15016,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:876 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" + // Pos:906 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" { - ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 522, + ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 542, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, @@ -14533,9 +15035,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:877 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" + // Pos:907 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" { - ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 523, + ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 543, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, @@ -14552,9 +15054,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:878 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" + // Pos:908 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" { - ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 524, + ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 544, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, @@ -14570,9 +15072,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:879 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" + // Pos:909 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" { - ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 525, + ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 545, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -14587,9 +15089,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:880 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" + // Pos:910 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" { - ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 526, + ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 546, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -14604,9 +15106,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:881 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" + // Pos:911 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" { - ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 527, + ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 547, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14621,26 +15123,26 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:882 Instruction:"PEXTRB Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" + // Pos:912 Instruction:"PEXTRB Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" { - ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 527, + ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 547, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:883 Instruction:"PEXTRD Ey,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r ib"/"MRI" + // Pos:913 Instruction:"PEXTRD Md,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" { - ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 528, + ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 548, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14649,66 +15151,32 @@ const ND_INSTRUCTION gInstructions[2701] = 0, 0, { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:884 Instruction:"PEXTRQ Ey,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r ib"/"MRI" + // Pos:914 Instruction:"PEXTRD Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" { - ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 529, + ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 548, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:885 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" + // Pos:915 Instruction:"PEXTRQ Mq,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" { - ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 530, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:886 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" - { - ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 530, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:887 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" - { - ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 530, + ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 549, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14717,15 +15185,15 @@ const ND_INSTRUCTION gInstructions[2701] = 0, 0, { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:888 Instruction:"PEXTRW Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" + // Pos:916 Instruction:"PEXTRQ Ry,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" { - ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 530, + ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 549, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14734,79 +15202,83 @@ const ND_INSTRUCTION gInstructions[2701] = 0, 0, { - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:889 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" + // Pos:917 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" { - ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 531, + ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 550, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:890 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" + // Pos:918 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" { - ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 532, + ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 550, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:891 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" + // Pos:919 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" { - ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 533, + ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 550, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:892 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" + // Pos:920 Instruction:"PEXTRW Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" { - ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 534, + ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 550, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:893 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" + // Pos:921 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" { - ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 535, + ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 551, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14820,9 +15292,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:894 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" + // Pos:922 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" { - ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 536, + ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 552, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14836,9 +15308,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:895 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" + // Pos:923 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" { - ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 537, + ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 553, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14852,9 +15324,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:896 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" + // Pos:924 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" { - ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 538, + ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 554, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14868,9 +15340,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:897 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" + // Pos:925 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" { - ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 539, + ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 555, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14884,9 +15356,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:898 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" + // Pos:926 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" { - ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 540, + ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 556, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14900,9 +15372,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:899 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" + // Pos:927 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" { - ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 541, + ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 557, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14916,9 +15388,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:900 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" + // Pos:928 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" { - ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 542, + ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 558, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14932,9 +15404,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:901 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" + // Pos:929 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" { - ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 543, + ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 559, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14948,9 +15420,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:902 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" + // Pos:930 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" { - ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 544, + ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 560, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14964,9 +15436,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:903 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" + // Pos:931 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" { - ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 545, + ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 561, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14980,25 +15452,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:904 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" + // Pos:932 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" { - ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 546, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:905 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" - { - ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 547, + ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 562, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -15012,9 +15468,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:906 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" + // Pos:933 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" { - ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 548, + ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 563, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -15028,25 +15484,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:907 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" - { - ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 549, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:908 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" + // Pos:934 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" { - ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 550, + ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 564, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -15060,9 +15500,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:909 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" + // Pos:935 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" { - ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 551, + ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 565, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -15076,9 +15516,105 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:910 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" + // Pos:936 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" { - ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 552, + ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 566, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:937 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" + { + ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 567, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:938 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" + { + ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 568, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:939 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" + { + ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 569, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:940 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" + { + ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 570, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:941 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" + { + ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 571, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:942 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" + { + ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 572, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15092,9 +15628,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:911 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" + // Pos:943 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" { - ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 552, + ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 572, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15108,9 +15644,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:912 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" + // Pos:944 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" { - ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 553, + ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 573, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15124,9 +15660,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:913 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" + // Pos:945 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" { - ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 553, + ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 573, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15140,9 +15676,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:914 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" + // Pos:946 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" { - ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 554, + ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 574, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15156,9 +15692,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:915 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" + // Pos:947 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" { - ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 554, + ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 574, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15172,9 +15708,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:916 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" + // Pos:948 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" { - ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 555, + ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 575, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15188,9 +15724,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:917 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" + // Pos:949 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" { - ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 556, + ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 576, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15204,9 +15740,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:918 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" + // Pos:950 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" { - ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 556, + ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 576, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15220,9 +15756,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:919 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" + // Pos:951 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" { - ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 557, + ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 577, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15236,9 +15772,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:920 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" + // Pos:952 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" { - ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 557, + ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 577, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15252,9 +15788,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:921 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" + // Pos:953 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" { - ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 558, + ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 578, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15268,9 +15804,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:922 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" + // Pos:954 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" { - ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 558, + ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 578, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15284,9 +15820,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:923 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" + // Pos:955 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" { - ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 559, + ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 579, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -15300,9 +15836,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:924 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" + // Pos:956 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" { - ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 560, + ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 580, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -15316,9 +15852,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:925 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" + // Pos:957 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" { - ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 561, + ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 581, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15333,9 +15869,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:926 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" + // Pos:958 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" { - ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 561, + ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 581, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15350,9 +15886,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:927 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + // Pos:959 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" { - ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 562, + ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 582, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15367,9 +15903,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:928 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + // Pos:960 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" { - ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 563, + ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 583, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15384,9 +15920,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:929 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" + // Pos:961 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" { - ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 564, + ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 584, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15401,9 +15937,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:930 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" + // Pos:962 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" { - ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 564, + ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 584, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15418,9 +15954,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:931 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" + // Pos:963 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" { - ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 564, + ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 584, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15435,9 +15971,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:932 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" + // Pos:964 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" { - ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 564, + ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 584, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15452,9 +15988,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:933 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" + // Pos:965 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" { - ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 565, + ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 585, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15468,9 +16004,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:934 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" + // Pos:966 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" { - ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 565, + ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 585, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15484,9 +16020,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:935 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" + // Pos:967 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" { - ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 566, + ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 586, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15500,9 +16036,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:936 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" + // Pos:968 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" { - ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 566, + ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 586, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15516,9 +16052,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:937 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" + // Pos:969 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" { - ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 567, + ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 587, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15532,9 +16068,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:938 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" + // Pos:970 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" { - ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 568, + ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 588, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15548,9 +16084,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:939 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" + // Pos:971 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" { - ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 569, + ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 589, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15564,9 +16100,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:940 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" + // Pos:972 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" { - ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 569, + ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 589, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15580,9 +16116,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:941 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" + // Pos:973 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" { - ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 570, + ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 590, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15596,9 +16132,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:942 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" + // Pos:974 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" { - ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 570, + ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 590, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15612,9 +16148,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:943 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" + // Pos:975 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" { - ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 571, + ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 591, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15628,9 +16164,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:944 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" + // Pos:976 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" { - ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 572, + ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 592, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15644,9 +16180,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:945 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" + // Pos:977 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" { - ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 573, + ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 593, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15660,9 +16196,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:946 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" + // Pos:978 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" { - ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 574, + ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 594, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15676,9 +16212,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:947 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" + // Pos:979 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" { - ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 575, + ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 595, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15692,9 +16228,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:948 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" + // Pos:980 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" { - ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 575, + ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 595, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15708,9 +16244,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:949 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" + // Pos:981 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" { - ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 576, + ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 596, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15724,9 +16260,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:950 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" + // Pos:982 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" { - ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 576, + ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 596, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15740,9 +16276,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:951 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" + // Pos:983 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" { - ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 577, + ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 597, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15756,9 +16292,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:952 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" + // Pos:984 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" { - ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 578, + ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 598, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15772,41 +16308,41 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:953 Instruction:"PMOVMSKB Gd,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" + // Pos:985 Instruction:"PMOVMSKB Gy,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" { - ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 579, + ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 599, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, 0, { - OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, - // Pos:954 Instruction:"PMOVMSKB Gd,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" + // Pos:986 Instruction:"PMOVMSKB Gy,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" { - ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 579, + ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 599, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { - OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, - // Pos:955 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" + // Pos:987 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" { - ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 580, + ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 600, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15820,9 +16356,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:956 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" + // Pos:988 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" { - ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 581, + ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 601, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15836,9 +16372,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:957 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" + // Pos:989 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" { - ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 582, + ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 602, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15852,9 +16388,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:958 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" + // Pos:990 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" { - ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 583, + ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 603, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15868,9 +16404,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:959 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" + // Pos:991 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" { - ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 584, + ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 604, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15884,9 +16420,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:960 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" + // Pos:992 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" { - ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 585, + ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 605, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15900,9 +16436,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:961 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" + // Pos:993 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" { - ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 586, + ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 606, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15916,9 +16452,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:962 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" + // Pos:994 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" { - ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 587, + ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 607, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15932,9 +16468,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:963 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" + // Pos:995 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" { - ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 588, + ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 608, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15948,9 +16484,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:964 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" + // Pos:996 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" { - ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 589, + ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 609, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15964,9 +16500,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:965 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" + // Pos:997 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" { - ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 590, + ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 610, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15980,9 +16516,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:966 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" + // Pos:998 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" { - ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 591, + ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 611, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15996,9 +16532,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:967 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" + // Pos:999 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" { - ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 592, + ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 612, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -16012,9 +16548,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:968 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" + // Pos:1000 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" { - ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 593, + ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 613, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -16028,9 +16564,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:969 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" + // Pos:1001 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" { - ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 593, + ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 613, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -16044,9 +16580,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:970 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" + // Pos:1002 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" { - ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 594, + ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 614, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -16060,9 +16596,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:971 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" + // Pos:1003 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" { - ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 595, + ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 615, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16076,9 +16612,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:972 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" + // Pos:1004 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" { - ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 595, + ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 615, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16092,9 +16628,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:973 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" + // Pos:1005 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" { - ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 596, + ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 616, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16108,9 +16644,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:974 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" + // Pos:1006 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" { - ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 596, + ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 616, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16124,9 +16660,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:975 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" + // Pos:1007 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" { - ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 597, + ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 617, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -16140,9 +16676,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:976 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" + // Pos:1008 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" { - ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 598, + ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 618, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16156,9 +16692,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:977 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" + // Pos:1009 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" { - ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 598, + ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 618, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16172,9 +16708,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:978 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" + // Pos:1010 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" { - ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 599, + ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 619, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -16188,9 +16724,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:979 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" + // Pos:1011 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" { - ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 599, + ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 619, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16204,9 +16740,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:980 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" + // Pos:1012 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16220,9 +16756,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:981 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" + // Pos:1013 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16236,9 +16772,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:982 Instruction:"POP ES" Encoding:"0x07"/"" + // Pos:1014 Instruction:"POP ES" Encoding:"0x07"/"" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -16252,9 +16788,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:983 Instruction:"POP SS" Encoding:"0x17"/"" + // Pos:1015 Instruction:"POP SS" Encoding:"0x17"/"" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -16268,9 +16804,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:984 Instruction:"POP DS" Encoding:"0x1F"/"" + // Pos:1016 Instruction:"POP DS" Encoding:"0x1F"/"" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -16284,9 +16820,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:985 Instruction:"POP Zv" Encoding:"0x58"/"O" + // Pos:1017 Instruction:"POP Zv" Encoding:"0x58"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16300,9 +16836,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:986 Instruction:"POP Zv" Encoding:"0x59"/"O" + // Pos:1018 Instruction:"POP Zv" Encoding:"0x59"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16316,9 +16852,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:987 Instruction:"POP Zv" Encoding:"0x5A"/"O" + // Pos:1019 Instruction:"POP Zv" Encoding:"0x5A"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16332,9 +16868,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:988 Instruction:"POP Zv" Encoding:"0x5B"/"O" + // Pos:1020 Instruction:"POP Zv" Encoding:"0x5B"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16348,9 +16884,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:989 Instruction:"POP Zv" Encoding:"0x5C"/"O" + // Pos:1021 Instruction:"POP Zv" Encoding:"0x5C"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16364,9 +16900,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:990 Instruction:"POP Zv" Encoding:"0x5D"/"O" + // Pos:1022 Instruction:"POP Zv" Encoding:"0x5D"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16380,9 +16916,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:991 Instruction:"POP Zv" Encoding:"0x5E"/"O" + // Pos:1023 Instruction:"POP Zv" Encoding:"0x5E"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16396,9 +16932,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:992 Instruction:"POP Zv" Encoding:"0x5F"/"O" + // Pos:1024 Instruction:"POP Zv" Encoding:"0x5F"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16412,9 +16948,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:993 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" + // Pos:1025 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 600, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, @@ -16428,9 +16964,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:994 Instruction:"POPA" Encoding:"ds16 0x61"/"" + // Pos:1026 Instruction:"POPA" Encoding:"ds16 0x61"/"" { - ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 601, + ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 621, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -16444,9 +16980,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:995 Instruction:"POPAD" Encoding:"ds32 0x61"/"" + // Pos:1027 Instruction:"POPAD" Encoding:"ds32 0x61"/"" { - ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 602, + ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 622, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -16460,9 +16996,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:996 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM" + // Pos:1028 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM" { - ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 603, + ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 623, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, @@ -16477,9 +17013,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:997 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" + // Pos:1029 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" { - ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 604, + ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 624, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16493,9 +17029,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:998 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" + // Pos:1030 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" { - ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 605, + ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 625, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16509,9 +17045,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:999 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" + // Pos:1031 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" { - ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 606, + ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 626, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16525,9 +17061,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1000 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" + // Pos:1032 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" { - ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 607, + ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 627, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16541,9 +17077,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1001 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" + // Pos:1033 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" { - ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 607, + ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 627, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16557,9 +17093,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1002 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M" + // Pos:1034 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M" { - ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 608, + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 628, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16572,9 +17108,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1003 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M" + // Pos:1035 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M" { - ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 608, + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 628, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16587,9 +17123,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1004 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M" + // Pos:1036 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M" { - ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 608, + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 628, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16602,9 +17138,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1005 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M" + // Pos:1037 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M" { - ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 608, + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 628, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16617,9 +17153,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1006 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M" + // Pos:1038 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M" { - ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 609, + ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16632,9 +17168,39 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1007 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M" + // Pos:1039 Instruction:"PREFETCHIT0 Mb" Encoding:"piti riprel 0x0F 0x18 /7:mem"/"M" + { + ND_INS_PREFETCHIT0, ND_CAT_PREFETCH, ND_SET_PREFETCHITI, 630, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_PREFETCHITI, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1040 Instruction:"PREFETCHIT1 Mb" Encoding:"piti riprel 0x0F 0x18 /6:mem"/"M" { - ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 610, + ND_INS_PREFETCHIT1, ND_CAT_PREFETCH, ND_SET_PREFETCHITI, 631, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_PREFETCHITI, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1041 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M" + { + ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 632, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16647,9 +17213,24 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1008 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M" + // Pos:1042 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M" + { + ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 633, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1043 Instruction:"PREFETCHNTA Mb" Encoding:"piti 0x0F 0x18 /0:mem"/"M" { - ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 611, + ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 633, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -16662,9 +17243,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1009 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M" + // Pos:1044 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M" { - ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 612, + ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 634, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -16677,9 +17258,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1010 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M" + // Pos:1045 Instruction:"PREFETCHT0 Mb" Encoding:"piti 0x0F 0x18 /1:mem"/"M" { - ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 613, + ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 634, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -16692,9 +17273,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1011 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M" + // Pos:1046 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M" { - ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 614, + ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 635, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -16707,9 +17288,54 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1012 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M" + // Pos:1047 Instruction:"PREFETCHT1 Mb" Encoding:"piti 0x0F 0x18 /2:mem"/"M" { - ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 615, + ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 635, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1048 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M" + { + ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 636, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1049 Instruction:"PREFETCHT2 Mb" Encoding:"piti 0x0F 0x18 /3:mem"/"M" + { + ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 636, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1050 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M" + { + ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 637, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16722,9 +17348,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1013 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M" + // Pos:1051 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M" { - ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 616, + ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 638, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16737,9 +17363,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1014 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" + // Pos:1052 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" { - ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 617, + ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 639, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16753,9 +17379,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1015 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" + // Pos:1053 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" { - ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 617, + ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 639, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16769,9 +17395,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1016 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" + // Pos:1054 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" { - ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 618, + ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 640, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -16785,9 +17411,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1017 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" + // Pos:1055 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" { - ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 618, + ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 640, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -16801,9 +17427,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1018 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" + // Pos:1056 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" { - ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 619, + ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 641, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16818,9 +17444,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1019 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" + // Pos:1057 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" { - ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 620, + ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 642, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16835,9 +17461,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1020 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" + // Pos:1058 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" { - ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 621, + ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 643, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16852,9 +17478,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1021 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" + // Pos:1059 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" { - ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 622, + ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 644, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16869,9 +17495,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1022 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" + // Pos:1060 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" { - ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 623, + ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 645, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -16885,9 +17511,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1023 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" + // Pos:1061 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" { - ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 623, + ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 645, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -16901,9 +17527,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1024 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" + // Pos:1062 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" { - ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 624, + ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 646, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -16917,9 +17543,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1025 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" + // Pos:1063 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" { - ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 624, + ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 646, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -16933,9 +17559,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1026 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" + // Pos:1064 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" { - ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 625, + ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 647, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -16949,9 +17575,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1027 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" + // Pos:1065 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" { - ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 625, + ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 647, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -16965,9 +17591,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1028 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" + // Pos:1066 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" { - ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 626, + ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 648, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16981,9 +17607,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1029 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" + // Pos:1067 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" { - ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 626, + ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 648, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16997,9 +17623,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1030 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" + // Pos:1068 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" { - ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 626, + ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 648, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17013,9 +17639,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1031 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" + // Pos:1069 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" { - ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 626, + ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 648, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17029,9 +17655,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1032 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" + // Pos:1070 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" { - ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 627, + ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 649, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17045,9 +17671,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1033 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" + // Pos:1071 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" { - ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 628, + ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 650, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17061,9 +17687,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1034 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" + // Pos:1072 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" { - ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 628, + ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 650, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17077,9 +17703,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1035 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" + // Pos:1073 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" { - ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 628, + ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 650, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17093,9 +17719,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1036 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" + // Pos:1074 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" { - ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 628, + ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 650, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17109,9 +17735,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1037 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" + // Pos:1075 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" { - ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 629, + ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 651, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17125,9 +17751,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1038 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" + // Pos:1076 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" { - ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 629, + ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 651, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17141,9 +17767,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1039 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" + // Pos:1077 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" { - ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 629, + ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 651, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17157,9 +17783,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1040 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" + // Pos:1078 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" { - ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 629, + ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 651, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17173,9 +17799,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1041 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" + // Pos:1079 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" { - ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 630, + ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 652, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, @@ -17189,9 +17815,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1042 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" + // Pos:1080 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" { - ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 631, + ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 653, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17205,9 +17831,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1043 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" + // Pos:1081 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" { - ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 631, + ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 653, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17221,9 +17847,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1044 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" + // Pos:1082 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" { - ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 631, + ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 653, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17237,9 +17863,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1045 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" + // Pos:1083 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" { - ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 631, + ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 653, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17253,9 +17879,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1046 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" + // Pos:1084 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" { - ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 632, + ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 654, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17269,9 +17895,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1047 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" + // Pos:1085 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" { - ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 632, + ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 654, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17285,9 +17911,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1048 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" + // Pos:1086 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" { - ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 632, + ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 654, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17301,9 +17927,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1049 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" + // Pos:1087 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" { - ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 632, + ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 654, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17317,9 +17943,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1050 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" + // Pos:1088 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" { - ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 633, + ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17333,9 +17959,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1051 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" + // Pos:1089 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" { - ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 633, + ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17349,9 +17975,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1052 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" + // Pos:1090 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" { - ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 633, + ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17365,9 +17991,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1053 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" + // Pos:1091 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" { - ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 633, + ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17381,9 +18007,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1054 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" + // Pos:1092 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" { - ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 634, + ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 656, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17397,9 +18023,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1055 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" + // Pos:1093 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" { - ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 635, + ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 657, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17413,9 +18039,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1056 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" + // Pos:1094 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" { - ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 635, + ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 657, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17429,9 +18055,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1057 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" + // Pos:1095 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" { - ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 635, + ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 657, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17445,9 +18071,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1058 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" + // Pos:1096 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" { - ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 635, + ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 657, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17461,9 +18087,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1059 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" + // Pos:1097 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" { - ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 636, + ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 658, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17477,9 +18103,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1060 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" + // Pos:1098 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" { - ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 636, + ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 658, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17493,9 +18119,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1061 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" + // Pos:1099 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" { - ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 636, + ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 658, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17509,9 +18135,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1062 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" + // Pos:1100 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" { - ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 636, + ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 658, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17525,9 +18151,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1063 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" + // Pos:1101 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" { - ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 637, + ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 659, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17541,9 +18167,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1064 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" + // Pos:1102 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" { - ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 637, + ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 659, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17557,9 +18183,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1065 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" + // Pos:1103 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" { - ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 638, + ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 660, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17573,9 +18199,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1066 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" + // Pos:1104 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" { - ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 638, + ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 660, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17589,9 +18215,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1067 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" + // Pos:1105 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" { - ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 639, + ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 661, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17605,9 +18231,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1068 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" + // Pos:1106 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" { - ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 639, + ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 661, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17621,9 +18247,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1069 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" + // Pos:1107 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" { - ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 640, + ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 662, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17637,9 +18263,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1070 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" + // Pos:1108 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" { - ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 640, + ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 662, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17653,9 +18279,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1071 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" + // Pos:1109 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" { - ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 641, + ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 663, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17669,9 +18295,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1072 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" + // Pos:1110 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" { - ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 641, + ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 663, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17685,9 +18311,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1073 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" + // Pos:1111 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" { - ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 642, + ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 664, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17701,9 +18327,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1074 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" + // Pos:1112 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" { - ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 642, + ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 664, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17717,9 +18343,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1075 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" + // Pos:1113 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" { - ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 643, + ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 665, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17733,9 +18359,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1076 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" + // Pos:1114 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" { - ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 643, + ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 665, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17749,9 +18375,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1077 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" + // Pos:1115 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" { - ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 644, + ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 666, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17765,9 +18391,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1078 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" + // Pos:1116 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" { - ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 644, + ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 666, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17781,9 +18407,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1079 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" + // Pos:1117 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" { - ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 645, + ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 667, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -17797,9 +18423,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1080 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" + // Pos:1118 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" { - ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 646, + ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 668, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -17814,9 +18440,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1081 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" + // Pos:1119 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" { - ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 647, + ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 669, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NO66|ND_FLAG_MODRM, ND_CFF_PTWRITE, @@ -17829,9 +18455,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1082 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" + // Pos:1120 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" { - ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 648, + ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 670, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17845,9 +18471,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1083 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" + // Pos:1121 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" { - ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 648, + ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 670, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17861,9 +18487,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1084 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" + // Pos:1122 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" { - ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 649, + ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 671, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17877,9 +18503,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1085 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" + // Pos:1123 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" { - ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 649, + ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 671, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17893,9 +18519,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1086 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" + // Pos:1124 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" { - ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 650, + ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 672, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17909,9 +18535,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1087 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" + // Pos:1125 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" { - ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 651, + ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 673, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17925,9 +18551,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1088 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" + // Pos:1126 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" { - ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 651, + ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 673, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17941,9 +18567,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1089 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" + // Pos:1127 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" { - ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 652, + ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 674, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17957,9 +18583,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1090 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" + // Pos:1128 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" { - ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 652, + ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 674, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17973,9 +18599,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1091 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" + // Pos:1129 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" { - ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 653, + ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 675, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17989,9 +18615,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1092 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" + // Pos:1130 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" { - ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 653, + ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 675, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -18005,9 +18631,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1093 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" + // Pos:1131 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" { - ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 654, + ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 676, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -18021,9 +18647,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1094 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" + // Pos:1132 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" { - ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 655, + ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 677, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -18037,9 +18663,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1095 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" + // Pos:1133 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" { - ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 655, + ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 677, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -18053,9 +18679,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1096 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" + // Pos:1134 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18069,9 +18695,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1097 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" + // Pos:1135 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18085,9 +18711,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1098 Instruction:"PUSH ES" Encoding:"0x06"/"" + // Pos:1136 Instruction:"PUSH ES" Encoding:"0x06"/"" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -18101,9 +18727,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1099 Instruction:"PUSH CS" Encoding:"0x0E"/"" + // Pos:1137 Instruction:"PUSH CS" Encoding:"0x0E"/"" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -18113,13 +18739,13 @@ const ND_INSTRUCTION gInstructions[2701] = 0, { OP(ND_OPT_SEG_CS, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, - // Pos:1100 Instruction:"PUSH SS" Encoding:"0x16"/"" + // Pos:1138 Instruction:"PUSH SS" Encoding:"0x16"/"" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -18133,9 +18759,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1101 Instruction:"PUSH DS" Encoding:"0x1E"/"" + // Pos:1139 Instruction:"PUSH DS" Encoding:"0x1E"/"" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -18149,9 +18775,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1102 Instruction:"PUSH Zv" Encoding:"0x50"/"O" + // Pos:1140 Instruction:"PUSH Zv" Encoding:"0x50"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18165,9 +18791,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1103 Instruction:"PUSH Zv" Encoding:"0x51"/"O" + // Pos:1141 Instruction:"PUSH Zv" Encoding:"0x51"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18181,9 +18807,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1104 Instruction:"PUSH Zv" Encoding:"0x52"/"O" + // Pos:1142 Instruction:"PUSH Zv" Encoding:"0x52"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18197,9 +18823,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1105 Instruction:"PUSH Zv" Encoding:"0x53"/"O" + // Pos:1143 Instruction:"PUSH Zv" Encoding:"0x53"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18213,9 +18839,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1106 Instruction:"PUSH Zv" Encoding:"0x54"/"O" + // Pos:1144 Instruction:"PUSH Zv" Encoding:"0x54"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18229,9 +18855,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1107 Instruction:"PUSH Zv" Encoding:"0x55"/"O" + // Pos:1145 Instruction:"PUSH Zv" Encoding:"0x55"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18245,9 +18871,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1108 Instruction:"PUSH Zv" Encoding:"0x56"/"O" + // Pos:1146 Instruction:"PUSH Zv" Encoding:"0x56"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18261,9 +18887,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1109 Instruction:"PUSH Zv" Encoding:"0x57"/"O" + // Pos:1147 Instruction:"PUSH Zv" Encoding:"0x57"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18277,9 +18903,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1110 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" + // Pos:1148 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18293,9 +18919,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1111 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" + // Pos:1149 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18309,9 +18935,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1112 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" + // Pos:1150 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, @@ -18325,9 +18951,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1113 Instruction:"PUSHA" Encoding:"ds16 0x60"/"" + // Pos:1151 Instruction:"PUSHA" Encoding:"ds16 0x60"/"" { - ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 657, + ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -18341,9 +18967,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1114 Instruction:"PUSHAD" Encoding:"ds32 0x60"/"" + // Pos:1152 Instruction:"PUSHAD" Encoding:"ds32 0x60"/"" { - ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 658, + ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 680, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -18357,9 +18983,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1115 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" + // Pos:1153 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" { - ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 659, + ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 681, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18373,9 +18999,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1116 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" + // Pos:1154 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" { - ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 660, + ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 682, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18389,9 +19015,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1117 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" + // Pos:1155 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" { - ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 661, + ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 683, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18405,9 +19031,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1118 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" + // Pos:1156 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" { - ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 662, + ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 684, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, @@ -18423,9 +19049,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1119 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" + // Pos:1157 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" { - ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 663, + ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 685, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -18439,9 +19065,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1120 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" + // Pos:1158 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" { - ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 663, + ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 685, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -18455,9 +19081,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1121 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" + // Pos:1159 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 664, + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18472,9 +19098,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1122 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" + // Pos:1160 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 664, + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18489,9 +19115,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1123 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" + // Pos:1161 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 664, + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18506,9 +19132,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1124 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" + // Pos:1162 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 664, + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18523,9 +19149,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1125 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" + // Pos:1163 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 664, + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18540,9 +19166,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1126 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" + // Pos:1164 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 664, + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18557,9 +19183,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1127 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" + // Pos:1165 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" { - ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 665, + ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 687, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -18573,9 +19199,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1128 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" + // Pos:1166 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" { - ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 666, + ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 688, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -18589,9 +19215,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1129 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" + // Pos:1167 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 667, + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 689, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18606,9 +19232,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1130 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" + // Pos:1168 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 667, + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 689, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18623,9 +19249,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1131 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" + // Pos:1169 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 667, + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 689, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18640,9 +19266,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1132 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" + // Pos:1170 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 667, + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 689, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18657,9 +19283,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1133 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" + // Pos:1171 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 667, + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 689, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18674,9 +19300,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1134 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" + // Pos:1172 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 667, + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 689, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18691,9 +19317,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1135 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M" + // Pos:1173 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M" { - ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 668, + ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 690, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, @@ -18707,9 +19333,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1136 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M" + // Pos:1174 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M" { - ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 669, + ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 691, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, @@ -18723,9 +19349,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1137 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" + // Pos:1175 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" { - ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 670, + ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 692, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MSR, @@ -18741,9 +19367,26 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1138 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" + // Pos:1176 Instruction:"RDMSRLIST" Encoding:"0xF2 0x0F 0x01 /0xC6"/"" { - ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 671, + ND_INS_RDMSRLIST, ND_CAT_SYSTEM, ND_SET_MSRLIST, 693, + 0, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_MSRLIST, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_MEM_SMSRT, ND_OPS_4096, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_MEM_DMSRT, ND_OPS_4096, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1177 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" + { + ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 694, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPID, @@ -18757,9 +19400,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1139 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" + // Pos:1178 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" { - ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 672, + ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 695, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, @@ -18775,9 +19418,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1140 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" + // Pos:1179 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" { - ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 673, + ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 696, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -18793,9 +19436,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1141 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/"" + // Pos:1180 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/"" { - ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 674, + ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 697, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, @@ -18811,9 +19454,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1142 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M" + // Pos:1181 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M" { - ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 675, + ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 698, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, @@ -18827,9 +19470,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1143 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" + // Pos:1182 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" { - ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 675, + ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 698, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, @@ -18843,9 +19486,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1144 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M" + // Pos:1183 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M" { - ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 676, + ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 699, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, @@ -18859,9 +19502,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1145 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" + // Pos:1184 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" { - ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 676, + ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 699, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, @@ -18875,9 +19518,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1146 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M" + // Pos:1185 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M" { - ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 677, + ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 700, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18890,9 +19533,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1147 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M" + // Pos:1186 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M" { - ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 678, + ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 701, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -18906,9 +19549,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1148 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M" + // Pos:1187 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M" { - ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 679, + ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -18922,9 +19565,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1149 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" + // Pos:1188 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" { - ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 680, + ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 703, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -18939,9 +19582,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1150 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" + // Pos:1189 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" { - ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 681, + ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 704, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDTSCP, @@ -18958,9 +19601,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1151 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" + // Pos:1190 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" { - ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 682, + ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 705, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -18977,9 +19620,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1152 Instruction:"RETF" Encoding:"0xCB"/"" + // Pos:1191 Instruction:"RETF" Encoding:"0xCB"/"" { - ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 682, + ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 705, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -18995,9 +19638,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1153 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" + // Pos:1192 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" { - ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 683, + ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 706, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -19014,9 +19657,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1154 Instruction:"RETN" Encoding:"0xC3"/"" + // Pos:1193 Instruction:"RETN" Encoding:"0xC3"/"" { - ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 683, + ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 706, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -19031,9 +19674,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1155 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" + // Pos:1194 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" { - ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 684, + ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 707, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, @@ -19050,9 +19693,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1156 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" + // Pos:1195 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" { - ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 685, + ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 708, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, @@ -19067,9 +19710,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1157 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" + // Pos:1196 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 686, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 709, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19084,9 +19727,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1158 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" + // Pos:1197 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 686, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 709, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19101,9 +19744,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1159 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" + // Pos:1198 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 686, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 709, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19118,9 +19761,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1160 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" + // Pos:1199 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 686, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 709, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19135,9 +19778,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1161 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" + // Pos:1200 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 686, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 709, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19152,9 +19795,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1162 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" + // Pos:1201 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 686, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 709, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19169,9 +19812,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1163 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" + // Pos:1202 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 687, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19186,9 +19829,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1164 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" + // Pos:1203 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 687, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19203,9 +19846,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1165 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" + // Pos:1204 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 687, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19220,9 +19863,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1166 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" + // Pos:1205 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 687, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19237,9 +19880,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1167 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" + // Pos:1206 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 687, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19254,9 +19897,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1168 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" + // Pos:1207 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 687, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19271,9 +19914,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1169 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" + // Pos:1208 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" { - ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 688, + ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 711, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -19288,9 +19931,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1170 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" + // Pos:1209 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" { - ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 689, + ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -19305,9 +19948,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1171 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" + // Pos:1210 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" { - ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 690, + ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 713, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -19322,9 +19965,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1172 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" + // Pos:1211 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" { - ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 691, + ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 714, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -19339,9 +19982,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1173 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" + // Pos:1212 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" { - ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 692, + ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 715, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -19356,9 +19999,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1174 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM" + // Pos:1213 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM" { - ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 693, + ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 716, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19372,9 +20015,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1175 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M" + // Pos:1214 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M" { - ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 694, + ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 717, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19387,9 +20030,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1176 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" + // Pos:1215 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" { - ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 695, + ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 718, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -19404,9 +20047,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1177 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" + // Pos:1216 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" { - ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 696, + ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 719, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -19420,9 +20063,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1178 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" + // Pos:1217 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" { - ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 697, + ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 720, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -19436,9 +20079,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1179 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" + // Pos:1218 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" { - ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 698, + ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 721, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -19452,9 +20095,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1180 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M" + // Pos:1219 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M" { - ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 699, + ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 722, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19467,9 +20110,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1181 Instruction:"SAHF" Encoding:"0x9E"/"" + // Pos:1220 Instruction:"SAHF" Encoding:"0x9E"/"" { - ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 700, + ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 723, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19483,9 +20126,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1182 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" + // Pos:1221 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 701, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 724, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19500,9 +20143,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1183 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" + // Pos:1222 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 701, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 724, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19517,9 +20160,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1184 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" + // Pos:1223 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 701, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 724, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19534,9 +20177,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1185 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" + // Pos:1224 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 701, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 724, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19551,9 +20194,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1186 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" + // Pos:1225 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 701, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 724, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19568,9 +20211,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1187 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" + // Pos:1226 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 701, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 724, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19585,9 +20228,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1188 Instruction:"SALC" Encoding:"0xD6"/"" + // Pos:1227 Instruction:"SALC" Encoding:"0xD6"/"" { - ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 702, + ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 725, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19601,9 +20244,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1189 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" + // Pos:1228 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 703, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19618,9 +20261,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1190 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" + // Pos:1229 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 703, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19635,9 +20278,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1191 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" + // Pos:1230 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 703, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19652,9 +20295,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1192 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" + // Pos:1231 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 703, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19669,9 +20312,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1193 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" + // Pos:1232 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 703, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19686,9 +20329,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1194 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" + // Pos:1233 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 703, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19703,9 +20346,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1195 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" + // Pos:1234 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" { - ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 704, + ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 727, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -19720,9 +20363,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1196 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" + // Pos:1235 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" { - ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 705, + ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 728, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -19736,9 +20379,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1197 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" + // Pos:1236 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19753,9 +20396,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1198 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" + // Pos:1237 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19770,9 +20413,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1199 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" + // Pos:1238 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19787,9 +20430,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1200 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" + // Pos:1239 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19804,9 +20447,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1201 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" + // Pos:1240 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19821,9 +20464,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1202 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" + // Pos:1241 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19838,9 +20481,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1203 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" + // Pos:1242 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19855,9 +20498,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1204 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" + // Pos:1243 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19872,9 +20515,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1205 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" + // Pos:1244 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -19889,9 +20532,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1206 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" + // Pos:1245 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 706, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19906,9 +20549,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1207 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" + // Pos:1246 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 707, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 730, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19924,9 +20567,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1208 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" + // Pos:1247 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 707, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 730, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19943,9 +20586,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1209 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" + // Pos:1248 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 708, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 731, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19961,9 +20604,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1210 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" + // Pos:1249 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 708, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 731, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19980,9 +20623,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1211 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" + // Pos:1250 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 709, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19998,9 +20641,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1212 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" + // Pos:1251 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 709, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20017,9 +20660,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1213 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" + // Pos:1252 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 710, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20035,9 +20678,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1214 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" + // Pos:1253 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 710, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20054,9 +20697,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1215 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" + // Pos:1254 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" { - ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 711, + ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 734, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -20069,9 +20712,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1216 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" + // Pos:1255 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" { - ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 712, + ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 735, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -20088,9 +20731,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1217 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" + // Pos:1256 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" { - ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 713, + ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 736, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -20103,9 +20746,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1218 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M" + // Pos:1257 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M" { - ND_INS_SENDUIPI, ND_CAT_UINTR, ND_SET_UINTR, 714, + ND_INS_SENDUIPI, ND_CAT_UINTR, ND_SET_UINTR, 737, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, @@ -20118,9 +20761,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1219 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" + // Pos:1258 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" { - ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 715, + ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 738, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_SERIALIZE, @@ -20133,9 +20776,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1220 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" + // Pos:1259 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 716, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 739, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20149,9 +20792,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1221 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" + // Pos:1260 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 717, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 740, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20165,9 +20808,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1222 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" + // Pos:1261 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 718, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 741, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20181,9 +20824,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1223 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" + // Pos:1262 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 719, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 742, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20197,9 +20840,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1224 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" + // Pos:1263 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 720, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 743, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20213,9 +20856,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1225 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" + // Pos:1264 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 721, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 744, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20229,9 +20872,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1226 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" + // Pos:1265 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 722, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 745, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20245,9 +20888,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1227 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" + // Pos:1266 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 723, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 746, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20261,9 +20904,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1228 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" + // Pos:1267 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 724, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 747, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20277,9 +20920,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1229 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" + // Pos:1268 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 725, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 748, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20293,9 +20936,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1230 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" + // Pos:1269 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 726, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 749, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20309,9 +20952,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1231 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" + // Pos:1270 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 727, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 750, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20325,9 +20968,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1232 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" + // Pos:1271 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 728, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 751, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20341,9 +20984,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1233 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" + // Pos:1272 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 729, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 752, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20357,9 +21000,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1234 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" + // Pos:1273 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 730, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 753, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20373,9 +21016,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1235 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" + // Pos:1274 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" { - ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 731, + ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 754, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -20389,9 +21032,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1236 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" + // Pos:1275 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 732, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 755, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20405,9 +21048,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1237 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" + // Pos:1276 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" { - ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 733, + ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 756, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -20420,9 +21063,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1238 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" + // Pos:1277 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" { - ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 734, + ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 757, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20436,9 +21079,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1239 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" + // Pos:1278 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" { - ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 735, + ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 758, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20452,9 +21095,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1240 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" + // Pos:1279 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" { - ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 736, + ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 759, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20468,9 +21111,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1241 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" + // Pos:1280 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" { - ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 737, + ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 760, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20484,9 +21127,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1242 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" + // Pos:1281 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" { - ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 738, + ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 761, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20501,9 +21144,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1243 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" + // Pos:1282 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" { - ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 739, + ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 762, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20517,9 +21160,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1244 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" + // Pos:1283 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" { - ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 740, + ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 763, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20533,9 +21176,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1245 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" + // Pos:1284 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" { - ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 741, + ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 764, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20550,9 +21193,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1246 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" + // Pos:1285 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 742, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 765, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20567,9 +21210,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1247 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" + // Pos:1286 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 742, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 765, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20584,9 +21227,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1248 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" + // Pos:1287 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 742, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 765, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20601,9 +21244,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1249 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" + // Pos:1288 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 742, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 765, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20618,9 +21261,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1250 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" + // Pos:1289 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 742, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 765, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20635,9 +21278,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1251 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" + // Pos:1290 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 742, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 765, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20652,9 +21295,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1252 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" + // Pos:1291 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" { - ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 743, + ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 766, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20670,9 +21313,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1253 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" + // Pos:1292 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" { - ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 743, + ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 766, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20688,9 +21331,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1254 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" + // Pos:1293 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" { - ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 744, + ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 767, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -20705,9 +21348,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1255 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" + // Pos:1294 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 745, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 768, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20722,9 +21365,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1256 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" + // Pos:1295 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 745, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 768, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20739,9 +21382,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1257 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" + // Pos:1296 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 745, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 768, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20756,9 +21399,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1258 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" + // Pos:1297 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 745, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 768, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20773,9 +21416,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1259 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" + // Pos:1298 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 745, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 768, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20790,9 +21433,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1260 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" + // Pos:1299 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 745, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 768, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20807,9 +21450,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1261 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" + // Pos:1300 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" { - ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 746, + ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 769, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20825,9 +21468,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1262 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" + // Pos:1301 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" { - ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 746, + ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 769, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20843,9 +21486,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1263 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" + // Pos:1302 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" { - ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 747, + ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 770, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -20860,9 +21503,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1264 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" + // Pos:1303 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" { - ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 748, + ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 771, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -20877,9 +21520,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1265 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" + // Pos:1304 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" { - ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 749, + ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 772, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -20894,9 +21537,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1266 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" + // Pos:1305 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" { - ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 750, + ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 773, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20910,9 +21553,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1267 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" + // Pos:1306 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" { - ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 751, + ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 774, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -20925,9 +21568,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1268 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" + // Pos:1307 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" { - ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 752, + ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 775, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20941,9 +21584,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1269 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" + // Pos:1308 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" { - ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 752, + ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 775, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20957,9 +21600,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1270 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" + // Pos:1309 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" { - ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 753, + ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 776, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, @@ -20972,9 +21615,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1271 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/"" + // Pos:1310 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/"" { - ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 754, + ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 777, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20987,9 +21630,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1272 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" + // Pos:1311 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" { - ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 755, + ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 778, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21003,9 +21646,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1273 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" + // Pos:1312 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" { - ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 755, + ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 778, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21019,9 +21662,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1274 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" + // Pos:1313 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" { - ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 756, + ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 779, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21034,9 +21677,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1275 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" + // Pos:1314 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 757, + ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 780, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -21050,9 +21693,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1276 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" + // Pos:1315 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 758, + ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 781, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -21066,9 +21709,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1277 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" + // Pos:1316 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 759, + ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 782, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -21082,9 +21725,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1278 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" + // Pos:1317 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 760, + ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 783, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -21098,9 +21741,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1279 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" + // Pos:1318 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" { - ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 761, + ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 784, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, @@ -21113,9 +21756,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1280 Instruction:"STC" Encoding:"0xF9"/"" + // Pos:1319 Instruction:"STC" Encoding:"0xF9"/"" { - ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 762, + ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 785, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21128,9 +21771,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1281 Instruction:"STD" Encoding:"0xFD"/"" + // Pos:1320 Instruction:"STD" Encoding:"0xFD"/"" { - ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 763, + ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 786, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21143,9 +21786,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1282 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" + // Pos:1321 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" { - ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 764, + ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 787, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -21158,9 +21801,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1283 Instruction:"STI" Encoding:"0xFB"/"" + // Pos:1322 Instruction:"STI" Encoding:"0xFB"/"" { - ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 765, + ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 788, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21173,9 +21816,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1284 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" + // Pos:1323 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" { - ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 766, + ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 789, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -21189,9 +21832,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1285 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" + // Pos:1324 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 767, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 790, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21207,9 +21850,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1286 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" + // Pos:1325 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 767, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 790, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21226,9 +21869,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1287 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" + // Pos:1326 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 768, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 791, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21244,9 +21887,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1288 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" + // Pos:1327 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 768, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 791, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21263,9 +21906,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1289 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" + // Pos:1328 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 769, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21281,9 +21924,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1290 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" + // Pos:1329 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 769, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21300,9 +21943,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1291 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" + // Pos:1330 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 770, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21318,9 +21961,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1292 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" + // Pos:1331 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 770, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21337,9 +21980,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1293 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" + // Pos:1332 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" { - ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 771, + ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 794, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21353,9 +21996,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1294 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" + // Pos:1333 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" { - ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 771, + ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 794, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21369,9 +22012,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1295 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" + // Pos:1334 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" { - ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 772, + ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 795, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -21384,9 +22027,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1296 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/"" + // Pos:1335 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/"" { - ND_INS_STUI, ND_CAT_UINTR, ND_SET_UINTR, 773, + ND_INS_STUI, ND_CAT_UINTR, ND_SET_UINTR, 796, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, @@ -21399,9 +22042,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1297 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" + // Pos:1336 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21416,9 +22059,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1298 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" + // Pos:1337 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21433,9 +22076,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1299 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" + // Pos:1338 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21450,9 +22093,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1300 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" + // Pos:1339 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21467,9 +22110,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1301 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" + // Pos:1340 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21484,9 +22127,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1302 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" + // Pos:1341 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21501,9 +22144,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1303 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" + // Pos:1342 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21518,9 +22161,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1304 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" + // Pos:1343 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21535,9 +22178,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1305 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" + // Pos:1344 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -21552,9 +22195,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1306 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" + // Pos:1345 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 774, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21569,9 +22212,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1307 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" + // Pos:1346 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" { - ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 775, + ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 798, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -21585,9 +22228,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1308 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" + // Pos:1347 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" { - ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 776, + ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 799, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -21601,9 +22244,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1309 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" + // Pos:1348 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" { - ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 777, + ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 800, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -21617,9 +22260,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1310 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" + // Pos:1349 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" { - ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 778, + ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 801, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -21633,9 +22276,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1311 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR" + // Pos:1350 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR" { - ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 779, + ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 802, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21649,9 +22292,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1312 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M" + // Pos:1351 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M" { - ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 780, + ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 803, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21664,9 +22307,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1313 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M" + // Pos:1352 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M" { - ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 781, + ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 804, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21679,9 +22322,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1314 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" + // Pos:1353 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" { - ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 782, + ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 805, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -21695,9 +22338,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1315 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" + // Pos:1354 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" { - ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 783, + ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 806, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 10), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT, ND_CFF_FSC, @@ -21719,9 +22362,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1316 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" + // Pos:1355 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" { - ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 784, + ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 807, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT, ND_CFF_SEP, @@ -21742,9 +22385,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1317 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" + // Pos:1356 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" { - ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 785, + ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 808, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_SEP, @@ -21761,9 +22404,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1318 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" + // Pos:1357 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" { - ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 786, + ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 809, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_FSC, @@ -21783,9 +22426,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1319 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" + // Pos:1358 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" { - ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 787, + ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 810, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -21799,9 +22442,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1320 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" + // Pos:1359 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" { - ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 788, + ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 811, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21814,9 +22457,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1321 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" + // Pos:1360 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" { - ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 789, + ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 812, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, @@ -21831,9 +22474,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1322 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" + // Pos:1361 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 790, + ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 813, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, @@ -21848,9 +22491,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1323 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" + // Pos:1362 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 791, + ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 814, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, @@ -21865,9 +22508,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1324 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" + // Pos:1363 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 792, + ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 815, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, @@ -21882,9 +22525,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1325 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" + // Pos:1364 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 793, + ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 816, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, @@ -21899,9 +22542,26 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1326 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" + // Pos:1365 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/"" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, + ND_INS_TDPFP16PS, ND_CAT_AMX, ND_SET_AMXFP16, 817, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXFP16, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1366 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21916,9 +22576,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1327 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" + // Pos:1367 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21933,9 +22593,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1328 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" + // Pos:1368 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21950,9 +22610,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1329 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" + // Pos:1369 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21967,9 +22627,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1330 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" + // Pos:1370 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21984,9 +22644,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1331 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" + // Pos:1371 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22001,9 +22661,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1332 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" + // Pos:1372 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22018,9 +22678,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1333 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" + // Pos:1373 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 794, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22035,9 +22695,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1334 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/"" + // Pos:1374 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/"" { - ND_INS_TESTUI, ND_CAT_UINTR, ND_SET_UINTR, 795, + ND_INS_TESTUI, ND_CAT_UINTR, ND_SET_UINTR, 819, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, @@ -22051,9 +22711,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1335 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:1375 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" { - ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 796, + ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 820, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -22067,9 +22727,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1336 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:1376 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" { - ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 797, + ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 821, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -22083,9 +22743,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1337 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" + // Pos:1377 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" { - ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 798, + ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 822, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -22098,9 +22758,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1338 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:1378 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" { - ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 799, + ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 823, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -22114,9 +22774,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1339 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" + // Pos:1379 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" { - ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 800, + ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 824, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -22129,9 +22789,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1340 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/"" + // Pos:1380 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/"" { - ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 801, + ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 825, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, @@ -22144,9 +22804,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1341 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" + // Pos:1381 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" { - ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 802, + ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 826, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, @@ -22162,9 +22822,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1342 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM" + // Pos:1382 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM" { - ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 803, + ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 827, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, @@ -22179,9 +22839,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1343 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" + // Pos:1383 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" { - ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 804, + ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 828, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -22195,9 +22855,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1344 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" + // Pos:1384 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" { - ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 805, + ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 829, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -22212,9 +22872,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1345 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" + // Pos:1385 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" { - ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 806, + ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 830, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -22229,9 +22889,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1346 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" + // Pos:1386 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" { - ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 807, + ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 831, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22245,9 +22905,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1347 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" + // Pos:1387 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" { - ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 808, + ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 832, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22261,9 +22921,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1348 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" + // Pos:1388 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" { - ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 809, + ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 833, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -22276,9 +22936,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1349 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/"" + // Pos:1389 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/"" { - ND_INS_UIRET, ND_CAT_RET, ND_SET_UINTR, 810, + ND_INS_UIRET, ND_CAT_RET, ND_SET_UINTR, 834, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 6), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, @@ -22296,9 +22956,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1350 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" + // Pos:1390 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" { - ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 811, + ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 835, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, @@ -22312,9 +22972,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1351 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" + // Pos:1391 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" { - ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 812, + ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 836, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, @@ -22329,9 +22989,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1352 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" + // Pos:1392 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" { - ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 813, + ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 837, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -22345,9 +23005,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1353 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" + // Pos:1393 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" { - ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 814, + ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 838, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -22361,9 +23021,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1354 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" + // Pos:1394 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" { - ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 815, + ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 839, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -22377,9 +23037,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1355 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" + // Pos:1395 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" { - ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 816, + ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 840, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -22393,9 +23053,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1356 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" + // Pos:1396 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" { - ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 817, + ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 841, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, @@ -22411,9 +23071,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1357 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" + // Pos:1397 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" { - ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 818, + ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 842, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, @@ -22429,9 +23089,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1358 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" + // Pos:1398 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" { - ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 819, + ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 843, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, @@ -22447,9 +23107,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1359 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" + // Pos:1399 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" { - ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 820, + ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 844, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, @@ -22465,9 +23125,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1360 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" + // Pos:1400 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" { - ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 821, + ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 845, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22483,9 +23143,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1361 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" + // Pos:1401 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" { - ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 821, + ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 845, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22500,9 +23160,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1362 Instruction:"VADDPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM" + // Pos:1402 Instruction:"VADDPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM" { - ND_INS_VADDPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 822, + ND_INS_VADDPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 846, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -22518,9 +23178,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1363 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" + // Pos:1403 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" { - ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 823, + ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 847, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22536,9 +23196,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1364 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" + // Pos:1404 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" { - ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 823, + ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 847, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22553,9 +23213,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1365 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" + // Pos:1405 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" { - ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 824, + ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 848, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22571,9 +23231,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1366 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" + // Pos:1406 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" { - ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 824, + ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 848, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22588,9 +23248,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1367 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM" + // Pos:1407 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM" { - ND_INS_VADDSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 825, + ND_INS_VADDSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 849, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -22606,9 +23266,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1368 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" + // Pos:1408 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" { - ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 826, + ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 850, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22624,9 +23284,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1369 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" + // Pos:1409 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" { - ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 826, + ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 850, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22641,9 +23301,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1370 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" + // Pos:1410 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" { - ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 827, + ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 851, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22658,9 +23318,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1371 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" + // Pos:1411 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" { - ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 828, + ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 852, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22675,9 +23335,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1372 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:1412 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { - ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 829, + ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 853, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, @@ -22692,9 +23352,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1373 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:1413 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { - ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 829, + ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 853, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -22709,9 +23369,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1374 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:1414 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { - ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 830, + ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 854, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, @@ -22726,9 +23386,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1375 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:1415 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { - ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 830, + ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 854, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -22743,9 +23403,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1376 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:1416 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { - ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 831, + ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 855, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, @@ -22760,9 +23420,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1377 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:1417 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { - ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 831, + ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 855, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -22777,9 +23437,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1378 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:1418 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { - ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 832, + ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 856, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, @@ -22794,9 +23454,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1379 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:1419 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { - ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 832, + ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 856, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -22811,9 +23471,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1380 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" + // Pos:1420 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" { - ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 833, + ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 857, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -22827,9 +23487,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1381 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" + // Pos:1421 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" { - ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 834, + ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 858, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -22844,9 +23504,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1382 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" + // Pos:1422 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" { - ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 835, + ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 859, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22863,9 +23523,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1383 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" + // Pos:1423 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" { - ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 836, + ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 860, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22882,9 +23542,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1384 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" + // Pos:1424 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" { - ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 837, + ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 861, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -22900,9 +23560,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1385 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" + // Pos:1425 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" { - ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 837, + ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 861, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22917,9 +23577,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1386 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" + // Pos:1426 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" { - ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 838, + ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 862, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -22935,9 +23595,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1387 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" + // Pos:1427 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" { - ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 838, + ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 862, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22952,9 +23612,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1388 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" + // Pos:1428 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" { - ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 839, + ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 863, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -22970,9 +23630,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1389 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" + // Pos:1429 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" { - ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 839, + ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 863, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22987,9 +23647,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1390 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" + // Pos:1430 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" { - ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 840, + ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 864, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23005,9 +23665,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1391 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" + // Pos:1431 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" { - ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 840, + ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 864, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23022,9 +23682,41 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1392 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" + // Pos:1432 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM" { - ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 841, + ND_INS_VBCSTNEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 865, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1433 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM" + { + ND_INS_VBCSTNESH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 866, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1434 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" + { + ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 867, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23040,9 +23732,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1393 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" + // Pos:1435 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" { - ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 842, + ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 868, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23058,9 +23750,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1394 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" + // Pos:1436 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" { - ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 843, + ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 869, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23076,9 +23768,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1395 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" + // Pos:1437 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" { - ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 844, + ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 870, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23094,9 +23786,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1396 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" + // Pos:1438 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" { - ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 845, + ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 871, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23112,9 +23804,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1397 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" + // Pos:1439 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" { - ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 846, + ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 872, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23130,9 +23822,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1398 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" + // Pos:1440 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" { - ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 847, + ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 873, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23146,9 +23838,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1399 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" + // Pos:1441 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" { - ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 848, + ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 874, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23163,9 +23855,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1400 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" + // Pos:1442 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" { - ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 849, + ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 875, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23180,9 +23872,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1401 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" + // Pos:1443 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" { - ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 850, + ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 876, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23197,9 +23889,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1402 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" + // Pos:1444 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" { - ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 851, + ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 877, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23214,9 +23906,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1403 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" + // Pos:1445 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" { - ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 852, + ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 878, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23231,9 +23923,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1404 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" + // Pos:1446 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" { - ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 853, + ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 879, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -23247,9 +23939,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1405 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" + // Pos:1447 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" { - ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 854, + ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 880, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23264,9 +23956,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1406 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" + // Pos:1448 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" { - ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 855, + ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 881, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23281,9 +23973,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1407 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" + // Pos:1449 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" { - ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 856, + ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 882, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23298,9 +23990,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1408 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" + // Pos:1450 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" { - ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 857, + ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 883, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23315,9 +24007,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1409 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" + // Pos:1451 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" { - ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 858, + ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 884, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23332,9 +24024,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1410 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" + // Pos:1452 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" { - ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 859, + ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 885, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23349,9 +24041,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1411 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" + // Pos:1453 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" { - ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 859, + ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 885, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23365,9 +24057,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1412 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" + // Pos:1454 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" { - ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 860, + ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 886, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23382,9 +24074,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1413 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" + // Pos:1455 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" { - ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 860, + ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 886, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23398,9 +24090,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1414 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" + // Pos:1456 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 861, + ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 887, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23417,9 +24109,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1415 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" + // Pos:1457 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 861, + ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 887, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23435,9 +24127,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1416 Instruction:"VCMPPH rK{K},aKq,Hn,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:1458 Instruction:"VCMPPH rK{K},aKq,Hn,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 862, + ND_INS_VCMPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 888, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -23454,9 +24146,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1417 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:1459 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 863, + ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 889, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23473,9 +24165,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1418 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:1460 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 863, + ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 889, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23491,9 +24183,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1419 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" + // Pos:1461 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 864, + ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 890, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23510,9 +24202,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1420 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:1462 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 864, + ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 890, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23528,9 +24220,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1421 Instruction:"VCMPSH rK{K},aKq,Hn,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI" + // Pos:1463 Instruction:"VCMPSH rK{K},aKq,Hn,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 865, + ND_INS_VCMPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 891, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -23547,9 +24239,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1422 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:1464 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 866, + ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 892, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23566,9 +24258,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1423 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:1465 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 866, + ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 892, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23584,9 +24276,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1424 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" + // Pos:1466 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" { - ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 867, + ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 893, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23601,9 +24293,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1425 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" + // Pos:1467 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" { - ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 867, + ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 893, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23618,9 +24310,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1426 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM" + // Pos:1468 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM" { - ND_INS_VCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 868, + ND_INS_VCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 894, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -23635,9 +24327,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1427 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" + // Pos:1469 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" { - ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 869, + ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 895, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23652,9 +24344,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1428 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" + // Pos:1470 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" { - ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 869, + ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 895, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23669,9 +24361,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1429 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" + // Pos:1471 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" { - ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 870, + ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 896, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23686,9 +24378,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1430 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" + // Pos:1472 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" { - ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 871, + ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 897, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23703,9 +24395,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1431 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" + // Pos:1473 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 872, + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 898, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23720,9 +24412,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1432 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" + // Pos:1474 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 872, + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 898, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23736,9 +24428,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1433 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" + // Pos:1475 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 872, + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 898, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23752,9 +24444,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1434 Instruction:"VCVTDQ2PH Vh{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM" + // Pos:1476 Instruction:"VCVTDQ2PH Vh{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 873, + ND_INS_VCVTDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 899, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -23769,9 +24461,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1435 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" + // Pos:1477 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 874, + ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 900, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23786,9 +24478,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1436 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" + // Pos:1478 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" { - ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 874, + ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 900, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23802,9 +24494,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1437 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" + // Pos:1479 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" { - ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 875, + ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 901, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, @@ -23820,9 +24512,73 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1438 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" + // Pos:1480 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM" { - ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 876, + ND_INS_VCVTNEEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 902, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1481 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM" + { + ND_INS_VCVTNEEPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 903, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1482 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM" + { + ND_INS_VCVTNEOBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 904, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1483 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM" + { + ND_INS_VCVTNEOPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 905, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1484 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" + { + ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 906, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, @@ -23837,9 +24593,25 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1439 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" + // Pos:1485 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM" + { + ND_INS_VCVTNEPS2BF16, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 906, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1486 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" { - ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 877, + ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 907, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23854,9 +24626,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1440 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" + // Pos:1487 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" { - ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 877, + ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 907, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23870,9 +24642,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1441 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM" + // Pos:1488 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM" { - ND_INS_VCVTPD2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 878, + ND_INS_VCVTPD2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 908, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -23887,9 +24659,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1442 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" + // Pos:1489 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 879, + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 909, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23904,9 +24676,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1443 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" + // Pos:1490 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 879, + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 909, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23920,9 +24692,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1444 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" + // Pos:1491 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 879, + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 909, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23936,9 +24708,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1445 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" + // Pos:1492 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" { - ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 880, + ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 910, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23953,9 +24725,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1446 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" + // Pos:1493 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" { - ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 881, + ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 911, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23970,9 +24742,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1447 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" + // Pos:1494 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" { - ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 882, + ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 912, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23987,9 +24759,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1448 Instruction:"VCVTPH2DQ Vn{K}{z},aKq,Wh|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM" + // Pos:1495 Instruction:"VCVTPH2DQ Vn{K}{z},aKq,Wh|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 883, + ND_INS_VCVTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 913, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24004,9 +24776,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1449 Instruction:"VCVTPH2PD Vn{K}{z},aKq,Wf|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM" + // Pos:1496 Instruction:"VCVTPH2PD Vn{K}{z},aKq,Wf|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM" { - ND_INS_VCVTPH2PD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 884, + ND_INS_VCVTPH2PD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 914, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24021,9 +24793,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1450 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" + // Pos:1497 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 885, + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 915, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24038,9 +24810,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1451 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" + // Pos:1498 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 885, + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 915, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, @@ -24054,9 +24826,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1452 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" + // Pos:1499 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 885, + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 915, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, @@ -24070,9 +24842,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1453 Instruction:"VCVTPH2PSX Vn{K}{z},aKq,Wh|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM" + // Pos:1500 Instruction:"VCVTPH2PSX Vn{K}{z},aKq,Wh|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM" { - ND_INS_VCVTPH2PSX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 886, + ND_INS_VCVTPH2PSX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 916, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24087,9 +24859,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1454 Instruction:"VCVTPH2QQ Vn{K}{z},aKq,Wf|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM" + // Pos:1501 Instruction:"VCVTPH2QQ Vn{K}{z},aKq,Wf|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM" { - ND_INS_VCVTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 887, + ND_INS_VCVTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 917, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24104,9 +24876,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1455 Instruction:"VCVTPH2UDQ Vn{K}{z},aKq,Wh|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM" + // Pos:1502 Instruction:"VCVTPH2UDQ Vn{K}{z},aKq,Wh|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VCVTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 888, + ND_INS_VCVTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 918, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24121,9 +24893,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1456 Instruction:"VCVTPH2UQQ Vn{K}{z},aKq,Wf|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:1503 Instruction:"VCVTPH2UQQ Vn{K}{z},aKq,Wf|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VCVTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 889, + ND_INS_VCVTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 919, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24138,9 +24910,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1457 Instruction:"VCVTPH2UW Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM" + // Pos:1504 Instruction:"VCVTPH2UW Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM" { - ND_INS_VCVTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 890, + ND_INS_VCVTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 920, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24155,9 +24927,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1458 Instruction:"VCVTPH2W Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM" + // Pos:1505 Instruction:"VCVTPH2W Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM" { - ND_INS_VCVTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 891, + ND_INS_VCVTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 921, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24172,9 +24944,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1459 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" + // Pos:1506 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 892, + ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 922, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24189,9 +24961,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1460 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" + // Pos:1507 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" { - ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 892, + ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 922, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24205,9 +24977,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1461 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" + // Pos:1508 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 893, + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 923, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24222,9 +24994,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1462 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" + // Pos:1509 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 893, + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 923, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24238,9 +25010,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1463 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" + // Pos:1510 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 893, + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 923, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24254,9 +25026,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1464 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" + // Pos:1511 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 894, + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 924, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24272,9 +25044,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1465 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" + // Pos:1512 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 894, + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 924, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, @@ -24289,9 +25061,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1466 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" + // Pos:1513 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 894, + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 924, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, @@ -24306,9 +25078,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1467 Instruction:"VCVTPS2PHX Vh{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM" + // Pos:1514 Instruction:"VCVTPS2PHX Vh{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM" { - ND_INS_VCVTPS2PHX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 895, + ND_INS_VCVTPS2PHX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 925, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24323,9 +25095,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1468 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" + // Pos:1515 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" { - ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 896, + ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 926, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24340,9 +25112,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1469 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" + // Pos:1516 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 897, + ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 927, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24357,9 +25129,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1470 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:1517 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 898, + ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 928, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24374,9 +25146,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1471 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" + // Pos:1518 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" { - ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 899, + ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 929, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24391,9 +25163,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1472 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM" + // Pos:1519 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM" { - ND_INS_VCVTQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 900, + ND_INS_VCVTQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 930, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24408,9 +25180,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1473 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" + // Pos:1520 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" { - ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 901, + ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 931, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24425,9 +25197,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1474 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM" + // Pos:1521 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM" { - ND_INS_VCVTSD2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 902, + ND_INS_VCVTSD2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 932, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24443,9 +25215,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1475 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" + // Pos:1522 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 903, + ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 933, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24459,9 +25231,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1476 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" + // Pos:1523 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 903, + ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 933, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24475,9 +25247,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1477 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" + // Pos:1524 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" { - ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 904, + ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 934, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24493,9 +25265,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1478 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" + // Pos:1525 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" { - ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 904, + ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 934, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24510,9 +25282,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1479 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" + // Pos:1526 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" { - ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 905, + ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 935, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24526,9 +25298,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1480 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM" + // Pos:1527 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM" { - ND_INS_VCVTSH2SD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 906, + ND_INS_VCVTSH2SD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 936, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24544,9 +25316,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1481 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:1528 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 907, + ND_INS_VCVTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 937, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24560,9 +25332,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1482 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM" + // Pos:1529 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM" { - ND_INS_VCVTSH2SS, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 908, + ND_INS_VCVTSH2SS, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 938, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24578,9 +25350,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1483 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM" + // Pos:1530 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM" { - ND_INS_VCVTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 909, + ND_INS_VCVTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 939, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24594,9 +25366,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1484 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" + // Pos:1531 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 910, + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 940, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24611,9 +25383,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1485 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" + // Pos:1532 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 910, + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 940, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24628,9 +25400,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1486 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" + // Pos:1533 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 910, + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 940, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24645,9 +25417,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1487 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:1534 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 911, + ND_INS_VCVTSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 941, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24662,9 +25434,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1488 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:1535 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 912, + ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 942, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24679,9 +25451,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1489 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:1536 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 912, + ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 942, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24696,9 +25468,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1490 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" + // Pos:1537 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" { - ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 913, + ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 943, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24714,9 +25486,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1491 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" + // Pos:1538 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" { - ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 913, + ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 943, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24731,9 +25503,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1492 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM" + // Pos:1539 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM" { - ND_INS_VCVTSS2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 914, + ND_INS_VCVTSS2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 944, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24749,9 +25521,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1493 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:1540 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 915, + ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 945, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24765,9 +25537,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1494 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:1541 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 915, + ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 945, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24781,9 +25553,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1495 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" + // Pos:1542 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" { - ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 916, + ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 946, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24797,9 +25569,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1496 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" + // Pos:1543 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" { - ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 917, + ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 947, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24814,9 +25586,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1497 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" + // Pos:1544 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" { - ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 917, + ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 947, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24830,9 +25602,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1498 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" + // Pos:1545 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 918, + ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 948, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24847,9 +25619,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1499 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" + // Pos:1546 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" { - ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 919, + ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 949, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24864,9 +25636,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1500 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" + // Pos:1547 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" { - ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 920, + ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 950, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24881,9 +25653,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1501 Instruction:"VCVTTPH2DQ Vn{K}{z},aKq,Wh|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM" + // Pos:1548 Instruction:"VCVTTPH2DQ Vn{K}{z},aKq,Wh|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 921, + ND_INS_VCVTTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 951, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24898,9 +25670,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1502 Instruction:"VCVTTPH2QQ Vn{K}{z},aKq,Wf|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM" + // Pos:1549 Instruction:"VCVTTPH2QQ Vn{K}{z},aKq,Wf|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 922, + ND_INS_VCVTTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 952, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24915,9 +25687,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1503 Instruction:"VCVTTPH2UDQ Vn{K}{z},aKq,Wh|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM" + // Pos:1550 Instruction:"VCVTTPH2UDQ Vn{K}{z},aKq,Wh|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VCVTTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 923, + ND_INS_VCVTTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 953, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24932,9 +25704,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1504 Instruction:"VCVTTPH2UQQ Vn{K}{z},aKq,Wf|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:1551 Instruction:"VCVTTPH2UQQ Vn{K}{z},aKq,Wf|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VCVTTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 924, + ND_INS_VCVTTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 954, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24949,9 +25721,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1505 Instruction:"VCVTTPH2UW Vn{K}{z},aKq,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM" + // Pos:1552 Instruction:"VCVTTPH2UW Vn{K}{z},aKq,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM" { - ND_INS_VCVTTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 925, + ND_INS_VCVTTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 955, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24966,9 +25738,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1506 Instruction:"VCVTTPH2W Vn{K}{z},aKq,Wn|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM" + // Pos:1553 Instruction:"VCVTTPH2W Vn{K}{z},aKq,Wn|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM" { - ND_INS_VCVTTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 926, + ND_INS_VCVTTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 956, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24983,9 +25755,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1507 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" + // Pos:1554 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 927, + ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 957, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25000,9 +25772,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1508 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" + // Pos:1555 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" { - ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 927, + ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 957, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25016,9 +25788,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1509 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" + // Pos:1556 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 928, + ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 958, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25033,9 +25805,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1510 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" + // Pos:1557 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 929, + ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 959, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25050,9 +25822,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1511 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:1558 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 930, + ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 960, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25067,9 +25839,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1512 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" + // Pos:1559 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 931, + ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 961, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25083,9 +25855,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1513 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" + // Pos:1560 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 931, + ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 961, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25099,9 +25871,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1514 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" + // Pos:1561 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" { - ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 932, + ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 962, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25115,9 +25887,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1515 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:1562 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 933, + ND_INS_VCVTTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 963, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25131,9 +25903,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1516 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM" + // Pos:1563 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM" { - ND_INS_VCVTTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 934, + ND_INS_VCVTTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 964, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25147,9 +25919,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1517 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:1564 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 935, + ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 965, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25163,9 +25935,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1518 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:1565 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 935, + ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 965, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25179,9 +25951,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1519 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" + // Pos:1566 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" { - ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 936, + ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 966, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25195,9 +25967,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1520 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" + // Pos:1567 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 937, + ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 967, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25212,9 +25984,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1521 Instruction:"VCVTUDQ2PH Vh{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM" + // Pos:1568 Instruction:"VCVTUDQ2PH Vh{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTUDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 938, + ND_INS_VCVTUDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 968, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25229,9 +26001,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1522 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" + // Pos:1569 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 939, + ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 969, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25246,9 +26018,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1523 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" + // Pos:1570 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 940, + ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 970, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25263,9 +26035,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1524 Instruction:"VCVTUQQ2PH Vf{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM" + // Pos:1571 Instruction:"VCVTUQQ2PH Vf{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTUQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 941, + ND_INS_VCVTUQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 971, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25280,9 +26052,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1525 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" + // Pos:1572 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 942, + ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 972, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25297,9 +26069,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1526 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" + // Pos:1573 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 943, + ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 973, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25314,9 +26086,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1527 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" + // Pos:1574 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 943, + ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 973, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25331,9 +26103,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1528 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM" + // Pos:1575 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 944, + ND_INS_VCVTUSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 974, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25348,9 +26120,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1529 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" + // Pos:1576 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 945, + ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 975, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25365,9 +26137,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1530 Instruction:"VCVTUW2PH Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM" + // Pos:1577 Instruction:"VCVTUW2PH Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM" { - ND_INS_VCVTUW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 946, + ND_INS_VCVTUW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 976, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25382,9 +26154,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1531 Instruction:"VCVTW2PH Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM" + // Pos:1578 Instruction:"VCVTW2PH Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM" { - ND_INS_VCVTW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 947, + ND_INS_VCVTW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 977, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25399,9 +26171,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1532 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" + // Pos:1579 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" { - ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 948, + ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 978, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -25418,9 +26190,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1533 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" + // Pos:1580 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" { - ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 949, + ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 979, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25436,9 +26208,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1534 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" + // Pos:1581 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" { - ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 949, + ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 979, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25453,9 +26225,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1535 Instruction:"VDIVPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM" + // Pos:1582 Instruction:"VDIVPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM" { - ND_INS_VDIVPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 950, + ND_INS_VDIVPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 980, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25471,9 +26243,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1536 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" + // Pos:1583 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" { - ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 951, + ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 981, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25489,9 +26261,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1537 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" + // Pos:1584 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" { - ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 951, + ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 981, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25506,9 +26278,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1538 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" + // Pos:1585 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" { - ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 952, + ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 982, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25524,9 +26296,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1539 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" + // Pos:1586 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" { - ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 952, + ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 982, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25541,9 +26313,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1540 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM" + // Pos:1587 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM" { - ND_INS_VDIVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 953, + ND_INS_VDIVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 983, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25559,9 +26331,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1541 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" + // Pos:1588 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" { - ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 954, + ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 984, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25577,9 +26349,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1542 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" + // Pos:1589 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" { - ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 954, + ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 984, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25594,9 +26366,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1543 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" + // Pos:1590 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" { - ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 955, + ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 985, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, @@ -25612,9 +26384,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1544 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" + // Pos:1591 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" { - ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 956, + ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 986, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25630,9 +26402,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1545 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" + // Pos:1592 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" { - ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 957, + ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 987, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25648,9 +26420,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1546 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" + // Pos:1593 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" { - ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 958, + ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 988, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -25664,9 +26436,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1547 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" + // Pos:1594 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" { - ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 959, + ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 989, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -25680,9 +26452,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1548 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" + // Pos:1595 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" { - ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 960, + ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 990, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -25697,9 +26469,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1549 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" + // Pos:1596 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" { - ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 961, + ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 991, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -25714,9 +26486,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1550 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" + // Pos:1597 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" { - ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 962, + ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 992, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25731,9 +26503,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1551 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" + // Pos:1598 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" { - ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 963, + ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 993, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25748,9 +26520,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1552 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" + // Pos:1599 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" { - ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 964, + ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 994, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25765,9 +26537,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1553 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" + // Pos:1600 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" { - ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 965, + ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 995, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25783,9 +26555,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1554 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" + // Pos:1601 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" { - ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 966, + ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 996, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25801,9 +26573,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1555 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" + // Pos:1602 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" { - ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 967, + ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 997, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25819,9 +26591,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1556 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" + // Pos:1603 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" { - ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 968, + ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 998, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25837,9 +26609,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1557 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" + // Pos:1604 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" { - ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 969, + ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 999, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -25854,9 +26626,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1558 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" + // Pos:1605 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" { - ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 970, + ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1000, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25872,9 +26644,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1559 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" + // Pos:1606 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" { - ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 971, + ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1001, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25890,9 +26662,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1560 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" + // Pos:1607 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" { - ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 972, + ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1002, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25908,9 +26680,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1561 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" + // Pos:1608 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" { - ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 973, + ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1003, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25926,9 +26698,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1562 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + // Pos:1609 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 974, + ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1004, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25943,9 +26715,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1563 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + // Pos:1610 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 974, + ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1004, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25960,9 +26732,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1564 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + // Pos:1611 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 974, + ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1004, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25977,9 +26749,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1565 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + // Pos:1612 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 974, + ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1004, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25994,9 +26766,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1566 Instruction:"VFCMADDCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM" + // Pos:1613 Instruction:"VFCMADDCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM" { - ND_INS_VFCMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 975, + ND_INS_VFCMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1005, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26012,9 +26784,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1567 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM" + // Pos:1614 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM" { - ND_INS_VFCMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 976, + ND_INS_VFCMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1006, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26030,9 +26802,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1568 Instruction:"VFCMULCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM" + // Pos:1615 Instruction:"VFCMULCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM" { - ND_INS_VFCMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 977, + ND_INS_VFCMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1007, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26048,9 +26820,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1569 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM" + // Pos:1616 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM" { - ND_INS_VFCMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 978, + ND_INS_VFCMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1008, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26066,9 +26838,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1570 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" + // Pos:1617 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 979, + ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1009, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26085,9 +26857,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1571 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" + // Pos:1618 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 980, + ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1010, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26104,9 +26876,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1572 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" + // Pos:1619 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 981, + ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 1011, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26123,9 +26895,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1573 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" + // Pos:1620 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 982, + ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 1012, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26142,9 +26914,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1574 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" + // Pos:1621 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" { - ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 983, + ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1013, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26160,9 +26932,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1575 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" + // Pos:1622 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" { - ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 983, + ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1013, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26177,9 +26949,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1576 Instruction:"VFMADD132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM" + // Pos:1623 Instruction:"VFMADD132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM" { - ND_INS_VFMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 984, + ND_INS_VFMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1014, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26195,9 +26967,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1577 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" + // Pos:1624 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" { - ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 985, + ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1015, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26213,9 +26985,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1578 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" + // Pos:1625 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" { - ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 985, + ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1015, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26230,9 +27002,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1579 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" + // Pos:1626 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" { - ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 986, + ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1016, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26248,9 +27020,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1580 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" + // Pos:1627 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" { - ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 986, + ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1016, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26265,9 +27037,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1581 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM" + // Pos:1628 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM" { - ND_INS_VFMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 987, + ND_INS_VFMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1017, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26283,9 +27055,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1582 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" + // Pos:1629 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" { - ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 988, + ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1018, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26301,9 +27073,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1583 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" + // Pos:1630 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" { - ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 988, + ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1018, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26318,9 +27090,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1584 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" + // Pos:1631 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" { - ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 989, + ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1019, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26336,9 +27108,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1585 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" + // Pos:1632 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" { - ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 989, + ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1019, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26353,9 +27125,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1586 Instruction:"VFMADD213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM" + // Pos:1633 Instruction:"VFMADD213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM" { - ND_INS_VFMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 990, + ND_INS_VFMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1020, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26371,9 +27143,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1587 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" + // Pos:1634 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" { - ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 991, + ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1021, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26389,9 +27161,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1588 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" + // Pos:1635 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" { - ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 991, + ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1021, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26406,9 +27178,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1589 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" + // Pos:1636 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" { - ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 992, + ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1022, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26424,9 +27196,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1590 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" + // Pos:1637 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" { - ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 992, + ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1022, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26441,9 +27213,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1591 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM" + // Pos:1638 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM" { - ND_INS_VFMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 993, + ND_INS_VFMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1023, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26459,9 +27231,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1592 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" + // Pos:1639 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" { - ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 994, + ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1024, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26477,9 +27249,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1593 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" + // Pos:1640 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" { - ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 994, + ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1024, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26494,9 +27266,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1594 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" + // Pos:1641 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" { - ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 995, + ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1025, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26512,9 +27284,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1595 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" + // Pos:1642 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" { - ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 995, + ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1025, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26529,9 +27301,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1596 Instruction:"VFMADD231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM" + // Pos:1643 Instruction:"VFMADD231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM" { - ND_INS_VFMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 996, + ND_INS_VFMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1026, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26547,9 +27319,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1597 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" + // Pos:1644 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" { - ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 997, + ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1027, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26565,9 +27337,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1598 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" + // Pos:1645 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" { - ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 997, + ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1027, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26582,9 +27354,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1599 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" + // Pos:1646 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" { - ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 998, + ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1028, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26600,9 +27372,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1600 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" + // Pos:1647 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" { - ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 998, + ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1028, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26617,9 +27389,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1601 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM" + // Pos:1648 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM" { - ND_INS_VFMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 999, + ND_INS_VFMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1029, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26635,9 +27407,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1602 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" + // Pos:1649 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" { - ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1000, + ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1030, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26653,9 +27425,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1603 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" + // Pos:1650 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" { - ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1000, + ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1030, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26670,9 +27442,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1604 Instruction:"VFMADDCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM" + // Pos:1651 Instruction:"VFMADDCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM" { - ND_INS_VFMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1001, + ND_INS_VFMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1031, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26688,9 +27460,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1605 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM" + // Pos:1652 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM" { - ND_INS_VFMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1002, + ND_INS_VFMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1032, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26706,9 +27478,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1606 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" + // Pos:1653 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" { - ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1003, + ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1033, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26724,9 +27496,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1607 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" + // Pos:1654 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" { - ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1003, + ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1033, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26742,9 +27514,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1608 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" + // Pos:1655 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" { - ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1004, + ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1034, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26760,9 +27532,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1609 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" + // Pos:1656 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" { - ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1004, + ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1034, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26778,9 +27550,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1610 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" + // Pos:1657 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" { - ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1005, + ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1035, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26796,9 +27568,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1611 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" + // Pos:1658 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" { - ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1005, + ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1035, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26814,9 +27586,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1612 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" + // Pos:1659 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" { - ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1006, + ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1036, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26832,9 +27604,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1613 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" + // Pos:1660 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" { - ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1006, + ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1036, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26850,9 +27622,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1614 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" + // Pos:1661 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" { - ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1007, + ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1037, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26868,9 +27640,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1615 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" + // Pos:1662 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" { - ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1007, + ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1037, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26885,9 +27657,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1616 Instruction:"VFMADDSUB132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM" + // Pos:1663 Instruction:"VFMADDSUB132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM" { - ND_INS_VFMADDSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1008, + ND_INS_VFMADDSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1038, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26903,9 +27675,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1617 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" + // Pos:1664 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" { - ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1009, + ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1039, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26921,9 +27693,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1618 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" + // Pos:1665 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" { - ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1009, + ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1039, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26938,9 +27710,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1619 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" + // Pos:1666 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" { - ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1010, + ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1040, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26956,9 +27728,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1620 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" + // Pos:1667 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" { - ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1010, + ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1040, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26973,9 +27745,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1621 Instruction:"VFMADDSUB213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM" + // Pos:1668 Instruction:"VFMADDSUB213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM" { - ND_INS_VFMADDSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1011, + ND_INS_VFMADDSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1041, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26991,9 +27763,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1622 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" + // Pos:1669 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" { - ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1012, + ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1042, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27009,9 +27781,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1623 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" + // Pos:1670 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" { - ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1012, + ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1042, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27026,9 +27798,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1624 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" + // Pos:1671 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" { - ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1013, + ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1043, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27044,9 +27816,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1625 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" + // Pos:1672 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" { - ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1013, + ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1043, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27061,9 +27833,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1626 Instruction:"VFMADDSUB231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM" + // Pos:1673 Instruction:"VFMADDSUB231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM" { - ND_INS_VFMADDSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1014, + ND_INS_VFMADDSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1044, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27079,9 +27851,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1627 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" + // Pos:1674 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" { - ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1015, + ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1045, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27097,9 +27869,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1628 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" + // Pos:1675 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" { - ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1015, + ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1045, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27114,9 +27886,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1629 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" + // Pos:1676 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" { - ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1016, + ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1046, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27132,9 +27904,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1630 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" + // Pos:1677 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" { - ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1016, + ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1046, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27150,9 +27922,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1631 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" + // Pos:1678 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" { - ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1017, + ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1047, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27168,9 +27940,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1632 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" + // Pos:1679 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" { - ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1017, + ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1047, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27186,9 +27958,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1633 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" + // Pos:1680 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" { - ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1018, + ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1048, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27204,9 +27976,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1634 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" + // Pos:1681 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" { - ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1018, + ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1048, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27221,9 +27993,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1635 Instruction:"VFMSUB132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM" + // Pos:1682 Instruction:"VFMSUB132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM" { - ND_INS_VFMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1019, + ND_INS_VFMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1049, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27239,9 +28011,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1636 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" + // Pos:1683 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" { - ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1020, + ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1050, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27257,9 +28029,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1637 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" + // Pos:1684 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" { - ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1020, + ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1050, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27274,9 +28046,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1638 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" + // Pos:1685 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" { - ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1021, + ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1051, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27292,9 +28064,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1639 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" + // Pos:1686 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" { - ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1021, + ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1051, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27309,9 +28081,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1640 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM" + // Pos:1687 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM" { - ND_INS_VFMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1022, + ND_INS_VFMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1052, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27327,9 +28099,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1641 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" + // Pos:1688 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" { - ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1023, + ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1053, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27345,9 +28117,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1642 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" + // Pos:1689 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" { - ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1023, + ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1053, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27362,9 +28134,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1643 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" + // Pos:1690 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" { - ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1024, + ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1054, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27380,9 +28152,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1644 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" + // Pos:1691 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" { - ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1024, + ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1054, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27397,9 +28169,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1645 Instruction:"VFMSUB213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM" + // Pos:1692 Instruction:"VFMSUB213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM" { - ND_INS_VFMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1025, + ND_INS_VFMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1055, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27415,9 +28187,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1646 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" + // Pos:1693 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" { - ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1026, + ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1056, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27433,9 +28205,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1647 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" + // Pos:1694 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" { - ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1026, + ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1056, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27450,9 +28222,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1648 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" + // Pos:1695 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" { - ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1027, + ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1057, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27468,9 +28240,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1649 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" + // Pos:1696 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" { - ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1027, + ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1057, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27485,9 +28257,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1650 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM" + // Pos:1697 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM" { - ND_INS_VFMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1028, + ND_INS_VFMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1058, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27503,9 +28275,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1651 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" + // Pos:1698 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" { - ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1029, + ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1059, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27521,9 +28293,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1652 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" + // Pos:1699 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" { - ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1029, + ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1059, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27538,9 +28310,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1653 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" + // Pos:1700 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" { - ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1030, + ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1060, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27556,9 +28328,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1654 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" + // Pos:1701 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" { - ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1030, + ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1060, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27573,9 +28345,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1655 Instruction:"VFMSUB231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM" + // Pos:1702 Instruction:"VFMSUB231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM" { - ND_INS_VFMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1031, + ND_INS_VFMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1061, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27591,9 +28363,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1656 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" + // Pos:1703 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" { - ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1032, + ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1062, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27609,9 +28381,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1657 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" + // Pos:1704 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" { - ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1032, + ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1062, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27626,9 +28398,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1658 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" + // Pos:1705 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" { - ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1033, + ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1063, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27644,9 +28416,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1659 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" + // Pos:1706 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" { - ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1033, + ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1063, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27661,9 +28433,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1660 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM" + // Pos:1707 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM" { - ND_INS_VFMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1034, + ND_INS_VFMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1064, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27679,9 +28451,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1661 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" + // Pos:1708 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" { - ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1035, + ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1065, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27697,9 +28469,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1662 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" + // Pos:1709 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" { - ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1035, + ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1065, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27714,9 +28486,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1663 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" + // Pos:1710 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" { - ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1036, + ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1066, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27732,9 +28504,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1664 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" + // Pos:1711 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" { - ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1036, + ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1066, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27749,9 +28521,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1665 Instruction:"VFMSUBADD132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM" + // Pos:1712 Instruction:"VFMSUBADD132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM" { - ND_INS_VFMSUBADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1037, + ND_INS_VFMSUBADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1067, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27767,9 +28539,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1666 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" + // Pos:1713 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" { - ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1038, + ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1068, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27785,9 +28557,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1667 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" + // Pos:1714 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" { - ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1038, + ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1068, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27802,9 +28574,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1668 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" + // Pos:1715 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" { - ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1039, + ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1069, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27820,9 +28592,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1669 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" + // Pos:1716 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" { - ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1039, + ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1069, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27837,9 +28609,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1670 Instruction:"VFMSUBADD213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM" + // Pos:1717 Instruction:"VFMSUBADD213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM" { - ND_INS_VFMSUBADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1040, + ND_INS_VFMSUBADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1070, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27855,9 +28627,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1671 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" + // Pos:1718 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" { - ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1041, + ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1071, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27873,9 +28645,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1672 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" + // Pos:1719 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" { - ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1041, + ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1071, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27890,9 +28662,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1673 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" + // Pos:1720 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" { - ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1042, + ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1072, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27908,9 +28680,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1674 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" + // Pos:1721 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" { - ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1042, + ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1072, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27925,9 +28697,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1675 Instruction:"VFMSUBADD231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM" + // Pos:1722 Instruction:"VFMSUBADD231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM" { - ND_INS_VFMSUBADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1043, + ND_INS_VFMSUBADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1073, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27943,9 +28715,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1676 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" + // Pos:1723 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" { - ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1044, + ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1074, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27961,9 +28733,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1677 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" + // Pos:1724 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" { - ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1044, + ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1074, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27978,9 +28750,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1678 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" + // Pos:1725 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" { - ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1045, + ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1075, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27996,9 +28768,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1679 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" + // Pos:1726 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" { - ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1045, + ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1075, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28014,9 +28786,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1680 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" + // Pos:1727 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" { - ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1046, + ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1076, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28032,9 +28804,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1681 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" + // Pos:1728 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" { - ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1046, + ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1076, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28050,9 +28822,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1682 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" + // Pos:1729 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" { - ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1047, + ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1077, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28068,9 +28840,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1683 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" + // Pos:1730 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" { - ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1047, + ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1077, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28086,9 +28858,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1684 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" + // Pos:1731 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" { - ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1048, + ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1078, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28104,9 +28876,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1685 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" + // Pos:1732 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" { - ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1048, + ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1078, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28122,9 +28894,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1686 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" + // Pos:1733 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" { - ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1049, + ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1079, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28140,9 +28912,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1687 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" + // Pos:1734 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" { - ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1049, + ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1079, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28158,9 +28930,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1688 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" + // Pos:1735 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" { - ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1050, + ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1080, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28176,9 +28948,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1689 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" + // Pos:1736 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" { - ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1050, + ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1080, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28194,9 +28966,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1690 Instruction:"VFMULCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM" + // Pos:1737 Instruction:"VFMULCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM" { - ND_INS_VFMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1051, + ND_INS_VFMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1081, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28212,9 +28984,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1691 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM" + // Pos:1738 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM" { - ND_INS_VFMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1052, + ND_INS_VFMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1082, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28230,9 +29002,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1692 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" + // Pos:1739 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" { - ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1053, + ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1083, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28248,9 +29020,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1693 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" + // Pos:1740 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" { - ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1053, + ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1083, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28265,9 +29037,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1694 Instruction:"VFNMADD132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM" + // Pos:1741 Instruction:"VFNMADD132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM" { - ND_INS_VFNMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1054, + ND_INS_VFNMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1084, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28283,9 +29055,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1695 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" + // Pos:1742 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" { - ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1055, + ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1085, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28301,9 +29073,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1696 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" + // Pos:1743 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" { - ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1055, + ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1085, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28318,9 +29090,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1697 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" + // Pos:1744 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" { - ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1056, + ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1086, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28336,9 +29108,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1698 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" + // Pos:1745 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" { - ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1056, + ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1086, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28353,9 +29125,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1699 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM" + // Pos:1746 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM" { - ND_INS_VFNMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1057, + ND_INS_VFNMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1087, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28371,9 +29143,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1700 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" + // Pos:1747 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" { - ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1058, + ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1088, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28389,9 +29161,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1701 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" + // Pos:1748 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" { - ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1058, + ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1088, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28406,9 +29178,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1702 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" + // Pos:1749 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" { - ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1059, + ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1089, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28424,9 +29196,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1703 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" + // Pos:1750 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" { - ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1059, + ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1089, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28441,9 +29213,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1704 Instruction:"VFNMADD213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM" + // Pos:1751 Instruction:"VFNMADD213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM" { - ND_INS_VFNMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1060, + ND_INS_VFNMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1090, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28459,9 +29231,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1705 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" + // Pos:1752 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" { - ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1061, + ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1091, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28477,9 +29249,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1706 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" + // Pos:1753 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" { - ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1061, + ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1091, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28494,9 +29266,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1707 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" + // Pos:1754 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" { - ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1062, + ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1092, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28512,9 +29284,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1708 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" + // Pos:1755 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" { - ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1062, + ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1092, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28529,9 +29301,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1709 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM" + // Pos:1756 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM" { - ND_INS_VFNMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1063, + ND_INS_VFNMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1093, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28547,9 +29319,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1710 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" + // Pos:1757 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" { - ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1064, + ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1094, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28565,9 +29337,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1711 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" + // Pos:1758 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" { - ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1064, + ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1094, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28582,9 +29354,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1712 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" + // Pos:1759 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" { - ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1065, + ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1095, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28600,9 +29372,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1713 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" + // Pos:1760 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" { - ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1065, + ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1095, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28617,9 +29389,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1714 Instruction:"VFNMADD231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM" + // Pos:1761 Instruction:"VFNMADD231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM" { - ND_INS_VFNMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1066, + ND_INS_VFNMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1096, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28635,9 +29407,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1715 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" + // Pos:1762 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" { - ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1067, + ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1097, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28653,9 +29425,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1716 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" + // Pos:1763 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" { - ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1067, + ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1097, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28670,9 +29442,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1717 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" + // Pos:1764 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" { - ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1068, + ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1098, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28688,9 +29460,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1718 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" + // Pos:1765 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" { - ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1068, + ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1098, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28705,9 +29477,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1719 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM" + // Pos:1766 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM" { - ND_INS_VFNMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1069, + ND_INS_VFNMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1099, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28723,9 +29495,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1720 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" + // Pos:1767 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" { - ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1070, + ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1100, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28741,9 +29513,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1721 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" + // Pos:1768 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" { - ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1070, + ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1100, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28758,9 +29530,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1722 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" + // Pos:1769 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" { - ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1071, + ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1101, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28776,9 +29548,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1723 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" + // Pos:1770 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" { - ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1071, + ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1101, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28794,9 +29566,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1724 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" + // Pos:1771 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" { - ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1072, + ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1102, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28812,9 +29584,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1725 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" + // Pos:1772 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" { - ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1072, + ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1102, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28830,9 +29602,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1726 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" + // Pos:1773 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" { - ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1073, + ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1103, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28848,9 +29620,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1727 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" + // Pos:1774 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" { - ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1073, + ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1103, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28866,9 +29638,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1728 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" + // Pos:1775 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" { - ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1074, + ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1104, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28884,9 +29656,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1729 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" + // Pos:1776 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" { - ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1074, + ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1104, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28902,9 +29674,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1730 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" + // Pos:1777 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" { - ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1075, + ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1105, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28920,9 +29692,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1731 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" + // Pos:1778 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" { - ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1075, + ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1105, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28937,9 +29709,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1732 Instruction:"VFNMSUB132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM" + // Pos:1779 Instruction:"VFNMSUB132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM" { - ND_INS_VFNMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1076, + ND_INS_VFNMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1106, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28955,9 +29727,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1733 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" + // Pos:1780 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" { - ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1077, + ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1107, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28973,9 +29745,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1734 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" + // Pos:1781 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" { - ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1077, + ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1107, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28990,9 +29762,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1735 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" + // Pos:1782 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" { - ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1078, + ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1108, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29008,9 +29780,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1736 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" + // Pos:1783 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" { - ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1078, + ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1108, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29025,9 +29797,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1737 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM" + // Pos:1784 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM" { - ND_INS_VFNMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1079, + ND_INS_VFNMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29043,9 +29815,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1738 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" + // Pos:1785 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" { - ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1080, + ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29061,9 +29833,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1739 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" + // Pos:1786 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" { - ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1080, + ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29078,9 +29850,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1740 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" + // Pos:1787 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" { - ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1081, + ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1111, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29096,9 +29868,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1741 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" + // Pos:1788 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" { - ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1081, + ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1111, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29113,9 +29885,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1742 Instruction:"VFNMSUB213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM" + // Pos:1789 Instruction:"VFNMSUB213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM" { - ND_INS_VFNMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1082, + ND_INS_VFNMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1112, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29131,9 +29903,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1743 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" + // Pos:1790 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" { - ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1083, + ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29149,9 +29921,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1744 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" + // Pos:1791 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" { - ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1083, + ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29166,9 +29938,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1745 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" + // Pos:1792 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" { - ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1084, + ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1114, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29184,9 +29956,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1746 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" + // Pos:1793 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" { - ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1084, + ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1114, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29201,9 +29973,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1747 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM" + // Pos:1794 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM" { - ND_INS_VFNMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1085, + ND_INS_VFNMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1115, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29219,9 +29991,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1748 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" + // Pos:1795 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" { - ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1086, + ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1116, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29237,9 +30009,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1749 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" + // Pos:1796 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" { - ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1086, + ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1116, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29254,9 +30026,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1750 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" + // Pos:1797 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" { - ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1087, + ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1117, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29272,9 +30044,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1751 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" + // Pos:1798 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" { - ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1087, + ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1117, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29289,9 +30061,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1752 Instruction:"VFNMSUB231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM" + // Pos:1799 Instruction:"VFNMSUB231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM" { - ND_INS_VFNMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1088, + ND_INS_VFNMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1118, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29307,9 +30079,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1753 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" + // Pos:1800 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" { - ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1089, + ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1119, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29325,9 +30097,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1754 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" + // Pos:1801 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" { - ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1089, + ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1119, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29342,9 +30114,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1755 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" + // Pos:1802 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" { - ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1090, + ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1120, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29360,9 +30132,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1756 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" + // Pos:1803 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" { - ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1090, + ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1120, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29377,9 +30149,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1757 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM" + // Pos:1804 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM" { - ND_INS_VFNMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1091, + ND_INS_VFNMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1121, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29395,9 +30167,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1758 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" + // Pos:1805 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" { - ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1092, + ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1122, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29413,9 +30185,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1759 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" + // Pos:1806 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" { - ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1092, + ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1122, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29430,9 +30202,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1760 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" + // Pos:1807 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" { - ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1093, + ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1123, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29448,9 +30220,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1761 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" + // Pos:1808 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" { - ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1093, + ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1123, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29466,9 +30238,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1762 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" + // Pos:1809 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" { - ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1094, + ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1124, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29484,9 +30256,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1763 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" + // Pos:1810 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" { - ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1094, + ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1124, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29502,9 +30274,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1764 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" + // Pos:1811 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" { - ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1095, + ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1125, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29520,9 +30292,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1765 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" + // Pos:1812 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" { - ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1095, + ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1125, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29538,9 +30310,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1766 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" + // Pos:1813 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" { - ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1096, + ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1126, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29556,9 +30328,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1767 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" + // Pos:1814 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" { - ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1096, + ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1126, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29574,9 +30346,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1768 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" + // Pos:1815 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" { - ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1097, + ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1127, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -29592,9 +30364,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1769 Instruction:"VFPCLASSPH rKq{K},aKq,Wn|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI" + // Pos:1816 Instruction:"VFPCLASSPH rKq{K},aKq,Wn|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI" { - ND_INS_VFPCLASSPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1098, + ND_INS_VFPCLASSPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1128, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29610,9 +30382,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1770 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" + // Pos:1817 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" { - ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1099, + ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1129, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -29628,9 +30400,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1771 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" + // Pos:1818 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" { - ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1100, + ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1130, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -29646,9 +30418,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1772 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI" + // Pos:1819 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI" { - ND_INS_VFPCLASSSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1101, + ND_INS_VFPCLASSSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1131, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29664,9 +30436,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1773 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" + // Pos:1820 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" { - ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1102, + ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1132, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -29682,9 +30454,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1774 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" + // Pos:1821 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" { - ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1103, + ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1133, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -29698,9 +30470,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1775 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" + // Pos:1822 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" { - ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1104, + ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1134, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -29714,9 +30486,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1776 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" + // Pos:1823 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" { - ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1105, + ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1135, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -29730,9 +30502,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1777 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" + // Pos:1824 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" { - ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1106, + ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1136, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -29746,9 +30518,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1778 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" + // Pos:1825 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" { - ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1107, + ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1137, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29763,9 +30535,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1779 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" + // Pos:1826 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" { - ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1107, + ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1137, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -29780,9 +30552,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1780 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" + // Pos:1827 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" { - ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1108, + ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1138, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29797,9 +30569,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1781 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" + // Pos:1828 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" { - ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1108, + ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1138, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -29814,9 +30586,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1782 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" + // Pos:1829 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" { - ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1109, + ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1139, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -29830,9 +30602,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1783 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" + // Pos:1830 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" { - ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1110, + ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1140, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -29846,9 +30618,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1784 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" + // Pos:1831 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" { - ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1111, + ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1141, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -29862,9 +30634,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1785 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" + // Pos:1832 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" { - ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1112, + ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1142, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -29878,9 +30650,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1786 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" + // Pos:1833 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" { - ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1113, + ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1143, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -29894,9 +30666,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1787 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" + // Pos:1834 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" { - ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1114, + ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1144, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -29910,9 +30682,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1788 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" + // Pos:1835 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" { - ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1115, + ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1145, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -29926,9 +30698,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1789 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" + // Pos:1836 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" { - ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1116, + ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1146, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -29942,9 +30714,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1790 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" + // Pos:1837 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" { - ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1117, + ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1147, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29959,9 +30731,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1791 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" + // Pos:1838 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" { - ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1117, + ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1147, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -29976,9 +30748,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1792 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" + // Pos:1839 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" { - ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1118, + ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1148, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29993,9 +30765,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1793 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" + // Pos:1840 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" { - ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1118, + ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1148, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -30010,9 +30782,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1794 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" + // Pos:1841 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" { - ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1119, + ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30027,9 +30799,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1795 Instruction:"VGETEXPPH Vn{K}{z},aKq,Wn|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM" + // Pos:1842 Instruction:"VGETEXPPH Vn{K}{z},aKq,Wn|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM" { - ND_INS_VGETEXPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1120, + ND_INS_VGETEXPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1150, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30044,9 +30816,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1796 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" + // Pos:1843 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" { - ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1121, + ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1151, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30061,9 +30833,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1797 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" + // Pos:1844 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" { - ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1122, + ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1152, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30079,9 +30851,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1798 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM" + // Pos:1845 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM" { - ND_INS_VGETEXPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1123, + ND_INS_VGETEXPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1153, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30097,9 +30869,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1799 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" + // Pos:1846 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" { - ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1124, + ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1154, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30115,9 +30887,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1800 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" + // Pos:1847 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" { - ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1125, + ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1155, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30133,9 +30905,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1801 Instruction:"VGETMANTPH Vn{K}{z},aKq,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI" + // Pos:1848 Instruction:"VGETMANTPH Vn{K}{z},aKq,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI" { - ND_INS_VGETMANTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1126, + ND_INS_VGETMANTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1156, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30151,9 +30923,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1802 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" + // Pos:1849 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" { - ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1127, + ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1157, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30169,9 +30941,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1803 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" + // Pos:1850 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" { - ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1128, + ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1158, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30188,9 +30960,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1804 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI" + // Pos:1851 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI" { - ND_INS_VGETMANTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1129, + ND_INS_VGETMANTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1159, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30207,9 +30979,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1805 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" + // Pos:1852 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" { - ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1130, + ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1160, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30226,9 +30998,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1806 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" + // Pos:1853 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" { - ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1131, + ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1161, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -30245,9 +31017,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1807 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" + // Pos:1854 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" { - ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1131, + ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1161, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -30263,9 +31035,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1808 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" + // Pos:1855 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" { - ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1132, + ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1162, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -30282,9 +31054,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1809 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" + // Pos:1856 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" { - ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1132, + ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1162, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -30300,9 +31072,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1810 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" + // Pos:1857 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" { - ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1133, + ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1163, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -30318,9 +31090,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1811 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" + // Pos:1858 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" { - ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1133, + ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1163, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -30335,9 +31107,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1812 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" + // Pos:1859 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" { - ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1134, + ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1164, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30352,9 +31124,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1813 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" + // Pos:1860 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" { - ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1135, + ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1165, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30369,9 +31141,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1814 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" + // Pos:1861 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" { - ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1136, + ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1166, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30386,9 +31158,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1815 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" + // Pos:1862 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" { - ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1137, + ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1167, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30403,9 +31175,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1816 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" + // Pos:1863 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" { - ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1138, + ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30421,9 +31193,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1817 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" + // Pos:1864 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" { - ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1139, + ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1169, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30440,9 +31212,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1818 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" + // Pos:1865 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" { - ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1140, + ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1170, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -30459,9 +31231,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1819 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" + // Pos:1866 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" { - ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1141, + ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1171, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -30478,9 +31250,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1820 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" + // Pos:1867 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" { - ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1142, + ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1172, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30497,9 +31269,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1821 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" + // Pos:1868 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" { - ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1143, + ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1173, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -30515,9 +31287,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1822 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" + // Pos:1869 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" { - ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1144, + ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1174, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30534,9 +31306,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1823 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" + // Pos:1870 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" { - ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1145, + ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1175, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -30553,9 +31325,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1824 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" + // Pos:1871 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" { - ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1146, + ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1176, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -30572,9 +31344,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1825 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" + // Pos:1872 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" { - ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1147, + ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1177, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30591,9 +31363,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1826 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + // Pos:1873 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" { - ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1148, + ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1178, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30609,9 +31381,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1827 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + // Pos:1874 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" { - ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1148, + ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1178, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30627,9 +31399,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1828 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + // Pos:1875 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" { - ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1148, + ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1178, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30645,9 +31417,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1829 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + // Pos:1876 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" { - ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1148, + ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1178, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30663,9 +31435,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1830 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" + // Pos:1877 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" { - ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1149, + ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1179, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30679,9 +31451,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1831 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" + // Pos:1878 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" { - ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1150, + ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1180, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, @@ -30695,9 +31467,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1832 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" + // Pos:1879 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" { - ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1151, + ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1181, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30712,9 +31484,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1833 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" + // Pos:1880 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" { - ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1152, + ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1182, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30729,9 +31501,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1834 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" + // Pos:1881 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" { - ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1152, + ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1182, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30746,9 +31518,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1835 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" + // Pos:1882 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" { - ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1153, + ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1183, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30763,9 +31535,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1836 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" + // Pos:1883 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" { - ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1153, + ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1183, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30780,9 +31552,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1837 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" + // Pos:1884 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" { - ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1154, + ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1184, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30798,9 +31570,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1838 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" + // Pos:1885 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" { - ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1154, + ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1184, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30815,9 +31587,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1839 Instruction:"VMAXPH Vn{K}{z},aKq,Hn,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM" + // Pos:1886 Instruction:"VMAXPH Vn{K}{z},aKq,Hn,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM" { - ND_INS_VMAXPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1155, + ND_INS_VMAXPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1185, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30833,9 +31605,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1840 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" + // Pos:1887 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" { - ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1156, + ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1186, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30851,9 +31623,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1841 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" + // Pos:1888 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" { - ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1156, + ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1186, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30868,9 +31640,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1842 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" + // Pos:1889 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" { - ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1157, + ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1187, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30886,9 +31658,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1843 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" + // Pos:1890 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" { - ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1157, + ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1187, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30903,9 +31675,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1844 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM" + // Pos:1891 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM" { - ND_INS_VMAXSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1158, + ND_INS_VMAXSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1188, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30921,9 +31693,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1845 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" + // Pos:1892 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" { - ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1159, + ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1189, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30939,9 +31711,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1846 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" + // Pos:1893 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" { - ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1159, + ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1189, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30956,9 +31728,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1847 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/"" + // Pos:1894 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/"" { - ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1160, + ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1190, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -30971,9 +31743,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1848 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" + // Pos:1895 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" { - ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1161, + ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1191, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -30987,9 +31759,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1849 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" + // Pos:1896 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" { - ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1162, + ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1192, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -31002,9 +31774,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1850 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" + // Pos:1897 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" { - ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1163, + ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1193, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -31017,9 +31789,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1851 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" + // Pos:1898 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" { - ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1163, + ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1193, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -31032,9 +31804,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1852 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" + // Pos:1899 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" { - ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1164, + ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1194, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31050,9 +31822,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1853 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" + // Pos:1900 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" { - ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1164, + ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1194, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31067,9 +31839,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1854 Instruction:"VMINPH Vn{K}{z},aKq,Hn,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM" + // Pos:1901 Instruction:"VMINPH Vn{K}{z},aKq,Hn,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM" { - ND_INS_VMINPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1165, + ND_INS_VMINPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1195, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -31085,9 +31857,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1855 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" + // Pos:1902 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" { - ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1166, + ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1196, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31103,9 +31875,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1856 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" + // Pos:1903 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" { - ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1166, + ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1196, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31120,9 +31892,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1857 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" + // Pos:1904 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" { - ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1167, + ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1197, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31138,9 +31910,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1858 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" + // Pos:1905 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" { - ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1167, + ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1197, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31155,9 +31927,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1859 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM" + // Pos:1906 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM" { - ND_INS_VMINSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1168, + ND_INS_VMINSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1198, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -31173,9 +31945,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1860 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" + // Pos:1907 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" { - ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1169, + ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1199, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31191,9 +31963,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1861 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" + // Pos:1908 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" { - ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1169, + ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1199, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31208,9 +31980,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1862 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/"" + // Pos:1909 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/"" { - ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1170, + ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1200, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -31223,9 +31995,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1863 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" + // Pos:1910 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" { - ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1171, + ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1201, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -31238,9 +32010,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1864 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/"" + // Pos:1911 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/"" { - ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1172, + ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1202, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -31253,9 +32025,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1865 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" + // Pos:1912 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" { - ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1172, + ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1202, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -31268,9 +32040,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1866 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" + // Pos:1913 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1173, + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1203, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31285,9 +32057,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1867 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" + // Pos:1914 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1173, + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1203, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31302,9 +32074,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1868 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" + // Pos:1915 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1173, + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1203, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31318,9 +32090,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1869 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" + // Pos:1916 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1173, + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1203, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31334,9 +32106,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1870 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" + // Pos:1917 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1174, + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1204, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31351,9 +32123,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1871 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" + // Pos:1918 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1174, + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1204, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31368,9 +32140,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1872 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" + // Pos:1919 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1174, + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1204, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31384,9 +32156,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1873 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" + // Pos:1920 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1174, + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1204, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31400,9 +32172,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1874 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + // Pos:1921 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1175, + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1205, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31416,9 +32188,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1875 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + // Pos:1922 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1175, + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1205, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31432,9 +32204,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1876 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + // Pos:1923 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1175, + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1205, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31448,9 +32220,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1877 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + // Pos:1924 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1175, + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1205, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31464,9 +32236,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1878 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" + // Pos:1925 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1176, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1206, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31481,9 +32253,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1879 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" + // Pos:1926 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1176, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1206, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31498,9 +32270,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1880 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" + // Pos:1927 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1176, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1206, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31515,9 +32287,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1881 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" + // Pos:1928 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1176, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1206, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31531,9 +32303,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1882 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" + // Pos:1929 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1176, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1206, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31547,9 +32319,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1883 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" + // Pos:1930 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" { - ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1177, + ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1207, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31563,9 +32335,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1884 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" + // Pos:1931 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" { - ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1177, + ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1207, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31579,9 +32351,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1885 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" + // Pos:1932 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" { - ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1178, + ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1208, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31596,9 +32368,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1886 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" + // Pos:1933 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" { - ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1178, + ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1208, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31613,9 +32385,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1887 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" + // Pos:1934 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" { - ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1179, + ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31630,9 +32402,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1888 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" + // Pos:1935 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" { - ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1179, + ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31647,9 +32419,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1889 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" + // Pos:1936 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" { - ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1180, + ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1210, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31663,9 +32435,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1890 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" + // Pos:1937 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" { - ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1180, + ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1210, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31679,9 +32451,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1891 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" + // Pos:1938 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" { - ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1181, + ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1211, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -31696,9 +32468,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1892 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" + // Pos:1939 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" { - ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1181, + ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1211, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -31713,9 +32485,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1893 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" + // Pos:1940 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" { - ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1182, + ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1212, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31730,9 +32502,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1894 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" + // Pos:1941 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" { - ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1182, + ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1212, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31747,9 +32519,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1895 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" + // Pos:1942 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" { - ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1183, + ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1213, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31764,9 +32536,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1896 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" + // Pos:1943 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" { - ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1183, + ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1213, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31781,9 +32553,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1897 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" + // Pos:1944 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" { - ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1184, + ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1214, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -31798,9 +32570,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1898 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" + // Pos:1945 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" { - ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1184, + ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1214, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -31815,9 +32587,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1899 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" + // Pos:1946 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" { - ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1185, + ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1215, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31832,9 +32604,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1900 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" + // Pos:1947 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" { - ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1185, + ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1215, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31849,9 +32621,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1901 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" + // Pos:1948 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1186, + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31866,9 +32638,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1902 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" + // Pos:1949 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1186, + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31882,9 +32654,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1903 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" + // Pos:1950 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1186, + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1216, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31899,9 +32671,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1904 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" + // Pos:1951 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1186, + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1216, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31915,9 +32687,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1905 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" + // Pos:1952 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1187, + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1217, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31932,9 +32704,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1906 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" + // Pos:1953 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1187, + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1217, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31948,9 +32720,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1907 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" + // Pos:1954 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1187, + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1217, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31965,9 +32737,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1908 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" + // Pos:1955 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1187, + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1217, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31981,9 +32753,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1909 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" + // Pos:1956 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" { - ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1188, + ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1218, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31998,9 +32770,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1910 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" + // Pos:1957 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" { - ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1188, + ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1218, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32015,9 +32787,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1911 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" + // Pos:1958 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1189, + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1219, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32032,9 +32804,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1912 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" + // Pos:1959 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1189, + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1219, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32048,9 +32820,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1913 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" + // Pos:1960 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1189, + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1219, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32065,9 +32837,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1914 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" + // Pos:1961 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1189, + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1219, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32081,9 +32853,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1915 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" + // Pos:1962 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1190, + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32098,9 +32870,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1916 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" + // Pos:1963 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1190, + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32114,9 +32886,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1917 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" + // Pos:1964 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1190, + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32131,9 +32903,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1918 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" + // Pos:1965 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1190, + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32147,12 +32919,12 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1919 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" + // Pos:1966 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" { - ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1191, + ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1221, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -32163,12 +32935,12 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1920 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" + // Pos:1967 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" { - ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1192, + ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1222, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -32179,9 +32951,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1921 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" + // Pos:1968 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" { - ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1193, + ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1223, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32195,9 +32967,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1922 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" + // Pos:1969 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" { - ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1193, + ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1223, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32211,9 +32983,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1923 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" + // Pos:1970 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" { - ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1194, + ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1224, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32227,9 +32999,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1924 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" + // Pos:1971 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" { - ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1194, + ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1224, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32243,9 +33015,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1925 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" + // Pos:1972 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" { - ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1195, + ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1225, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32259,9 +33031,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1926 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" + // Pos:1973 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" { - ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1195, + ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1225, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32275,9 +33047,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1927 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" + // Pos:1974 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" { - ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1196, + ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1226, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32291,9 +33063,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1928 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" + // Pos:1975 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" { - ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1196, + ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1226, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32307,9 +33079,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1929 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + // Pos:1976 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1197, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32323,9 +33095,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1930 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + // Pos:1977 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1197, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32339,9 +33111,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1931 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" + // Pos:1978 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1197, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32355,9 +33127,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1932 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" + // Pos:1979 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1197, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32371,9 +33143,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1933 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + // Pos:1980 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1197, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32387,9 +33159,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1934 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + // Pos:1981 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1197, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32403,9 +33175,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1935 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" + // Pos:1982 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1197, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32419,9 +33191,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1936 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" + // Pos:1983 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1197, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32435,9 +33207,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1937 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" + // Pos:1984 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1198, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32452,9 +33224,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1938 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" + // Pos:1985 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1198, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32470,9 +33242,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1939 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" + // Pos:1986 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1198, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32487,9 +33259,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1940 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" + // Pos:1987 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1198, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32505,9 +33277,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1941 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" + // Pos:1988 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1198, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32522,9 +33294,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1942 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" + // Pos:1989 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1198, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32538,9 +33310,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1943 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" + // Pos:1990 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1198, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32555,9 +33327,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1944 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" + // Pos:1991 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1198, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32571,9 +33343,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1945 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM" + // Pos:1992 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM" { - ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1199, + ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -32588,9 +33360,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1946 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM" + // Pos:1993 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM" { - ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1199, + ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), 0, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -32606,9 +33378,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1947 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR" + // Pos:1994 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR" { - ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1199, + ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -32623,9 +33395,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1948 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR" + // Pos:1995 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR" { - ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1199, + ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), 0, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -32641,9 +33413,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1949 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" + // Pos:1996 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" { - ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1200, + ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1230, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32658,9 +33430,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1950 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" + // Pos:1997 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" { - ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1200, + ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1230, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32674,9 +33446,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1951 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" + // Pos:1998 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" { - ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1201, + ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32691,9 +33463,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1952 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" + // Pos:1999 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" { - ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1201, + ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32707,9 +33479,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1953 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" + // Pos:2000 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1202, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32724,9 +33496,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1954 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" + // Pos:2001 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1202, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32742,9 +33514,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1955 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" + // Pos:2002 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1202, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32759,9 +33531,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1956 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" + // Pos:2003 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1202, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32777,9 +33549,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1957 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" + // Pos:2004 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1202, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32794,9 +33566,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1958 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" + // Pos:2005 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1202, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32810,9 +33582,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1959 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" + // Pos:2006 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1202, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32827,9 +33599,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1960 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" + // Pos:2007 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1202, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32843,9 +33615,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1961 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" + // Pos:2008 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1203, + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32860,9 +33632,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1962 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" + // Pos:2009 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1203, + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32877,9 +33649,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1963 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" + // Pos:2010 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1203, + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32893,9 +33665,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1964 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" + // Pos:2011 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1203, + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32909,9 +33681,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1965 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" + // Pos:2012 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1204, + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1234, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32926,9 +33698,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1966 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" + // Pos:2013 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1204, + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1234, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32943,9 +33715,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1967 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" + // Pos:2014 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1204, + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1234, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32959,9 +33731,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1968 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" + // Pos:2015 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1204, + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1234, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32975,9 +33747,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1969 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM" + // Pos:2016 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM" { - ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1205, + ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1235, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -32991,9 +33763,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1970 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM" + // Pos:2017 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM" { - ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1205, + ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1235, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33007,9 +33779,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1971 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR" + // Pos:2018 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR" { - ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1205, + ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1235, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33023,9 +33795,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1972 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR" + // Pos:2019 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR" { - ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1205, + ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1235, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33039,9 +33811,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1973 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" + // Pos:2020 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" { - ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1206, + ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33057,9 +33829,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1974 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" + // Pos:2021 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" { - ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1207, + ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1237, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -33073,9 +33845,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1975 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" + // Pos:2022 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" { - ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1208, + ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1238, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -33089,9 +33861,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1976 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" + // Pos:2023 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" { - ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1209, + ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1239, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, @@ -33106,9 +33878,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1977 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/"" + // Pos:2024 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/"" { - ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1210, + ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1240, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -33121,9 +33893,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1978 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" + // Pos:2025 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" { - ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1211, + ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1241, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -33136,9 +33908,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1979 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" + // Pos:2026 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" { - ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1212, + ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1242, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -33151,9 +33923,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1980 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" + // Pos:2027 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" { - ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1213, + ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1243, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33169,9 +33941,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1981 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" + // Pos:2028 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" { - ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1213, + ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1243, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33186,9 +33958,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1982 Instruction:"VMULPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM" + // Pos:2029 Instruction:"VMULPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM" { - ND_INS_VMULPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1214, + ND_INS_VMULPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1244, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33204,9 +33976,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1983 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" + // Pos:2030 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" { - ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1215, + ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1245, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33222,9 +33994,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1984 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" + // Pos:2031 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" { - ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1215, + ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1245, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33239,9 +34011,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1985 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" + // Pos:2032 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" { - ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1216, + ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1246, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33257,9 +34029,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1986 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" + // Pos:2033 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" { - ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1216, + ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1246, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33274,9 +34046,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1987 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM" + // Pos:2034 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM" { - ND_INS_VMULSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1217, + ND_INS_VMULSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1247, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33292,9 +34064,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1988 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" + // Pos:2035 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" { - ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1218, + ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1248, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33310,9 +34082,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1989 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" + // Pos:2036 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" { - ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1218, + ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1248, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33327,9 +34099,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1990 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" + // Pos:2037 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" { - ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1219, + ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1249, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, @@ -33344,9 +34116,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1991 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/"" + // Pos:2038 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/"" { - ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1220, + ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1250, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -33359,9 +34131,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1992 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" + // Pos:2039 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" { - ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1221, + ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1251, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -33375,9 +34147,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1993 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" + // Pos:2040 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" { - ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1222, + ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1252, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -33393,9 +34165,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1994 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" + // Pos:2041 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" { - ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1222, + ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1252, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33410,9 +34182,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1995 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" + // Pos:2042 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" { - ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1223, + ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1253, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -33428,9 +34200,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1996 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" + // Pos:2043 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" { - ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1223, + ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1253, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33445,9 +34217,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1997 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" + // Pos:2044 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" { - ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1224, + ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1254, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, @@ -33462,9 +34234,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1998 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" + // Pos:2045 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" { - ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1225, + ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1255, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, @@ -33479,9 +34251,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:1999 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" + // Pos:2046 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" { - ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1226, + ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1256, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, @@ -33497,9 +34269,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2000 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" + // Pos:2047 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" { - ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1227, + ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1257, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, @@ -33515,9 +34287,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2001 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" + // Pos:2048 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" { - ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1228, + ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1258, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33532,9 +34304,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2002 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" + // Pos:2049 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" { - ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1228, + ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1258, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33548,9 +34320,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2003 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" + // Pos:2050 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" { - ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1229, + ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1259, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33565,9 +34337,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2004 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" + // Pos:2051 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" { - ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1229, + ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1259, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33581,9 +34353,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2005 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" + // Pos:2052 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" { - ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1230, + ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1260, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33598,9 +34370,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2006 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" + // Pos:2053 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" { - ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1231, + ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1261, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33615,9 +34387,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2007 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" + // Pos:2054 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" { - ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1231, + ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1261, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33631,9 +34403,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2008 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" + // Pos:2055 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" { - ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1232, + ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1262, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33649,9 +34421,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2009 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" + // Pos:2056 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" { - ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1232, + ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1262, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33666,9 +34438,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2010 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" + // Pos:2057 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" { - ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1233, + ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1263, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33684,9 +34456,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2011 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" + // Pos:2058 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" { - ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1233, + ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1263, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33701,9 +34473,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2012 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" + // Pos:2059 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" { - ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1234, + ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1264, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33719,9 +34491,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2013 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" + // Pos:2060 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" { - ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1234, + ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1264, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33736,9 +34508,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2014 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" + // Pos:2061 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" { - ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1235, + ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1265, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33754,9 +34526,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2015 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" + // Pos:2062 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" { - ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1235, + ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1265, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33771,9 +34543,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2016 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" + // Pos:2063 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" { - ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1236, + ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1266, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33789,9 +34561,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2017 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" + // Pos:2064 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" { - ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1236, + ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1266, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33806,9 +34578,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2018 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" + // Pos:2065 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" { - ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1237, + ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1267, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33824,9 +34596,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2019 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" + // Pos:2066 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" { - ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1237, + ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1267, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33841,9 +34613,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2020 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" + // Pos:2067 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" { - ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1238, + ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1268, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33859,9 +34631,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2021 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" + // Pos:2068 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" { - ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1238, + ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1268, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33876,9 +34648,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2022 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" + // Pos:2069 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" { - ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1239, + ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1269, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33894,9 +34666,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2023 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" + // Pos:2070 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" { - ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1239, + ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1269, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33911,9 +34683,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2024 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" + // Pos:2071 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" { - ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1240, + ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1270, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33929,9 +34701,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2025 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" + // Pos:2072 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" { - ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1240, + ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1270, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33946,9 +34718,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2026 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" + // Pos:2073 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" { - ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1241, + ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1271, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33964,9 +34736,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2027 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:2074 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" { - ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1241, + ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1271, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33981,9 +34753,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2028 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" + // Pos:2075 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" { - ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1242, + ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1272, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33999,9 +34771,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2029 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:2076 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" { - ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1242, + ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1272, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34016,9 +34788,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2030 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" + // Pos:2077 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" { - ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1243, + ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1273, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34034,9 +34806,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2031 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" + // Pos:2078 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" { - ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1243, + ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1273, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34051,9 +34823,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2032 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" + // Pos:2079 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" { - ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1244, + ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1274, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34070,9 +34842,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2033 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" + // Pos:2080 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" { - ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1244, + ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1274, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34088,9 +34860,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2034 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" + // Pos:2081 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" { - ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1245, + ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1275, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34105,9 +34877,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2035 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" + // Pos:2082 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" { - ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1246, + ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1276, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34123,9 +34895,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2036 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:2083 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" { - ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1247, + ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1277, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34140,9 +34912,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2037 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" + // Pos:2084 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" { - ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1248, + ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1278, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34158,9 +34930,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2038 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" + // Pos:2085 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" { - ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1249, + ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1279, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34176,9 +34948,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2039 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" + // Pos:2086 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" { - ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1250, + ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1280, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34194,9 +34966,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2040 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" + // Pos:2087 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" { - ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1251, + ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1281, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34212,9 +34984,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2041 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" + // Pos:2088 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" { - ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1251, + ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1281, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34229,9 +35001,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2042 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" + // Pos:2089 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" { - ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1252, + ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34247,9 +35019,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2043 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" + // Pos:2090 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" { - ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1252, + ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34264,9 +35036,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2044 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" + // Pos:2091 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" { - ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1253, + ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1283, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -34282,9 +35054,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2045 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" + // Pos:2092 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" { - ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1254, + ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1284, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34300,9 +35072,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2046 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" + // Pos:2093 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" { - ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1255, + ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1285, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34318,9 +35090,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2047 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" + // Pos:2094 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" { - ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1256, + ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1286, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34336,9 +35108,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2048 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" + // Pos:2095 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" { - ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1257, + ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1287, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34354,9 +35126,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2049 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" + // Pos:2096 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" { - ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1258, + ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1288, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34372,9 +35144,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2050 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" + // Pos:2097 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" { - ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1259, + ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1289, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34390,9 +35162,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2051 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:2098 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1260, + ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1290, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34407,9 +35179,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2052 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" + // Pos:2099 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" { - ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1260, + ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1290, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34424,9 +35196,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2053 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" + // Pos:2100 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" { - ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1260, + ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1290, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -34440,9 +35212,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2054 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" + // Pos:2101 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" { - ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1261, + ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1291, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34457,9 +35229,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2055 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" + // Pos:2102 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" { - ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1261, + ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1291, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34474,9 +35246,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2056 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" + // Pos:2103 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" { - ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1261, + ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1291, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -34490,9 +35262,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2057 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" + // Pos:2104 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" { - ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1262, + ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1292, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -34506,9 +35278,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2058 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" + // Pos:2105 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" { - ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1263, + ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1293, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -34522,9 +35294,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2059 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" + // Pos:2106 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" { - ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1264, + ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1294, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34539,9 +35311,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2060 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" + // Pos:2107 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" { - ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1264, + ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1294, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34556,9 +35328,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2061 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" + // Pos:2108 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" { - ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1264, + ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1294, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -34572,9 +35344,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2062 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:2109 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1265, + ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1295, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34589,9 +35361,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2063 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" + // Pos:2110 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" { - ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1265, + ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1295, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34606,9 +35378,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2064 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" + // Pos:2111 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" { - ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1265, + ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1295, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -34622,9 +35394,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2065 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + // Pos:2112 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" { - ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1266, + ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1296, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, @@ -34640,9 +35412,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2066 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + // Pos:2113 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" { - ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1266, + ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1296, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, @@ -34658,9 +35430,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2067 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" + // Pos:2114 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" { - ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1267, + ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1297, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -34676,9 +35448,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2068 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" + // Pos:2115 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" { - ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1267, + ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1297, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -34694,9 +35466,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2069 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" + // Pos:2116 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" { - ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1268, + ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1298, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34713,9 +35485,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2070 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" + // Pos:2117 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" { - ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1269, + ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1299, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34732,9 +35504,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2071 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" + // Pos:2118 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" { - ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1270, + ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1300, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34750,9 +35522,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2072 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" + // Pos:2119 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" { - ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1270, + ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1300, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34767,9 +35539,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2073 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" + // Pos:2120 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" { - ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1271, + ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1301, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34785,9 +35557,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2074 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" + // Pos:2121 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" { - ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1271, + ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1301, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34802,9 +35574,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2075 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" + // Pos:2122 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" { - ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1272, + ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34820,9 +35592,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2076 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" + // Pos:2123 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" { - ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1272, + ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34837,9 +35609,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2077 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" + // Pos:2124 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" { - ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1273, + ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34855,9 +35627,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2078 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" + // Pos:2125 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" { - ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1273, + ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34872,9 +35644,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2079 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" + // Pos:2126 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" { - ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1274, + ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1304, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34893,9 +35665,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2080 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" + // Pos:2127 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" { - ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1275, + ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1305, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34914,9 +35686,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2081 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" + // Pos:2128 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" { - ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1276, + ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1306, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34932,9 +35704,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2082 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" + // Pos:2129 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" { - ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1276, + ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1306, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34949,9 +35721,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2083 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" + // Pos:2130 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" { - ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1277, + ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1307, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34967,9 +35739,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2084 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" + // Pos:2131 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" { - ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1277, + ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1307, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34984,9 +35756,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2085 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" + // Pos:2132 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" { - ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1278, + ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1308, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35002,9 +35774,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2086 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" + // Pos:2133 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" { - ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1278, + ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1308, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35019,9 +35791,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2087 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" + // Pos:2134 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" { - ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1279, + ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1309, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35037,9 +35809,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2088 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" + // Pos:2135 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" { - ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1279, + ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1309, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35054,9 +35826,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2089 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" + // Pos:2136 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" { - ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1280, + ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1310, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35073,9 +35845,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2090 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" + // Pos:2137 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" { - ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1281, + ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1311, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35092,9 +35864,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2091 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" + // Pos:2138 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" { - ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1282, + ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1312, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35111,9 +35883,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2092 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" + // Pos:2139 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" { - ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1283, + ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1313, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35130,9 +35902,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2093 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" + // Pos:2140 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" { - ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1284, + ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1314, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35149,9 +35921,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2094 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" + // Pos:2141 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" { - ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1285, + ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1315, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35168,9 +35940,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2095 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" + // Pos:2142 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" { - ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1286, + ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1316, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35187,9 +35959,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2096 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" + // Pos:2143 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" { - ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1287, + ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1317, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35206,9 +35978,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2097 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" + // Pos:2144 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" { - ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1288, + ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1318, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35224,9 +35996,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2098 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" + // Pos:2145 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" { - ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1289, + ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1319, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35242,9 +36014,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2099 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" + // Pos:2146 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" { - ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1290, + ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1320, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -35259,9 +36031,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2100 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" + // Pos:2147 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" { - ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1291, + ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1321, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35276,9 +36048,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2101 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" + // Pos:2148 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" { - ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1292, + ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1322, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35293,9 +36065,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2102 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" + // Pos:2149 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" { - ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1293, + ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1323, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -35310,9 +36082,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2103 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" + // Pos:2150 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" { - ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1294, + ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1324, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35328,9 +36100,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2104 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" + // Pos:2151 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" { - ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1295, + ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1325, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35346,9 +36118,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2105 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" + // Pos:2152 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" { - ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1296, + ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1326, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35364,9 +36136,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2106 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" + // Pos:2153 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" { - ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1297, + ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1327, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35382,9 +36154,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2107 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" + // Pos:2154 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" { - ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1298, + ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1328, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35400,9 +36172,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2108 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" + // Pos:2155 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" { - ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1299, + ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1329, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35418,9 +36190,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2109 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" + // Pos:2156 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" { - ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1300, + ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1330, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -35435,9 +36207,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2110 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" + // Pos:2157 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" { - ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1301, + ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1331, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -35452,9 +36224,77 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2111 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" + // Pos:2158 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM" + { + ND_INS_VPDPBSSD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1332, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2159 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM" + { + ND_INS_VPDPBSSDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1333, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2160 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM" { - ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1302, + ND_INS_VPDPBSUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1334, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2161 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM" + { + ND_INS_VPDPBSUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1335, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2162 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" + { + ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1336, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, @@ -35470,9 +36310,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2112 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM" + // Pos:2163 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM" { - ND_INS_VPDPBUSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1302, + ND_INS_VPDPBUSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1336, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, @@ -35487,9 +36327,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2113 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" + // Pos:2164 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" { - ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1303, + ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1337, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, @@ -35505,9 +36345,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2114 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM" + // Pos:2165 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM" { - ND_INS_VPDPBUSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1303, + ND_INS_VPDPBUSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1337, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, @@ -35522,9 +36362,43 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2115 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" + // Pos:2166 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM" { - ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1304, + ND_INS_VPDPBUUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1338, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2167 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM" + { + ND_INS_VPDPBUUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1339, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2168 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" + { + ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1340, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, @@ -35540,9 +36414,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2116 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM" + // Pos:2169 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM" { - ND_INS_VPDPWSSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1304, + ND_INS_VPDPWSSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1340, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, @@ -35557,9 +36431,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2117 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" + // Pos:2170 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" { - ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1305, + ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1341, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, @@ -35575,9 +36449,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2118 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM" + // Pos:2171 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM" { - ND_INS_VPDPWSSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1305, + ND_INS_VPDPWSSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1341, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, @@ -35592,9 +36466,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2119 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" + // Pos:2172 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" { - ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1306, + ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1342, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35610,9 +36484,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2120 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" + // Pos:2173 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" { - ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1307, + ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1343, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -35628,9 +36502,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2121 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" + // Pos:2174 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" { - ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1308, + ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1344, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, @@ -35646,9 +36520,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2122 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" + // Pos:2175 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" { - ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1309, + ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1345, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35664,9 +36538,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2123 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" + // Pos:2176 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" { - ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1309, + ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1345, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -35681,9 +36555,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2124 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" + // Pos:2177 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" { - ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1310, + ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1346, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, @@ -35699,9 +36573,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2125 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" + // Pos:2178 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" { - ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1311, + ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1347, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35717,9 +36591,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2126 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" + // Pos:2179 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" { - ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1312, + ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1348, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35735,9 +36609,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2127 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" + // Pos:2180 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" { - ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1313, + ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1349, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35753,9 +36627,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2128 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" + // Pos:2181 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" { - ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1314, + ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1350, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35771,9 +36645,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2129 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" + // Pos:2182 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" { - ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1315, + ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1351, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35789,9 +36663,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2130 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML" + // Pos:2183 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML" { - ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1316, + ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1352, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35808,9 +36682,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2131 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM" + // Pos:2184 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM" { - ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1316, + ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1352, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35827,9 +36701,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2132 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML" + // Pos:2185 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML" { - ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1317, + ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1353, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35846,9 +36720,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2133 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM" + // Pos:2186 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM" { - ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1317, + ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1353, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35865,9 +36739,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2134 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" + // Pos:2187 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" { - ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1318, + ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1354, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35883,9 +36757,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2135 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" + // Pos:2188 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" { - ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1318, + ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1354, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35901,9 +36775,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2136 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" + // Pos:2189 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" { - ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1318, + ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1354, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35918,9 +36792,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2137 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" + // Pos:2190 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" { - ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1318, + ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1354, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35935,9 +36809,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2138 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" + // Pos:2191 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" { - ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1319, + ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35953,9 +36827,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2139 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" + // Pos:2192 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" { - ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1319, + ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35971,9 +36845,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2140 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" + // Pos:2193 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" { - ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1319, + ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35988,9 +36862,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2141 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" + // Pos:2194 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" { - ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1319, + ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36005,9 +36879,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2142 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" + // Pos:2195 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" { - ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1320, + ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36023,9 +36897,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2143 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" + // Pos:2196 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" { - ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1320, + ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36041,9 +36915,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2144 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" + // Pos:2197 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" { - ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1320, + ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36059,9 +36933,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2145 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" + // Pos:2198 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" { - ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1320, + ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -36076,9 +36950,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2146 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" + // Pos:2199 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" { - ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1321, + ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36094,9 +36968,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2147 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" + // Pos:2200 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" { - ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1321, + ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36112,9 +36986,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2148 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" + // Pos:2201 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" { - ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1321, + ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -36129,9 +37003,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2149 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" + // Pos:2202 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" { - ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1322, + ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1358, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36147,9 +37021,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2150 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" + // Pos:2203 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" { - ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1322, + ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1358, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36165,9 +37039,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2151 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" + // Pos:2204 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" { - ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1322, + ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1358, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -36182,9 +37056,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2152 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" + // Pos:2205 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" { - ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1323, + ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1359, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, @@ -36200,9 +37074,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2153 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" + // Pos:2206 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" { - ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1324, + ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1360, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36218,9 +37092,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2154 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" + // Pos:2207 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" { - ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1325, + ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36236,9 +37110,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2155 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" + // Pos:2208 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" { - ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1326, + ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36254,9 +37128,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2156 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" + // Pos:2209 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" { - ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1327, + ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36272,9 +37146,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2157 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" + // Pos:2210 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" { - ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1328, + ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36290,9 +37164,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2158 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" + // Pos:2211 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" { - ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1329, + ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1365, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36308,9 +37182,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2159 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" + // Pos:2212 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" { - ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1330, + ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1366, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -36325,9 +37199,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2160 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" + // Pos:2213 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" { - ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1331, + ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1367, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36342,9 +37216,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2161 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" + // Pos:2214 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" { - ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1332, + ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1368, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36359,9 +37233,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2162 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" + // Pos:2215 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" { - ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1333, + ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1369, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -36376,9 +37250,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2163 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + // Pos:2216 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" { - ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1334, + ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1370, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36393,12 +37267,12 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2164 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + // Pos:2217 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" { - ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1334, + ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1370, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, @@ -36410,9 +37284,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2165 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + // Pos:2218 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" { - ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1334, + ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1370, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36427,26 +37301,26 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2166 Instruction:"VPEXTRB Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + // Pos:2219 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" { - ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1334, + ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1370, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:2167 Instruction:"VPEXTRD Ed,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI" + // Pos:2220 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" { - ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1335, + ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1371, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -36455,15 +37329,32 @@ const ND_INSTRUCTION gInstructions[2701] = 0, 0, { - OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2221 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" + { + ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1371, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:2168 Instruction:"VPEXTRD Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI" + // Pos:2222 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" { - ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1335, + ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1371, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36472,15 +37363,32 @@ const ND_INSTRUCTION gInstructions[2701] = 0, 0, { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2223 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" + { + ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1371, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:2169 Instruction:"VPEXTRQ Eq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI" + // Pos:2224 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" { - ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1336, + ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1372, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -36489,15 +37397,32 @@ const ND_INSTRUCTION gInstructions[2701] = 0, 0, { - OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2225 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" + { + ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1372, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:2170 Instruction:"VPEXTRQ Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI" + // Pos:2226 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" { - ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1336, + ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1372, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36506,15 +37431,32 @@ const ND_INSTRUCTION gInstructions[2701] = 0, 0, { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:2171 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + // Pos:2227 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1337, + ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1372, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2228 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + { + ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36529,9 +37471,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2172 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + // Pos:2229 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1337, + ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36546,12 +37488,12 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2173 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + // Pos:2230 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1337, + ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, @@ -36563,12 +37505,12 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2174 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + // Pos:2231 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" { - ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1337, + ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -36580,9 +37522,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2175 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + // Pos:2232 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1337, + ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36597,26 +37539,26 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2176 Instruction:"VPEXTRW Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + // Pos:2233 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1337, + ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:2177 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" + // Pos:2234 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" { - ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1338, + ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36631,9 +37573,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2178 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" + // Pos:2235 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" { - ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1338, + ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -36648,9 +37590,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2179 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" + // Pos:2236 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" { - ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1339, + ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1375, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36665,9 +37607,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2180 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" + // Pos:2237 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" { - ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1339, + ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1375, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -36682,9 +37624,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2181 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" + // Pos:2238 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" { - ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1340, + ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1376, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36699,9 +37641,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2182 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" + // Pos:2239 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" { - ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1340, + ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1376, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -36716,9 +37658,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2183 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" + // Pos:2240 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" { - ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1341, + ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1377, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36733,9 +37675,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2184 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" + // Pos:2241 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" { - ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1341, + ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1377, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -36750,9 +37692,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2185 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" + // Pos:2242 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" { - ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1342, + ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1378, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36766,9 +37708,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2186 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" + // Pos:2243 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" { - ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1343, + ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1379, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36782,9 +37724,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2187 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" + // Pos:2244 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" { - ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1344, + ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1380, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36798,9 +37740,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2188 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" + // Pos:2245 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" { - ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1345, + ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1381, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36815,9 +37757,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2189 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" + // Pos:2246 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" { - ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1346, + ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1382, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36831,9 +37773,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2190 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" + // Pos:2247 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" { - ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1347, + ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1383, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36848,9 +37790,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2191 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" + // Pos:2248 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" { - ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1348, + ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1384, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36864,9 +37806,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2192 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" + // Pos:2249 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" { - ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1349, + ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1385, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36880,9 +37822,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2193 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" + // Pos:2250 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" { - ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1350, + ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1386, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36896,9 +37838,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2194 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" + // Pos:2251 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" { - ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1351, + ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1387, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36912,9 +37854,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2195 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" + // Pos:2252 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" { - ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1352, + ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1388, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36928,9 +37870,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2196 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" + // Pos:2253 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" { - ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1353, + ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1389, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36944,9 +37886,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2197 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" + // Pos:2254 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" { - ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1354, + ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1390, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36961,9 +37903,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2198 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" + // Pos:2255 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" { - ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1355, + ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1391, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36977,9 +37919,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2199 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" + // Pos:2256 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" { - ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1356, + ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1392, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36993,9 +37935,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2200 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" + // Pos:2257 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" { - ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1357, + ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1393, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37009,9 +37951,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2201 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" + // Pos:2258 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" { - ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1358, + ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1394, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37025,9 +37967,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2202 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" + // Pos:2259 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" { - ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1359, + ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1395, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37042,9 +37984,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2203 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" + // Pos:2260 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" { - ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1360, + ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1396, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37058,9 +38000,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2204 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" + // Pos:2261 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" { - ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1361, + ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1397, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37075,9 +38017,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2205 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" + // Pos:2262 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" { - ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1362, + ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1398, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37092,9 +38034,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2206 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" + // Pos:2263 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" { - ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1363, + ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1399, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37108,9 +38050,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2207 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + // Pos:2264 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" { - ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1364, + ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1400, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37126,9 +38068,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2208 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + // Pos:2265 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" { - ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1364, + ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1400, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37144,9 +38086,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2209 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + // Pos:2266 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" { - ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1364, + ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1400, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37162,9 +38104,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2210 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + // Pos:2267 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" { - ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1364, + ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1400, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37180,9 +38122,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2211 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + // Pos:2268 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" { - ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1365, + ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1401, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -37198,9 +38140,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2212 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + // Pos:2269 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" { - ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1365, + ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1401, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37216,9 +38158,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2213 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + // Pos:2270 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" { - ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1366, + ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1402, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -37234,9 +38176,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2214 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + // Pos:2271 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" { - ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1366, + ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1402, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37252,9 +38194,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2215 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + // Pos:2272 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" { - ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1367, + ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1403, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37270,9 +38212,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2216 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + // Pos:2273 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" { - ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1367, + ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1403, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37288,9 +38230,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2217 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + // Pos:2274 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" { - ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1367, + ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1403, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37306,9 +38248,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2218 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + // Pos:2275 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" { - ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1367, + ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1403, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37324,9 +38266,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2219 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" + // Pos:2276 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" { - ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1368, + ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1404, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -37341,9 +38283,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2220 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" + // Pos:2277 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" { - ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1369, + ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1405, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -37358,9 +38300,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2221 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" + // Pos:2278 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" { - ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1370, + ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1406, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37376,9 +38318,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2222 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" + // Pos:2279 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" { - ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1371, + ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1407, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37394,9 +38336,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2223 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" + // Pos:2280 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" { - ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1372, + ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1408, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37412,9 +38354,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2224 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" + // Pos:2281 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" { - ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1373, + ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1409, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37430,9 +38372,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2225 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" + // Pos:2282 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" { - ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1374, + ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1410, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37448,9 +38390,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2226 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" + // Pos:2283 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" { - ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1375, + ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1411, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37466,9 +38408,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2227 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" + // Pos:2284 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" { - ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1376, + ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1412, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37484,9 +38426,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2228 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" + // Pos:2285 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" { - ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1377, + ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1413, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37502,9 +38444,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2229 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" + // Pos:2286 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" { - ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1378, + ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1414, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37520,9 +38462,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2230 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" + // Pos:2287 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" { - ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1379, + ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1415, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37538,9 +38480,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2231 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" + // Pos:2288 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" { - ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1380, + ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1416, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37556,9 +38498,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2232 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" + // Pos:2289 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" { - ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1381, + ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1417, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37574,9 +38516,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2233 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" + // Pos:2290 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" { - ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1382, + ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1418, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, @@ -37592,9 +38534,26 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2234 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" + // Pos:2291 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM" { - ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1383, + ND_INS_VPMADD52HUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1418, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXIFMA, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2292 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" + { + ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1419, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, @@ -37610,9 +38569,26 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2235 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" + // Pos:2293 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM" { - ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1384, + ND_INS_VPMADD52LUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1419, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXIFMA, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2294 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" + { + ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1420, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37628,9 +38604,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2236 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" + // Pos:2295 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" { - ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1384, + ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1420, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37645,9 +38621,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2237 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" + // Pos:2296 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" { - ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1385, + ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1421, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37663,9 +38639,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2238 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" + // Pos:2297 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" { - ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1385, + ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1421, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37680,9 +38656,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2239 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" + // Pos:2298 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" { - ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1386, + ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1422, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -37697,9 +38673,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2240 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" + // Pos:2299 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" { - ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1386, + ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1422, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -37714,9 +38690,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2241 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" + // Pos:2300 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" { - ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1387, + ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1423, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -37731,9 +38707,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2242 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" + // Pos:2301 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" { - ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1387, + ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1423, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -37748,9 +38724,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2243 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" + // Pos:2302 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" { - ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1388, + ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1424, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37766,9 +38742,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2244 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" + // Pos:2303 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" { - ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1388, + ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1424, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37783,9 +38759,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2245 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" + // Pos:2304 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" { - ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1389, + ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1425, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37801,9 +38777,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2246 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" + // Pos:2305 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" { - ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1389, + ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1425, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37818,9 +38794,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2247 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" + // Pos:2306 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" { - ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1390, + ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1426, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37836,9 +38812,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2248 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" + // Pos:2307 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" { - ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1391, + ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1427, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37854,9 +38830,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2249 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" + // Pos:2308 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" { - ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1391, + ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1427, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37871,9 +38847,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2250 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" + // Pos:2309 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" { - ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1392, + ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1428, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37889,9 +38865,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2251 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:2310 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" { - ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1392, + ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1428, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37906,9 +38882,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2252 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" + // Pos:2311 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" { - ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1393, + ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1429, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37924,9 +38900,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2253 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" + // Pos:2312 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" { - ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1393, + ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1429, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37941,9 +38917,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2254 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" + // Pos:2313 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" { - ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1394, + ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1430, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37959,9 +38935,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2255 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" + // Pos:2314 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" { - ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1395, + ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1431, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37977,9 +38953,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2256 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" + // Pos:2315 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" { - ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1395, + ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1431, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37994,9 +38970,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2257 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" + // Pos:2316 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" { - ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1396, + ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1432, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38012,9 +38988,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2258 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" + // Pos:2317 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" { - ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1396, + ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1432, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38029,9 +39005,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2259 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" + // Pos:2318 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" { - ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1397, + ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1433, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38047,9 +39023,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2260 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" + // Pos:2319 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" { - ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1397, + ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1433, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38064,9 +39040,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2261 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" + // Pos:2320 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" { - ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1398, + ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1434, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38082,9 +39058,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2262 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" + // Pos:2321 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" { - ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1399, + ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1435, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38100,9 +39076,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2263 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" + // Pos:2322 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" { - ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1399, + ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1435, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38117,9 +39093,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2264 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" + // Pos:2323 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" { - ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1400, + ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1436, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38135,9 +39111,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2265 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" + // Pos:2324 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" { - ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1400, + ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1436, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38152,9 +39128,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2266 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" + // Pos:2325 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" { - ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1401, + ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1437, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38170,9 +39146,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2267 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" + // Pos:2326 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" { - ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1401, + ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1437, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38187,9 +39163,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2268 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" + // Pos:2327 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" { - ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1402, + ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1438, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38205,9 +39181,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2269 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" + // Pos:2328 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" { - ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1403, + ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1439, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38223,9 +39199,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2270 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" + // Pos:2329 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" { - ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1403, + ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1439, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38240,9 +39216,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2271 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" + // Pos:2330 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" { - ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1404, + ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1440, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38256,9 +39232,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2272 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" + // Pos:2331 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" { - ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1405, + ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1441, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -38272,9 +39248,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2273 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" + // Pos:2332 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" { - ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1406, + ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1442, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38289,9 +39265,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2274 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" + // Pos:2333 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" { - ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1407, + ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1443, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38306,9 +39282,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2275 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" + // Pos:2334 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" { - ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1408, + ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1444, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38322,9 +39298,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2276 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" + // Pos:2335 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" { - ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1409, + ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1445, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -38338,9 +39314,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2277 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" + // Pos:2336 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" { - ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1410, + ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1446, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -38354,9 +39330,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2278 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" + // Pos:2337 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" { - ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1411, + ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1447, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38370,12 +39346,12 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2279 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" + // Pos:2338 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" { - ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1412, + ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1448, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -38386,9 +39362,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2280 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" + // Pos:2339 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" { - ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1413, + ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1449, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -38402,9 +39378,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2281 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" + // Pos:2340 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" { - ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1414, + ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1450, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38419,9 +39395,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2282 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" + // Pos:2341 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" { - ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1415, + ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1451, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38436,9 +39412,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2283 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" + // Pos:2342 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" { - ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1416, + ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1452, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38453,9 +39429,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2284 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" + // Pos:2343 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" { - ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1417, + ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1453, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38470,9 +39446,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2285 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" + // Pos:2344 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" { - ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1418, + ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1454, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38487,9 +39463,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2286 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" + // Pos:2345 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" { - ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1419, + ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1455, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38504,9 +39480,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2287 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" + // Pos:2346 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" { - ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1420, + ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1456, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38521,9 +39497,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2288 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" + // Pos:2347 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" { - ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1421, + ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1457, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38538,9 +39514,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2289 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" + // Pos:2348 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" { - ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1422, + ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1458, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38555,9 +39531,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2290 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" + // Pos:2349 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" { - ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1423, + ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1459, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38572,9 +39548,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2291 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" + // Pos:2350 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" { - ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1423, + ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1459, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38588,9 +39564,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2292 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" + // Pos:2351 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" { - ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1423, + ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1459, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -38604,9 +39580,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2293 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" + // Pos:2352 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" { - ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1424, + ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1460, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38621,9 +39597,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2294 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" + // Pos:2353 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" { - ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1424, + ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1460, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38637,9 +39613,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2295 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" + // Pos:2354 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" { - ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1424, + ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1460, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -38653,9 +39629,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2296 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" + // Pos:2355 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" { - ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1425, + ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1461, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38670,9 +39646,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2297 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" + // Pos:2356 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" { - ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1425, + ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1461, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38686,9 +39662,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2298 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" + // Pos:2357 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" { - ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1425, + ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1461, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -38702,9 +39678,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2299 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" + // Pos:2358 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" { - ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1426, + ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1462, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38719,9 +39695,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2300 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" + // Pos:2359 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" { - ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1426, + ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1462, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38735,9 +39711,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2301 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" + // Pos:2360 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" { - ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1426, + ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1462, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -38751,9 +39727,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2302 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" + // Pos:2361 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" { - ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1427, + ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1463, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38768,9 +39744,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2303 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" + // Pos:2362 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" { - ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1427, + ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1463, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38784,9 +39760,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2304 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" + // Pos:2363 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" { - ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1427, + ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1463, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -38800,9 +39776,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2305 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" + // Pos:2364 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" { - ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1428, + ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1464, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38817,9 +39793,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2306 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" + // Pos:2365 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" { - ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1428, + ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1464, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38833,9 +39809,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2307 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" + // Pos:2366 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" { - ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1428, + ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1464, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -38849,9 +39825,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2308 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" + // Pos:2367 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" { - ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1429, + ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1465, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38866,9 +39842,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2309 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" + // Pos:2368 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" { - ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1430, + ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1466, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38883,9 +39859,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2310 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" + // Pos:2369 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" { - ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1431, + ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1467, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38900,9 +39876,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2311 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" + // Pos:2370 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" { - ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1432, + ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1468, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38917,9 +39893,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2312 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" + // Pos:2371 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" { - ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1433, + ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1469, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38934,9 +39910,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2313 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" + // Pos:2372 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" { - ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1434, + ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1470, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38951,9 +39927,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2314 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" + // Pos:2373 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" { - ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1435, + ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1471, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38967,9 +39943,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2315 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" + // Pos:2374 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" { - ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1436, + ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1472, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38984,9 +39960,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2316 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" + // Pos:2375 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" { - ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1437, + ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1473, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39001,9 +39977,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2317 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" + // Pos:2376 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" { - ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1437, + ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1473, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39017,9 +39993,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2318 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" + // Pos:2377 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" { - ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1437, + ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1473, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39033,9 +40009,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2319 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" + // Pos:2378 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" { - ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1438, + ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1474, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39050,9 +40026,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2320 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" + // Pos:2379 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" { - ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1438, + ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1474, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39066,9 +40042,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2321 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" + // Pos:2380 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" { - ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1438, + ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1474, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39082,9 +40058,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2322 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" + // Pos:2381 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" { - ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1439, + ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1475, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39099,9 +40075,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2323 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" + // Pos:2382 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" { - ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1439, + ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1475, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39115,9 +40091,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2324 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" + // Pos:2383 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" { - ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1439, + ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1475, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39131,9 +40107,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2325 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" + // Pos:2384 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" { - ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1440, + ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1476, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39148,9 +40124,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2326 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" + // Pos:2385 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" { - ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1440, + ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1476, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39164,9 +40140,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2327 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" + // Pos:2386 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" { - ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1440, + ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1476, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39180,9 +40156,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2328 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" + // Pos:2387 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" { - ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1441, + ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1477, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39197,9 +40173,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2329 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" + // Pos:2388 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" { - ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1441, + ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1477, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39213,9 +40189,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2330 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" + // Pos:2389 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" { - ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1441, + ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1477, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39229,9 +40205,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2331 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" + // Pos:2390 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" { - ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1442, + ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1478, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39246,9 +40222,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2332 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" + // Pos:2391 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" { - ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1442, + ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1478, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39262,9 +40238,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2333 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" + // Pos:2392 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" { - ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1442, + ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1478, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39278,9 +40254,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2334 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" + // Pos:2393 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" { - ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1443, + ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1479, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39296,9 +40272,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2335 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" + // Pos:2394 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" { - ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1443, + ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1479, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39313,9 +40289,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2336 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" + // Pos:2395 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" { - ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1444, + ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1480, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39331,9 +40307,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2337 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" + // Pos:2396 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" { - ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1444, + ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1480, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39348,9 +40324,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2338 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" + // Pos:2397 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" { - ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1445, + ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1481, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39366,9 +40342,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2339 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" + // Pos:2398 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" { - ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1445, + ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1481, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39383,9 +40359,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2340 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" + // Pos:2399 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" { - ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1446, + ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1482, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39401,9 +40377,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2341 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" + // Pos:2400 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" { - ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1446, + ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1482, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39418,9 +40394,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2342 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" + // Pos:2401 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" { - ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1447, + ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1483, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39436,9 +40412,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2343 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" + // Pos:2402 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" { - ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1447, + ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1483, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39453,9 +40429,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2344 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" + // Pos:2403 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" { - ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1448, + ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1484, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -39471,9 +40447,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2345 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" + // Pos:2404 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" { - ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1449, + ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1485, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39489,9 +40465,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2346 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" + // Pos:2405 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" { - ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1449, + ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1485, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39506,9 +40482,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2347 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" + // Pos:2406 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" { - ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1450, + ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1486, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, @@ -39524,9 +40500,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2348 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" + // Pos:2407 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" { - ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1451, + ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1487, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39542,9 +40518,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2349 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" + // Pos:2408 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" { - ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1451, + ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1487, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39559,9 +40535,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2350 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" + // Pos:2409 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" { - ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1452, + ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1488, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, @@ -39576,9 +40552,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2351 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" + // Pos:2410 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" { - ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1453, + ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1489, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, @@ -39593,9 +40569,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2352 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" + // Pos:2411 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" { - ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1454, + ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1490, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, @@ -39610,9 +40586,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2353 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" + // Pos:2412 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" { - ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1455, + ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1491, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, @@ -39627,9 +40603,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2354 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" + // Pos:2413 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" { - ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1456, + ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1492, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39644,9 +40620,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2355 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" + // Pos:2414 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" { - ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1457, + ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1493, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39662,9 +40638,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2356 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" + // Pos:2415 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" { - ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1458, + ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1494, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39680,9 +40656,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2357 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" + // Pos:2416 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" { - ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1459, + ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1495, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -39698,9 +40674,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2358 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" + // Pos:2417 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" { - ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1459, + ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1495, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -39716,9 +40692,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2359 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" + // Pos:2418 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" { - ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1460, + ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1496, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39734,9 +40710,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2360 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" + // Pos:2419 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" { - ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1461, + ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1497, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39752,9 +40728,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2361 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" + // Pos:2420 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" { - ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1462, + ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1498, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39770,9 +40746,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2362 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" + // Pos:2421 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" { - ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1463, + ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1499, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39788,9 +40764,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2363 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" + // Pos:2422 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" { - ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1464, + ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1500, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39806,9 +40782,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2364 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" + // Pos:2423 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" { - ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1465, + ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1501, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39824,9 +40800,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2365 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" + // Pos:2424 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" { - ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1466, + ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1502, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39842,9 +40818,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2366 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" + // Pos:2425 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" { - ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1467, + ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39860,9 +40836,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2367 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" + // Pos:2426 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" { - ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1468, + ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1504, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -39877,9 +40853,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2368 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" + // Pos:2427 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" { - ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1468, + ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1504, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -39894,9 +40870,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2369 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" + // Pos:2428 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" { - ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1468, + ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1504, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -39911,9 +40887,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2370 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" + // Pos:2429 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" { - ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1469, + ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1505, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -39928,9 +40904,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2371 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" + // Pos:2430 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" { - ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1469, + ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1505, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -39945,9 +40921,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2372 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" + // Pos:2431 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" { - ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1469, + ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1505, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -39962,9 +40938,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2373 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" + // Pos:2432 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" { - ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1470, + ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1506, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -39979,9 +40955,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2374 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" + // Pos:2433 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" { - ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1470, + ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1506, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -39996,9 +40972,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2375 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" + // Pos:2434 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" { - ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1470, + ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1506, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40013,9 +40989,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2376 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" + // Pos:2435 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" { - ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1471, + ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1507, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40030,9 +41006,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2377 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" + // Pos:2436 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" { - ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1471, + ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1507, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40047,9 +41023,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2378 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" + // Pos:2437 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" { - ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1471, + ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1507, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40064,9 +41040,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2379 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + // Pos:2438 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" { - ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1472, + ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1508, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40081,9 +41057,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2380 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + // Pos:2439 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" { - ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1472, + ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1508, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40098,9 +41074,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2381 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" + // Pos:2440 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" { - ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1473, + ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1509, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40115,9 +41091,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2382 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" + // Pos:2441 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" { - ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1474, + ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1510, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40132,9 +41108,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2383 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" + // Pos:2442 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" { - ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1475, + ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1511, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40149,9 +41125,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2384 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" + // Pos:2443 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" { - ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1476, + ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1512, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40166,9 +41142,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2385 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" + // Pos:2444 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" { - ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1477, + ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1513, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40183,9 +41159,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2386 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" + // Pos:2445 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" { - ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1477, + ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1513, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40200,9 +41176,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2387 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" + // Pos:2446 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" { - ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1478, + ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1514, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40217,9 +41193,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2388 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" + // Pos:2447 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" { - ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1478, + ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1514, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40234,9 +41210,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2389 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" + // Pos:2448 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" { - ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1479, + ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1515, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40251,9 +41227,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2390 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" + // Pos:2449 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" { - ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1479, + ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1515, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40268,9 +41244,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2391 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" + // Pos:2450 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" { - ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1480, + ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1516, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40285,9 +41261,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2392 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" + // Pos:2451 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" { - ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1480, + ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1516, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40302,9 +41278,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2393 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" + // Pos:2452 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1481, + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1517, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40319,9 +41295,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2394 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" + // Pos:2453 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1481, + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1517, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40336,9 +41312,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2395 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" + // Pos:2454 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1481, + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1517, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40353,9 +41329,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2396 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" + // Pos:2455 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1481, + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1517, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40370,9 +41346,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2397 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" + // Pos:2456 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" { - ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1482, + ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1518, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40387,9 +41363,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2398 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" + // Pos:2457 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" { - ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1483, + ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1519, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -40406,9 +41382,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2399 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" + // Pos:2458 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" { - ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1484, + ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1520, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -40425,9 +41401,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2400 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" + // Pos:2459 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" { - ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1485, + ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1521, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -40443,9 +41419,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2401 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" + // Pos:2460 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" { - ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1486, + ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1522, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -40461,9 +41437,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2402 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" + // Pos:2461 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" { - ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1487, + ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1523, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -40479,9 +41455,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2403 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" + // Pos:2462 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" { - ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1488, + ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1524, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -40498,9 +41474,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2404 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" + // Pos:2463 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" { - ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1489, + ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1525, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40515,9 +41491,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2405 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" + // Pos:2464 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" { - ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1489, + ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1525, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40532,9 +41508,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2406 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" + // Pos:2465 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" { - ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1490, + ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1526, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40549,9 +41525,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2407 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" + // Pos:2466 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" { - ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1491, + ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1527, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -40568,9 +41544,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2408 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" + // Pos:2467 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" { - ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1492, + ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1528, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -40587,9 +41563,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2409 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" + // Pos:2468 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" { - ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1493, + ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1529, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -40605,9 +41581,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2410 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" + // Pos:2469 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" { - ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1494, + ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1530, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -40623,9 +41599,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2411 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" + // Pos:2470 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" { - ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1495, + ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1531, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -40641,9 +41617,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2412 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" + // Pos:2471 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" { - ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1496, + ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1532, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -40660,9 +41636,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2413 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" + // Pos:2472 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" { - ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1497, + ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1533, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40678,9 +41654,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2414 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" + // Pos:2473 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" { - ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1497, + ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1533, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40695,9 +41671,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2415 Instruction:"VPSHUFBITQMB rK{K},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" + // Pos:2474 Instruction:"VPSHUFBITQMB rK{K},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" { - ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1498, + ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1534, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, @@ -40713,9 +41689,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2416 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" + // Pos:2475 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" { - ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1499, + ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1535, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40731,9 +41707,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2417 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" + // Pos:2476 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" { - ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1499, + ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1535, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40748,9 +41724,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2418 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" + // Pos:2477 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" { - ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1500, + ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1536, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40766,9 +41742,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2419 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" + // Pos:2478 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" { - ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1500, + ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1536, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40783,9 +41759,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2420 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" + // Pos:2479 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" { - ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1501, + ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1537, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40801,9 +41777,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2421 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" + // Pos:2480 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" { - ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1501, + ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1537, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40818,9 +41794,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2422 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" + // Pos:2481 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" { - ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1502, + ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1538, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40835,9 +41811,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2423 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" + // Pos:2482 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" { - ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1503, + ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1539, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40852,9 +41828,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2424 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" + // Pos:2483 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" { - ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1504, + ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1540, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40869,9 +41845,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2425 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" + // Pos:2484 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" { - ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1505, + ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1541, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40887,9 +41863,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2426 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" + // Pos:2485 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" { - ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1505, + ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1541, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40905,9 +41881,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2427 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" + // Pos:2486 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" { - ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1505, + ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1541, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40922,9 +41898,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2428 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" + // Pos:2487 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" { - ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1505, + ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1541, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40939,9 +41915,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2429 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" + // Pos:2488 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" { - ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1506, + ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1542, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40956,9 +41932,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2430 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" + // Pos:2489 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" { - ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1506, + ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1542, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40973,9 +41949,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2431 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" + // Pos:2490 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" { - ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1507, + ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1543, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40991,9 +41967,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2432 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" + // Pos:2491 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" { - ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1507, + ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1543, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41009,9 +41985,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2433 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" + // Pos:2492 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" { - ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1507, + ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1543, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41026,9 +42002,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2434 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" + // Pos:2493 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" { - ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1507, + ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1543, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41043,9 +42019,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2435 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" + // Pos:2494 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" { - ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1508, + ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1544, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41061,9 +42037,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2436 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" + // Pos:2495 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" { - ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1508, + ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1544, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -41078,9 +42054,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2437 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" + // Pos:2496 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" { - ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1509, + ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1545, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41096,9 +42072,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2438 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" + // Pos:2497 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" { - ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1509, + ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1545, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -41113,9 +42089,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2439 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" + // Pos:2498 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" { - ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1510, + ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1546, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41131,9 +42107,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2440 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" + // Pos:2499 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" { - ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1511, + ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1547, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41149,9 +42125,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2441 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" + // Pos:2500 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" { - ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1511, + ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1547, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41167,9 +42143,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2442 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" + // Pos:2501 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" { - ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1511, + ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1547, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41184,9 +42160,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2443 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" + // Pos:2502 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" { - ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1511, + ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1547, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41201,9 +42177,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2444 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" + // Pos:2503 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" { - ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1512, + ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1548, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41219,9 +42195,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2445 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" + // Pos:2504 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" { - ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1512, + ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1548, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41237,9 +42213,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2446 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" + // Pos:2505 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" { - ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1512, + ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1548, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41254,9 +42230,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2447 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" + // Pos:2506 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" { - ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1512, + ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1548, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41271,9 +42247,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2448 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" + // Pos:2507 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" { - ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1513, + ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1549, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41289,9 +42265,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2449 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" + // Pos:2508 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" { - ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1513, + ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1549, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41307,9 +42283,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2450 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" + // Pos:2509 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" { - ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1514, + ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1550, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41325,9 +42301,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2451 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" + // Pos:2510 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" { - ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1514, + ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1550, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -41342,9 +42318,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2452 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" + // Pos:2511 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" { - ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1515, + ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1551, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41360,9 +42336,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2453 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" + // Pos:2512 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" { - ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1516, + ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1552, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41378,9 +42354,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2454 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" + // Pos:2513 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" { - ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1517, + ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1553, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41396,9 +42372,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2455 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" + // Pos:2514 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" { - ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1517, + ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1553, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41414,9 +42390,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2456 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" + // Pos:2515 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" { - ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1517, + ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1553, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41431,9 +42407,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2457 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" + // Pos:2516 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" { - ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1517, + ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1553, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41448,9 +42424,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2458 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" + // Pos:2517 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" { - ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1518, + ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1554, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41466,9 +42442,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2459 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" + // Pos:2518 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" { - ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1518, + ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1554, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41484,9 +42460,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2460 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" + // Pos:2519 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" { - ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1518, + ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1554, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41501,9 +42477,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2461 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" + // Pos:2520 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" { - ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1518, + ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1554, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41518,9 +42494,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2462 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" + // Pos:2521 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" { - ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1519, + ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1555, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41535,9 +42511,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2463 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" + // Pos:2522 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" { - ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1519, + ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1555, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41552,9 +42528,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2464 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" + // Pos:2523 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" { - ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1520, + ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1556, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41570,9 +42546,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2465 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" + // Pos:2524 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" { - ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1520, + ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1556, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41588,9 +42564,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2466 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" + // Pos:2525 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" { - ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1520, + ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1556, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41605,9 +42581,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2467 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" + // Pos:2526 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" { - ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1520, + ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1556, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41622,9 +42598,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2468 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" + // Pos:2527 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" { - ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1521, + ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1557, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41640,9 +42616,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2469 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" + // Pos:2528 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" { - ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1521, + ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1557, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -41657,9 +42633,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2470 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" + // Pos:2529 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" { - ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1522, + ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1558, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41675,9 +42651,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2471 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" + // Pos:2530 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" { - ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1522, + ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1558, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -41692,9 +42668,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2472 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" + // Pos:2531 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" { - ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1523, + ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1559, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41710,9 +42686,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2473 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" + // Pos:2532 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" { - ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1524, + ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1560, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41728,9 +42704,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2474 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" + // Pos:2533 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" { - ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1524, + ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1560, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41746,9 +42722,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2475 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" + // Pos:2534 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" { - ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1524, + ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1560, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41763,9 +42739,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2476 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" + // Pos:2535 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" { - ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1524, + ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1560, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41780,9 +42756,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2477 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" + // Pos:2536 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" { - ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1525, + ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1561, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41798,9 +42774,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2478 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" + // Pos:2537 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" { - ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1525, + ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1561, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41815,9 +42791,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2479 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" + // Pos:2538 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" { - ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1526, + ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1562, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41833,9 +42809,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2480 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" + // Pos:2539 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" { - ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1526, + ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1562, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41850,9 +42826,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2481 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" + // Pos:2540 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" { - ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1527, + ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1563, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41868,9 +42844,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2482 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" + // Pos:2541 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" { - ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1527, + ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1563, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41885,9 +42861,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2483 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" + // Pos:2542 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" { - ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1528, + ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1564, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41903,9 +42879,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2484 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" + // Pos:2543 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" { - ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1528, + ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1564, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41920,9 +42896,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2485 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" + // Pos:2544 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" { - ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1529, + ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1565, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41938,9 +42914,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2486 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" + // Pos:2545 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" { - ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1529, + ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1565, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41955,9 +42931,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2487 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" + // Pos:2546 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" { - ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1530, + ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1566, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41973,9 +42949,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2488 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" + // Pos:2547 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" { - ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1530, + ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1566, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41990,9 +42966,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2489 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" + // Pos:2548 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" { - ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1531, + ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1567, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42008,9 +42984,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2490 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" + // Pos:2549 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" { - ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1531, + ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1567, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42025,9 +43001,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2491 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" + // Pos:2550 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" { - ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1532, + ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1568, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42043,9 +43019,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2492 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" + // Pos:2551 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" { - ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1532, + ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1568, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42060,9 +43036,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2493 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" + // Pos:2552 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" { - ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1533, + ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1569, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42079,9 +43055,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2494 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" + // Pos:2553 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" { - ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1534, + ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1570, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42098,9 +43074,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2495 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" + // Pos:2554 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" { - ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1535, + ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1571, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42115,9 +43091,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2496 Instruction:"VPTESTMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" + // Pos:2555 Instruction:"VPTESTMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" { - ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1536, + ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1572, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42133,9 +43109,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2497 Instruction:"VPTESTMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" + // Pos:2556 Instruction:"VPTESTMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" { - ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1537, + ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1573, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42151,9 +43127,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2498 Instruction:"VPTESTMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" + // Pos:2557 Instruction:"VPTESTMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" { - ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1538, + ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1574, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42169,9 +43145,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2499 Instruction:"VPTESTMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" + // Pos:2558 Instruction:"VPTESTMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" { - ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1539, + ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1575, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42187,9 +43163,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2500 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" + // Pos:2559 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" { - ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1540, + ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1576, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42205,9 +43181,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2501 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" + // Pos:2560 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" { - ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1541, + ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1577, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42223,9 +43199,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2502 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" + // Pos:2561 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" { - ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1542, + ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1578, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42241,9 +43217,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2503 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" + // Pos:2562 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" { - ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1543, + ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1579, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42259,9 +43235,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2504 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" + // Pos:2563 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" { - ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1544, + ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1580, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42277,9 +43253,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2505 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" + // Pos:2564 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" { - ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1544, + ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1580, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42294,9 +43270,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2506 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" + // Pos:2565 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" { - ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1545, + ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1581, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42312,9 +43288,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2507 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" + // Pos:2566 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" { - ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1545, + ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1581, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42329,9 +43305,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2508 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" + // Pos:2567 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" { - ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1546, + ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1582, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42347,9 +43323,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2509 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" + // Pos:2568 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" { - ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1546, + ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1582, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42364,9 +43340,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2510 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" + // Pos:2569 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" { - ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1547, + ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1583, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42382,9 +43358,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2511 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" + // Pos:2570 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" { - ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1547, + ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1583, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42399,9 +43375,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2512 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" + // Pos:2571 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" { - ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1548, + ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1584, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42417,9 +43393,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2513 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" + // Pos:2572 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" { - ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1548, + ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1584, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42434,9 +43410,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2514 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" + // Pos:2573 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" { - ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1549, + ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1585, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42452,9 +43428,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2515 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" + // Pos:2574 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" { - ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1549, + ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1585, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42469,9 +43445,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2516 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" + // Pos:2575 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" { - ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1550, + ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1586, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42487,9 +43463,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2517 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" + // Pos:2576 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" { - ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1550, + ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1586, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42504,9 +43480,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2518 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" + // Pos:2577 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" { - ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1551, + ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1587, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42522,9 +43498,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2519 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" + // Pos:2578 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" { - ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1551, + ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1587, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42539,9 +43515,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2520 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" + // Pos:2579 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" { - ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1552, + ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1588, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42556,9 +43532,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2521 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" + // Pos:2580 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" { - ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1553, + ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1589, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42574,9 +43550,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2522 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" + // Pos:2581 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" { - ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1554, + ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1590, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42592,9 +43568,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2523 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" + // Pos:2582 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" { - ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1555, + ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1591, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -42611,9 +43587,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2524 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" + // Pos:2583 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" { - ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1556, + ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1592, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -42630,9 +43606,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2525 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" + // Pos:2584 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" { - ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1557, + ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1593, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -42649,9 +43625,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2526 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" + // Pos:2585 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" { - ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1558, + ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1594, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -42668,9 +43644,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2527 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" + // Pos:2586 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" { - ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1559, + ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1595, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42685,9 +43661,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2528 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" + // Pos:2587 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" { - ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1560, + ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1596, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42702,9 +43678,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2529 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" + // Pos:2588 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" { - ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1561, + ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1597, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42720,9 +43696,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2530 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" + // Pos:2589 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" { - ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1562, + ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1598, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42738,9 +43714,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2531 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" + // Pos:2590 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" { - ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1563, + ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1599, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -42755,9 +43731,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2532 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" + // Pos:2591 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" { - ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1564, + ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1600, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -42772,9 +43748,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2533 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" + // Pos:2592 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" { - ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1565, + ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1601, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -42790,9 +43766,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2534 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" + // Pos:2593 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" { - ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1566, + ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1602, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -42808,9 +43784,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2535 Instruction:"VRCPPH Vn{K}{z},aKq,Wn|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM" + // Pos:2594 Instruction:"VRCPPH Vn{K}{z},aKq,Wn|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM" { - ND_INS_VRCPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1567, + ND_INS_VRCPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1603, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -42825,9 +43801,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2536 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" + // Pos:2595 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" { - ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1568, + ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1604, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42841,9 +43817,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2537 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM" + // Pos:2596 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM" { - ND_INS_VRCPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1569, + ND_INS_VRCPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1605, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -42859,9 +43835,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2538 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" + // Pos:2597 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" { - ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1570, + ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1606, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42876,9 +43852,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2539 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" + // Pos:2598 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" { - ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1571, + ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1607, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -42894,9 +43870,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2540 Instruction:"VREDUCEPH Vn{K}{z},aKq,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI" + // Pos:2599 Instruction:"VREDUCEPH Vn{K}{z},aKq,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI" { - ND_INS_VREDUCEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1572, + ND_INS_VREDUCEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1608, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -42912,9 +43888,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2541 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" + // Pos:2600 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" { - ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1573, + ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1609, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -42930,9 +43906,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2542 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" + // Pos:2601 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" { - ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1574, + ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1610, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -42949,9 +43925,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2543 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI" + // Pos:2602 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI" { - ND_INS_VREDUCESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1575, + ND_INS_VREDUCESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1611, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -42968,9 +43944,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2544 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" + // Pos:2603 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" { - ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1576, + ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1612, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -42987,9 +43963,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2545 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" + // Pos:2604 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" { - ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1577, + ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1613, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43005,9 +43981,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2546 Instruction:"VRNDSCALEPH Vn{K}{z},aKq,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI" + // Pos:2605 Instruction:"VRNDSCALEPH Vn{K}{z},aKq,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI" { - ND_INS_VRNDSCALEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1578, + ND_INS_VRNDSCALEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1614, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43023,9 +43999,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2547 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" + // Pos:2606 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" { - ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1579, + ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1615, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43041,9 +44017,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2548 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" + // Pos:2607 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" { - ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1580, + ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1616, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43060,9 +44036,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2549 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI" + // Pos:2608 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI" { - ND_INS_VRNDSCALESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1581, + ND_INS_VRNDSCALESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1617, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43079,9 +44055,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2550 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" + // Pos:2609 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" { - ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1582, + ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1618, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43098,9 +44074,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2551 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" + // Pos:2610 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" { - ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1583, + ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1619, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43115,9 +44091,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2552 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" + // Pos:2611 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" { - ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1584, + ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1620, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43132,9 +44108,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2553 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" + // Pos:2612 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" { - ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1585, + ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1621, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43150,9 +44126,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2554 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" + // Pos:2613 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" { - ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1586, + ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1622, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43168,9 +44144,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2555 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" + // Pos:2614 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" { - ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1587, + ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1623, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43185,9 +44161,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2556 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" + // Pos:2615 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" { - ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1588, + ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1624, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43202,9 +44178,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2557 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" + // Pos:2616 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" { - ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1589, + ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1625, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43220,9 +44196,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2558 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" + // Pos:2617 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" { - ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1590, + ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1626, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43238,9 +44214,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2559 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" + // Pos:2618 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" { - ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1591, + ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1627, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -43255,9 +44231,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2560 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" + // Pos:2619 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" { - ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1592, + ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1628, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -43272,9 +44248,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2561 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" + // Pos:2620 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" { - ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1593, + ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1629, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -43290,9 +44266,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2562 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" + // Pos:2621 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" { - ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1594, + ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1630, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -43308,9 +44284,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2563 Instruction:"VRSQRTPH Vn{K}{z},aKq,Wn|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM" + // Pos:2622 Instruction:"VRSQRTPH Vn{K}{z},aKq,Wn|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM" { - ND_INS_VRSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1595, + ND_INS_VRSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1631, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43325,9 +44301,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2564 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" + // Pos:2623 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" { - ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1596, + ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1632, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43341,9 +44317,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2565 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM" + // Pos:2624 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM" { - ND_INS_VRSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1597, + ND_INS_VRSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1633, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43359,9 +44335,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2566 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" + // Pos:2625 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" { - ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1598, + ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1634, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43376,9 +44352,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2567 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" + // Pos:2626 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" { - ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1599, + ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1635, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43394,9 +44370,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2568 Instruction:"VSCALEFPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM" + // Pos:2627 Instruction:"VSCALEFPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM" { - ND_INS_VSCALEFPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1600, + ND_INS_VSCALEFPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1636, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43412,9 +44388,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2569 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" + // Pos:2628 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" { - ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1601, + ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1637, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43430,9 +44406,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2570 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" + // Pos:2629 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" { - ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1602, + ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1638, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43448,9 +44424,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2571 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM" + // Pos:2630 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM" { - ND_INS_VSCALEFSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1603, + ND_INS_VSCALEFSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1639, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43466,9 +44442,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2572 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" + // Pos:2631 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" { - ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1604, + ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1640, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43484,9 +44460,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2573 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" + // Pos:2632 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" { - ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1605, + ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1641, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43501,9 +44477,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2574 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" + // Pos:2633 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" { - ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1606, + ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1642, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43518,9 +44494,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2575 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" + // Pos:2634 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" { - ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1607, + ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1643, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -43534,9 +44510,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2576 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" + // Pos:2635 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" { - ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1608, + ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1644, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -43550,9 +44526,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2577 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" + // Pos:2636 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" { - ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1609, + ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1645, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -43566,9 +44542,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2578 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" + // Pos:2637 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" { - ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1610, + ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1646, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -43582,9 +44558,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2579 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" + // Pos:2638 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" { - ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1611, + ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1647, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -43598,9 +44574,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2580 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" + // Pos:2639 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" { - ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1612, + ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1648, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -43614,9 +44590,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2581 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" + // Pos:2640 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" { - ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1613, + ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1649, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -43630,9 +44606,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2582 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" + // Pos:2641 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" { - ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1614, + ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1650, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -43646,9 +44622,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2583 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" + // Pos:2642 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" { - ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1615, + ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1651, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43663,9 +44639,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2584 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" + // Pos:2643 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" { - ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1616, + ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1652, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43680,9 +44656,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2585 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" + // Pos:2644 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" { - ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1617, + ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1653, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43699,9 +44675,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2586 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" + // Pos:2645 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" { - ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1618, + ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1654, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43718,9 +44694,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2587 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" + // Pos:2646 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" { - ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1619, + ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1655, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43737,9 +44713,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2588 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" + // Pos:2647 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" { - ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1620, + ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1656, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43756,9 +44732,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2589 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" + // Pos:2648 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" { - ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1621, + ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1657, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43775,9 +44751,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2590 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" + // Pos:2649 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" { - ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1621, + ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1657, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43793,9 +44769,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2591 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" + // Pos:2650 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" { - ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1622, + ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1658, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43812,9 +44788,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2592 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" + // Pos:2651 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" { - ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1622, + ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1658, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43830,9 +44806,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2593 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" + // Pos:2652 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" { - ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1623, + ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1659, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43847,9 +44823,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2594 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" + // Pos:2653 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" { - ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1623, + ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1659, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43863,9 +44839,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2595 Instruction:"VSQRTPH Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM" + // Pos:2654 Instruction:"VSQRTPH Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM" { - ND_INS_VSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1624, + ND_INS_VSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1660, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43880,9 +44856,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2596 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" + // Pos:2655 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" { - ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1625, + ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1661, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43897,9 +44873,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2597 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" + // Pos:2656 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" { - ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1625, + ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1661, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43913,9 +44889,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2598 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" + // Pos:2657 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" { - ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1626, + ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1662, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43931,9 +44907,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2599 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" + // Pos:2658 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" { - ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1626, + ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1662, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43948,9 +44924,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2600 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM" + // Pos:2659 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM" { - ND_INS_VSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1627, + ND_INS_VSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1663, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43966,9 +44942,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2601 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" + // Pos:2660 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" { - ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1628, + ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1664, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43984,9 +44960,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2602 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" + // Pos:2661 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" { - ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1628, + ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1664, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44001,9 +44977,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2603 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" + // Pos:2662 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" { - ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1629, + ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1665, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, @@ -44017,9 +44993,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2604 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" + // Pos:2663 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" { - ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1630, + ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1666, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44035,9 +45011,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2605 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" + // Pos:2664 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" { - ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1630, + ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1666, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44052,9 +45028,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2606 Instruction:"VSUBPH Vn{K}{z},aKq,Hn,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM" + // Pos:2665 Instruction:"VSUBPH Vn{K}{z},aKq,Hn,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM" { - ND_INS_VSUBPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1631, + ND_INS_VSUBPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1667, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -44070,9 +45046,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2607 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" + // Pos:2666 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" { - ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1632, + ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1668, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44088,9 +45064,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2608 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" + // Pos:2667 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" { - ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1632, + ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1668, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44105,9 +45081,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2609 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" + // Pos:2668 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" { - ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1633, + ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1669, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44123,9 +45099,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2610 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" + // Pos:2669 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" { - ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1633, + ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1669, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44140,9 +45116,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2611 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM" + // Pos:2670 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM" { - ND_INS_VSUBSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1634, + ND_INS_VSUBSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1670, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -44158,9 +45134,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2612 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" + // Pos:2671 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" { - ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1635, + ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1671, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44176,9 +45152,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2613 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" + // Pos:2672 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" { - ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1635, + ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1671, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44193,9 +45169,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2614 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" + // Pos:2673 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" { - ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1636, + ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1672, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44210,9 +45186,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2615 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" + // Pos:2674 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" { - ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1637, + ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1673, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44227,9 +45203,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2616 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" + // Pos:2675 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" { - ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1638, + ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1674, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44244,9 +45220,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2617 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" + // Pos:2676 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" { - ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1638, + ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1674, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44261,9 +45237,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2618 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM" + // Pos:2677 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM" { - ND_INS_VUCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1639, + ND_INS_VUCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1675, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -44278,9 +45254,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2619 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" + // Pos:2678 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" { - ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1640, + ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1676, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44295,9 +45271,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2620 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" + // Pos:2679 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" { - ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1640, + ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1676, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44312,9 +45288,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2621 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" + // Pos:2680 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" { - ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1641, + ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1677, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44330,9 +45306,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2622 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" + // Pos:2681 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" { - ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1641, + ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1677, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44347,9 +45323,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2623 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" + // Pos:2682 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" { - ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1642, + ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1678, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44365,9 +45341,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2624 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" + // Pos:2683 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" { - ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1642, + ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1678, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44382,9 +45358,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2625 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" + // Pos:2684 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" { - ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1643, + ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44400,9 +45376,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2626 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" + // Pos:2685 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" { - ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1643, + ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44417,9 +45393,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2627 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" + // Pos:2686 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" { - ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1644, + ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1680, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44435,9 +45411,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2628 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" + // Pos:2687 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" { - ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1644, + ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1680, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44452,9 +45428,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2629 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" + // Pos:2688 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" { - ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1645, + ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1681, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -44470,9 +45446,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2630 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" + // Pos:2689 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" { - ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1645, + ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1681, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44487,9 +45463,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2631 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" + // Pos:2690 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" { - ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1646, + ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1682, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -44505,9 +45481,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2632 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" + // Pos:2691 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" { - ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1646, + ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1682, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44522,9 +45498,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2633 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" + // Pos:2692 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" { - ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1647, + ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1683, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, @@ -44537,9 +45513,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2634 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" + // Pos:2693 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" { - ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1648, + ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1684, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, @@ -44552,9 +45528,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2635 Instruction:"WAIT" Encoding:"0x9B"/"" + // Pos:2694 Instruction:"WAIT" Encoding:"0x9B"/"" { - ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1649, + ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1685, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, 0, 0, @@ -44567,9 +45543,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2636 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" + // Pos:2695 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" { - ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1650, + ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1686, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -44582,9 +45558,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2637 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/"" + // Pos:2696 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/"" { - ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1651, + ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1687, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_WBNOINVD, @@ -44597,9 +45573,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2638 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M" + // Pos:2697 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M" { - ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1652, + ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1688, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, @@ -44613,9 +45589,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2639 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M" + // Pos:2698 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M" { - ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1653, + ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1689, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, @@ -44629,9 +45605,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2640 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" + // Pos:2699 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" { - ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1654, + ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1690, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, ND_CFF_MSR, @@ -44647,9 +45623,44 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2641 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" + // Pos:2700 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/"" + { + ND_INS_WRMSRLIST, ND_CAT_SYSTEM, ND_SET_MSRLIST, 1691, + 0, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_MSRLIST, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_MEM_SMSRT, ND_OPS_4096, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_MEM_DMSRT, ND_OPS_4096, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2701 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/"" + { + ND_INS_WRMSRNS, ND_CAT_SYSTEM, ND_SET_WRMSRNS, 1692, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WRMSRNS, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2702 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" { - ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1655, + ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1693, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, @@ -44665,9 +45676,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2642 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M" + // Pos:2703 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M" { - ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1656, + ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1694, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -44680,9 +45691,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2643 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" + // Pos:2704 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" { - ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1657, + ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1695, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -44696,9 +45707,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2644 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" + // Pos:2705 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" { - ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1658, + ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1696, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -44712,9 +45723,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2645 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + // Pos:2706 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" { - ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1659, + ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1697, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -44728,9 +45739,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2646 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + // Pos:2707 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" { - ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1660, + ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1698, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -44744,9 +45755,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2647 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" + // Pos:2708 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" { - ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1661, + ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1699, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, @@ -44761,9 +45772,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2648 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" + // Pos:2709 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" { - ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1662, + ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1700, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -44778,9 +45789,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2649 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" + // Pos:2710 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" { - ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1662, + ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1700, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -44795,9 +45806,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2650 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" + // Pos:2711 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" { - ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1663, + ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1701, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, @@ -44812,9 +45823,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2651 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" + // Pos:2712 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1664, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -44828,9 +45839,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2652 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" + // Pos:2713 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1664, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -44844,9 +45855,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2653 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O" + // Pos:2714 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1664, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -44860,9 +45871,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2654 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O" + // Pos:2715 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1664, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -44876,9 +45887,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2655 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O" + // Pos:2716 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1664, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -44892,9 +45903,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2656 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O" + // Pos:2717 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1664, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -44908,9 +45919,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2657 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O" + // Pos:2718 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1664, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -44924,9 +45935,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2658 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O" + // Pos:2719 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1664, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -44940,9 +45951,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2659 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O" + // Pos:2720 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1664, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -44956,9 +45967,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2660 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O" + // Pos:2721 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1664, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -44972,9 +45983,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2661 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/"" + // Pos:2722 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/"" { - ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1665, + ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1703, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -44987,9 +45998,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2662 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/"" + // Pos:2723 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/"" { - ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1666, + ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1704, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45002,9 +46013,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2663 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/"" + // Pos:2724 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/"" { - ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1667, + ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1705, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45017,9 +46028,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2664 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/"" + // Pos:2725 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/"" { - ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1668, + ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1706, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45032,9 +46043,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2665 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/"" + // Pos:2726 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/"" { - ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1669, + ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1707, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45047,9 +46058,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2666 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" + // Pos:2727 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" { - ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1670, + ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1708, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, @@ -45062,9 +46073,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2667 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" + // Pos:2728 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" { - ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1671, + ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1709, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -45080,9 +46091,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2668 Instruction:"XLATB" Encoding:"0xD7"/"" + // Pos:2729 Instruction:"XLATB" Encoding:"0xD7"/"" { - ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1672, + ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -45096,9 +46107,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2669 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" + // Pos:2730 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1673, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45113,9 +46124,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2670 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" + // Pos:2731 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1673, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45130,9 +46141,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2671 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" + // Pos:2732 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1673, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45147,9 +46158,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2672 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" + // Pos:2733 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1673, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45164,9 +46175,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2673 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" + // Pos:2734 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1673, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -45181,9 +46192,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2674 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" + // Pos:2735 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1673, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -45198,9 +46209,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2675 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" + // Pos:2736 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1673, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45215,9 +46226,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2676 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" + // Pos:2737 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1673, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45232,9 +46243,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2677 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" + // Pos:2738 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1673, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -45249,9 +46260,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2678 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" + // Pos:2739 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1673, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45266,9 +46277,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2679 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" + // Pos:2740 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" { - ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1674, + ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -45282,9 +46293,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2680 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" + // Pos:2741 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" { - ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1675, + ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1713, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -45298,9 +46309,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2681 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" + // Pos:2742 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" { - ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1676, + ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1714, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, @@ -45313,9 +46324,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2682 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" + // Pos:2743 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" { - ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1677, + ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1715, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -45332,9 +46343,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2683 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" + // Pos:2744 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" { - ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1678, + ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1716, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -45351,9 +46362,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2684 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" + // Pos:2745 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" { - ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1679, + ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1717, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, @@ -45370,9 +46381,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2685 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" + // Pos:2746 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" { - ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1680, + ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1718, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, @@ -45389,9 +46400,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2686 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" + // Pos:2747 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" { - ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1681, + ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1719, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -45408,9 +46419,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2687 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" + // Pos:2748 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" { - ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1682, + ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1720, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -45427,9 +46438,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2688 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" + // Pos:2749 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" { - ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1683, + ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1721, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, @@ -45446,9 +46457,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2689 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" + // Pos:2750 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" { - ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1684, + ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1722, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, @@ -45465,9 +46476,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2690 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" + // Pos:2751 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" { - ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1685, + ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1723, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -45484,9 +46495,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2691 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" + // Pos:2752 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" { - ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1686, + ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1724, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -45503,9 +46514,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2692 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" + // Pos:2753 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" { - ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1687, + ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1725, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, @@ -45522,9 +46533,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2693 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" + // Pos:2754 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" { - ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1688, + ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, @@ -45541,9 +46552,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2694 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" + // Pos:2755 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" { - ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1689, + ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1727, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -45559,9 +46570,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2695 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/"" + // Pos:2756 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/"" { - ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1690, + ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1728, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45574,9 +46585,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2696 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/"" + // Pos:2757 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/"" { - ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1691, + ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1729, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45589,9 +46600,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2697 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/"" + // Pos:2758 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/"" { - ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1692, + ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1730, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45604,9 +46615,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2698 Instruction:"XSTORE" Encoding:"0xF3 0x0F 0xA7 /0xC0"/"" + // Pos:2759 Instruction:"XSTORE" Encoding:"0xF3 0x0F 0xA7 /0xC0"/"" { - ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1692, + ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1730, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45619,9 +46630,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2699 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" + // Pos:2760 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" { - ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1693, + ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1731, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, @@ -45634,9 +46645,9 @@ const ND_INSTRUCTION gInstructions[2701] = }, }, - // Pos:2700 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" + // Pos:2761 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" { - ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1694, + ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1732, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, diff --git a/bddisasm/include/mnemonics.h b/bddisasm/include/mnemonics.h index 59d0d79..df99b65 100644 --- a/bddisasm/include/mnemonics.h +++ b/bddisasm/include/mnemonics.h @@ -2,36 +2,44 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ + +// +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! +// + #ifndef MNEMONICS_H #define MNEMONICS_H -const char *gMnemonics[1695] = +const char *gMnemonics[1733] = { - "AAA", "AAD", "AAM", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS", - "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", "AESDEC", "AESDEC128KL", - "AESDEC256KL", "AESDECLAST", "AESDECWIDE128KL", "AESDECWIDE256KL", - "AESENC", "AESENC128KL", "AESENC256KL", "AESENCLAST", "AESENCWIDE128KL", - "AESENCWIDE256KL", "AESIMC", "AESKEYGENASSIST", "ALTINST", "AND", - "ANDN", "ANDNPD", "ANDNPS", "ANDPD", "ANDPS", "ARPL", "BEXTR", - "BLCFILL", "BLCI", "BLCIC", "BLCMSK", "BLCS", "BLENDPD", "BLENDPS", - "BLENDVPD", "BLENDVPS", "BLSFILL", "BLSI", "BLSIC", "BLSMSK", - "BLSR", "BNDCL", "BNDCN", "BNDCU", "BNDLDX", "BNDMK", "BNDMOV", - "BNDSTX", "BOUND", "BSF", "BSR", "BSWAP", "BT", "BTC", "BTR", - "BTS", "BZHI", "CALL", "CALLF", "CBW", "CDQ", "CDQE", "CLAC", - "CLC", "CLD", "CLDEMOTE", "CLEVICT0", "CLEVICT1", "CLFLUSH", - "CLFLUSHOPT", "CLGI", "CLI", "CLRSSBSY", "CLTS", "CLUI", "CLWB", - "CLZERO", "CMC", "CMOVBE", "CMOVC", "CMOVL", "CMOVLE", "CMOVNBE", - "CMOVNC", "CMOVNL", "CMOVNLE", "CMOVNO", "CMOVNP", "CMOVNS", - "CMOVNZ", "CMOVO", "CMOVP", "CMOVS", "CMOVZ", "CMP", "CMPPD", - "CMPPS", "CMPSB", "CMPSD", "CMPSQ", "CMPSS", "CMPSW", "CMPXCHG", - "CMPXCHG16B", "CMPXCHG8B", "COMISD", "COMISS", "CPUID", "CPU_READ", - "CPU_WRITE", "CQO", "CRC32", "CVTDQ2PD", "CVTDQ2PS", "CVTPD2DQ", - "CVTPD2PI", "CVTPD2PS", "CVTPI2PD", "CVTPI2PS", "CVTPS2DQ", "CVTPS2PD", - "CVTPS2PI", "CVTSD2SI", "CVTSD2SS", "CVTSI2SD", "CVTSI2SS", "CVTSS2SD", - "CVTSS2SI", "CVTTPD2DQ", "CVTTPD2PI", "CVTTPS2DQ", "CVTTPS2PI", - "CVTTSD2SI", "CVTTSS2SI", "CWD", "CWDE", "DAA", "DAS", "DEC", - "DELAY", "DIV", "DIVPD", "DIVPS", "DIVSD", "DIVSS", "DMINT", - "DPPD", "DPPS", "EMMS", "ENCLS", "ENCLU", "ENCLV", "ENCODEKEY128", + "AAA", "AAD", "AADD", "AAM", "AAND", "AAS", "ADC", "ADCX", "ADD", + "ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", + "AESDEC", "AESDEC128KL", "AESDEC256KL", "AESDECLAST", "AESDECWIDE128KL", + "AESDECWIDE256KL", "AESENC", "AESENC128KL", "AESENC256KL", "AESENCLAST", + "AESENCWIDE128KL", "AESENCWIDE256KL", "AESIMC", "AESKEYGENASSIST", + "ALTINST", "AND", "ANDN", "ANDNPD", "ANDNPS", "ANDPD", "ANDPS", + "AOR", "ARPL", "AXOR", "BEXTR", "BLCFILL", "BLCI", "BLCIC", "BLCMSK", + "BLCS", "BLENDPD", "BLENDPS", "BLENDVPD", "BLENDVPS", "BLSFILL", + "BLSI", "BLSIC", "BLSMSK", "BLSR", "BNDCL", "BNDCN", "BNDCU", + "BNDLDX", "BNDMK", "BNDMOV", "BNDSTX", "BOUND", "BSF", "BSR", + "BSWAP", "BT", "BTC", "BTR", "BTS", "BZHI", "CALL", "CALLF", + "CBW", "CDQ", "CDQE", "CLAC", "CLC", "CLD", "CLDEMOTE", "CLEVICT0", + "CLEVICT1", "CLFLUSH", "CLFLUSHOPT", "CLGI", "CLI", "CLRSSBSY", + "CLTS", "CLUI", "CLWB", "CLZERO", "CMC", "CMOVBE", "CMOVC", "CMOVL", + "CMOVLE", "CMOVNBE", "CMOVNC", "CMOVNL", "CMOVNLE", "CMOVNO", + "CMOVNP", "CMOVNS", "CMOVNZ", "CMOVO", "CMOVP", "CMOVS", "CMOVZ", + "CMP", "CMPBEXADD", "CMPCXADD", "CMPLEXADD", "CMPLXADD", "CMPNBEXADD", + "CMPNCXADD", "CMPNLEXADD", "CMPNLXADD", "CMPNOXADD", "CMPNPXADD", + "CMPNSXADD", "CMPNZXADD", "CMPOXADD", "CMPPD", "CMPPS", "CMPPXADD", + "CMPSB", "CMPSD", "CMPSQ", "CMPSS", "CMPSW", "CMPSXADD", "CMPXCHG", + "CMPXCHG16B", "CMPXCHG8B", "CMPZXADD", "COMISD", "COMISS", "CPUID", + "CPU_READ", "CPU_WRITE", "CQO", "CRC32", "CVTDQ2PD", "CVTDQ2PS", + "CVTPD2DQ", "CVTPD2PI", "CVTPD2PS", "CVTPI2PD", "CVTPI2PS", "CVTPS2DQ", + "CVTPS2PD", "CVTPS2PI", "CVTSD2SI", "CVTSD2SS", "CVTSI2SD", "CVTSI2SS", + "CVTSS2SD", "CVTSS2SI", "CVTTPD2DQ", "CVTTPD2PI", "CVTTPS2DQ", + "CVTTPS2PI", "CVTTSD2SI", "CVTTSS2SI", "CWD", "CWDE", "DAA", + "DAS", "DEC", "DELAY", "DIV", "DIVPD", "DIVPS", "DIVSD", "DIVSS", + "DMINT", "DPPD", "DPPS", "EMMS", "ENCLS", "ENCLU", "ENCLV", "ENCODEKEY128", "ENCODEKEY256", "ENDBR32", "ENDBR64", "ENQCMD", "ENQCMDS", "ENTER", "ERETS", "ERETU", "EXTRACTPS", "EXTRQ", "F2XM1", "FABS", "FADD", "FADDP", "FBLD", "FBSTP", "FCHS", "FCMOVB", "FCMOVBE", "FCMOVE", @@ -98,50 +106,52 @@ const char *gMnemonics[1695] = "PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", "PMULHUW", "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", "POPAD", "POPCNT", "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", "PREFETCHE", - "PREFETCHM", "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", - "PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", - "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", - "PSLLQ", "PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", - "PSRLQ", "PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", - "PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE", - "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", - "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSHA", "PUSHAD", - "PUSHFD", "PUSHFQ", "PUSHFW", "PVALIDATE", "PXOR", "RCL", "RCPPS", - "RCPSS", "RCR", "RDFSBASE", "RDGSBASE", "RDMSR", "RDPID", "RDPKRU", - "RDPMC", "RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", - "RDTSC", "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPUPDATE", - "ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", - "RSDC", "RSLDT", "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", - "SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", - "SCASD", "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", - "SENDUIPI", "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", - "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", - "SETO", "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", - "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", - "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", - "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", - "SMINT", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", - "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", - "STOSQ", "STOSW", "STR", "STTILECFG", "STUI", "SUB", "SUBPD", - "SUBPS", "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", - "SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TDCALL", - "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TEST", - "TESTUI", "TILELOADD", "TILELOADDT1", "TILERELEASE", "TILESTORED", - "TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", "UCOMISD", - "UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR", "UMWAIT", - "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "V4FMADDPS", - "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", "VADDPH", - "VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD", "VADDSUBPS", - "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC", - "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", "VANDNPS", - "VANDPD", "VANDPS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", - "VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", - "VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", - "VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", - "VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", - "VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD", + "PREFETCHIT0", "PREFETCHIT1", "PREFETCHM", "PREFETCHNTA", "PREFETCHT0", + "PREFETCHT1", "PREFETCHT2", "PREFETCHW", "PREFETCHWT1", "PSADBW", + "PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFLW", "PSHUFW", "PSIGNB", + "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", "PSLLW", "PSMASH", + "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", "PSRLW", "PSUBB", + "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", "PSUBW", + "PSWAPD", "PTEST", "PTWRITE", "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", + "PUNPCKHWD", "PUNPCKLBW", "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", + "PUSH", "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW", "PVALIDATE", + "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", "RDGSBASE", + "RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", "RDPMC", "RDPRU", "RDRAND", + "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC", "RDTSCP", "RETF", + "RETN", "RMPADJUST", "RMPUPDATE", "ROL", "ROR", "RORX", "ROUNDPD", + "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSDC", "RSLDT", "RSM", "RSQRTPS", + "RSQRTSS", "RSTORSSP", "RSTS", "SAHF", "SAL", "SALC", "SAR", + "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD", "SCASQ", "SCASW", + "SEAMCALL", "SEAMOPS", "SEAMRET", "SENDUIPI", "SERIALIZE", "SETBE", + "SETC", "SETL", "SETLE", "SETNBE", "SETNC", "SETNL", "SETNLE", + "SETNO", "SETNP", "SETNS", "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY", + "SETZ", "SFENCE", "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", + "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2", "SHL", + "SHLD", "SHLX", "SHR", "SHRD", "SHRX", "SHUFPD", "SHUFPS", "SIDT", + "SKINIT", "SLDT", "SLWPCB", "SMINT", "SMSW", "SPFLT", "SQRTPD", + "SQRTPS", "SQRTSD", "SQRTSS", "STAC", "STC", "STD", "STGI", "STI", + "STMXCSR", "STOSB", "STOSD", "STOSQ", "STOSW", "STR", "STTILECFG", + "STUI", "SUB", "SUBPD", "SUBPS", "SUBSD", "SUBSS", "SVDC", "SVLDT", + "SVTS", "SWAPGS", "SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET", + "T1MSKC", "TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", + "TDPBUUD", "TDPFP16PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDT1", + "TILERELEASE", "TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", + "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", + "UIRET", "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", + "UNPCKLPS", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", + "VADDPD", "VADDPH", "VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD", + "VADDSUBPS", "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", + "VAESIMC", "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", + "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS", "VBCSTNESH2PS", + "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", + "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", + "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", + "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", + "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", "VCMPPD", + "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD", "VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", - "VCVTDQ2PH", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEPS2BF16", + "VCVTDQ2PH", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEEBF162PS", + "VCVTNEEPH2PS", "VCVTNEOBF162PS", "VCVTNEOPH2PS", "VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2PD", "VCVTPH2PS", "VCVTPH2PSX", "VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", "VCVTPH2W", @@ -226,9 +236,10 @@ const char *gMnemonics[1695] = "VPCMPUB", "VPCMPUD", "VPCMPUQ", "VPCMPUW", "VPCMPW", "VPCOMB", "VPCOMD", "VPCOMPRESSB", "VPCOMPRESSD", "VPCOMPRESSQ", "VPCOMPRESSW", "VPCOMQ", "VPCOMUB", "VPCOMUD", "VPCOMUQ", "VPCOMUW", "VPCOMW", - "VPCONFLICTD", "VPCONFLICTQ", "VPDPBUSD", "VPDPBUSDS", "VPDPWSSD", - "VPDPWSSDS", "VPERM2F128", "VPERM2I128", "VPERMB", "VPERMD", - "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q", + "VPCONFLICTD", "VPCONFLICTQ", "VPDPBSSD", "VPDPBSSDS", "VPDPBSUD", + "VPDPBSUDS", "VPDPBUSD", "VPDPBUSDS", "VPDPBUUD", "VPDPBUUDS", + "VPDPWSSD", "VPDPWSSDS", "VPERM2F128", "VPERM2I128", "VPERMB", + "VPERMD", "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q", "VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD", "VPERMILPS", "VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", "VPERMT2PD", "VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", "VPEXPANDD", @@ -290,14 +301,14 @@ const char *gMnemonics[1695] = "VSUBSH", "VSUBSS", "VTESTPD", "VTESTPS", "VUCOMISD", "VUCOMISH", "VUCOMISS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS", "VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT", "WBINVD", - "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRPKRU", "WRSHR", - "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT", "XADD", "XBEGIN", - "XCHG", "XCRYPTCBC", "XCRYPTCFB", "XCRYPTCTR", "XCRYPTECB", "XCRYPTOFB", - "XEND", "XGETBV", "XLATB", "XOR", "XORPD", "XORPS", "XRESLDTRK", - "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64", "XSAVE", "XSAVE64", - "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64", "XSAVES", "XSAVES64", - "XSETBV", "XSHA1", "XSHA256", "XSTORE", "XSUSLDTRK", "XTEST", - + "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRMSRLIST", "WRMSRNS", + "WRPKRU", "WRSHR", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT", + "XADD", "XBEGIN", "XCHG", "XCRYPTCBC", "XCRYPTCFB", "XCRYPTCTR", + "XCRYPTECB", "XCRYPTOFB", "XEND", "XGETBV", "XLATB", "XOR", "XORPD", + "XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64", + "XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64", + "XSAVES", "XSAVES64", "XSETBV", "XSHA1", "XSHA256", "XSTORE", + "XSUSLDTRK", "XTEST", }; diff --git a/bddisasm/include/table_evex.h b/bddisasm/include/table_evex.h index ca8b3ac..d3fd3b6 100644 --- a/bddisasm/include/table_evex.h +++ b/bddisasm/include/table_evex.h @@ -2,13 +2,18 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ + +// +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! +// + #ifndef TABLE_EVEX_H #define TABLE_EVEX_H const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_03_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1356] + (const void *)&gInstructions[1396] }; const ND_TABLE_VEX_W gEvexTable_root_02_9a_03_mem_02_w = @@ -43,13 +48,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9a_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1633] + (const void *)&gInstructions[1680] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1636] + (const void *)&gInstructions[1683] }; const ND_TABLE_VEX_W gEvexTable_root_02_9a_01_w = @@ -75,7 +80,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_03_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1357] + (const void *)&gInstructions[1397] }; const ND_TABLE_VEX_W gEvexTable_root_02_9b_03_mem_w = @@ -99,13 +104,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9b_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1638] + (const void *)&gInstructions[1685] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1641] + (const void *)&gInstructions[1688] }; const ND_TABLE_VEX_W gEvexTable_root_02_9b_01_w = @@ -131,7 +136,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_03_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1358] + (const void *)&gInstructions[1398] }; const ND_TABLE_VEX_W gEvexTable_root_02_aa_03_mem_02_w = @@ -166,13 +171,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_aa_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1643] + (const void *)&gInstructions[1690] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1646] + (const void *)&gInstructions[1693] }; const ND_TABLE_VEX_W gEvexTable_root_02_aa_01_w = @@ -198,7 +203,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_aa_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_03_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1359] + (const void *)&gInstructions[1399] }; const ND_TABLE_VEX_W gEvexTable_root_02_ab_03_mem_w = @@ -222,13 +227,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_ab_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1648] + (const void *)&gInstructions[1695] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1651] + (const void *)&gInstructions[1698] }; const ND_TABLE_VEX_W gEvexTable_root_02_ab_01_w = @@ -254,7 +259,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ab_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_de_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1372] + (const void *)&gInstructions[1412] }; const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp = @@ -271,7 +276,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_df_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1374] + (const void *)&gInstructions[1414] }; const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp = @@ -288,7 +293,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_dc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1376] + (const void *)&gInstructions[1416] }; const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp = @@ -305,7 +310,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_dd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1378] + (const void *)&gInstructions[1418] }; const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp = @@ -322,13 +327,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1392] + (const void *)&gInstructions[1434] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1393] + (const void *)&gInstructions[1435] }; const ND_TABLE_VEX_W gEvexTable_root_02_65_01_w = @@ -354,13 +359,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_65_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1399] + (const void *)&gInstructions[1441] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1410] + (const void *)&gInstructions[1452] }; const ND_TABLE_VEX_W gEvexTable_root_02_19_01_w = @@ -386,13 +391,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_19_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1400] + (const void *)&gInstructions[1442] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1402] + (const void *)&gInstructions[1444] }; const ND_TABLE_VEX_W gEvexTable_root_02_1a_01_mem_w = @@ -427,13 +432,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1401] + (const void *)&gInstructions[1443] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1403] + (const void *)&gInstructions[1445] }; const ND_TABLE_VEX_W gEvexTable_root_02_1b_01_mem_02_w = @@ -479,13 +484,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1405] + (const void *)&gInstructions[1447] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2059] + (const void *)&gInstructions[2106] }; const ND_TABLE_VEX_W gEvexTable_root_02_59_01_w = @@ -511,13 +516,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_59_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1406] + (const void *)&gInstructions[1448] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1408] + (const void *)&gInstructions[1450] }; const ND_TABLE_VEX_W gEvexTable_root_02_5a_01_mem_w = @@ -552,13 +557,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1407] + (const void *)&gInstructions[1449] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1409] + (const void *)&gInstructions[1451] }; const ND_TABLE_VEX_W gEvexTable_root_02_5b_01_mem_02_w = @@ -604,7 +609,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_18_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1412] + (const void *)&gInstructions[1454] }; const ND_TABLE_VEX_W gEvexTable_root_02_18_01_w = @@ -630,13 +635,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_18_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1429] + (const void *)&gInstructions[1471] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1430] + (const void *)&gInstructions[1472] }; const ND_TABLE_VEX_W gEvexTable_root_02_8a_01_w = @@ -662,7 +667,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1437] + (const void *)&gInstructions[1479] }; const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w = @@ -677,7 +682,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1438] + (const void *)&gInstructions[1484] }; const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w = @@ -692,7 +697,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2411] + (const void *)&gInstructions[2470] }; const ND_TABLE_VEX_W gEvexTable_root_02_72_01_w = @@ -718,7 +723,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_72_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1450] + (const void *)&gInstructions[1497] }; const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w = @@ -733,7 +738,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2309] + (const void *)&gInstructions[2368] }; const ND_TABLE_VEX_W gEvexTable_root_02_13_02_w = @@ -759,7 +764,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_13_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1543] + (const void *)&gInstructions[1590] }; const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w = @@ -774,7 +779,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_03_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1999] + (const void *)&gInstructions[2046] }; const ND_TABLE_VEX_W gEvexTable_root_02_52_03_mem_02_w = @@ -809,7 +814,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_52_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2115] + (const void *)&gInstructions[2168] }; const ND_TABLE_VEX_W gEvexTable_root_02_52_01_w = @@ -835,13 +840,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_52_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1548] + (const void *)&gInstructions[1595] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1549] + (const void *)&gInstructions[1596] }; const ND_TABLE_VEX_W gEvexTable_root_02_c8_01_02_w = @@ -878,13 +883,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1550] + (const void *)&gInstructions[1597] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1551] + (const void *)&gInstructions[1598] }; const ND_TABLE_VEX_W gEvexTable_root_02_88_01_w = @@ -910,13 +915,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_88_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1574] + (const void *)&gInstructions[1621] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1577] + (const void *)&gInstructions[1624] }; const ND_TABLE_VEX_W gEvexTable_root_02_98_01_w = @@ -942,13 +947,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_98_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1579] + (const void *)&gInstructions[1626] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1582] + (const void *)&gInstructions[1629] }; const ND_TABLE_VEX_W gEvexTable_root_02_99_01_w = @@ -974,13 +979,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_99_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1584] + (const void *)&gInstructions[1631] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1587] + (const void *)&gInstructions[1634] }; const ND_TABLE_VEX_W gEvexTable_root_02_a8_01_w = @@ -1006,13 +1011,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1589] + (const void *)&gInstructions[1636] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1592] + (const void *)&gInstructions[1639] }; const ND_TABLE_VEX_W gEvexTable_root_02_a9_01_w = @@ -1038,13 +1043,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1594] + (const void *)&gInstructions[1641] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1597] + (const void *)&gInstructions[1644] }; const ND_TABLE_VEX_W gEvexTable_root_02_b8_01_w = @@ -1070,13 +1075,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1599] + (const void *)&gInstructions[1646] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1602] + (const void *)&gInstructions[1649] }; const ND_TABLE_VEX_W gEvexTable_root_02_b9_01_w = @@ -1102,13 +1107,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1614] + (const void *)&gInstructions[1661] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1617] + (const void *)&gInstructions[1664] }; const ND_TABLE_VEX_W gEvexTable_root_02_96_01_w = @@ -1134,13 +1139,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_96_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1619] + (const void *)&gInstructions[1666] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1622] + (const void *)&gInstructions[1669] }; const ND_TABLE_VEX_W gEvexTable_root_02_a6_01_w = @@ -1166,13 +1171,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1624] + (const void *)&gInstructions[1671] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1627] + (const void *)&gInstructions[1674] }; const ND_TABLE_VEX_W gEvexTable_root_02_b6_01_w = @@ -1198,13 +1203,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1653] + (const void *)&gInstructions[1700] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1656] + (const void *)&gInstructions[1703] }; const ND_TABLE_VEX_W gEvexTable_root_02_ba_01_w = @@ -1230,13 +1235,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ba_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1658] + (const void *)&gInstructions[1705] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1661] + (const void *)&gInstructions[1708] }; const ND_TABLE_VEX_W gEvexTable_root_02_bb_01_w = @@ -1262,13 +1267,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1663] + (const void *)&gInstructions[1710] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1666] + (const void *)&gInstructions[1713] }; const ND_TABLE_VEX_W gEvexTable_root_02_97_01_w = @@ -1294,13 +1299,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_97_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1668] + (const void *)&gInstructions[1715] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1671] + (const void *)&gInstructions[1718] }; const ND_TABLE_VEX_W gEvexTable_root_02_a7_01_w = @@ -1326,13 +1331,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1673] + (const void *)&gInstructions[1720] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1676] + (const void *)&gInstructions[1723] }; const ND_TABLE_VEX_W gEvexTable_root_02_b7_01_w = @@ -1358,13 +1363,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1692] + (const void *)&gInstructions[1739] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1695] + (const void *)&gInstructions[1742] }; const ND_TABLE_VEX_W gEvexTable_root_02_9c_01_w = @@ -1390,13 +1395,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1697] + (const void *)&gInstructions[1744] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1700] + (const void *)&gInstructions[1747] }; const ND_TABLE_VEX_W gEvexTable_root_02_9d_01_w = @@ -1422,13 +1427,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1702] + (const void *)&gInstructions[1749] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1705] + (const void *)&gInstructions[1752] }; const ND_TABLE_VEX_W gEvexTable_root_02_ac_01_w = @@ -1454,13 +1459,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ac_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1707] + (const void *)&gInstructions[1754] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1710] + (const void *)&gInstructions[1757] }; const ND_TABLE_VEX_W gEvexTable_root_02_ad_01_w = @@ -1486,13 +1491,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ad_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1712] + (const void *)&gInstructions[1759] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1715] + (const void *)&gInstructions[1762] }; const ND_TABLE_VEX_W gEvexTable_root_02_bc_01_w = @@ -1518,13 +1523,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1717] + (const void *)&gInstructions[1764] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1720] + (const void *)&gInstructions[1767] }; const ND_TABLE_VEX_W gEvexTable_root_02_bd_01_w = @@ -1550,13 +1555,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1730] + (const void *)&gInstructions[1777] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1733] + (const void *)&gInstructions[1780] }; const ND_TABLE_VEX_W gEvexTable_root_02_9e_01_w = @@ -1582,13 +1587,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1735] + (const void *)&gInstructions[1782] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1738] + (const void *)&gInstructions[1785] }; const ND_TABLE_VEX_W gEvexTable_root_02_9f_01_w = @@ -1614,13 +1619,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1740] + (const void *)&gInstructions[1787] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1743] + (const void *)&gInstructions[1790] }; const ND_TABLE_VEX_W gEvexTable_root_02_ae_01_w = @@ -1646,13 +1651,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ae_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1745] + (const void *)&gInstructions[1792] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1748] + (const void *)&gInstructions[1795] }; const ND_TABLE_VEX_W gEvexTable_root_02_af_01_w = @@ -1678,13 +1683,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_af_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1750] + (const void *)&gInstructions[1797] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1753] + (const void *)&gInstructions[1800] }; const ND_TABLE_VEX_W gEvexTable_root_02_be_01_w = @@ -1710,13 +1715,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_be_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1755] + (const void *)&gInstructions[1802] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1758] + (const void *)&gInstructions[1805] }; const ND_TABLE_VEX_W gEvexTable_root_02_bf_01_w = @@ -1742,13 +1747,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bf_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1778] + (const void *)&gInstructions[1825] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1780] + (const void *)&gInstructions[1827] }; const ND_TABLE_VEX_W gEvexTable_root_02_92_01_mem_w = @@ -1783,13 +1788,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_92_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1782] + (const void *)&gInstructions[1829] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1783] + (const void *)&gInstructions[1830] }; const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_01_02_w = @@ -1815,13 +1820,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_01_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1786] + (const void *)&gInstructions[1833] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1787] + (const void *)&gInstructions[1834] }; const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_02_02_w = @@ -1847,13 +1852,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_02_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2575] + (const void *)&gInstructions[2634] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2576] + (const void *)&gInstructions[2635] }; const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_05_02_w = @@ -1879,13 +1884,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_05_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2579] + (const void *)&gInstructions[2638] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2580] + (const void *)&gInstructions[2639] }; const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_06_02_w = @@ -1946,13 +1951,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1784] + (const void *)&gInstructions[1831] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1785] + (const void *)&gInstructions[1832] }; const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_01_02_w = @@ -1978,13 +1983,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_01_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1788] + (const void *)&gInstructions[1835] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1789] + (const void *)&gInstructions[1836] }; const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_02_02_w = @@ -2010,13 +2015,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_02_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2577] + (const void *)&gInstructions[2636] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2578] + (const void *)&gInstructions[2637] }; const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_05_02_w = @@ -2042,13 +2047,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_05_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2581] + (const void *)&gInstructions[2640] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2582] + (const void *)&gInstructions[2641] }; const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_06_02_w = @@ -2109,13 +2114,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1790] + (const void *)&gInstructions[1837] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1792] + (const void *)&gInstructions[1839] }; const ND_TABLE_VEX_W gEvexTable_root_02_93_01_mem_w = @@ -2150,13 +2155,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_93_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1794] + (const void *)&gInstructions[1841] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1796] + (const void *)&gInstructions[1843] }; const ND_TABLE_VEX_W gEvexTable_root_02_42_01_w = @@ -2182,13 +2187,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_42_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1797] + (const void *)&gInstructions[1844] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1799] + (const void *)&gInstructions[1846] }; const ND_TABLE_VEX_W gEvexTable_root_02_43_01_w = @@ -2214,7 +2219,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_43_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_cf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1810] + (const void *)&gInstructions[1857] }; const ND_TABLE_VEX_W gEvexTable_root_02_cf_01_w = @@ -2240,7 +2245,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cf_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1923] + (const void *)&gInstructions[1970] }; const ND_TABLE_VEX_W gEvexTable_root_02_2a_01_mem_w = @@ -2264,7 +2269,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2057] + (const void *)&gInstructions[2104] }; const ND_TABLE_VEX_W gEvexTable_root_02_2a_02_reg_w = @@ -2299,13 +2304,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1997] + (const void *)&gInstructions[2044] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1998] + (const void *)&gInstructions[2045] }; const ND_TABLE_VEX_W gEvexTable_root_02_68_03_w = @@ -2331,7 +2336,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_68_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_03_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2000] + (const void *)&gInstructions[2047] }; const ND_TABLE_VEX_W gEvexTable_root_02_53_03_mem_02_w = @@ -2366,7 +2371,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_53_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2117] + (const void *)&gInstructions[2170] }; const ND_TABLE_VEX_W gEvexTable_root_02_53_01_w = @@ -2392,7 +2397,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_53_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2001] + (const void *)&gInstructions[2048] }; const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp = @@ -2409,7 +2414,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2003] + (const void *)&gInstructions[2050] }; const ND_TABLE_VEX_W gEvexTable_root_02_1e_01_w = @@ -2435,7 +2440,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2005] + (const void *)&gInstructions[2052] }; const ND_TABLE_VEX_W gEvexTable_root_02_1f_01_w = @@ -2461,7 +2466,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2006] + (const void *)&gInstructions[2053] }; const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp = @@ -2478,7 +2483,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2012] + (const void *)&gInstructions[2059] }; const ND_TABLE_VEX_W gEvexTable_root_02_2b_01_w = @@ -2504,13 +2509,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2045] + (const void *)&gInstructions[2092] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2048] + (const void *)&gInstructions[2095] }; const ND_TABLE_VEX_W gEvexTable_root_02_66_01_w = @@ -2536,13 +2541,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_66_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2046] + (const void *)&gInstructions[2093] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2047] + (const void *)&gInstructions[2094] }; const ND_TABLE_VEX_W gEvexTable_root_02_64_01_w = @@ -2568,7 +2573,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_64_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2051] + (const void *)&gInstructions[2098] }; const ND_TABLE_VEX_W gEvexTable_root_02_78_01_w = @@ -2594,7 +2599,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_78_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7a_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2052] + (const void *)&gInstructions[2099] }; const ND_TABLE_VEX_W gEvexTable_root_02_7a_01_reg_w = @@ -2629,7 +2634,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_58_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2054] + (const void *)&gInstructions[2101] }; const ND_TABLE_VEX_W gEvexTable_root_02_58_01_w = @@ -2655,13 +2660,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_58_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2055] + (const void *)&gInstructions[2102] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2060] + (const void *)&gInstructions[2107] }; const ND_TABLE_VEX_W gEvexTable_root_02_7c_01_reg_wi = @@ -2696,7 +2701,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2058] + (const void *)&gInstructions[2105] }; const ND_TABLE_VEX_W gEvexTable_root_02_3a_02_reg_w = @@ -2720,7 +2725,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_3a_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2269] + (const void *)&gInstructions[2328] }; const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp = @@ -2737,7 +2742,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2062] + (const void *)&gInstructions[2109] }; const ND_TABLE_VEX_W gEvexTable_root_02_79_01_w = @@ -2763,7 +2768,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_79_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7b_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2063] + (const void *)&gInstructions[2110] }; const ND_TABLE_VEX_W gEvexTable_root_02_7b_01_reg_w = @@ -2798,7 +2803,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2075] + (const void *)&gInstructions[2122] }; const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w = @@ -2813,13 +2818,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2271] + (const void *)&gInstructions[2330] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2314] + (const void *)&gInstructions[2373] }; const ND_TABLE_VEX_W gEvexTable_root_02_29_02_reg_w = @@ -2854,7 +2859,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_29_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_37_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2085] + (const void *)&gInstructions[2132] }; const ND_TABLE_VEX_W gEvexTable_root_02_37_01_w = @@ -2880,13 +2885,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_37_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2099] + (const void *)&gInstructions[2146] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2102] + (const void *)&gInstructions[2149] }; const ND_TABLE_VEX_W gEvexTable_root_02_63_01_w = @@ -2912,13 +2917,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_63_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2100] + (const void *)&gInstructions[2147] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2101] + (const void *)&gInstructions[2148] }; const ND_TABLE_VEX_W gEvexTable_root_02_8b_01_w = @@ -2944,13 +2949,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2109] + (const void *)&gInstructions[2156] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2110] + (const void *)&gInstructions[2157] }; const ND_TABLE_VEX_W gEvexTable_root_02_c4_01_w = @@ -2976,7 +2981,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_50_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2111] + (const void *)&gInstructions[2162] }; const ND_TABLE_VEX_W gEvexTable_root_02_50_01_w = @@ -3002,7 +3007,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_50_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_51_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2113] + (const void *)&gInstructions[2164] }; const ND_TABLE_VEX_W gEvexTable_root_02_51_01_w = @@ -3028,13 +3033,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_51_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2121] + (const void *)&gInstructions[2174] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2158] + (const void *)&gInstructions[2211] }; const ND_TABLE_VEX_W gEvexTable_root_02_8d_01_w = @@ -3060,13 +3065,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2122] + (const void *)&gInstructions[2175] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2149] + (const void *)&gInstructions[2202] }; const ND_TABLE_VEX_W gEvexTable_root_02_36_01_w = @@ -3092,13 +3097,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_36_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2124] + (const void *)&gInstructions[2177] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2129] + (const void *)&gInstructions[2182] }; const ND_TABLE_VEX_W gEvexTable_root_02_75_01_w = @@ -3124,13 +3129,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_75_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2125] + (const void *)&gInstructions[2178] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2128] + (const void *)&gInstructions[2181] }; const ND_TABLE_VEX_W gEvexTable_root_02_76_01_w = @@ -3156,13 +3161,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_76_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2126] + (const void *)&gInstructions[2179] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2127] + (const void *)&gInstructions[2180] }; const ND_TABLE_VEX_W gEvexTable_root_02_77_01_w = @@ -3188,7 +3193,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_77_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_0d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2134] + (const void *)&gInstructions[2187] }; const ND_TABLE_VEX_W gEvexTable_root_02_0d_01_w = @@ -3214,7 +3219,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_0c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2138] + (const void *)&gInstructions[2191] }; const ND_TABLE_VEX_W gEvexTable_root_02_0c_01_w = @@ -3240,13 +3245,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2142] + (const void *)&gInstructions[2195] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2146] + (const void *)&gInstructions[2199] }; const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w = @@ -3261,13 +3266,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2143] + (const void *)&gInstructions[2196] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2147] + (const void *)&gInstructions[2200] }; const ND_TABLE_VEX_W gEvexTable_root_02_16_01_02_w = @@ -3304,13 +3309,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_16_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2152] + (const void *)&gInstructions[2205] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2157] + (const void *)&gInstructions[2210] }; const ND_TABLE_VEX_W gEvexTable_root_02_7d_01_w = @@ -3336,13 +3341,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2153] + (const void *)&gInstructions[2206] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2156] + (const void *)&gInstructions[2209] }; const ND_TABLE_VEX_W gEvexTable_root_02_7e_01_w = @@ -3368,13 +3373,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2154] + (const void *)&gInstructions[2207] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2155] + (const void *)&gInstructions[2208] }; const ND_TABLE_VEX_W gEvexTable_root_02_7f_01_w = @@ -3400,13 +3405,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2159] + (const void *)&gInstructions[2212] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2162] + (const void *)&gInstructions[2215] }; const ND_TABLE_VEX_W gEvexTable_root_02_62_01_w = @@ -3432,13 +3437,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_62_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2160] + (const void *)&gInstructions[2213] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2161] + (const void *)&gInstructions[2214] }; const ND_TABLE_VEX_W gEvexTable_root_02_89_01_w = @@ -3464,13 +3469,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_89_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2177] + (const void *)&gInstructions[2234] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2179] + (const void *)&gInstructions[2236] }; const ND_TABLE_VEX_W gEvexTable_root_02_90_01_mem_w = @@ -3505,13 +3510,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_90_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2181] + (const void *)&gInstructions[2238] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2183] + (const void *)&gInstructions[2240] }; const ND_TABLE_VEX_W gEvexTable_root_02_91_01_mem_w = @@ -3546,13 +3551,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_91_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2219] + (const void *)&gInstructions[2276] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2220] + (const void *)&gInstructions[2277] }; const ND_TABLE_VEX_W gEvexTable_root_02_44_01_w = @@ -3578,7 +3583,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_44_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b5_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2233] + (const void *)&gInstructions[2290] }; const ND_TABLE_VEX_W gEvexTable_root_02_b5_01_w = @@ -3604,7 +3609,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2234] + (const void *)&gInstructions[2292] }; const ND_TABLE_VEX_W gEvexTable_root_02_b4_01_w = @@ -3630,7 +3635,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2235] + (const void *)&gInstructions[2294] }; const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp = @@ -3647,7 +3652,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2243] + (const void *)&gInstructions[2302] }; const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp = @@ -3664,13 +3669,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2245] + (const void *)&gInstructions[2304] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2247] + (const void *)&gInstructions[2306] }; const ND_TABLE_VEX_W gEvexTable_root_02_3d_01_w = @@ -3696,13 +3701,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2252] + (const void *)&gInstructions[2311] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2254] + (const void *)&gInstructions[2313] }; const ND_TABLE_VEX_W gEvexTable_root_02_3f_01_w = @@ -3728,7 +3733,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2255] + (const void *)&gInstructions[2314] }; const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp = @@ -3745,19 +3750,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2257] + (const void *)&gInstructions[2316] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2276] + (const void *)&gInstructions[2335] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2277] + (const void *)&gInstructions[2336] }; const ND_TABLE_VEX_W gEvexTable_root_02_38_02_reg_w = @@ -3792,13 +3797,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_38_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2259] + (const void *)&gInstructions[2318] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2261] + (const void *)&gInstructions[2320] }; const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w = @@ -3813,13 +3818,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2272] + (const void *)&gInstructions[2331] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2280] + (const void *)&gInstructions[2339] }; const ND_TABLE_VEX_W gEvexTable_root_02_39_02_reg_w = @@ -3854,13 +3859,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_39_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2266] + (const void *)&gInstructions[2325] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2268] + (const void *)&gInstructions[2327] }; const ND_TABLE_VEX_W gEvexTable_root_02_3b_01_w = @@ -3886,7 +3891,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2273] + (const void *)&gInstructions[2332] }; const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w = @@ -3901,7 +3906,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2316] + (const void *)&gInstructions[2375] }; const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp = @@ -3918,7 +3923,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2274] + (const void *)&gInstructions[2333] }; const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w = @@ -3933,7 +3938,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2328] + (const void *)&gInstructions[2387] }; const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp = @@ -3950,13 +3955,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2275] + (const void *)&gInstructions[2334] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2278] + (const void *)&gInstructions[2337] }; const ND_TABLE_VEX_W gEvexTable_root_02_28_02_reg_w = @@ -3980,7 +3985,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_28_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2334] + (const void *)&gInstructions[2393] }; const ND_TABLE_VEX_W gEvexTable_root_02_28_01_w = @@ -4006,7 +4011,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_28_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2281] + (const void *)&gInstructions[2340] }; const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w = @@ -4021,7 +4026,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2319] + (const void *)&gInstructions[2378] }; const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp = @@ -4038,7 +4043,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2282] + (const void *)&gInstructions[2341] }; const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w = @@ -4053,7 +4058,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2325] + (const void *)&gInstructions[2384] }; const ND_TABLE_VEX_W gEvexTable_root_02_35_01_w = @@ -4079,7 +4084,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_35_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2283] + (const void *)&gInstructions[2342] }; const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w = @@ -4094,7 +4099,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2331] + (const void *)&gInstructions[2390] }; const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp = @@ -4111,7 +4116,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2284] + (const void *)&gInstructions[2343] }; const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w = @@ -4126,7 +4131,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2290] + (const void *)&gInstructions[2349] }; const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp = @@ -4143,7 +4148,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2285] + (const void *)&gInstructions[2344] }; const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w = @@ -4158,7 +4163,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2302] + (const void *)&gInstructions[2361] }; const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp = @@ -4175,7 +4180,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2286] + (const void *)&gInstructions[2345] }; const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w = @@ -4190,7 +4195,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2293] + (const void *)&gInstructions[2352] }; const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp = @@ -4207,7 +4212,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2287] + (const void *)&gInstructions[2346] }; const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w = @@ -4222,7 +4227,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2299] + (const void *)&gInstructions[2358] }; const ND_TABLE_VEX_W gEvexTable_root_02_25_01_w = @@ -4248,7 +4253,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_25_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2288] + (const void *)&gInstructions[2347] }; const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w = @@ -4263,7 +4268,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2305] + (const void *)&gInstructions[2364] }; const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp = @@ -4280,7 +4285,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2289] + (const void *)&gInstructions[2348] }; const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w = @@ -4295,7 +4300,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2296] + (const void *)&gInstructions[2355] }; const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp = @@ -4312,7 +4317,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2308] + (const void *)&gInstructions[2367] }; const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w = @@ -4327,7 +4332,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2453] + (const void *)&gInstructions[2512] }; const ND_TABLE_VEX_W gEvexTable_root_02_11_01_w = @@ -4353,7 +4358,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_11_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2310] + (const void *)&gInstructions[2369] }; const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w = @@ -4368,7 +4373,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2439] + (const void *)&gInstructions[2498] }; const ND_TABLE_VEX_W gEvexTable_root_02_12_01_w = @@ -4394,7 +4399,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_12_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2311] + (const void *)&gInstructions[2370] }; const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w = @@ -4409,13 +4414,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2361] + (const void *)&gInstructions[2420] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2362] + (const void *)&gInstructions[2421] }; const ND_TABLE_VEX_W gEvexTable_root_02_15_01_w = @@ -4441,7 +4446,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_15_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2312] + (const void *)&gInstructions[2371] }; const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w = @@ -4456,13 +4461,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2365] + (const void *)&gInstructions[2424] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2366] + (const void *)&gInstructions[2425] }; const ND_TABLE_VEX_W gEvexTable_root_02_14_01_w = @@ -4488,7 +4493,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_14_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2313] + (const void *)&gInstructions[2372] }; const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w = @@ -4503,7 +4508,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2472] + (const void *)&gInstructions[2531] }; const ND_TABLE_VEX_W gEvexTable_root_02_10_01_w = @@ -4529,7 +4534,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_10_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2315] + (const void *)&gInstructions[2374] }; const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w = @@ -4544,7 +4549,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2322] + (const void *)&gInstructions[2381] }; const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp = @@ -4561,7 +4566,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_0b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2336] + (const void *)&gInstructions[2395] }; const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp = @@ -4578,13 +4583,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2342] + (const void *)&gInstructions[2401] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2344] + (const void *)&gInstructions[2403] }; const ND_TABLE_VEX_W gEvexTable_root_02_40_01_w = @@ -4610,7 +4615,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_40_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_83_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2347] + (const void *)&gInstructions[2406] }; const ND_TABLE_VEX_W gEvexTable_root_02_83_01_w = @@ -4636,13 +4641,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_83_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2350] + (const void *)&gInstructions[2409] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2353] + (const void *)&gInstructions[2412] }; const ND_TABLE_VEX_W gEvexTable_root_02_54_01_w = @@ -4668,13 +4673,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_54_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2351] + (const void *)&gInstructions[2410] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2352] + (const void *)&gInstructions[2411] }; const ND_TABLE_VEX_W gEvexTable_root_02_55_01_w = @@ -4700,13 +4705,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_55_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2381] + (const void *)&gInstructions[2440] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2382] + (const void *)&gInstructions[2441] }; const ND_TABLE_VEX_W gEvexTable_root_02_a0_01_mem_w = @@ -4741,13 +4746,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a0_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2383] + (const void *)&gInstructions[2442] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2384] + (const void *)&gInstructions[2443] }; const ND_TABLE_VEX_W gEvexTable_root_02_a1_01_mem_w = @@ -4782,13 +4787,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a1_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2400] + (const void *)&gInstructions[2459] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2401] + (const void *)&gInstructions[2460] }; const ND_TABLE_VEX_W gEvexTable_root_02_71_01_w = @@ -4814,7 +4819,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_71_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_70_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2402] + (const void *)&gInstructions[2461] }; const ND_TABLE_VEX_W gEvexTable_root_02_70_01_w = @@ -4840,13 +4845,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_70_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2409] + (const void *)&gInstructions[2468] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2410] + (const void *)&gInstructions[2469] }; const ND_TABLE_VEX_W gEvexTable_root_02_73_01_w = @@ -4872,7 +4877,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_73_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2413] + (const void *)&gInstructions[2472] }; const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp = @@ -4889,7 +4894,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_8f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2415] + (const void *)&gInstructions[2474] }; const ND_TABLE_VEX_W gEvexTable_root_02_8f_01_w = @@ -4915,13 +4920,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2435] + (const void *)&gInstructions[2494] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2437] + (const void *)&gInstructions[2496] }; const ND_TABLE_VEX_W gEvexTable_root_02_47_01_w = @@ -4947,13 +4952,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_47_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2450] + (const void *)&gInstructions[2509] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2452] + (const void *)&gInstructions[2511] }; const ND_TABLE_VEX_W gEvexTable_root_02_46_01_w = @@ -4979,13 +4984,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_46_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2468] + (const void *)&gInstructions[2527] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2470] + (const void *)&gInstructions[2529] }; const ND_TABLE_VEX_W gEvexTable_root_02_45_01_w = @@ -5011,13 +5016,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_45_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2496] + (const void *)&gInstructions[2555] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2499] + (const void *)&gInstructions[2558] }; const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w = @@ -5032,13 +5037,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2500] + (const void *)&gInstructions[2559] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2503] + (const void *)&gInstructions[2562] }; const ND_TABLE_VEX_W gEvexTable_root_02_26_02_w = @@ -5064,13 +5069,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_26_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2497] + (const void *)&gInstructions[2556] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2498] + (const void *)&gInstructions[2557] }; const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w = @@ -5085,13 +5090,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2501] + (const void *)&gInstructions[2560] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2502] + (const void *)&gInstructions[2561] }; const ND_TABLE_VEX_W gEvexTable_root_02_27_02_w = @@ -5117,13 +5122,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_27_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2527] + (const void *)&gInstructions[2586] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2528] + (const void *)&gInstructions[2587] }; const ND_TABLE_VEX_W gEvexTable_root_02_4c_01_w = @@ -5149,13 +5154,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2529] + (const void *)&gInstructions[2588] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2530] + (const void *)&gInstructions[2589] }; const ND_TABLE_VEX_W gEvexTable_root_02_4d_01_w = @@ -5181,13 +5186,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2531] + (const void *)&gInstructions[2590] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2532] + (const void *)&gInstructions[2591] }; const ND_TABLE_VEX_W gEvexTable_root_02_ca_01_02_w = @@ -5224,13 +5229,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ca_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2533] + (const void *)&gInstructions[2592] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2534] + (const void *)&gInstructions[2593] }; const ND_TABLE_VEX_W gEvexTable_root_02_cb_01_w = @@ -5256,13 +5261,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2555] + (const void *)&gInstructions[2614] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2556] + (const void *)&gInstructions[2615] }; const ND_TABLE_VEX_W gEvexTable_root_02_4e_01_w = @@ -5288,13 +5293,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2557] + (const void *)&gInstructions[2616] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2558] + (const void *)&gInstructions[2617] }; const ND_TABLE_VEX_W gEvexTable_root_02_4f_01_w = @@ -5320,13 +5325,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2559] + (const void *)&gInstructions[2618] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2560] + (const void *)&gInstructions[2619] }; const ND_TABLE_VEX_W gEvexTable_root_02_cc_01_02_w = @@ -5363,13 +5368,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2561] + (const void *)&gInstructions[2620] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2562] + (const void *)&gInstructions[2621] }; const ND_TABLE_VEX_W gEvexTable_root_02_cd_01_w = @@ -5395,13 +5400,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2567] + (const void *)&gInstructions[2626] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2569] + (const void *)&gInstructions[2628] }; const ND_TABLE_VEX_W gEvexTable_root_02_2c_01_w = @@ -5427,13 +5432,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2570] + (const void *)&gInstructions[2629] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2572] + (const void *)&gInstructions[2631] }; const ND_TABLE_VEX_W gEvexTable_root_02_2d_01_w = @@ -5459,13 +5464,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2573] + (const void *)&gInstructions[2632] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2574] + (const void *)&gInstructions[2633] }; const ND_TABLE_VEX_W gEvexTable_root_02_a2_01_mem_w = @@ -5500,13 +5505,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2583] + (const void *)&gInstructions[2642] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2584] + (const void *)&gInstructions[2643] }; const ND_TABLE_VEX_W gEvexTable_root_02_a3_01_mem_w = @@ -5804,7 +5809,7 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode = const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1360] + (const void *)&gInstructions[1400] }; const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w = @@ -5819,7 +5824,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1363] + (const void *)&gInstructions[1403] }; const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w = @@ -5834,7 +5839,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1365] + (const void *)&gInstructions[1405] }; const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w = @@ -5849,7 +5854,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1368] + (const void *)&gInstructions[1408] }; const ND_TABLE_VEX_W gEvexTable_root_01_58_02_w = @@ -5875,7 +5880,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_58_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1384] + (const void *)&gInstructions[1424] }; const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w = @@ -5890,7 +5895,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1386] + (const void *)&gInstructions[1426] }; const ND_TABLE_VEX_W gEvexTable_root_01_55_00_w = @@ -5916,7 +5921,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_55_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1388] + (const void *)&gInstructions[1428] }; const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w = @@ -5931,7 +5936,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1390] + (const void *)&gInstructions[1430] }; const ND_TABLE_VEX_W gEvexTable_root_01_54_00_w = @@ -5957,7 +5962,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_54_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1414] + (const void *)&gInstructions[1456] }; const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w = @@ -5972,7 +5977,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1417] + (const void *)&gInstructions[1459] }; const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w = @@ -5987,7 +5992,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1419] + (const void *)&gInstructions[1461] }; const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w = @@ -6002,7 +6007,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1422] + (const void *)&gInstructions[1464] }; const ND_TABLE_VEX_W gEvexTable_root_01_c2_02_w = @@ -6028,7 +6033,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1424] + (const void *)&gInstructions[1466] }; const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w = @@ -6043,7 +6048,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1427] + (const void *)&gInstructions[1469] }; const ND_TABLE_VEX_W gEvexTable_root_01_2f_00_w = @@ -6069,13 +6074,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1431] + (const void *)&gInstructions[1473] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1471] + (const void *)&gInstructions[1518] }; const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w = @@ -6090,7 +6095,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1439] + (const void *)&gInstructions[1486] }; const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w = @@ -6105,7 +6110,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1496] + (const void *)&gInstructions[1543] }; const ND_TABLE_VEX_W gEvexTable_root_01_e6_01_w = @@ -6131,13 +6136,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1435] + (const void *)&gInstructions[1477] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1473] + (const void *)&gInstructions[1520] }; const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w = @@ -6152,7 +6157,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1459] + (const void *)&gInstructions[1506] }; const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w = @@ -6167,7 +6172,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1507] + (const void *)&gInstructions[1554] }; const ND_TABLE_VEX_W gEvexTable_root_01_5b_02_w = @@ -6193,7 +6198,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1442] + (const void *)&gInstructions[1489] }; const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w = @@ -6208,7 +6213,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1461] + (const void *)&gInstructions[1508] }; const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w = @@ -6223,7 +6228,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1477] + (const void *)&gInstructions[1524] }; const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w = @@ -6238,7 +6243,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1490] + (const void *)&gInstructions[1537] }; const ND_TABLE_VEX_W gEvexTable_root_01_5a_02_w = @@ -6264,13 +6269,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1445] + (const void *)&gInstructions[1492] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1468] + (const void *)&gInstructions[1515] }; const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w = @@ -6285,13 +6290,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1526] + (const void *)&gInstructions[1573] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1527] + (const void *)&gInstructions[1574] }; const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_wi = @@ -6306,7 +6311,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_wi = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1529] + (const void *)&gInstructions[1576] }; const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp = @@ -6323,13 +6328,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1446] + (const void *)&gInstructions[1493] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1469] + (const void *)&gInstructions[1516] }; const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w = @@ -6344,13 +6349,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1447] + (const void *)&gInstructions[1494] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1470] + (const void *)&gInstructions[1517] }; const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w = @@ -6365,13 +6370,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1479] + (const void *)&gInstructions[1526] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1495] + (const void *)&gInstructions[1542] }; const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp = @@ -6388,13 +6393,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1475] + (const void *)&gInstructions[1522] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1493] + (const void *)&gInstructions[1540] }; const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp = @@ -6411,13 +6416,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1484] + (const void *)&gInstructions[1531] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1485] + (const void *)&gInstructions[1532] }; const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_wi = @@ -6432,7 +6437,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_wi = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1488] + (const void *)&gInstructions[1535] }; const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp = @@ -6449,13 +6454,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1498] + (const void *)&gInstructions[1545] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1509] + (const void *)&gInstructions[1556] }; const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w = @@ -6470,13 +6475,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1520] + (const void *)&gInstructions[1567] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1523] + (const void *)&gInstructions[1570] }; const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w = @@ -6491,13 +6496,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1522] + (const void *)&gInstructions[1569] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1525] + (const void *)&gInstructions[1572] }; const ND_TABLE_VEX_W gEvexTable_root_01_7a_03_w = @@ -6523,13 +6528,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1499] + (const void *)&gInstructions[1546] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1510] + (const void *)&gInstructions[1557] }; const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w = @@ -6544,13 +6549,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1500] + (const void *)&gInstructions[1547] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1511] + (const void *)&gInstructions[1558] }; const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w = @@ -6565,13 +6570,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1514] + (const void *)&gInstructions[1561] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1519] + (const void *)&gInstructions[1566] }; const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp = @@ -6588,13 +6593,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1512] + (const void *)&gInstructions[1559] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1517] + (const void *)&gInstructions[1564] }; const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp = @@ -6611,7 +6616,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1533] + (const void *)&gInstructions[1580] }; const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w = @@ -6626,7 +6631,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1536] + (const void *)&gInstructions[1583] }; const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w = @@ -6641,7 +6646,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1538] + (const void *)&gInstructions[1585] }; const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w = @@ -6656,7 +6661,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1541] + (const void *)&gInstructions[1588] }; const ND_TABLE_VEX_W gEvexTable_root_01_5e_02_w = @@ -6682,7 +6687,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1837] + (const void *)&gInstructions[1884] }; const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w = @@ -6697,7 +6702,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1840] + (const void *)&gInstructions[1887] }; const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w = @@ -6712,7 +6717,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1842] + (const void *)&gInstructions[1889] }; const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w = @@ -6727,7 +6732,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1845] + (const void *)&gInstructions[1892] }; const ND_TABLE_VEX_W gEvexTable_root_01_5f_02_w = @@ -6753,7 +6758,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1852] + (const void *)&gInstructions[1899] }; const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w = @@ -6768,7 +6773,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1855] + (const void *)&gInstructions[1902] }; const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w = @@ -6783,7 +6788,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1857] + (const void *)&gInstructions[1904] }; const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w = @@ -6798,7 +6803,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1860] + (const void *)&gInstructions[1907] }; const ND_TABLE_VEX_W gEvexTable_root_01_5d_02_w = @@ -6824,7 +6829,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1866] + (const void *)&gInstructions[1913] }; const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w = @@ -6839,7 +6844,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1870] + (const void *)&gInstructions[1917] }; const ND_TABLE_VEX_W gEvexTable_root_01_28_00_w = @@ -6865,7 +6870,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_28_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1867] + (const void *)&gInstructions[1914] }; const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w = @@ -6880,7 +6885,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1871] + (const void *)&gInstructions[1918] }; const ND_TABLE_VEX_W gEvexTable_root_01_29_00_w = @@ -6906,13 +6911,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_29_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1874] + (const void *)&gInstructions[1921] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1929] + (const void *)&gInstructions[1976] }; const ND_TABLE_VEX_W gEvexTable_root_01_6e_01_00_wi = @@ -6949,13 +6954,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1875] + (const void *)&gInstructions[1922] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1930] + (const void *)&gInstructions[1977] }; const ND_TABLE_VEX_W gEvexTable_root_01_7e_01_00_wi = @@ -6981,7 +6986,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_7e_01_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_02_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1931] + (const void *)&gInstructions[1978] }; const ND_TABLE_VEX_W gEvexTable_root_01_7e_02_00_w = @@ -7018,7 +7023,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1878] + (const void *)&gInstructions[1925] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w = @@ -7033,7 +7038,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1879] + (const void *)&gInstructions[1926] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w = @@ -7048,7 +7053,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1880] + (const void *)&gInstructions[1927] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_03_02_w = @@ -7074,7 +7079,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_03_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1899] + (const void *)&gInstructions[1946] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_00_reg_00_w = @@ -7100,7 +7105,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_00_reg_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1915] + (const void *)&gInstructions[1962] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_00_mem_00_w = @@ -7135,7 +7140,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_00_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1911] + (const void *)&gInstructions[1958] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_01_mem_00_w = @@ -7170,7 +7175,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1951] + (const void *)&gInstructions[1998] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_02_w = @@ -7196,13 +7201,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_12_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1885] + (const void *)&gInstructions[1932] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1887] + (const void *)&gInstructions[1934] }; const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w = @@ -7217,13 +7222,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1891] + (const void *)&gInstructions[1938] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1897] + (const void *)&gInstructions[1944] }; const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w = @@ -7238,13 +7243,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1893] + (const void *)&gInstructions[1940] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1895] + (const void *)&gInstructions[1942] }; const ND_TABLE_VEX_W gEvexTable_root_01_6f_02_w = @@ -7270,13 +7275,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1886] + (const void *)&gInstructions[1933] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1888] + (const void *)&gInstructions[1935] }; const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w = @@ -7291,13 +7296,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1892] + (const void *)&gInstructions[1939] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1898] + (const void *)&gInstructions[1945] }; const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w = @@ -7312,13 +7317,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1894] + (const void *)&gInstructions[1941] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1896] + (const void *)&gInstructions[1943] }; const ND_TABLE_VEX_W gEvexTable_root_01_7f_02_w = @@ -7344,7 +7349,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1901] + (const void *)&gInstructions[1948] }; const ND_TABLE_VEX_W gEvexTable_root_01_16_01_mem_00_w = @@ -7379,7 +7384,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1905] + (const void *)&gInstructions[1952] }; const ND_TABLE_VEX_W gEvexTable_root_01_16_00_mem_00_w = @@ -7405,7 +7410,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_16_00_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1909] + (const void *)&gInstructions[1956] }; const ND_TABLE_VEX_W gEvexTable_root_01_16_00_reg_00_w = @@ -7440,7 +7445,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_00_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1949] + (const void *)&gInstructions[1996] }; const ND_TABLE_VEX_W gEvexTable_root_01_16_02_w = @@ -7466,7 +7471,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_16_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1902] + (const void *)&gInstructions[1949] }; const ND_TABLE_VEX_W gEvexTable_root_01_17_01_mem_00_w = @@ -7501,7 +7506,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1906] + (const void *)&gInstructions[1953] }; const ND_TABLE_VEX_W gEvexTable_root_01_17_00_mem_00_w = @@ -7547,7 +7552,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_17_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1912] + (const void *)&gInstructions[1959] }; const ND_TABLE_VEX_W gEvexTable_root_01_13_01_mem_00_w = @@ -7582,7 +7587,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1916] + (const void *)&gInstructions[1963] }; const ND_TABLE_VEX_W gEvexTable_root_01_13_00_mem_00_w = @@ -7628,7 +7633,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_13_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e7_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1921] + (const void *)&gInstructions[1968] }; const ND_TABLE_VEX_W gEvexTable_root_01_e7_01_mem_w = @@ -7663,7 +7668,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1925] + (const void *)&gInstructions[1972] }; const ND_TABLE_VEX_W gEvexTable_root_01_2b_01_mem_w = @@ -7687,7 +7692,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1927] + (const void *)&gInstructions[1974] }; const ND_TABLE_VEX_W gEvexTable_root_01_2b_00_mem_w = @@ -7722,7 +7727,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d6_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1932] + (const void *)&gInstructions[1979] }; const ND_TABLE_VEX_W gEvexTable_root_01_d6_01_00_w = @@ -7759,7 +7764,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1937] + (const void *)&gInstructions[1984] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w = @@ -7774,7 +7779,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1938] + (const void *)&gInstructions[1985] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_03_reg_w = @@ -7798,7 +7803,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1953] + (const void *)&gInstructions[2000] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w = @@ -7813,7 +7818,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1954] + (const void *)&gInstructions[2001] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_02_reg_w = @@ -7837,7 +7842,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1961] + (const void *)&gInstructions[2008] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w = @@ -7852,7 +7857,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1965] + (const void *)&gInstructions[2012] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_00_w = @@ -7878,7 +7883,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_10_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1939] + (const void *)&gInstructions[1986] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w = @@ -7893,7 +7898,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1940] + (const void *)&gInstructions[1987] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_03_reg_w = @@ -7917,7 +7922,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1955] + (const void *)&gInstructions[2002] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w = @@ -7932,7 +7937,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1956] + (const void *)&gInstructions[2003] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_02_reg_w = @@ -7956,7 +7961,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1962] + (const void *)&gInstructions[2009] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w = @@ -7971,7 +7976,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1966] + (const void *)&gInstructions[2013] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_00_w = @@ -7997,7 +8002,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_11_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1980] + (const void *)&gInstructions[2027] }; const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w = @@ -8012,7 +8017,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1983] + (const void *)&gInstructions[2030] }; const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w = @@ -8027,7 +8032,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1985] + (const void *)&gInstructions[2032] }; const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w = @@ -8042,7 +8047,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1988] + (const void *)&gInstructions[2035] }; const ND_TABLE_VEX_W gEvexTable_root_01_59_02_w = @@ -8068,7 +8073,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_59_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1993] + (const void *)&gInstructions[2040] }; const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w = @@ -8083,7 +8088,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1995] + (const void *)&gInstructions[2042] }; const ND_TABLE_VEX_W gEvexTable_root_01_56_00_w = @@ -8109,7 +8114,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_56_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2008] + (const void *)&gInstructions[2055] }; const ND_TABLE_VEX_W gEvexTable_root_01_6b_01_w = @@ -8135,7 +8140,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_63_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2010] + (const void *)&gInstructions[2057] }; const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp = @@ -8152,7 +8157,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_67_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2014] + (const void *)&gInstructions[2061] }; const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp = @@ -8169,7 +8174,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2016] + (const void *)&gInstructions[2063] }; const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp = @@ -8186,7 +8191,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fe_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2018] + (const void *)&gInstructions[2065] }; const ND_TABLE_VEX_W gEvexTable_root_01_fe_01_w = @@ -8212,7 +8217,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fe_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2020] + (const void *)&gInstructions[2067] }; const ND_TABLE_VEX_W gEvexTable_root_01_d4_01_w = @@ -8238,7 +8243,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ec_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2022] + (const void *)&gInstructions[2069] }; const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp = @@ -8255,7 +8260,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ed_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2024] + (const void *)&gInstructions[2071] }; const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp = @@ -8272,7 +8277,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_dc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2026] + (const void *)&gInstructions[2073] }; const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp = @@ -8289,7 +8294,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_dd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2028] + (const void *)&gInstructions[2075] }; const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp = @@ -8306,7 +8311,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2030] + (const void *)&gInstructions[2077] }; const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp = @@ -8323,13 +8328,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2035] + (const void *)&gInstructions[2082] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2039] + (const void *)&gInstructions[2086] }; const ND_TABLE_VEX_W gEvexTable_root_01_db_01_w = @@ -8355,13 +8360,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_db_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2037] + (const void *)&gInstructions[2084] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2038] + (const void *)&gInstructions[2085] }; const ND_TABLE_VEX_W gEvexTable_root_01_df_01_w = @@ -8387,7 +8392,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_df_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2040] + (const void *)&gInstructions[2087] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp = @@ -8404,7 +8409,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2042] + (const void *)&gInstructions[2089] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp = @@ -8421,7 +8426,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_74_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2071] + (const void *)&gInstructions[2118] }; const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp = @@ -8438,7 +8443,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_76_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2073] + (const void *)&gInstructions[2120] }; const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp = @@ -8455,7 +8460,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_75_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2077] + (const void *)&gInstructions[2124] }; const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp = @@ -8472,7 +8477,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_64_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2081] + (const void *)&gInstructions[2128] }; const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp = @@ -8489,7 +8494,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_66_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2083] + (const void *)&gInstructions[2130] }; const ND_TABLE_VEX_W gEvexTable_root_01_66_01_w = @@ -8515,7 +8520,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_66_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_65_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2087] + (const void *)&gInstructions[2134] }; const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp = @@ -8532,7 +8537,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c5_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2171] + (const void *)&gInstructions[2228] }; const ND_TABLE_VEX_L gEvexTable_root_01_c5_01_reg_l = @@ -8569,7 +8574,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2215] + (const void *)&gInstructions[2272] }; const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l = @@ -8586,7 +8591,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2216] + (const void *)&gInstructions[2273] }; const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_reg_l = @@ -8623,7 +8628,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2237] + (const void *)&gInstructions[2296] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp = @@ -8640,7 +8645,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ee_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2248] + (const void *)&gInstructions[2307] }; const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp = @@ -8657,7 +8662,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_de_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2250] + (const void *)&gInstructions[2309] }; const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp = @@ -8674,7 +8679,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ea_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2262] + (const void *)&gInstructions[2321] }; const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp = @@ -8691,7 +8696,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_da_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2264] + (const void *)&gInstructions[2323] }; const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp = @@ -8708,7 +8713,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e4_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2338] + (const void *)&gInstructions[2397] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp = @@ -8725,7 +8730,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2340] + (const void *)&gInstructions[2399] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp = @@ -8742,7 +8747,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2345] + (const void *)&gInstructions[2404] }; const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp = @@ -8759,7 +8764,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2348] + (const void *)&gInstructions[2407] }; const ND_TABLE_VEX_W gEvexTable_root_01_f4_01_w = @@ -8785,13 +8790,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2355] + (const void *)&gInstructions[2414] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2356] + (const void *)&gInstructions[2415] }; const ND_TABLE_VEX_W gEvexTable_root_01_eb_01_w = @@ -8817,13 +8822,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_eb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2359] + (const void *)&gInstructions[2418] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2360] + (const void *)&gInstructions[2419] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w = @@ -8838,13 +8843,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2363] + (const void *)&gInstructions[2422] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2364] + (const void *)&gInstructions[2423] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w = @@ -8859,7 +8864,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_06_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2425] + (const void *)&gInstructions[2484] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w = @@ -8874,13 +8879,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2444] + (const void *)&gInstructions[2503] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2448] + (const void *)&gInstructions[2507] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w = @@ -8895,7 +8900,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2458] + (const void *)&gInstructions[2517] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_02_w = @@ -8936,7 +8941,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_72_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2379] + (const void *)&gInstructions[2438] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp = @@ -8953,7 +8958,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2416] + (const void *)&gInstructions[2475] }; const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w = @@ -8968,13 +8973,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2418] + (const void *)&gInstructions[2477] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2420] + (const void *)&gInstructions[2479] }; const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp = @@ -8991,7 +8996,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f2_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2426] + (const void *)&gInstructions[2485] }; const ND_TABLE_VEX_W gEvexTable_root_01_f2_01_w = @@ -9017,13 +9022,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2429] + (const void *)&gInstructions[2488] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_06_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2431] + (const void *)&gInstructions[2490] }; const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w = @@ -9038,13 +9043,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2462] + (const void *)&gInstructions[2521] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2464] + (const void *)&gInstructions[2523] }; const ND_TABLE_VEX_W gEvexTable_root_01_73_01_02_w = @@ -9085,7 +9090,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_73_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f3_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2432] + (const void *)&gInstructions[2491] }; const ND_TABLE_VEX_W gEvexTable_root_01_f3_01_w = @@ -9111,19 +9116,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f3_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2440] + (const void *)&gInstructions[2499] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2454] + (const void *)&gInstructions[2513] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2473] + (const void *)&gInstructions[2532] }; const ND_TABLE_MODRM_REG gEvexTable_root_01_71_01_modrmreg = @@ -9155,7 +9160,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_71_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2441] + (const void *)&gInstructions[2500] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp = @@ -9172,13 +9177,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2445] + (const void *)&gInstructions[2504] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2449] + (const void *)&gInstructions[2508] }; const ND_TABLE_VEX_W gEvexTable_root_01_e2_01_w = @@ -9204,7 +9209,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2455] + (const void *)&gInstructions[2514] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp = @@ -9221,7 +9226,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d2_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2459] + (const void *)&gInstructions[2518] }; const ND_TABLE_VEX_W gEvexTable_root_01_d2_01_w = @@ -9247,7 +9252,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d3_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2465] + (const void *)&gInstructions[2524] }; const ND_TABLE_VEX_W gEvexTable_root_01_d3_01_w = @@ -9273,7 +9278,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d3_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2474] + (const void *)&gInstructions[2533] }; const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp = @@ -9290,7 +9295,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2477] + (const void *)&gInstructions[2536] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp = @@ -9307,7 +9312,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fa_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2479] + (const void *)&gInstructions[2538] }; const ND_TABLE_VEX_W gEvexTable_root_01_fa_01_w = @@ -9333,7 +9338,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fa_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2481] + (const void *)&gInstructions[2540] }; const ND_TABLE_VEX_W gEvexTable_root_01_fb_01_w = @@ -9359,7 +9364,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2483] + (const void *)&gInstructions[2542] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp = @@ -9376,7 +9381,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2485] + (const void *)&gInstructions[2544] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp = @@ -9393,7 +9398,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2487] + (const void *)&gInstructions[2546] }; const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp = @@ -9410,7 +9415,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2489] + (const void *)&gInstructions[2548] }; const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp = @@ -9427,7 +9432,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2491] + (const void *)&gInstructions[2550] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp = @@ -9444,7 +9449,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_68_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2504] + (const void *)&gInstructions[2563] }; const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp = @@ -9461,7 +9466,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2506] + (const void *)&gInstructions[2565] }; const ND_TABLE_VEX_W gEvexTable_root_01_6a_01_w = @@ -9487,7 +9492,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2508] + (const void *)&gInstructions[2567] }; const ND_TABLE_VEX_W gEvexTable_root_01_6d_01_w = @@ -9513,7 +9518,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_69_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2510] + (const void *)&gInstructions[2569] }; const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp = @@ -9530,7 +9535,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_60_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2512] + (const void *)&gInstructions[2571] }; const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp = @@ -9547,7 +9552,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_62_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2514] + (const void *)&gInstructions[2573] }; const ND_TABLE_VEX_W gEvexTable_root_01_62_01_w = @@ -9573,7 +9578,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_62_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2516] + (const void *)&gInstructions[2575] }; const ND_TABLE_VEX_W gEvexTable_root_01_6c_01_w = @@ -9599,7 +9604,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_61_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2518] + (const void *)&gInstructions[2577] }; const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp = @@ -9616,13 +9621,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2521] + (const void *)&gInstructions[2580] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2522] + (const void *)&gInstructions[2581] }; const ND_TABLE_VEX_W gEvexTable_root_01_ef_01_w = @@ -9648,7 +9653,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ef_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2589] + (const void *)&gInstructions[2648] }; const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w = @@ -9663,7 +9668,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2591] + (const void *)&gInstructions[2650] }; const ND_TABLE_VEX_W gEvexTable_root_01_c6_00_w = @@ -9689,7 +9694,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2593] + (const void *)&gInstructions[2652] }; const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w = @@ -9704,7 +9709,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2596] + (const void *)&gInstructions[2655] }; const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w = @@ -9719,7 +9724,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2598] + (const void *)&gInstructions[2657] }; const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w = @@ -9734,7 +9739,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2601] + (const void *)&gInstructions[2660] }; const ND_TABLE_VEX_W gEvexTable_root_01_51_02_w = @@ -9760,7 +9765,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_51_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2604] + (const void *)&gInstructions[2663] }; const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w = @@ -9775,7 +9780,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2607] + (const void *)&gInstructions[2666] }; const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w = @@ -9790,7 +9795,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2609] + (const void *)&gInstructions[2668] }; const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w = @@ -9805,7 +9810,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2612] + (const void *)&gInstructions[2671] }; const ND_TABLE_VEX_W gEvexTable_root_01_5c_02_w = @@ -9831,7 +9836,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2616] + (const void *)&gInstructions[2675] }; const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w = @@ -9846,7 +9851,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2619] + (const void *)&gInstructions[2678] }; const ND_TABLE_VEX_W gEvexTable_root_01_2e_00_w = @@ -9872,7 +9877,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2621] + (const void *)&gInstructions[2680] }; const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w = @@ -9887,7 +9892,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2623] + (const void *)&gInstructions[2682] }; const ND_TABLE_VEX_W gEvexTable_root_01_15_00_w = @@ -9913,7 +9918,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_15_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2625] + (const void *)&gInstructions[2684] }; const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w = @@ -9928,7 +9933,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2627] + (const void *)&gInstructions[2686] }; const ND_TABLE_VEX_W gEvexTable_root_01_14_00_w = @@ -9954,7 +9959,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_14_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2629] + (const void *)&gInstructions[2688] }; const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w = @@ -9969,7 +9974,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2631] + (const void *)&gInstructions[2690] }; const ND_TABLE_VEX_W gEvexTable_root_01_57_00_w = @@ -10258,7 +10263,7 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode = const ND_TABLE_INSTRUCTION gEvexTable_root_05_58_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1362] + (const void *)&gInstructions[1402] }; const ND_TABLE_VEX_W gEvexTable_root_05_58_00_w = @@ -10273,7 +10278,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_58_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_58_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1367] + (const void *)&gInstructions[1407] }; const ND_TABLE_VEX_W gEvexTable_root_05_58_02_w = @@ -10299,7 +10304,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_58_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_2f_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1426] + (const void *)&gInstructions[1468] }; const ND_TABLE_VEX_W gEvexTable_root_05_2f_00_w = @@ -10325,13 +10330,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1434] + (const void *)&gInstructions[1476] }; const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1472] + (const void *)&gInstructions[1519] }; const ND_TABLE_VEX_W gEvexTable_root_05_5b_00_w = @@ -10346,7 +10351,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5b_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1448] + (const void *)&gInstructions[1495] }; const ND_TABLE_VEX_W gEvexTable_root_05_5b_01_w = @@ -10361,7 +10366,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5b_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1501] + (const void *)&gInstructions[1548] }; const ND_TABLE_VEX_W gEvexTable_root_05_5b_02_w = @@ -10387,7 +10392,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1441] + (const void *)&gInstructions[1488] }; const ND_TABLE_VEX_W gEvexTable_root_05_5a_01_w = @@ -10402,7 +10407,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1449] + (const void *)&gInstructions[1496] }; const ND_TABLE_VEX_W gEvexTable_root_05_5a_00_w = @@ -10417,7 +10422,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1474] + (const void *)&gInstructions[1521] }; const ND_TABLE_VEX_W gEvexTable_root_05_5a_03_w = @@ -10432,7 +10437,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1480] + (const void *)&gInstructions[1527] }; const ND_TABLE_VEX_W gEvexTable_root_05_5a_02_w = @@ -10458,7 +10463,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1454] + (const void *)&gInstructions[1501] }; const ND_TABLE_VEX_W gEvexTable_root_05_7b_01_w = @@ -10473,7 +10478,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7b_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7b_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1528] + (const void *)&gInstructions[1575] }; const ND_TABLE_VEX_PP gEvexTable_root_05_7b_pp = @@ -10490,7 +10495,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_79_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1455] + (const void *)&gInstructions[1502] }; const ND_TABLE_VEX_W gEvexTable_root_05_79_00_w = @@ -10505,7 +10510,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_79_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1456] + (const void *)&gInstructions[1503] }; const ND_TABLE_VEX_W gEvexTable_root_05_79_01_w = @@ -10520,7 +10525,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_79_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_79_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1483] + (const void *)&gInstructions[1530] }; const ND_TABLE_VEX_PP gEvexTable_root_05_79_pp = @@ -10537,7 +10542,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_79_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1457] + (const void *)&gInstructions[1504] }; const ND_TABLE_VEX_W gEvexTable_root_05_7d_00_w = @@ -10552,7 +10557,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1458] + (const void *)&gInstructions[1505] }; const ND_TABLE_VEX_W gEvexTable_root_05_7d_01_w = @@ -10567,7 +10572,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1530] + (const void *)&gInstructions[1577] }; const ND_TABLE_VEX_W gEvexTable_root_05_7d_03_w = @@ -10582,7 +10587,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1531] + (const void *)&gInstructions[1578] }; const ND_TABLE_VEX_W gEvexTable_root_05_7d_02_w = @@ -10608,7 +10613,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_1d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1467] + (const void *)&gInstructions[1514] }; const ND_TABLE_VEX_W gEvexTable_root_05_1d_01_w = @@ -10623,7 +10628,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_1d_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_1d_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1492] + (const void *)&gInstructions[1539] }; const ND_TABLE_VEX_W gEvexTable_root_05_1d_00_w = @@ -10649,7 +10654,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_1d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_2d_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1481] + (const void *)&gInstructions[1528] }; const ND_TABLE_VEX_PP gEvexTable_root_05_2d_pp = @@ -10666,7 +10671,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_2a_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1487] + (const void *)&gInstructions[1534] }; const ND_TABLE_VEX_PP gEvexTable_root_05_2a_pp = @@ -10683,7 +10688,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1502] + (const void *)&gInstructions[1549] }; const ND_TABLE_VEX_W gEvexTable_root_05_7a_01_w = @@ -10698,13 +10703,13 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7a_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7a_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1521] + (const void *)&gInstructions[1568] }; const ND_TABLE_INSTRUCTION gEvexTable_root_05_7a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1524] + (const void *)&gInstructions[1571] }; const ND_TABLE_VEX_W gEvexTable_root_05_7a_03_w = @@ -10730,7 +10735,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_78_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1503] + (const void *)&gInstructions[1550] }; const ND_TABLE_VEX_W gEvexTable_root_05_78_00_w = @@ -10745,7 +10750,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_78_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1504] + (const void *)&gInstructions[1551] }; const ND_TABLE_VEX_W gEvexTable_root_05_78_01_w = @@ -10760,7 +10765,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_78_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_78_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1516] + (const void *)&gInstructions[1563] }; const ND_TABLE_VEX_W gEvexTable_root_05_78_02_wi = @@ -10786,7 +10791,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_78_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7c_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1505] + (const void *)&gInstructions[1552] }; const ND_TABLE_VEX_W gEvexTable_root_05_7c_00_w = @@ -10801,7 +10806,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7c_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1506] + (const void *)&gInstructions[1553] }; const ND_TABLE_VEX_W gEvexTable_root_05_7c_01_w = @@ -10827,7 +10832,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_2c_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1515] + (const void *)&gInstructions[1562] }; const ND_TABLE_VEX_PP gEvexTable_root_05_2c_pp = @@ -10844,7 +10849,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5e_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1535] + (const void *)&gInstructions[1582] }; const ND_TABLE_VEX_W gEvexTable_root_05_5e_00_w = @@ -10859,7 +10864,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5e_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5e_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1540] + (const void *)&gInstructions[1587] }; const ND_TABLE_VEX_W gEvexTable_root_05_5e_02_w = @@ -10885,7 +10890,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5f_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1839] + (const void *)&gInstructions[1886] }; const ND_TABLE_VEX_W gEvexTable_root_05_5f_00_w = @@ -10900,7 +10905,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5f_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5f_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1844] + (const void *)&gInstructions[1891] }; const ND_TABLE_VEX_W gEvexTable_root_05_5f_02_w = @@ -10926,7 +10931,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5d_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1854] + (const void *)&gInstructions[1901] }; const ND_TABLE_VEX_W gEvexTable_root_05_5d_00_w = @@ -10941,7 +10946,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5d_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5d_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1859] + (const void *)&gInstructions[1906] }; const ND_TABLE_VEX_W gEvexTable_root_05_5d_02_w = @@ -10967,7 +10972,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_10_02_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1945] + (const void *)&gInstructions[1992] }; const ND_TABLE_VEX_W gEvexTable_root_05_10_02_mem_w = @@ -10982,7 +10987,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_10_02_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_10_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1946] + (const void *)&gInstructions[1993] }; const ND_TABLE_VEX_W gEvexTable_root_05_10_02_reg_w = @@ -11017,7 +11022,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_10_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_11_02_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1947] + (const void *)&gInstructions[1994] }; const ND_TABLE_VEX_W gEvexTable_root_05_11_02_mem_w = @@ -11032,7 +11037,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_11_02_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_11_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1948] + (const void *)&gInstructions[1995] }; const ND_TABLE_VEX_W gEvexTable_root_05_11_02_reg_w = @@ -11067,7 +11072,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_11_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_6e_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1969] + (const void *)&gInstructions[2016] }; const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_mem_l = @@ -11084,7 +11089,7 @@ const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_05_6e_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1970] + (const void *)&gInstructions[2017] }; const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_reg_l = @@ -11121,7 +11126,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_6e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7e_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1971] + (const void *)&gInstructions[2018] }; const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_mem_l = @@ -11138,7 +11143,7 @@ const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7e_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1972] + (const void *)&gInstructions[2019] }; const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_reg_l = @@ -11175,7 +11180,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_59_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1982] + (const void *)&gInstructions[2029] }; const ND_TABLE_VEX_W gEvexTable_root_05_59_00_w = @@ -11190,7 +11195,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_59_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_59_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1987] + (const void *)&gInstructions[2034] }; const ND_TABLE_VEX_W gEvexTable_root_05_59_02_w = @@ -11216,7 +11221,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_59_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_51_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2595] + (const void *)&gInstructions[2654] }; const ND_TABLE_VEX_W gEvexTable_root_05_51_00_w = @@ -11231,7 +11236,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_51_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_51_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2600] + (const void *)&gInstructions[2659] }; const ND_TABLE_VEX_W gEvexTable_root_05_51_02_w = @@ -11257,7 +11262,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_51_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5c_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2606] + (const void *)&gInstructions[2665] }; const ND_TABLE_VEX_W gEvexTable_root_05_5c_00_w = @@ -11272,7 +11277,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5c_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5c_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2611] + (const void *)&gInstructions[2670] }; const ND_TABLE_VEX_W gEvexTable_root_05_5c_02_w = @@ -11298,7 +11303,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_2e_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2618] + (const void *)&gInstructions[2677] }; const ND_TABLE_VEX_W gEvexTable_root_05_2e_00_w = @@ -11587,13 +11592,13 @@ const ND_TABLE_OPCODE gEvexTable_root_05_opcode = const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1382] + (const void *)&gInstructions[1422] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1383] + (const void *)&gInstructions[1423] }; const ND_TABLE_VEX_W gEvexTable_root_03_03_01_w = @@ -11619,7 +11624,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_03_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_c2_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1416] + (const void *)&gInstructions[1458] }; const ND_TABLE_VEX_W gEvexTable_root_03_c2_00_w = @@ -11634,7 +11639,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_c2_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_c2_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1421] + (const void *)&gInstructions[1463] }; const ND_TABLE_VEX_W gEvexTable_root_03_c2_02_w = @@ -11660,7 +11665,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_c2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1464] + (const void *)&gInstructions[1511] }; const ND_TABLE_VEX_W gEvexTable_root_03_1d_01_w = @@ -11686,7 +11691,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_42_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1532] + (const void *)&gInstructions[1579] }; const ND_TABLE_VEX_W gEvexTable_root_03_42_01_w = @@ -11712,13 +11717,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_42_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1553] + (const void *)&gInstructions[1600] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1555] + (const void *)&gInstructions[1602] }; const ND_TABLE_VEX_W gEvexTable_root_03_19_01_w = @@ -11744,13 +11749,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_19_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1554] + (const void *)&gInstructions[1601] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1556] + (const void *)&gInstructions[1603] }; const ND_TABLE_VEX_W gEvexTable_root_03_1b_01_02_w = @@ -11787,13 +11792,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1558] + (const void *)&gInstructions[1605] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1560] + (const void *)&gInstructions[1607] }; const ND_TABLE_VEX_W gEvexTable_root_03_39_01_w = @@ -11819,13 +11824,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_39_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1559] + (const void *)&gInstructions[1606] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1561] + (const void *)&gInstructions[1608] }; const ND_TABLE_VEX_W gEvexTable_root_03_3b_01_02_w = @@ -11862,7 +11867,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1562] + (const void *)&gInstructions[1609] }; const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l = @@ -11879,7 +11884,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1563] + (const void *)&gInstructions[1610] }; const ND_TABLE_VEX_L gEvexTable_root_03_17_01_reg_l = @@ -11916,13 +11921,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_17_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1570] + (const void *)&gInstructions[1617] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1571] + (const void *)&gInstructions[1618] }; const ND_TABLE_VEX_W gEvexTable_root_03_54_01_w = @@ -11948,13 +11953,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_54_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1572] + (const void *)&gInstructions[1619] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1573] + (const void *)&gInstructions[1620] }; const ND_TABLE_VEX_W gEvexTable_root_03_55_01_w = @@ -11980,13 +11985,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_55_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1768] + (const void *)&gInstructions[1815] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1770] + (const void *)&gInstructions[1817] }; const ND_TABLE_VEX_W gEvexTable_root_03_66_01_w = @@ -12001,7 +12006,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_66_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1769] + (const void *)&gInstructions[1816] }; const ND_TABLE_VEX_W gEvexTable_root_03_66_00_w = @@ -12027,13 +12032,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_66_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1771] + (const void *)&gInstructions[1818] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1773] + (const void *)&gInstructions[1820] }; const ND_TABLE_VEX_W gEvexTable_root_03_67_01_w = @@ -12048,7 +12053,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_67_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1772] + (const void *)&gInstructions[1819] }; const ND_TABLE_VEX_W gEvexTable_root_03_67_00_w = @@ -12074,13 +12079,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_67_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1800] + (const void *)&gInstructions[1847] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1802] + (const void *)&gInstructions[1849] }; const ND_TABLE_VEX_W gEvexTable_root_03_26_01_w = @@ -12095,7 +12100,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_26_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1801] + (const void *)&gInstructions[1848] }; const ND_TABLE_VEX_W gEvexTable_root_03_26_00_w = @@ -12121,13 +12126,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_26_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1803] + (const void *)&gInstructions[1850] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1805] + (const void *)&gInstructions[1852] }; const ND_TABLE_VEX_W gEvexTable_root_03_27_01_w = @@ -12142,7 +12147,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_27_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1804] + (const void *)&gInstructions[1851] }; const ND_TABLE_VEX_W gEvexTable_root_03_27_00_w = @@ -12168,7 +12173,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_27_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_cf_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1806] + (const void *)&gInstructions[1853] }; const ND_TABLE_VEX_W gEvexTable_root_03_cf_01_w = @@ -12194,7 +12199,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_cf_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_ce_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1808] + (const void *)&gInstructions[1855] }; const ND_TABLE_VEX_W gEvexTable_root_03_ce_01_w = @@ -12220,13 +12225,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_ce_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1817] + (const void *)&gInstructions[1864] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1819] + (const void *)&gInstructions[1866] }; const ND_TABLE_VEX_W gEvexTable_root_03_18_01_w = @@ -12252,13 +12257,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_18_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1818] + (const void *)&gInstructions[1865] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1820] + (const void *)&gInstructions[1867] }; const ND_TABLE_VEX_W gEvexTable_root_03_1a_01_02_w = @@ -12295,13 +12300,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1822] + (const void *)&gInstructions[1869] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1824] + (const void *)&gInstructions[1871] }; const ND_TABLE_VEX_W gEvexTable_root_03_38_01_w = @@ -12327,13 +12332,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_38_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1823] + (const void *)&gInstructions[1870] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1825] + (const void *)&gInstructions[1872] }; const ND_TABLE_VEX_W gEvexTable_root_03_3a_01_02_w = @@ -12370,7 +12375,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1826] + (const void *)&gInstructions[1873] }; const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l = @@ -12387,7 +12392,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1827] + (const void *)&gInstructions[1874] }; const ND_TABLE_VEX_L gEvexTable_root_03_21_01_reg_l = @@ -12424,7 +12429,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_21_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_0f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2032] + (const void *)&gInstructions[2079] }; const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp = @@ -12441,7 +12446,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_44_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2065] + (const void *)&gInstructions[2112] }; const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp = @@ -12458,13 +12463,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2069] + (const void *)&gInstructions[2116] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2096] + (const void *)&gInstructions[2143] }; const ND_TABLE_VEX_W gEvexTable_root_03_3f_01_w = @@ -12490,13 +12495,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2070] + (const void *)&gInstructions[2117] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2091] + (const void *)&gInstructions[2138] }; const ND_TABLE_VEX_W gEvexTable_root_03_1f_01_w = @@ -12522,13 +12527,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2092] + (const void *)&gInstructions[2139] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2095] + (const void *)&gInstructions[2142] }; const ND_TABLE_VEX_W gEvexTable_root_03_3e_01_w = @@ -12554,13 +12559,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2093] + (const void *)&gInstructions[2140] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2094] + (const void *)&gInstructions[2141] }; const ND_TABLE_VEX_W gEvexTable_root_03_1e_01_w = @@ -12586,7 +12591,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_05_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2135] + (const void *)&gInstructions[2188] }; const ND_TABLE_VEX_W gEvexTable_root_03_05_01_w = @@ -12612,7 +12617,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_05_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_04_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2139] + (const void *)&gInstructions[2192] }; const ND_TABLE_VEX_W gEvexTable_root_03_04_01_w = @@ -12638,7 +12643,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_04_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2144] + (const void *)&gInstructions[2197] }; const ND_TABLE_VEX_W gEvexTable_root_03_01_01_w = @@ -12664,7 +12669,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_01_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_00_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2150] + (const void *)&gInstructions[2203] }; const ND_TABLE_VEX_W gEvexTable_root_03_00_01_w = @@ -12690,7 +12695,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_00_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2163] + (const void *)&gInstructions[2216] }; const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l = @@ -12707,7 +12712,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2164] + (const void *)&gInstructions[2217] }; const ND_TABLE_VEX_L gEvexTable_root_03_14_01_reg_l = @@ -12741,44 +12746,85 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_14_pp = } }; -const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_00_00_leaf = +const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2220] +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_mem_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2224] +}; + +const ND_TABLE_VEX_W gEvexTable_root_03_16_01_mem_00_wi = +{ + ND_ILUT_VEX_WI, + { + /* 00 */ (const void *)&gEvexTable_root_03_16_01_mem_00_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_16_01_mem_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gEvexTable_root_03_16_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gEvexTable_root_03_16_01_mem_00_wi, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2167] + (const void *)&gInstructions[2221] }; -const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_00_01_leaf = +const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2169] + (const void *)&gInstructions[2225] }; -const ND_TABLE_VEX_W gEvexTable_root_03_16_01_00_wi = +const ND_TABLE_VEX_W gEvexTable_root_03_16_01_reg_00_wi = { ND_ILUT_VEX_WI, { - /* 00 */ (const void *)&gEvexTable_root_03_16_01_00_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_16_01_00_01_leaf, + /* 00 */ (const void *)&gEvexTable_root_03_16_01_reg_00_00_leaf, + /* 01 */ (const void *)&gEvexTable_root_03_16_01_reg_00_01_leaf, } }; -const ND_TABLE_VEX_L gEvexTable_root_03_16_01_l = +const ND_TABLE_VEX_L gEvexTable_root_03_16_01_reg_l = { ND_ILUT_VEX_L, { - /* 00 */ (const void *)&gEvexTable_root_03_16_01_00_wi, + /* 00 */ (const void *)&gEvexTable_root_03_16_01_reg_00_wi, /* 01 */ ND_NULL, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; +const ND_TABLE_MODRM_MOD gEvexTable_root_03_16_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexTable_root_03_16_01_mem_l, + /* 01 */ (const void *)&gEvexTable_root_03_16_01_reg_l, + } +}; + const ND_TABLE_VEX_PP gEvexTable_root_03_16_pp = { ND_ILUT_VEX_PP, { /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_16_01_l, + /* 01 */ (const void *)&gEvexTable_root_03_16_01_modrmmod, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } @@ -12787,7 +12833,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_16_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2172] + (const void *)&gInstructions[2229] }; const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l = @@ -12804,7 +12850,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2173] + (const void *)&gInstructions[2230] }; const ND_TABLE_VEX_L gEvexTable_root_03_15_01_reg_l = @@ -12841,7 +12887,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_15_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2207] + (const void *)&gInstructions[2264] }; const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l = @@ -12858,7 +12904,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2208] + (const void *)&gInstructions[2265] }; const ND_TABLE_VEX_L gEvexTable_root_03_20_01_reg_l = @@ -12895,13 +12941,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_20_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2211] + (const void *)&gInstructions[2268] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2213] + (const void *)&gInstructions[2270] }; const ND_TABLE_VEX_W gEvexTable_root_03_22_01_00_wi = @@ -12938,13 +12984,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_22_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2398] + (const void *)&gInstructions[2457] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2399] + (const void *)&gInstructions[2458] }; const ND_TABLE_VEX_W gEvexTable_root_03_71_01_w = @@ -12970,7 +13016,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_71_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_70_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2403] + (const void *)&gInstructions[2462] }; const ND_TABLE_VEX_W gEvexTable_root_03_70_01_w = @@ -12996,13 +13042,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_70_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2407] + (const void *)&gInstructions[2466] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2408] + (const void *)&gInstructions[2467] }; const ND_TABLE_VEX_W gEvexTable_root_03_73_01_w = @@ -13028,7 +13074,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_73_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_72_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2412] + (const void *)&gInstructions[2471] }; const ND_TABLE_VEX_W gEvexTable_root_03_72_01_w = @@ -13054,13 +13100,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_72_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2493] + (const void *)&gInstructions[2552] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2494] + (const void *)&gInstructions[2553] }; const ND_TABLE_VEX_W gEvexTable_root_03_25_01_w = @@ -13086,13 +13132,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_25_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2523] + (const void *)&gInstructions[2582] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2524] + (const void *)&gInstructions[2583] }; const ND_TABLE_VEX_W gEvexTable_root_03_50_01_w = @@ -13118,13 +13164,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_50_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2525] + (const void *)&gInstructions[2584] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2526] + (const void *)&gInstructions[2585] }; const ND_TABLE_VEX_W gEvexTable_root_03_51_01_w = @@ -13150,13 +13196,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_51_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2539] + (const void *)&gInstructions[2598] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2541] + (const void *)&gInstructions[2600] }; const ND_TABLE_VEX_W gEvexTable_root_03_56_01_w = @@ -13171,7 +13217,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_56_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2540] + (const void *)&gInstructions[2599] }; const ND_TABLE_VEX_W gEvexTable_root_03_56_00_w = @@ -13197,13 +13243,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_56_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2542] + (const void *)&gInstructions[2601] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2544] + (const void *)&gInstructions[2603] }; const ND_TABLE_VEX_W gEvexTable_root_03_57_01_w = @@ -13218,7 +13264,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_57_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2543] + (const void *)&gInstructions[2602] }; const ND_TABLE_VEX_W gEvexTable_root_03_57_00_w = @@ -13244,7 +13290,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_57_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_09_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2545] + (const void *)&gInstructions[2604] }; const ND_TABLE_VEX_W gEvexTable_root_03_09_01_w = @@ -13270,7 +13316,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_09_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2546] + (const void *)&gInstructions[2605] }; const ND_TABLE_VEX_W gEvexTable_root_03_08_00_w = @@ -13285,7 +13331,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_08_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2547] + (const void *)&gInstructions[2606] }; const ND_TABLE_VEX_W gEvexTable_root_03_08_01_w = @@ -13311,7 +13357,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_08_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_0b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2548] + (const void *)&gInstructions[2607] }; const ND_TABLE_VEX_W gEvexTable_root_03_0b_01_w = @@ -13337,7 +13383,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2549] + (const void *)&gInstructions[2608] }; const ND_TABLE_VEX_W gEvexTable_root_03_0a_00_w = @@ -13352,7 +13398,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_0a_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2550] + (const void *)&gInstructions[2609] }; const ND_TABLE_VEX_W gEvexTable_root_03_0a_01_w = @@ -13378,13 +13424,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2585] + (const void *)&gInstructions[2644] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2586] + (const void *)&gInstructions[2645] }; const ND_TABLE_VEX_W gEvexTable_root_03_23_01_w = @@ -13410,13 +13456,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_23_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2587] + (const void *)&gInstructions[2646] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2588] + (const void *)&gInstructions[2647] }; const ND_TABLE_VEX_W gEvexTable_root_03_43_01_w = @@ -13705,7 +13751,7 @@ const ND_TABLE_OPCODE gEvexTable_root_03_opcode = const ND_TABLE_INSTRUCTION gEvexTable_root_06_13_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1453] + (const void *)&gInstructions[1500] }; const ND_TABLE_VEX_W gEvexTable_root_06_13_01_w = @@ -13720,7 +13766,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_13_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_06_13_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1482] + (const void *)&gInstructions[1529] }; const ND_TABLE_VEX_W gEvexTable_root_06_13_00_w = @@ -13746,7 +13792,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_13_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_56_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1566] + (const void *)&gInstructions[1613] }; const ND_TABLE_VEX_W gEvexTable_root_06_56_03_w = @@ -13761,7 +13807,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_56_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_06_56_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1604] + (const void *)&gInstructions[1651] }; const ND_TABLE_VEX_W gEvexTable_root_06_56_02_w = @@ -13787,7 +13833,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_56_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_57_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1567] + (const void *)&gInstructions[1614] }; const ND_TABLE_VEX_W gEvexTable_root_06_57_03_w = @@ -13802,7 +13848,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_57_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_06_57_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1605] + (const void *)&gInstructions[1652] }; const ND_TABLE_VEX_W gEvexTable_root_06_57_02_w = @@ -13828,7 +13874,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_57_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_d6_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1568] + (const void *)&gInstructions[1615] }; const ND_TABLE_VEX_W gEvexTable_root_06_d6_03_w = @@ -13843,7 +13889,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_d6_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_06_d6_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1690] + (const void *)&gInstructions[1737] }; const ND_TABLE_VEX_W gEvexTable_root_06_d6_02_w = @@ -13869,7 +13915,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_d6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_d7_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1569] + (const void *)&gInstructions[1616] }; const ND_TABLE_VEX_W gEvexTable_root_06_d7_03_w = @@ -13884,7 +13930,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_d7_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_06_d7_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1691] + (const void *)&gInstructions[1738] }; const ND_TABLE_VEX_W gEvexTable_root_06_d7_02_w = @@ -13910,7 +13956,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_d7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_98_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1576] + (const void *)&gInstructions[1623] }; const ND_TABLE_VEX_W gEvexTable_root_06_98_01_w = @@ -13936,7 +13982,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_98_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_99_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1581] + (const void *)&gInstructions[1628] }; const ND_TABLE_VEX_W gEvexTable_root_06_99_01_w = @@ -13962,7 +14008,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_99_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_a8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1586] + (const void *)&gInstructions[1633] }; const ND_TABLE_VEX_W gEvexTable_root_06_a8_01_w = @@ -13988,7 +14034,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_a9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1591] + (const void *)&gInstructions[1638] }; const ND_TABLE_VEX_W gEvexTable_root_06_a9_01_w = @@ -14014,7 +14060,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_b8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1596] + (const void *)&gInstructions[1643] }; const ND_TABLE_VEX_W gEvexTable_root_06_b8_01_w = @@ -14040,7 +14086,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_b9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1601] + (const void *)&gInstructions[1648] }; const ND_TABLE_VEX_W gEvexTable_root_06_b9_01_w = @@ -14066,7 +14112,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_96_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1616] + (const void *)&gInstructions[1663] }; const ND_TABLE_VEX_W gEvexTable_root_06_96_01_w = @@ -14092,7 +14138,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_96_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_a6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1621] + (const void *)&gInstructions[1668] }; const ND_TABLE_VEX_W gEvexTable_root_06_a6_01_w = @@ -14118,7 +14164,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_b6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1626] + (const void *)&gInstructions[1673] }; const ND_TABLE_VEX_W gEvexTable_root_06_b6_01_w = @@ -14144,7 +14190,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_9a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1635] + (const void *)&gInstructions[1682] }; const ND_TABLE_VEX_W gEvexTable_root_06_9a_01_w = @@ -14170,7 +14216,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_9b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1640] + (const void *)&gInstructions[1687] }; const ND_TABLE_VEX_W gEvexTable_root_06_9b_01_w = @@ -14196,7 +14242,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_aa_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1645] + (const void *)&gInstructions[1692] }; const ND_TABLE_VEX_W gEvexTable_root_06_aa_01_w = @@ -14222,7 +14268,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_aa_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_ab_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1650] + (const void *)&gInstructions[1697] }; const ND_TABLE_VEX_W gEvexTable_root_06_ab_01_w = @@ -14248,7 +14294,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ab_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_ba_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1655] + (const void *)&gInstructions[1702] }; const ND_TABLE_VEX_W gEvexTable_root_06_ba_01_w = @@ -14274,7 +14320,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ba_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_bb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1660] + (const void *)&gInstructions[1707] }; const ND_TABLE_VEX_W gEvexTable_root_06_bb_01_w = @@ -14300,7 +14346,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_97_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1665] + (const void *)&gInstructions[1712] }; const ND_TABLE_VEX_W gEvexTable_root_06_97_01_w = @@ -14326,7 +14372,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_97_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_a7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1670] + (const void *)&gInstructions[1717] }; const ND_TABLE_VEX_W gEvexTable_root_06_a7_01_w = @@ -14352,7 +14398,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_b7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1675] + (const void *)&gInstructions[1722] }; const ND_TABLE_VEX_W gEvexTable_root_06_b7_01_w = @@ -14378,7 +14424,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_9c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1694] + (const void *)&gInstructions[1741] }; const ND_TABLE_VEX_W gEvexTable_root_06_9c_01_w = @@ -14404,7 +14450,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_9d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1699] + (const void *)&gInstructions[1746] }; const ND_TABLE_VEX_W gEvexTable_root_06_9d_01_w = @@ -14430,7 +14476,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_ac_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1704] + (const void *)&gInstructions[1751] }; const ND_TABLE_VEX_W gEvexTable_root_06_ac_01_w = @@ -14456,7 +14502,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ac_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_ad_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1709] + (const void *)&gInstructions[1756] }; const ND_TABLE_VEX_W gEvexTable_root_06_ad_01_w = @@ -14482,7 +14528,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ad_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_bc_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1714] + (const void *)&gInstructions[1761] }; const ND_TABLE_VEX_W gEvexTable_root_06_bc_01_w = @@ -14508,7 +14554,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_bd_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1719] + (const void *)&gInstructions[1766] }; const ND_TABLE_VEX_W gEvexTable_root_06_bd_01_w = @@ -14534,7 +14580,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_9e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1732] + (const void *)&gInstructions[1779] }; const ND_TABLE_VEX_W gEvexTable_root_06_9e_01_w = @@ -14560,7 +14606,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_9f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1737] + (const void *)&gInstructions[1784] }; const ND_TABLE_VEX_W gEvexTable_root_06_9f_01_w = @@ -14586,7 +14632,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_ae_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1742] + (const void *)&gInstructions[1789] }; const ND_TABLE_VEX_W gEvexTable_root_06_ae_01_w = @@ -14612,7 +14658,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ae_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_af_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1747] + (const void *)&gInstructions[1794] }; const ND_TABLE_VEX_W gEvexTable_root_06_af_01_w = @@ -14638,7 +14684,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_af_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_be_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1752] + (const void *)&gInstructions[1799] }; const ND_TABLE_VEX_W gEvexTable_root_06_be_01_w = @@ -14664,7 +14710,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_be_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_bf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1757] + (const void *)&gInstructions[1804] }; const ND_TABLE_VEX_W gEvexTable_root_06_bf_01_w = @@ -14690,7 +14736,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bf_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_42_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1795] + (const void *)&gInstructions[1842] }; const ND_TABLE_VEX_W gEvexTable_root_06_42_01_w = @@ -14716,7 +14762,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_42_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_43_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1798] + (const void *)&gInstructions[1845] }; const ND_TABLE_VEX_W gEvexTable_root_06_43_01_w = @@ -14742,7 +14788,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_43_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_4c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2535] + (const void *)&gInstructions[2594] }; const ND_TABLE_VEX_W gEvexTable_root_06_4c_01_w = @@ -14768,7 +14814,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_4d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2537] + (const void *)&gInstructions[2596] }; const ND_TABLE_VEX_W gEvexTable_root_06_4d_01_w = @@ -14794,7 +14840,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_4e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2563] + (const void *)&gInstructions[2622] }; const ND_TABLE_VEX_W gEvexTable_root_06_4e_01_w = @@ -14820,7 +14866,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_4f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2565] + (const void *)&gInstructions[2624] }; const ND_TABLE_VEX_W gEvexTable_root_06_4f_01_w = @@ -14846,7 +14892,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_2c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2568] + (const void *)&gInstructions[2627] }; const ND_TABLE_VEX_W gEvexTable_root_06_2c_01_w = @@ -14872,7 +14918,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_2c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_2d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2571] + (const void *)&gInstructions[2630] }; const ND_TABLE_VEX_W gEvexTable_root_06_2d_01_w = diff --git a/bddisasm/include/table_root.h b/bddisasm/include/table_root.h index f32c6a7..b0647d4 100644 --- a/bddisasm/include/table_root.h +++ b/bddisasm/include/table_root.h @@ -2,6 +2,11 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ + +// +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! +// + #ifndef TABLE_ROOT_H #define TABLE_ROOT_H @@ -17,328 +22,72 @@ const ND_TABLE_INSTRUCTION gRootTable_root_d5_leaf = (const void *)&gInstructions[1] }; -const ND_TABLE_INSTRUCTION gRootTable_root_d4_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fc_mem_NP_leaf = { ND_ILUT_INSTRUCTION, (const void *)&gInstructions[2] }; -const ND_TABLE_INSTRUCTION gRootTable_root_3f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[3] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_10_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fc_mem_66_leaf = { ND_ILUT_INSTRUCTION, (const void *)&gInstructions[4] }; -const ND_TABLE_INSTRUCTION gRootTable_root_11_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[5] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_12_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[6] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_13_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[7] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_14_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[8] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_15_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[9] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[10] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[21] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[53] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[152] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[800] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1203] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1303] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2675] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_80_00_leaf, - /* 01 */ (const void *)&gRootTable_root_80_01_leaf, - /* 02 */ (const void *)&gRootTable_root_80_02_leaf, - /* 03 */ (const void *)&gRootTable_root_80_03_leaf, - /* 04 */ (const void *)&gRootTable_root_80_04_leaf, - /* 05 */ (const void *)&gRootTable_root_80_05_leaf, - /* 06 */ (const void *)&gRootTable_root_80_06_leaf, - /* 07 */ (const void *)&gRootTable_root_80_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[11] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[22] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[54] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[153] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[801] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1204] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1304] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2676] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_81_00_leaf, - /* 01 */ (const void *)&gRootTable_root_81_01_leaf, - /* 02 */ (const void *)&gRootTable_root_81_02_leaf, - /* 03 */ (const void *)&gRootTable_root_81_03_leaf, - /* 04 */ (const void *)&gRootTable_root_81_04_leaf, - /* 05 */ (const void *)&gRootTable_root_81_05_leaf, - /* 06 */ (const void *)&gRootTable_root_81_06_leaf, - /* 07 */ (const void *)&gRootTable_root_81_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[12] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_00_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fc_mem_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[23] + (const void *)&gInstructions[64] }; -const ND_TABLE_INSTRUCTION gRootTable_root_82_04_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fc_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[55] + (const void *)&gInstructions[66] }; -const ND_TABLE_INSTRUCTION gRootTable_root_82_07_leaf = +const ND_TABLE_MPREFIX gRootTable_root_0f_38_fc_mem_mprefix = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[154] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[802] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1205] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1305] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2677] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg = -{ - ND_ILUT_MODRM_REG, + ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_82_00_leaf, - /* 01 */ (const void *)&gRootTable_root_82_01_leaf, - /* 02 */ (const void *)&gRootTable_root_82_02_leaf, - /* 03 */ (const void *)&gRootTable_root_82_03_leaf, - /* 04 */ (const void *)&gRootTable_root_82_04_leaf, - /* 05 */ (const void *)&gRootTable_root_82_05_leaf, - /* 06 */ (const void *)&gRootTable_root_82_06_leaf, - /* 07 */ (const void *)&gRootTable_root_82_07_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_38_fc_mem_NP_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_38_fc_mem_66_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_38_fc_mem_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_38_fc_mem_F2_leaf, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_83_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[13] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[24] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[56] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[155] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[803] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1206] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1306] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf = +const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_fc_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2678] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg = -{ - ND_ILUT_MODRM_REG, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gRootTable_root_83_00_leaf, - /* 01 */ (const void *)&gRootTable_root_83_01_leaf, - /* 02 */ (const void *)&gRootTable_root_83_02_leaf, - /* 03 */ (const void *)&gRootTable_root_83_03_leaf, - /* 04 */ (const void *)&gRootTable_root_83_04_leaf, - /* 05 */ (const void *)&gRootTable_root_83_05_leaf, - /* 06 */ (const void *)&gRootTable_root_83_06_leaf, - /* 07 */ (const void *)&gRootTable_root_83_07_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_38_fc_mem_mprefix, + /* 01 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[14] + (const void *)&gInstructions[16] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[31] + (const void *)&gInstructions[33] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2643] + (const void *)&gInstructions[2704] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2644] + (const void *)&gInstructions[2705] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary = @@ -351,6 +100,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -368,13 +119,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f6_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[14] + (const void *)&gInstructions[16] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[31] + (const void *)&gInstructions[33] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f6_reg_mprefix = @@ -400,13 +151,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f6_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_de_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[32] + (const void *)&gInstructions[34] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_de_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[40] + (const void *)&gInstructions[42] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_de_mem_mprefix = @@ -423,7 +174,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_de_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_de_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[32] + (const void *)&gInstructions[34] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_de_reg_mprefix = @@ -449,13 +200,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_de_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dd_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[33] + (const void *)&gInstructions[35] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dd_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[41] + (const void *)&gInstructions[43] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_dd_mem_mprefix = @@ -472,7 +223,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_dd_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dd_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[41] + (const void *)&gInstructions[43] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_dd_reg_mprefix = @@ -498,13 +249,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_dd_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_df_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[34] + (const void *)&gInstructions[36] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_df_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[35] + (const void *)&gInstructions[37] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_df_mem_mprefix = @@ -521,7 +272,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_df_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_df_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[35] + (const void *)&gInstructions[37] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_df_reg_mprefix = @@ -547,7 +298,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_df_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_d8_mem_01_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[36] + (const void *)&gInstructions[38] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_01_mprefix = @@ -564,7 +315,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_d8_mem_03_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[37] + (const void *)&gInstructions[39] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_03_mprefix = @@ -581,7 +332,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_d8_mem_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[42] + (const void *)&gInstructions[44] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_00_mprefix = @@ -598,7 +349,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_d8_mem_02_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[43] + (const void *)&gInstructions[45] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_02_mprefix = @@ -639,13 +390,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_d8_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[38] + (const void *)&gInstructions[40] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[39] + (const void *)&gInstructions[41] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_mem_mprefix = @@ -662,13 +413,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[38] + (const void *)&gInstructions[40] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[584] + (const void *)&gInstructions[604] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_reg_mprefix = @@ -694,7 +445,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_dc_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_db_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[44] + (const void *)&gInstructions[46] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_db_mprefix = @@ -711,7 +462,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_db_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_15_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[72] + (const void *)&gInstructions[76] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_15_mprefix = @@ -728,7 +479,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_15_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_14_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[73] + (const void *)&gInstructions[77] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_14_mprefix = @@ -745,13 +496,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_14_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_F2_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[178] + (const void *)&gInstructions[198] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_F2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[179] + (const void *)&gInstructions[199] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_F2_mprefix = @@ -768,13 +519,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_F2_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[658] + (const void *)&gInstructions[678] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[659] + (const void *)&gInstructions[679] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_mprefix = @@ -791,13 +542,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_reg_F2_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[178] + (const void *)&gInstructions[198] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_reg_F2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[179] + (const void *)&gInstructions[199] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_reg_F2_mprefix = @@ -834,13 +585,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f0_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_F2_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[180] + (const void *)&gInstructions[200] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_F2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[181] + (const void *)&gInstructions[201] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_F2_mprefix = @@ -857,13 +608,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_F2_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[660] + (const void *)&gInstructions[680] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[661] + (const void *)&gInstructions[681] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_mprefix = @@ -880,13 +631,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_reg_F2_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[180] + (const void *)&gInstructions[200] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_reg_F2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[181] + (const void *)&gInstructions[201] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_reg_F2_mprefix = @@ -923,7 +674,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f1_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fa_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[232] + (const void *)&gInstructions[252] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_fa_reg_mprefix = @@ -949,7 +700,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_fa_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fb_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[233] + (const void *)&gInstructions[253] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_fb_reg_mprefix = @@ -975,19 +726,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_fb_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[236] + (const void *)&gInstructions[256] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[237] + (const void *)&gInstructions[257] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[667] + (const void *)&gInstructions[687] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f8_mem_mprefix = @@ -1013,7 +764,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f8_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cf_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[399] + (const void *)&gInstructions[419] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix = @@ -1030,7 +781,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_80_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[444] + (const void *)&gInstructions[464] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_80_mem_mprefix = @@ -1056,7 +807,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_80_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_82_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[448] + (const void *)&gInstructions[468] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_82_mem_mprefix = @@ -1082,7 +833,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_82_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_81_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[449] + (const void *)&gInstructions[469] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_81_mem_mprefix = @@ -1108,7 +859,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_81_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f9_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[668] + (const void *)&gInstructions[688] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f9_mem_mprefix = @@ -1134,7 +885,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f9_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_2a_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[686] + (const void *)&gInstructions[706] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_2a_mem_mprefix = @@ -1160,13 +911,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_2a_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1c_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[816] + (const void *)&gInstructions[846] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1c_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[817] + (const void *)&gInstructions[847] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_1c_mprefix = @@ -1183,13 +934,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1e_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[818] + (const void *)&gInstructions[848] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1e_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[819] + (const void *)&gInstructions[849] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_1e_mprefix = @@ -1206,13 +957,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1d_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[820] + (const void *)&gInstructions[850] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1d_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[821] + (const void *)&gInstructions[851] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_1d_mprefix = @@ -1229,7 +980,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1d_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_2b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[826] + (const void *)&gInstructions[856] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_2b_mprefix = @@ -1246,7 +997,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_2b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_10_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[857] + (const void *)&gInstructions[887] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_10_mprefix = @@ -1263,7 +1014,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_10_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_29_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[864] + (const void *)&gInstructions[894] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix = @@ -1280,7 +1031,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_37_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[873] + (const void *)&gInstructions[903] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix = @@ -1297,13 +1048,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[910] + (const void *)&gInstructions[942] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[911] + (const void *)&gInstructions[943] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix = @@ -1320,13 +1071,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[912] + (const void *)&gInstructions[944] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[913] + (const void *)&gInstructions[945] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix = @@ -1343,13 +1094,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[914] + (const void *)&gInstructions[946] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[915] + (const void *)&gInstructions[947] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix = @@ -1366,7 +1117,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_41_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[916] + (const void *)&gInstructions[948] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix = @@ -1383,13 +1134,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[917] + (const void *)&gInstructions[949] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[918] + (const void *)&gInstructions[950] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix = @@ -1406,13 +1157,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[919] + (const void *)&gInstructions[951] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[920] + (const void *)&gInstructions[952] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix = @@ -1429,13 +1180,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[921] + (const void *)&gInstructions[953] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[922] + (const void *)&gInstructions[954] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix = @@ -1452,13 +1203,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[933] + (const void *)&gInstructions[965] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[934] + (const void *)&gInstructions[966] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix = @@ -1475,7 +1226,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3c_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[937] + (const void *)&gInstructions[969] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix = @@ -1492,7 +1243,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3d_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[938] + (const void *)&gInstructions[970] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix = @@ -1509,7 +1260,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3f_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[943] + (const void *)&gInstructions[975] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix = @@ -1526,7 +1277,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3e_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[944] + (const void *)&gInstructions[976] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix = @@ -1543,7 +1294,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_38_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[945] + (const void *)&gInstructions[977] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix = @@ -1560,7 +1311,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_39_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[946] + (const void *)&gInstructions[978] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix = @@ -1577,7 +1328,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[951] + (const void *)&gInstructions[983] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix = @@ -1594,7 +1345,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[952] + (const void *)&gInstructions[984] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix = @@ -1611,7 +1362,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_21_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[955] + (const void *)&gInstructions[987] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix = @@ -1628,7 +1379,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_22_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[956] + (const void *)&gInstructions[988] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix = @@ -1645,7 +1396,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_20_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[957] + (const void *)&gInstructions[989] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix = @@ -1662,7 +1413,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_25_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[958] + (const void *)&gInstructions[990] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix = @@ -1679,7 +1430,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_23_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[959] + (const void *)&gInstructions[991] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix = @@ -1696,7 +1447,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_24_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[960] + (const void *)&gInstructions[992] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix = @@ -1713,7 +1464,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_31_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[961] + (const void *)&gInstructions[993] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix = @@ -1730,7 +1481,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_32_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[962] + (const void *)&gInstructions[994] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix = @@ -1747,7 +1498,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_30_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[963] + (const void *)&gInstructions[995] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix = @@ -1764,7 +1515,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_35_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[964] + (const void *)&gInstructions[996] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix = @@ -1781,7 +1532,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_33_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[965] + (const void *)&gInstructions[997] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix = @@ -1798,7 +1549,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_34_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[966] + (const void *)&gInstructions[998] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix = @@ -1815,7 +1566,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_28_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[967] + (const void *)&gInstructions[999] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix = @@ -1832,13 +1583,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[968] + (const void *)&gInstructions[1000] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[969] + (const void *)&gInstructions[1001] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix = @@ -1855,7 +1606,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_40_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[975] + (const void *)&gInstructions[1007] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix = @@ -1872,13 +1623,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1016] + (const void *)&gInstructions[1054] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1017] + (const void *)&gInstructions[1055] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix = @@ -1895,13 +1646,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1022] + (const void *)&gInstructions[1060] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1023] + (const void *)&gInstructions[1061] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix = @@ -1918,13 +1669,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1024] + (const void *)&gInstructions[1062] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1025] + (const void *)&gInstructions[1063] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix = @@ -1941,13 +1692,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1026] + (const void *)&gInstructions[1064] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1027] + (const void *)&gInstructions[1065] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix = @@ -1964,7 +1715,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_17_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1080] + (const void *)&gInstructions[1118] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix = @@ -1981,7 +1732,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c9_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1239] + (const void *)&gInstructions[1278] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix = @@ -1998,7 +1749,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_ca_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1240] + (const void *)&gInstructions[1279] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix = @@ -2015,7 +1766,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c8_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1241] + (const void *)&gInstructions[1280] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix = @@ -2032,7 +1783,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cc_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1243] + (const void *)&gInstructions[1282] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix = @@ -2049,7 +1800,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cd_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1244] + (const void *)&gInstructions[1283] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix = @@ -2066,7 +1817,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cb_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1245] + (const void *)&gInstructions[1284] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix = @@ -2083,13 +1834,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2645] + (const void *)&gInstructions[2706] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2646] + (const void *)&gInstructions[2707] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary = @@ -2102,6 +1853,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -2381,7 +2134,7 @@ const ND_TABLE_OPCODE gRootTable_root_0f_38_opcode = /* f9 */ (const void *)&gRootTable_root_0f_38_f9_modrmmod, /* fa */ (const void *)&gRootTable_root_0f_38_fa_modrmmod, /* fb */ (const void *)&gRootTable_root_0f_38_fb_modrmmod, - /* fc */ ND_NULL, + /* fc */ (const void *)&gRootTable_root_0f_38_fc_modrmmod, /* fd */ ND_NULL, /* fe */ ND_NULL, /* ff */ ND_NULL, @@ -2391,25 +2144,25 @@ const ND_TABLE_OPCODE gRootTable_root_0f_38_opcode = const ND_TABLE_INSTRUCTION gRootTable_root_0f_58_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[25] + (const void *)&gInstructions[27] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_58_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[26] + (const void *)&gInstructions[28] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_58_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[27] + (const void *)&gInstructions[29] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_58_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[28] + (const void *)&gInstructions[30] }; const ND_TABLE_MPREFIX gRootTable_root_0f_58_mprefix = @@ -2426,13 +2179,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_58_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d0_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[29] + (const void *)&gInstructions[31] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d0_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[30] + (const void *)&gInstructions[32] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d0_mprefix = @@ -2449,7 +2202,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d0_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_df_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[45] + (const void *)&gInstructions[47] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_df_mprefix = @@ -2466,7 +2219,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_df_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0d_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[70] + (const void *)&gInstructions[74] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0d_mprefix = @@ -2483,7 +2236,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0d_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0c_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[71] + (const void *)&gInstructions[75] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0c_mprefix = @@ -2500,7 +2253,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_41_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[226] + (const void *)&gInstructions[246] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_41_mprefix = @@ -2517,7 +2270,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_41_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_40_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[227] + (const void *)&gInstructions[247] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_40_mprefix = @@ -2534,7 +2287,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_40_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_17_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[241] + (const void *)&gInstructions[261] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_17_mprefix = @@ -2551,7 +2304,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_17_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cf_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[397] + (const void *)&gInstructions[417] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix = @@ -2568,7 +2321,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_ce_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[398] + (const void *)&gInstructions[418] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix = @@ -2585,7 +2338,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_f0_reg_00_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[403] + (const void *)&gInstructions[423] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_f0_reg_00_00_mprefix = @@ -2641,7 +2394,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_f0_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[433] + (const void *)&gInstructions[453] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix = @@ -2658,7 +2411,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[434] + (const void *)&gInstructions[454] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_reg_mprefix = @@ -2684,7 +2437,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_21_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_42_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[725] + (const void *)&gInstructions[745] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_42_mprefix = @@ -2701,13 +2454,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_42_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0f_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[845] + (const void *)&gInstructions[875] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0f_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[846] + (const void *)&gInstructions[876] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0f_mprefix = @@ -2724,7 +2477,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0f_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0e_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[858] + (const void *)&gInstructions[888] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0e_mprefix = @@ -2741,7 +2494,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_44_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[859] + (const void *)&gInstructions[889] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix = @@ -2758,7 +2511,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_61_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[867] + (const void *)&gInstructions[897] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix = @@ -2775,7 +2528,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_60_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[868] + (const void *)&gInstructions[898] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix = @@ -2792,7 +2545,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_63_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[876] + (const void *)&gInstructions[906] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix = @@ -2809,7 +2562,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_62_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[877] + (const void *)&gInstructions[907] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix = @@ -2826,7 +2579,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[881] + (const void *)&gInstructions[911] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix = @@ -2843,7 +2596,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[882] + (const void *)&gInstructions[912] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_reg_mprefix = @@ -2866,46 +2619,95 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_14_modrmmod = } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_66_None_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_mem_66_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[883] + (const void *)&gInstructions[913] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_66_rexw_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_mem_66_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[884] + (const void *)&gInstructions[915] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_16_mem_66_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_3a_16_mem_66_None_leaf, + /* 01 */ ND_NULL, + /* 02 */ (const void *)&gRootTable_root_0f_3a_16_mem_66_rexw_leaf, + /* 03 */ ND_NULL, + /* 04 */ ND_NULL, + /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_16_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_16_mem_66_auxiliary, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_reg_66_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[914] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_reg_66_rexw_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[916] }; -const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_16_66_auxiliary = +const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_16_reg_66_auxiliary = { ND_ILUT_AUXILIARY, { - /* 00 */ (const void *)&gRootTable_root_0f_3a_16_66_None_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_3a_16_reg_66_None_leaf, /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_3a_16_66_rexw_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_3a_16_reg_66_rexw_leaf, /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_16_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_16_reg_mprefix = { ND_ILUT_MAN_PREFIX, { /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_16_66_auxiliary, + /* 01 */ (const void *)&gRootTable_root_0f_3a_16_reg_66_auxiliary, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; +const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_16_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_3a_16_mem_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_3a_16_reg_mprefix, + } +}; + const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[887] + (const void *)&gInstructions[919] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix = @@ -2922,7 +2724,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[888] + (const void *)&gInstructions[920] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_reg_mprefix = @@ -2948,7 +2750,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_15_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[925] + (const void *)&gInstructions[957] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix = @@ -2965,7 +2767,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[926] + (const void *)&gInstructions[958] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_reg_mprefix = @@ -2991,13 +2793,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_20_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[927] + (const void *)&gInstructions[959] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[928] + (const void *)&gInstructions[960] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_22_66_auxiliary = @@ -3010,6 +2812,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_22_66_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -3027,7 +2831,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_22_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_09_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1170] + (const void *)&gInstructions[1209] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix = @@ -3044,7 +2848,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_08_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1171] + (const void *)&gInstructions[1210] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix = @@ -3061,7 +2865,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1172] + (const void *)&gInstructions[1211] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix = @@ -3078,7 +2882,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1173] + (const void *)&gInstructions[1212] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix = @@ -3095,7 +2899,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cc_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1242] + (const void *)&gInstructions[1281] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cc_mprefix = @@ -3135,7 +2939,7 @@ const ND_TABLE_OPCODE gRootTable_root_0f_3a_opcode = /* 13 */ ND_NULL, /* 14 */ (const void *)&gRootTable_root_0f_3a_14_modrmmod, /* 15 */ (const void *)&gRootTable_root_0f_3a_15_modrmmod, - /* 16 */ (const void *)&gRootTable_root_0f_3a_16_mprefix, + /* 16 */ (const void *)&gRootTable_root_0f_3a_16_modrmmod, /* 17 */ (const void *)&gRootTable_root_0f_3a_17_mprefix, /* 18 */ ND_NULL, /* 19 */ ND_NULL, @@ -3375,19 +3179,19 @@ const ND_TABLE_OPCODE gRootTable_root_0f_3a_opcode = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[46] + (const void *)&gInstructions[48] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_55_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[58] + (const void *)&gInstructions[60] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_55_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[59] + (const void *)&gInstructions[61] }; const ND_TABLE_MPREFIX gRootTable_root_0f_55_mprefix = @@ -3404,13 +3208,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_55_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_54_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[60] + (const void *)&gInstructions[62] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_54_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[61] + (const void *)&gInstructions[63] }; const ND_TABLE_MPREFIX gRootTable_root_0f_54_mprefix = @@ -3427,25 +3231,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_54_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[79] + (const void *)&gInstructions[83] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_mem_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[81] + (const void *)&gInstructions[85] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_mem_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[82] + (const void *)&gInstructions[86] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[84] + (const void *)&gInstructions[88] }; const ND_TABLE_MPREFIX gRootTable_root_0f_1a_mpx_mem_mprefix = @@ -3462,25 +3266,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_1a_mpx_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[79] + (const void *)&gInstructions[83] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[81] + (const void *)&gInstructions[85] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[84] + (const void *)&gInstructions[88] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[760] + (const void *)&gInstructions[790] }; const ND_TABLE_MPREFIX gRootTable_root_0f_1a_mpx_reg_mprefix = @@ -3506,7 +3310,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1a_mpx_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[754] + (const void *)&gInstructions[784] }; const ND_TABLE_FEATURE gRootTable_root_0f_1a_feature = @@ -3517,31 +3321,35 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1a_feature = /* 01 */ (const void *)&gRootTable_root_0f_1a_mpx_modrmmod, /* 02 */ ND_NULL, /* 03 */ ND_NULL, + /* 04 */ ND_NULL, + /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_mem_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[80] + (const void *)&gInstructions[84] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[83] + (const void *)&gInstructions[87] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[85] + (const void *)&gInstructions[89] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_mem_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[86] + (const void *)&gInstructions[90] }; const ND_TABLE_MPREFIX gRootTable_root_0f_1b_mpx_mem_mprefix = @@ -3558,25 +3366,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_1b_mpx_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[80] + (const void *)&gInstructions[84] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[85] + (const void *)&gInstructions[89] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[761] + (const void *)&gInstructions[791] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[762] + (const void *)&gInstructions[792] }; const ND_TABLE_MPREFIX gRootTable_root_0f_1b_mpx_reg_mprefix = @@ -3602,7 +3410,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1b_mpx_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[755] + (const void *)&gInstructions[785] }; const ND_TABLE_FEATURE gRootTable_root_0f_1b_feature = @@ -3613,19 +3421,23 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1b_feature = /* 01 */ (const void *)&gRootTable_root_0f_1b_mpx_modrmmod, /* 02 */ ND_NULL, /* 03 */ ND_NULL, + /* 04 */ ND_NULL, + /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[88] + (const void *)&gInstructions[92] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1342] + (const void *)&gInstructions[1382] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary = @@ -3638,19 +3450,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary = /* 03 */ ND_NULL, /* 04 */ (const void *)&gRootTable_root_0f_bc_aF3_leaf, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_bd_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[89] + (const void *)&gInstructions[93] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_bd_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[602] + (const void *)&gInstructions[622] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_bd_auxiliary = @@ -3663,85 +3477,87 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_bd_auxiliary = /* 03 */ ND_NULL, /* 04 */ (const void *)&gRootTable_root_0f_bd_aF3_leaf, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[90] + (const void *)&gInstructions[94] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[91] + (const void *)&gInstructions[95] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ca_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[92] + (const void *)&gInstructions[96] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_cb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[93] + (const void *)&gInstructions[97] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_cc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[94] + (const void *)&gInstructions[98] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_cd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[95] + (const void *)&gInstructions[99] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ce_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[96] + (const void *)&gInstructions[100] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_cf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[97] + (const void *)&gInstructions[101] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[98] + (const void *)&gInstructions[102] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[99] + (const void *)&gInstructions[103] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[100] + (const void *)&gInstructions[104] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[103] + (const void *)&gInstructions[107] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[105] + (const void *)&gInstructions[109] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_ba_modrmreg = @@ -3762,37 +3578,37 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_ba_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_bb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[101] + (const void *)&gInstructions[105] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_b3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[102] + (const void *)&gInstructions[106] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ab_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[104] + (const void *)&gInstructions[108] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[114] + (const void *)&gInstructions[118] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_02_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[239] + (const void *)&gInstructions[259] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_02_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[240] + (const void *)&gInstructions[260] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_02_mprefix = @@ -3809,13 +3625,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[229] + (const void *)&gInstructions[249] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1215] + (const void *)&gInstructions[1254] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix = @@ -3832,7 +3648,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[615] + (const void *)&gInstructions[635] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_00_mprefix = @@ -3849,7 +3665,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_01_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[733] + (const void *)&gInstructions[753] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix = @@ -3866,7 +3682,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1216] + (const void *)&gInstructions[1255] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix = @@ -3883,7 +3699,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_05_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1217] + (const void *)&gInstructions[1256] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix = @@ -3900,7 +3716,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_03_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1279] + (const void *)&gInstructions[1318] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix = @@ -3917,7 +3733,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_04_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1320] + (const void *)&gInstructions[1359] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_04_mprefix = @@ -3949,49 +3765,49 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_01_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[122] + (const void *)&gInstructions[126] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[446] + (const void *)&gInstructions[466] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1267] + (const void *)&gInstructions[1306] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1282] + (const void *)&gInstructions[1321] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1850] + (const void *)&gInstructions[1897] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1851] + (const void *)&gInstructions[1898] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1864] + (const void *)&gInstructions[1911] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1865] + (const void *)&gInstructions[1912] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix = @@ -4008,19 +3824,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1863] + (const void *)&gInstructions[1910] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1978] + (const void *)&gInstructions[2025] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1979] + (const void *)&gInstructions[2026] }; const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm = @@ -4041,13 +3857,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[126] + (const void *)&gInstructions[130] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1139] + (const void *)&gInstructions[1178] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix = @@ -4064,7 +3880,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_02_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1196] + (const void *)&gInstructions[1235] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix = @@ -4081,19 +3897,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1219] + (const void *)&gInstructions[1258] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1235] + (const void *)&gInstructions[1274] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2699] + (const void *)&gInstructions[2760] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix = @@ -4110,13 +3926,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1296] + (const void *)&gInstructions[1335] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2641] + (const void *)&gInstructions[2702] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix = @@ -4133,7 +3949,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_05_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1334] + (const void *)&gInstructions[1374] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix = @@ -4150,7 +3966,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_04_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1349] + (const void *)&gInstructions[1389] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix = @@ -4167,7 +3983,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2681] + (const void *)&gInstructions[2742] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix = @@ -4199,25 +4015,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_05_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[128] + (const void *)&gInstructions[132] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[447] + (const void *)&gInstructions[467] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1155] + (const void *)&gInstructions[1194] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1156] + (const void *)&gInstructions[1195] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix = @@ -4234,13 +4050,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[609] + (const void *)&gInstructions[629] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[616] + (const void *)&gInstructions[636] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_02_mprefix = @@ -4257,7 +4073,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_03_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[734] + (const void *)&gInstructions[754] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix = @@ -4274,19 +4090,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1041] + (const void *)&gInstructions[1079] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1118] + (const void *)&gInstructions[1156] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1340] + (const void *)&gInstructions[1380] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix = @@ -4303,19 +4119,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1141] + (const void *)&gInstructions[1180] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1150] + (const void *)&gInstructions[1189] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1314] + (const void *)&gInstructions[1353] }; const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm = @@ -4336,7 +4152,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[230] + (const void *)&gInstructions[250] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix = @@ -4353,7 +4169,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1849] + (const void *)&gInstructions[1896] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix = @@ -4370,7 +4186,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2666] + (const void *)&gInstructions[2727] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix = @@ -4387,7 +4203,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2667] + (const void *)&gInstructions[2728] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix = @@ -4404,7 +4220,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2694] + (const void *)&gInstructions[2755] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix = @@ -4421,7 +4237,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2700] + (const void *)&gInstructions[2761] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix = @@ -4453,7 +4269,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_02_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[231] + (const void *)&gInstructions[251] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_00_mprefix = @@ -4470,7 +4286,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_05_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[878] + (const void *)&gInstructions[908] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix = @@ -4484,10 +4300,39 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix = } }; +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1176] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2700] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_NP_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2701] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_06_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_06_NP_leaf, + /* 01 */ ND_NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_00_06_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_00_06_F2_leaf, + } +}; + const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1847] + (const void *)&gInstructions[1894] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix = @@ -4504,7 +4349,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1862] + (const void *)&gInstructions[1909] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix = @@ -4521,7 +4366,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1977] + (const void *)&gInstructions[2024] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix = @@ -4538,7 +4383,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1991] + (const void *)&gInstructions[2038] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_04_mprefix = @@ -4562,7 +4407,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm = /* 03 */ (const void *)&gRootTable_root_0f_01_reg_00_03_mprefix, /* 04 */ (const void *)&gRootTable_root_0f_01_reg_00_04_mprefix, /* 05 */ (const void *)&gRootTable_root_0f_01_reg_00_05_mprefix, - /* 06 */ ND_NULL, + /* 06 */ (const void *)&gRootTable_root_0f_01_reg_00_06_mprefix, /* 07 */ ND_NULL, } }; @@ -4570,13 +4415,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[583] + (const void *)&gInstructions[603] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1273] + (const void *)&gInstructions[1312] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg = @@ -4597,31 +4442,31 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[445] + (const void *)&gInstructions[465] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[576] + (const void *)&gInstructions[596] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[578] + (const void *)&gInstructions[598] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[583] + (const void *)&gInstructions[603] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_05_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1179] + (const void *)&gInstructions[1218] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix = @@ -4638,19 +4483,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1238] + (const void *)&gInstructions[1277] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1266] + (const void *)&gInstructions[1305] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1272] + (const void *)&gInstructions[1311] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_01_mem_modrmreg = @@ -4680,25 +4525,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_01_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[117] + (const void *)&gInstructions[121] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[763] + (const void *)&gInstructions[793] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[764] + (const void *)&gInstructions[794] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[765] + (const void *)&gInstructions[795] }; const ND_TABLE_MPREFIX gRootTable_root_0f_1c_cldm_mem_00_mprefix = @@ -4715,43 +4560,43 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_1c_cldm_mem_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[767] + (const void *)&gInstructions[797] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[768] + (const void *)&gInstructions[798] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[769] + (const void *)&gInstructions[799] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[770] + (const void *)&gInstructions[800] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[771] + (const void *)&gInstructions[801] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[772] + (const void *)&gInstructions[802] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[773] + (const void *)&gInstructions[803] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_mem_modrmreg = @@ -4772,49 +4617,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[766] + (const void *)&gInstructions[796] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[767] + (const void *)&gInstructions[797] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[768] + (const void *)&gInstructions[798] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[769] + (const void *)&gInstructions[799] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[770] + (const void *)&gInstructions[800] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[771] + (const void *)&gInstructions[801] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[772] + (const void *)&gInstructions[802] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[773] + (const void *)&gInstructions[803] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_reg_modrmreg = @@ -4844,7 +4689,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1c_cldm_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[756] + (const void *)&gInstructions[786] }; const ND_TABLE_FEATURE gRootTable_root_0f_1c_feature = @@ -4855,19 +4700,23 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1c_feature = /* 01 */ ND_NULL, /* 02 */ ND_NULL, /* 03 */ (const void *)&gRootTable_root_0f_1c_cldm_modrmmod, + /* 04 */ ND_NULL, + /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[120] + (const void *)&gInstructions[124] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_07_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[121] + (const void *)&gInstructions[125] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_07_mprefix = @@ -4884,25 +4733,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[124] + (const void *)&gInstructions[128] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[127] + (const void *)&gInstructions[131] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2690] + (const void *)&gInstructions[2751] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2691] + (const void *)&gInstructions[2752] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary = @@ -4915,6 +4764,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -4932,13 +4783,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[389] + (const void *)&gInstructions[409] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[390] + (const void *)&gInstructions[410] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_01_NP_auxiliary = @@ -4951,6 +4802,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_01_NP_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -4968,13 +4821,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[391] + (const void *)&gInstructions[411] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[392] + (const void *)&gInstructions[412] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_00_NP_auxiliary = @@ -4987,6 +4840,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_00_NP_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -5004,7 +4859,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[568] + (const void *)&gInstructions[588] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix = @@ -5021,19 +4876,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1081] + (const void *)&gInstructions[1119] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2686] + (const void *)&gInstructions[2747] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2687] + (const void *)&gInstructions[2748] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary = @@ -5046,6 +4901,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -5063,7 +4920,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_03_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1284] + (const void *)&gInstructions[1323] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix = @@ -5080,13 +4937,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2682] + (const void *)&gInstructions[2743] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2683] + (const void *)&gInstructions[2744] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary = @@ -5099,6 +4956,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -5131,13 +4990,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_ae_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[427] + (const void *)&gInstructions[447] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[428] + (const void *)&gInstructions[448] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary = @@ -5150,13 +5009,15 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[574] + (const void *)&gInstructions[594] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_05_mprefix = @@ -5173,25 +5034,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[610] + (const void *)&gInstructions[630] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1341] + (const void *)&gInstructions[1381] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1350] + (const void *)&gInstructions[1390] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1351] + (const void *)&gInstructions[1391] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix = @@ -5208,7 +5069,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_04_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1081] + (const void *)&gInstructions[1119] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix = @@ -5225,7 +5086,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_00_F3_64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1135] + (const void *)&gInstructions[1173] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_00_F3_auxiliary = @@ -5238,6 +5099,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_00_F3_auxiliary = /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_00_F3_64_leaf, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -5255,7 +5118,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_01_F3_64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1136] + (const void *)&gInstructions[1174] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_01_F3_auxiliary = @@ -5268,6 +5131,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_01_F3_auxiliary = /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_01_F3_64_leaf, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -5285,7 +5150,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1237] + (const void *)&gInstructions[1276] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix = @@ -5302,7 +5167,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_02_F3_64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2638] + (const void *)&gInstructions[2697] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary = @@ -5315,6 +5180,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary = /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_02_F3_64_leaf, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -5332,7 +5199,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_03_F3_64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2639] + (const void *)&gInstructions[2698] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary = @@ -5345,6 +5212,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary = /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_03_F3_64_leaf, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -5386,127 +5255,127 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_ae_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[125] + (const void *)&gInstructions[129] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_46_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[130] + (const void *)&gInstructions[134] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_42_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[131] + (const void *)&gInstructions[135] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_4c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[132] + (const void *)&gInstructions[136] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_4e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[133] + (const void *)&gInstructions[137] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_47_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[134] + (const void *)&gInstructions[138] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_43_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[135] + (const void *)&gInstructions[139] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_4d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[136] + (const void *)&gInstructions[140] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_4f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[137] + (const void *)&gInstructions[141] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_41_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[138] + (const void *)&gInstructions[142] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_4b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[139] + (const void *)&gInstructions[143] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_49_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[140] + (const void *)&gInstructions[144] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_45_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[141] + (const void *)&gInstructions[145] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_40_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[142] + (const void *)&gInstructions[146] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_4a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[143] + (const void *)&gInstructions[147] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_48_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[144] + (const void *)&gInstructions[148] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_44_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[145] + (const void *)&gInstructions[149] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[156] + (const void *)&gInstructions[173] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[157] + (const void *)&gInstructions[174] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[160] + (const void *)&gInstructions[178] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[165] + (const void *)&gInstructions[183] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c2_mprefix = @@ -5523,25 +5392,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c2_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_b0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[168] + (const void *)&gInstructions[187] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_b1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[169] + (const void *)&gInstructions[188] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_01_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[170] + (const void *)&gInstructions[189] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_01_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[171] + (const void *)&gInstructions[190] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary = @@ -5554,25 +5423,27 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1848] + (const void *)&gInstructions[1895] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1974] + (const void *)&gInstructions[2021] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1992] + (const void *)&gInstructions[2039] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix = @@ -5589,7 +5460,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1975] + (const void *)&gInstructions[2022] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix = @@ -5606,13 +5477,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2684] + (const void *)&gInstructions[2745] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2685] + (const void *)&gInstructions[2746] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary = @@ -5625,6 +5496,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -5642,13 +5515,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2688] + (const void *)&gInstructions[2749] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2689] + (const void *)&gInstructions[2750] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary = @@ -5661,6 +5534,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -5678,13 +5553,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2692] + (const void *)&gInstructions[2753] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2693] + (const void *)&gInstructions[2754] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary = @@ -5697,6 +5572,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -5729,19 +5606,19 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_c7_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1138] + (const void *)&gInstructions[1177] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1144] + (const void *)&gInstructions[1183] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1145] + (const void *)&gInstructions[1184] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix = @@ -5758,19 +5635,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1142] + (const void *)&gInstructions[1181] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1143] + (const void *)&gInstructions[1182] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1218] + (const void *)&gInstructions[1257] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_06_mprefix = @@ -5811,13 +5688,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_2f_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[172] + (const void *)&gInstructions[192] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2f_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[173] + (const void *)&gInstructions[193] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2f_mprefix = @@ -5834,37 +5711,37 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2f_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[174] + (const void *)&gInstructions[194] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_3d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[175] + (const void *)&gInstructions[195] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_3c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[176] + (const void *)&gInstructions[196] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[182] + (const void *)&gInstructions[202] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[184] + (const void *)&gInstructions[204] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[198] + (const void *)&gInstructions[218] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e6_mprefix = @@ -5881,19 +5758,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e6_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[183] + (const void *)&gInstructions[203] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[189] + (const void *)&gInstructions[209] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[200] + (const void *)&gInstructions[220] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5b_mprefix = @@ -5910,25 +5787,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[185] + (const void *)&gInstructions[205] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[191] + (const void *)&gInstructions[211] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[192] + (const void *)&gInstructions[212] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[197] + (const void *)&gInstructions[217] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2d_mprefix = @@ -5945,25 +5822,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2d_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[186] + (const void *)&gInstructions[206] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[190] + (const void *)&gInstructions[210] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[193] + (const void *)&gInstructions[213] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[196] + (const void *)&gInstructions[216] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5a_mprefix = @@ -5980,25 +5857,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[187] + (const void *)&gInstructions[207] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[188] + (const void *)&gInstructions[208] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[194] + (const void *)&gInstructions[214] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[195] + (const void *)&gInstructions[215] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2a_mprefix = @@ -6015,25 +5892,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[199] + (const void *)&gInstructions[219] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[201] + (const void *)&gInstructions[221] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[202] + (const void *)&gInstructions[222] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[203] + (const void *)&gInstructions[223] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2c_mprefix = @@ -6050,25 +5927,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[221] + (const void *)&gInstructions[241] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[222] + (const void *)&gInstructions[242] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[223] + (const void *)&gInstructions[243] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[224] + (const void *)&gInstructions[244] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5e_mprefix = @@ -6085,13 +5962,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_39_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[225] + (const void *)&gInstructions[245] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_77_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[228] + (const void *)&gInstructions[248] }; const ND_TABLE_MPREFIX gRootTable_root_0f_77_mprefix = @@ -6108,13 +5985,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_77_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_03_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[234] + (const void *)&gInstructions[254] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_03_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[786] + (const void *)&gInstructions[816] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_03_auxiliary = @@ -6127,19 +6004,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_03_auxiliary = /* 03 */ ND_NULL, /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_03_aF3_leaf, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_02_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[235] + (const void *)&gInstructions[255] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_02_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[785] + (const void *)&gInstructions[815] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_02_auxiliary = @@ -6152,43 +6031,45 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_02_auxiliary = /* 03 */ ND_NULL, /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_02_aF3_leaf, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[783] + (const void *)&gInstructions[813] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[784] + (const void *)&gInstructions[814] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[787] + (const void *)&gInstructions[817] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[788] + (const void *)&gInstructions[818] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[789] + (const void *)&gInstructions[819] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[790] + (const void *)&gInstructions[820] }; const ND_TABLE_MODRM_RM gRootTable_root_0f_1e_cet_reg_07_modrmrm = @@ -6209,25 +6090,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_1e_cet_reg_07_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[775] + (const void *)&gInstructions[805] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[776] + (const void *)&gInstructions[806] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_rexw_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[777] + (const void *)&gInstructions[807] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_rexw_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1148] + (const void *)&gInstructions[1187] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary = @@ -6240,13 +6121,15 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary = /* 03 */ ND_NULL, /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_rexw_aF3_leaf, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1147] + (const void *)&gInstructions[1186] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_auxiliary = @@ -6259,37 +6142,39 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_auxiliary = /* 03 */ ND_NULL, /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_aF3_leaf, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[778] + (const void *)&gInstructions[808] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[779] + (const void *)&gInstructions[809] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[780] + (const void *)&gInstructions[810] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[781] + (const void *)&gInstructions[811] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[782] + (const void *)&gInstructions[812] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_1e_cet_reg_modrmreg = @@ -6310,7 +6195,7 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_1e_cet_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[774] + (const void *)&gInstructions[804] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_1e_cet_modrmmod = @@ -6325,7 +6210,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1e_cet_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[758] + (const void *)&gInstructions[788] }; const ND_TABLE_FEATURE gRootTable_root_0f_1e_feature = @@ -6336,13 +6221,17 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1e_feature = /* 01 */ ND_NULL, /* 02 */ (const void *)&gRootTable_root_0f_1e_cet_modrmmod, /* 03 */ ND_NULL, + /* 04 */ ND_NULL, + /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_66_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[242] + (const void *)&gInstructions[262] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_78_None_66_modrmreg = @@ -6363,13 +6252,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_78_None_66_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[435] + (const void *)&gInstructions[455] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1976] + (const void *)&gInstructions[2023] }; const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix = @@ -6386,7 +6275,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1311] + (const void *)&gInstructions[1350] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_78_cyrix_modrmmod = @@ -6414,19 +6303,19 @@ const ND_TABLE_VENDOR gRootTable_root_0f_78_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[243] + (const void *)&gInstructions[263] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[436] + (const void *)&gInstructions[456] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1990] + (const void *)&gInstructions[2037] }; const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix = @@ -6443,7 +6332,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1990] + (const void *)&gInstructions[2037] }; const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_mem_mprefix = @@ -6469,7 +6358,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_None_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1174] + (const void *)&gInstructions[1213] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_cyrix_modrmmod = @@ -6497,13 +6386,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_79_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[286] + (const void *)&gInstructions[306] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_None_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[396] + (const void *)&gInstructions[416] }; const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix = @@ -6520,7 +6409,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_cyrix_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2642] + (const void *)&gInstructions[2703] }; const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor = @@ -6539,13 +6428,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[400] + (const void *)&gInstructions[420] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[401] + (const void *)&gInstructions[421] }; const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix = @@ -6562,7 +6451,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1313] + (const void *)&gInstructions[1352] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_7c_cyrix_modrmmod = @@ -6590,13 +6479,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7c_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[404] + (const void *)&gInstructions[424] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[405] + (const void *)&gInstructions[425] }; const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix = @@ -6613,7 +6502,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1180] + (const void *)&gInstructions[1219] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_7d_cyrix_modrmmod = @@ -6641,49 +6530,49 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7d_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_af_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[408] + (const void *)&gInstructions[428] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[443] + (const void *)&gInstructions[463] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[453] + (const void *)&gInstructions[473] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_82_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[455] + (const void *)&gInstructions[475] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_8c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[459] + (const void *)&gInstructions[479] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_8e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[461] + (const void *)&gInstructions[481] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[466] + (const void *)&gInstructions[486] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_06_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[579] + (const void *)&gInstructions[599] }; const ND_TABLE_MPREFIX gRootTable_root_0f_00_mem_06_mprefix = @@ -6700,37 +6589,37 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_00_mem_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[581] + (const void *)&gInstructions[601] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[599] + (const void *)&gInstructions[619] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1268] + (const void *)&gInstructions[1307] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1293] + (const void *)&gInstructions[1332] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1546] + (const void *)&gInstructions[1593] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1547] + (const void *)&gInstructions[1594] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg = @@ -6751,13 +6640,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[466] + (const void *)&gInstructions[486] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_06_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[580] + (const void *)&gInstructions[600] }; const ND_TABLE_MPREFIX gRootTable_root_0f_00_reg_06_mprefix = @@ -6774,37 +6663,37 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_00_reg_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[581] + (const void *)&gInstructions[601] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[599] + (const void *)&gInstructions[619] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1269] + (const void *)&gInstructions[1308] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1294] + (const void *)&gInstructions[1333] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1546] + (const void *)&gInstructions[1593] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1547] + (const void *)&gInstructions[1594] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg = @@ -6834,13 +6723,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_00_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[467] + (const void *)&gInstructions[487] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[996] + (const void *)&gInstructions[1028] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary = @@ -6853,91 +6742,93 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary = /* 03 */ ND_NULL, /* 04 */ (const void *)&gRootTable_root_0f_b8_aF3_leaf, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[470] + (const void *)&gInstructions[490] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_83_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[472] + (const void *)&gInstructions[492] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_8d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[474] + (const void *)&gInstructions[494] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_8f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[476] + (const void *)&gInstructions[496] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_81_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[478] + (const void *)&gInstructions[498] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_8b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[480] + (const void *)&gInstructions[500] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_89_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[482] + (const void *)&gInstructions[502] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[484] + (const void *)&gInstructions[504] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_80_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[486] + (const void *)&gInstructions[506] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_8a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[488] + (const void *)&gInstructions[508] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_88_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[491] + (const void *)&gInstructions[511] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_84_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[493] + (const void *)&gInstructions[513] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[565] + (const void *)&gInstructions[585] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[566] + (const void *)&gInstructions[586] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_02_modrmmod = @@ -6952,7 +6843,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_02_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f0_mem_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[567] + (const void *)&gInstructions[587] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f0_mem_mprefix = @@ -6978,7 +6869,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_f0_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_b4_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[575] + (const void *)&gInstructions[595] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod = @@ -6993,7 +6884,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_b5_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[577] + (const void *)&gInstructions[597] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod = @@ -7008,13 +6899,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[596] + (const void *)&gInstructions[616] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[597] + (const void *)&gInstructions[617] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_03_modrmmod = @@ -7029,7 +6920,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_03_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_b2_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[598] + (const void *)&gInstructions[618] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_b2_modrmmod = @@ -7044,13 +6935,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b2_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f7_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[603] + (const void *)&gInstructions[623] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f7_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[604] + (const void *)&gInstructions[624] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f7_reg_mprefix = @@ -7076,25 +6967,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_f7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[605] + (const void *)&gInstructions[625] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[606] + (const void *)&gInstructions[626] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[607] + (const void *)&gInstructions[627] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[608] + (const void *)&gInstructions[628] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5f_mprefix = @@ -7111,25 +7002,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5f_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[611] + (const void *)&gInstructions[631] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[612] + (const void *)&gInstructions[632] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[613] + (const void *)&gInstructions[633] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[614] + (const void *)&gInstructions[634] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5d_mprefix = @@ -7146,7 +7037,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5d_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_00_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[617] + (const void *)&gInstructions[637] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_00_00_mprefix = @@ -7178,7 +7069,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_00_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_01_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2695] + (const void *)&gInstructions[2756] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_01_00_mprefix = @@ -7210,7 +7101,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_01_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_02_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2696] + (const void *)&gInstructions[2757] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_02_00_mprefix = @@ -7266,49 +7157,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a6_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_20_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[618] + (const void *)&gInstructions[638] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_21_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[619] + (const void *)&gInstructions[639] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_22_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[620] + (const void *)&gInstructions[640] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_23_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[621] + (const void *)&gInstructions[641] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_24_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[622] + (const void *)&gInstructions[642] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_26_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[623] + (const void *)&gInstructions[643] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_28_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[654] + (const void *)&gInstructions[674] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_28_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[656] + (const void *)&gInstructions[676] }; const ND_TABLE_MPREFIX gRootTable_root_0f_28_mprefix = @@ -7325,13 +7216,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_28_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_29_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[655] + (const void *)&gInstructions[675] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_29_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[657] + (const void *)&gInstructions[677] }; const ND_TABLE_MPREFIX gRootTable_root_0f_29_mprefix = @@ -7348,13 +7239,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_29_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[662] + (const void *)&gInstructions[682] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[693] + (const void *)&gInstructions[713] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_NP_auxiliary = @@ -7367,19 +7258,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_NP_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_66_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[663] + (const void *)&gInstructions[683] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_66_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[694] + (const void *)&gInstructions[714] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_66_auxiliary = @@ -7392,6 +7285,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_66_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -7409,13 +7304,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[664] + (const void *)&gInstructions[684] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[696] + (const void *)&gInstructions[716] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_NP_auxiliary = @@ -7428,19 +7323,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_NP_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_66_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[665] + (const void *)&gInstructions[685] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_66_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[697] + (const void *)&gInstructions[717] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_66_auxiliary = @@ -7453,13 +7350,15 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_66_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[698] + (const void *)&gInstructions[718] }; const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix = @@ -7476,7 +7375,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_cyrix_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1271] + (const void *)&gInstructions[1310] }; const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor = @@ -7495,25 +7394,25 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[666] + (const void *)&gInstructions[686] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[674] + (const void *)&gInstructions[694] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[680] + (const void *)&gInstructions[700] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[709] + (const void *)&gInstructions[729] }; const ND_TABLE_MPREFIX gRootTable_root_0f_12_mem_mprefix = @@ -7530,19 +7429,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_12_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[666] + (const void *)&gInstructions[686] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[674] + (const void *)&gInstructions[694] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[709] + (const void *)&gInstructions[729] }; const ND_TABLE_MPREFIX gRootTable_root_0f_12_reg_mprefix = @@ -7568,19 +7467,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_12_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[669] + (const void *)&gInstructions[689] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[700] + (const void *)&gInstructions[720] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[701] + (const void *)&gInstructions[721] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d6_reg_mprefix = @@ -7597,7 +7496,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d6_reg_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[700] + (const void *)&gInstructions[720] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d6_mem_mprefix = @@ -7623,19 +7522,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_d6_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[670] + (const void *)&gInstructions[690] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[672] + (const void *)&gInstructions[692] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[695] + (const void *)&gInstructions[715] }; const ND_TABLE_MPREFIX gRootTable_root_0f_6f_mprefix = @@ -7652,19 +7551,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6f_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[671] + (const void *)&gInstructions[691] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[673] + (const void *)&gInstructions[693] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[699] + (const void *)&gInstructions[719] }; const ND_TABLE_MPREFIX gRootTable_root_0f_7f_mprefix = @@ -7681,19 +7580,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7f_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[675] + (const void *)&gInstructions[695] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[677] + (const void *)&gInstructions[697] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[708] + (const void *)&gInstructions[728] }; const ND_TABLE_MPREFIX gRootTable_root_0f_16_mem_mprefix = @@ -7710,13 +7609,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_16_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[679] + (const void *)&gInstructions[699] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[708] + (const void *)&gInstructions[728] }; const ND_TABLE_MPREFIX gRootTable_root_0f_16_reg_mprefix = @@ -7742,13 +7641,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_16_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[676] + (const void *)&gInstructions[696] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[678] + (const void *)&gInstructions[698] }; const ND_TABLE_MPREFIX gRootTable_root_0f_17_mem_mprefix = @@ -7774,13 +7673,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_17_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[681] + (const void *)&gInstructions[701] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[682] + (const void *)&gInstructions[702] }; const ND_TABLE_MPREFIX gRootTable_root_0f_13_mem_mprefix = @@ -7806,13 +7705,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_13_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_50_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[683] + (const void *)&gInstructions[703] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_50_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[684] + (const void *)&gInstructions[704] }; const ND_TABLE_MPREFIX gRootTable_root_0f_50_reg_mprefix = @@ -7838,13 +7737,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_50_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e7_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[685] + (const void *)&gInstructions[705] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e7_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[690] + (const void *)&gInstructions[710] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e7_mem_mprefix = @@ -7870,7 +7769,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_e7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c3_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[687] + (const void *)&gInstructions[707] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c3_mem_mprefix = @@ -7896,25 +7795,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c3_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[688] + (const void *)&gInstructions[708] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[689] + (const void *)&gInstructions[709] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[691] + (const void *)&gInstructions[711] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[692] + (const void *)&gInstructions[712] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2b_mem_mprefix = @@ -7940,25 +7839,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_2b_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[704] + (const void *)&gInstructions[724] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[712] + (const void *)&gInstructions[732] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[719] + (const void *)&gInstructions[739] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[721] + (const void *)&gInstructions[741] }; const ND_TABLE_MPREFIX gRootTable_root_0f_10_mprefix = @@ -7975,25 +7874,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_10_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[705] + (const void *)&gInstructions[725] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[713] + (const void *)&gInstructions[733] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[720] + (const void *)&gInstructions[740] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[722] + (const void *)&gInstructions[742] }; const ND_TABLE_MPREFIX gRootTable_root_0f_11_mprefix = @@ -8010,49 +7909,49 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_11_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_be_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[716] + (const void *)&gInstructions[736] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_bf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[717] + (const void *)&gInstructions[737] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[723] + (const void *)&gInstructions[743] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_b7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[724] + (const void *)&gInstructions[744] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[728] + (const void *)&gInstructions[748] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[729] + (const void *)&gInstructions[749] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[730] + (const void *)&gInstructions[750] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[731] + (const void *)&gInstructions[751] }; const ND_TABLE_MPREFIX gRootTable_root_0f_59_mprefix = @@ -8069,49 +7968,49 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_59_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[737] + (const void *)&gInstructions[757] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[738] + (const void *)&gInstructions[758] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[739] + (const void *)&gInstructions[759] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[740] + (const void *)&gInstructions[760] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[741] + (const void *)&gInstructions[761] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[742] + (const void *)&gInstructions[762] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[743] + (const void *)&gInstructions[763] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[744] + (const void *)&gInstructions[764] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_reg_modrmreg = @@ -8132,49 +8031,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1002] + (const void *)&gInstructions[1034] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1003] + (const void *)&gInstructions[1035] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1004] + (const void *)&gInstructions[1036] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1005] + (const void *)&gInstructions[1037] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1006] + (const void *)&gInstructions[1038] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1007] + (const void *)&gInstructions[1041] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1012] + (const void *)&gInstructions[1050] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1013] + (const void *)&gInstructions[1051] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_mem_modrmreg = @@ -8192,178 +8091,370 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_mem_modrmreg = } }; -const ND_TABLE_MODRM_MOD gRootTable_root_0f_0d_modrmmod = +const ND_TABLE_MODRM_MOD gRootTable_root_0f_0d_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gRootTable_root_0f_0d_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_0f_0d_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[765] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[766] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[767] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[768] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[769] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[770] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[771] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[772] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_18_None_reg_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_18_None_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_18_None_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_18_None_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_18_None_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_18_None_reg_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_18_None_reg_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_18_None_reg_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_18_None_reg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[769] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[770] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[771] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[772] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1042] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1044] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1046] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1048] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_0f_18_None_mem_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_18_None_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_18_None_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_18_None_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_18_None_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_18_None_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_18_None_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_18_None_mem_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_18_None_mem_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_18_None_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gRootTable_root_0f_0d_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_0f_0d_reg_modrmreg, + /* 00 */ (const void *)&gRootTable_root_0f_18_None_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_0f_18_None_reg_modrmreg, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_00_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[745] + (const void *)&gInstructions[774] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_01_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[746] + (const void *)&gInstructions[775] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_02_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[747] + (const void *)&gInstructions[776] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_03_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[748] + (const void *)&gInstructions[777] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_04_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[749] + (const void *)&gInstructions[778] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_05_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[750] + (const void *)&gInstructions[779] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_06_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[751] + (const void *)&gInstructions[781] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_07_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[752] + (const void *)&gInstructions[783] }; -const ND_TABLE_MODRM_REG gRootTable_root_0f_18_reg_modrmreg = +const ND_TABLE_MODRM_REG gRootTable_root_0f_18_piti_reg_modrmreg = { ND_ILUT_MODRM_REG, { - /* 00 */ (const void *)&gRootTable_root_0f_18_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_18_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_18_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_18_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_18_reg_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_18_reg_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_18_reg_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_18_reg_07_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_18_piti_reg_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_18_piti_reg_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_18_piti_reg_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_18_piti_reg_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_18_piti_reg_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_18_piti_reg_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_18_piti_reg_06_leaf, + /* 07 */ (const void *)&gRootTable_root_0f_18_piti_reg_07_leaf, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_04_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[749] + (const void *)&gInstructions[778] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_05_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[750] + (const void *)&gInstructions[779] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_06_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_06_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[751] + (const void *)&gInstructions[780] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_06_riprel_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1040] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_07_leaf = +const ND_TABLE_AUXILIARY gRootTable_root_0f_18_piti_mem_06_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_18_piti_mem_06_None_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + /* 04 */ ND_NULL, + /* 05 */ ND_NULL, + /* 06 */ (const void *)&gRootTable_root_0f_18_piti_mem_06_riprel_leaf, + /* 07 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_07_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[752] + (const void *)&gInstructions[782] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_00_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_07_riprel_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1008] + (const void *)&gInstructions[1039] +}; + +const ND_TABLE_AUXILIARY gRootTable_root_0f_18_piti_mem_07_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gRootTable_root_0f_18_piti_mem_07_None_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + /* 04 */ ND_NULL, + /* 05 */ ND_NULL, + /* 06 */ (const void *)&gRootTable_root_0f_18_piti_mem_07_riprel_leaf, + /* 07 */ ND_NULL, + } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_01_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1009] + (const void *)&gInstructions[1043] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_02_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1010] + (const void *)&gInstructions[1045] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_03_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1011] + (const void *)&gInstructions[1047] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1049] }; -const ND_TABLE_MODRM_REG gRootTable_root_0f_18_mem_modrmreg = +const ND_TABLE_MODRM_REG gRootTable_root_0f_18_piti_mem_modrmreg = { ND_ILUT_MODRM_REG, { - /* 00 */ (const void *)&gRootTable_root_0f_18_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_18_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_18_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_18_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_18_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_18_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_18_mem_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_18_mem_07_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_18_piti_mem_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_18_piti_mem_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_18_piti_mem_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_18_piti_mem_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_18_piti_mem_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_18_piti_mem_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_18_piti_mem_06_auxiliary, + /* 07 */ (const void *)&gRootTable_root_0f_18_piti_mem_07_auxiliary, } }; -const ND_TABLE_MODRM_MOD gRootTable_root_0f_18_modrmmod = +const ND_TABLE_MODRM_MOD gRootTable_root_0f_18_piti_modrmmod = { ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gRootTable_root_0f_18_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_0f_18_reg_modrmreg, + /* 00 */ (const void *)&gRootTable_root_0f_18_piti_mem_modrmreg, + /* 01 */ (const void *)&gRootTable_root_0f_18_piti_reg_modrmreg, + } +}; + +const ND_TABLE_FEATURE gRootTable_root_0f_18_feature = +{ + ND_ILUT_FEATURE, + { + /* 00 */ (const void *)&gRootTable_root_0f_18_None_modrmmod, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + /* 04 */ (const void *)&gRootTable_root_0f_18_piti_modrmmod, + /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_19_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[753] + (const void *)&gInstructions[773] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[757] + (const void *)&gInstructions[787] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[759] + (const void *)&gInstructions[789] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_56_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[804] + (const void *)&gInstructions[834] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_56_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[805] + (const void *)&gInstructions[835] }; const ND_TABLE_MPREFIX gRootTable_root_0f_56_mprefix = @@ -8380,13 +8471,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_56_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6b_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[822] + (const void *)&gInstructions[852] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[823] + (const void *)&gInstructions[853] }; const ND_TABLE_MPREFIX gRootTable_root_0f_6b_mprefix = @@ -8403,13 +8494,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_63_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[824] + (const void *)&gInstructions[854] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_63_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[825] + (const void *)&gInstructions[855] }; const ND_TABLE_MPREFIX gRootTable_root_0f_63_mprefix = @@ -8426,13 +8517,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_63_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_67_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[827] + (const void *)&gInstructions[857] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_67_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[828] + (const void *)&gInstructions[858] }; const ND_TABLE_MPREFIX gRootTable_root_0f_67_mprefix = @@ -8449,13 +8540,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_67_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_fc_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[829] + (const void *)&gInstructions[859] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_fc_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[830] + (const void *)&gInstructions[860] }; const ND_TABLE_MPREFIX gRootTable_root_0f_fc_mprefix = @@ -8472,13 +8563,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fc_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_fe_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[831] + (const void *)&gInstructions[861] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_fe_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[832] + (const void *)&gInstructions[862] }; const ND_TABLE_MPREFIX gRootTable_root_0f_fe_mprefix = @@ -8495,13 +8586,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fe_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d4_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[833] + (const void *)&gInstructions[863] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d4_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[834] + (const void *)&gInstructions[864] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d4_mprefix = @@ -8518,13 +8609,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d4_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ec_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[835] + (const void *)&gInstructions[865] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ec_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[836] + (const void *)&gInstructions[866] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ec_mprefix = @@ -8541,13 +8632,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ec_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ed_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[837] + (const void *)&gInstructions[867] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ed_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[838] + (const void *)&gInstructions[868] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ed_mprefix = @@ -8564,13 +8655,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ed_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_dc_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[839] + (const void *)&gInstructions[869] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_dc_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[840] + (const void *)&gInstructions[870] }; const ND_TABLE_MPREFIX gRootTable_root_0f_dc_mprefix = @@ -8587,13 +8678,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_dc_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_dd_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[841] + (const void *)&gInstructions[871] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_dd_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[842] + (const void *)&gInstructions[872] }; const ND_TABLE_MPREFIX gRootTable_root_0f_dd_mprefix = @@ -8610,13 +8701,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_dd_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_fd_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[843] + (const void *)&gInstructions[873] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_fd_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[844] + (const void *)&gInstructions[874] }; const ND_TABLE_MPREFIX gRootTable_root_0f_fd_mprefix = @@ -8633,13 +8724,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fd_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_db_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[847] + (const void *)&gInstructions[877] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_db_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[848] + (const void *)&gInstructions[878] }; const ND_TABLE_MPREFIX gRootTable_root_0f_db_mprefix = @@ -8656,13 +8747,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_db_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_df_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[849] + (const void *)&gInstructions[879] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_df_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[850] + (const void *)&gInstructions[880] }; const ND_TABLE_MPREFIX gRootTable_root_0f_df_mprefix = @@ -8679,13 +8770,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_df_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e0_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[852] + (const void *)&gInstructions[882] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e0_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[853] + (const void *)&gInstructions[883] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e0_mprefix = @@ -8702,157 +8793,157 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e0_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[854] + (const void *)&gInstructions[884] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[889] + (const void *)&gInstructions[921] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[890] + (const void *)&gInstructions[922] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_ae_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[891] + (const void *)&gInstructions[923] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[892] + (const void *)&gInstructions[924] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[893] + (const void *)&gInstructions[925] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_90_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[894] + (const void *)&gInstructions[926] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[895] + (const void *)&gInstructions[927] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[896] + (const void *)&gInstructions[928] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[897] + (const void *)&gInstructions[929] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[898] + (const void *)&gInstructions[930] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[899] + (const void *)&gInstructions[931] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[900] + (const void *)&gInstructions[932] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[901] + (const void *)&gInstructions[933] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[902] + (const void *)&gInstructions[934] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[903] + (const void *)&gInstructions[935] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[904] + (const void *)&gInstructions[936] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[905] + (const void *)&gInstructions[937] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[906] + (const void *)&gInstructions[938] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[907] + (const void *)&gInstructions[939] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[908] + (const void *)&gInstructions[940] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_aa_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[909] + (const void *)&gInstructions[941] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[923] + (const void *)&gInstructions[955] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[924] + (const void *)&gInstructions[956] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[970] + (const void *)&gInstructions[1002] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1079] + (const void *)&gInstructions[1117] }; const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow = @@ -9121,13 +9212,13 @@ const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e3_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[855] + (const void *)&gInstructions[885] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e3_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[856] + (const void *)&gInstructions[886] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e3_mprefix = @@ -9144,13 +9235,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e3_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[860] + (const void *)&gInstructions[890] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[861] + (const void *)&gInstructions[891] }; const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix = @@ -9167,13 +9258,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[862] + (const void *)&gInstructions[892] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[863] + (const void *)&gInstructions[893] }; const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix = @@ -9190,13 +9281,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[865] + (const void *)&gInstructions[895] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[866] + (const void *)&gInstructions[896] }; const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix = @@ -9213,13 +9304,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[869] + (const void *)&gInstructions[899] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[870] + (const void *)&gInstructions[900] }; const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix = @@ -9236,13 +9327,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[871] + (const void *)&gInstructions[901] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[872] + (const void *)&gInstructions[902] }; const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix = @@ -9259,13 +9350,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[874] + (const void *)&gInstructions[904] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[875] + (const void *)&gInstructions[905] }; const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix = @@ -9282,13 +9373,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[885] + (const void *)&gInstructions[917] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[886] + (const void *)&gInstructions[918] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c5_reg_mprefix = @@ -9314,13 +9405,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c5_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[929] + (const void *)&gInstructions[961] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[931] + (const void *)&gInstructions[963] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix = @@ -9337,13 +9428,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[930] + (const void *)&gInstructions[962] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[932] + (const void *)&gInstructions[964] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c4_mem_mprefix = @@ -9369,13 +9460,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c4_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[935] + (const void *)&gInstructions[967] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[936] + (const void *)&gInstructions[968] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix = @@ -9392,13 +9483,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[939] + (const void *)&gInstructions[971] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[940] + (const void *)&gInstructions[972] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix = @@ -9415,13 +9506,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[941] + (const void *)&gInstructions[973] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[942] + (const void *)&gInstructions[974] }; const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix = @@ -9438,13 +9529,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[947] + (const void *)&gInstructions[979] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[948] + (const void *)&gInstructions[980] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix = @@ -9461,13 +9552,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[949] + (const void *)&gInstructions[981] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[950] + (const void *)&gInstructions[982] }; const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix = @@ -9484,13 +9575,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[953] + (const void *)&gInstructions[985] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[954] + (const void *)&gInstructions[986] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d7_reg_mprefix = @@ -9516,13 +9607,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_d7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[971] + (const void *)&gInstructions[1003] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[972] + (const void *)&gInstructions[1004] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix = @@ -9539,13 +9630,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[973] + (const void *)&gInstructions[1005] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[974] + (const void *)&gInstructions[1006] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix = @@ -9562,13 +9653,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[976] + (const void *)&gInstructions[1008] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[977] + (const void *)&gInstructions[1009] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix = @@ -9585,13 +9676,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[978] + (const void *)&gInstructions[1010] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[979] + (const void *)&gInstructions[1011] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix = @@ -9608,25 +9699,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[980] + (const void *)&gInstructions[1012] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[981] + (const void *)&gInstructions[1013] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1000] + (const void *)&gInstructions[1032] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1001] + (const void *)&gInstructions[1033] }; const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix = @@ -9643,13 +9734,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1014] + (const void *)&gInstructions[1052] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1015] + (const void *)&gInstructions[1053] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix = @@ -9666,25 +9757,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1018] + (const void *)&gInstructions[1056] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1019] + (const void *)&gInstructions[1057] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1020] + (const void *)&gInstructions[1058] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1021] + (const void *)&gInstructions[1059] }; const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix = @@ -9701,13 +9792,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1028] + (const void *)&gInstructions[1066] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1029] + (const void *)&gInstructions[1067] }; const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix = @@ -9724,13 +9815,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1042] + (const void *)&gInstructions[1080] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1043] + (const void *)&gInstructions[1081] }; const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix = @@ -9747,13 +9838,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1050] + (const void *)&gInstructions[1088] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1051] + (const void *)&gInstructions[1089] }; const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_02_mprefix = @@ -9794,13 +9885,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_72_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1030] + (const void *)&gInstructions[1068] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1031] + (const void *)&gInstructions[1069] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix = @@ -9817,7 +9908,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_07_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1032] + (const void *)&gInstructions[1070] }; const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix = @@ -9834,13 +9925,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1033] + (const void *)&gInstructions[1071] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1034] + (const void *)&gInstructions[1072] }; const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix = @@ -9857,7 +9948,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_03_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1054] + (const void *)&gInstructions[1092] }; const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix = @@ -9874,13 +9965,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1055] + (const void *)&gInstructions[1093] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1056] + (const void *)&gInstructions[1094] }; const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_02_mprefix = @@ -9921,13 +10012,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_73_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1035] + (const void *)&gInstructions[1073] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1036] + (const void *)&gInstructions[1074] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix = @@ -9944,13 +10035,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1037] + (const void *)&gInstructions[1075] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1038] + (const void *)&gInstructions[1076] }; const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix = @@ -9967,13 +10058,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1046] + (const void *)&gInstructions[1084] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1047] + (const void *)&gInstructions[1085] }; const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix = @@ -9990,13 +10081,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1059] + (const void *)&gInstructions[1097] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1060] + (const void *)&gInstructions[1098] }; const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_02_mprefix = @@ -10037,13 +10128,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_71_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1039] + (const void *)&gInstructions[1077] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1040] + (const void *)&gInstructions[1078] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix = @@ -10060,13 +10151,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1044] + (const void *)&gInstructions[1082] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1045] + (const void *)&gInstructions[1083] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix = @@ -10083,13 +10174,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1048] + (const void *)&gInstructions[1086] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1049] + (const void *)&gInstructions[1087] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix = @@ -10106,13 +10197,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1052] + (const void *)&gInstructions[1090] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1053] + (const void *)&gInstructions[1091] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix = @@ -10129,13 +10220,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1057] + (const void *)&gInstructions[1095] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1058] + (const void *)&gInstructions[1096] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix = @@ -10152,13 +10243,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1061] + (const void *)&gInstructions[1099] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1062] + (const void *)&gInstructions[1100] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix = @@ -10175,13 +10266,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1063] + (const void *)&gInstructions[1101] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1064] + (const void *)&gInstructions[1102] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix = @@ -10198,13 +10289,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1065] + (const void *)&gInstructions[1103] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1066] + (const void *)&gInstructions[1104] }; const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix = @@ -10221,13 +10312,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1067] + (const void *)&gInstructions[1105] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1068] + (const void *)&gInstructions[1106] }; const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix = @@ -10244,13 +10335,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1069] + (const void *)&gInstructions[1107] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1070] + (const void *)&gInstructions[1108] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix = @@ -10267,13 +10358,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1071] + (const void *)&gInstructions[1109] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1072] + (const void *)&gInstructions[1110] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix = @@ -10290,13 +10381,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1073] + (const void *)&gInstructions[1111] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1074] + (const void *)&gInstructions[1112] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix = @@ -10313,13 +10404,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1075] + (const void *)&gInstructions[1113] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1076] + (const void *)&gInstructions[1114] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix = @@ -10336,13 +10427,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1077] + (const void *)&gInstructions[1115] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1078] + (const void *)&gInstructions[1116] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix = @@ -10359,13 +10450,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1082] + (const void *)&gInstructions[1120] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1083] + (const void *)&gInstructions[1121] }; const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix = @@ -10382,13 +10473,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1084] + (const void *)&gInstructions[1122] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1085] + (const void *)&gInstructions[1123] }; const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix = @@ -10405,7 +10496,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6d_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1086] + (const void *)&gInstructions[1124] }; const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix = @@ -10422,13 +10513,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1087] + (const void *)&gInstructions[1125] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1088] + (const void *)&gInstructions[1126] }; const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix = @@ -10445,13 +10536,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1089] + (const void *)&gInstructions[1127] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1090] + (const void *)&gInstructions[1128] }; const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix = @@ -10468,13 +10559,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1091] + (const void *)&gInstructions[1129] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1092] + (const void *)&gInstructions[1130] }; const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix = @@ -10491,7 +10582,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6c_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1093] + (const void *)&gInstructions[1131] }; const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix = @@ -10508,13 +10599,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1094] + (const void *)&gInstructions[1132] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1095] + (const void *)&gInstructions[1133] }; const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix = @@ -10531,25 +10622,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1096] + (const void *)&gInstructions[1134] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1097] + (const void *)&gInstructions[1135] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1119] + (const void *)&gInstructions[1157] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1120] + (const void *)&gInstructions[1158] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix = @@ -10566,13 +10657,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1127] + (const void *)&gInstructions[1165] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1128] + (const void *)&gInstructions[1166] }; const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix = @@ -10589,19 +10680,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1137] + (const void *)&gInstructions[1175] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_33_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1140] + (const void *)&gInstructions[1179] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_36_cyrix_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1146] + (const void *)&gInstructions[1185] }; const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor = @@ -10620,13 +10711,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_31_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1149] + (const void *)&gInstructions[1188] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7b_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1175] + (const void *)&gInstructions[1214] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_7b_cyrix_modrmmod = @@ -10654,19 +10745,19 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7b_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_aa_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1176] + (const void *)&gInstructions[1215] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1177] + (const void *)&gInstructions[1216] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1178] + (const void *)&gInstructions[1217] }; const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix = @@ -10683,133 +10774,133 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1220] + (const void *)&gInstructions[1259] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_92_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1221] + (const void *)&gInstructions[1260] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1222] + (const void *)&gInstructions[1261] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1223] + (const void *)&gInstructions[1262] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1224] + (const void *)&gInstructions[1263] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_93_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1225] + (const void *)&gInstructions[1264] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1226] + (const void *)&gInstructions[1265] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1227] + (const void *)&gInstructions[1266] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_91_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1228] + (const void *)&gInstructions[1267] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1229] + (const void *)&gInstructions[1268] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_99_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1230] + (const void *)&gInstructions[1269] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1231] + (const void *)&gInstructions[1270] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_90_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1232] + (const void *)&gInstructions[1271] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1233] + (const void *)&gInstructions[1272] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_98_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1234] + (const void *)&gInstructions[1273] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1236] + (const void *)&gInstructions[1275] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1252] + (const void *)&gInstructions[1291] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1253] + (const void *)&gInstructions[1292] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ac_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1261] + (const void *)&gInstructions[1300] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ad_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1262] + (const void *)&gInstructions[1301] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1264] + (const void *)&gInstructions[1303] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1265] + (const void *)&gInstructions[1304] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix = @@ -10826,25 +10917,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1275] + (const void *)&gInstructions[1314] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1276] + (const void *)&gInstructions[1315] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1277] + (const void *)&gInstructions[1316] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1278] + (const void *)&gInstructions[1317] }; const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix = @@ -10861,25 +10952,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1307] + (const void *)&gInstructions[1346] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1308] + (const void *)&gInstructions[1347] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1309] + (const void *)&gInstructions[1348] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1310] + (const void *)&gInstructions[1349] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix = @@ -10896,7 +10987,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7a_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1312] + (const void *)&gInstructions[1351] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_7a_cyrix_modrmmod = @@ -10924,37 +11015,37 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7a_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1315] + (const void *)&gInstructions[1354] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_34_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1316] + (const void *)&gInstructions[1355] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_35_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1317] + (const void *)&gInstructions[1356] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1318] + (const void *)&gInstructions[1357] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1344] + (const void *)&gInstructions[1384] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1345] + (const void *)&gInstructions[1385] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix = @@ -10971,31 +11062,31 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ff_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1346] + (const void *)&gInstructions[1386] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_b9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1347] + (const void *)&gInstructions[1387] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1348] + (const void *)&gInstructions[1388] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1352] + (const void *)&gInstructions[1392] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1353] + (const void *)&gInstructions[1393] }; const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix = @@ -11012,13 +11103,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1354] + (const void *)&gInstructions[1394] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1355] + (const void *)&gInstructions[1395] }; const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix = @@ -11035,13 +11126,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2636] + (const void *)&gInstructions[2695] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2637] + (const void *)&gInstructions[2696] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary = @@ -11054,31 +11145,33 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary = /* 03 */ ND_NULL, /* 04 */ (const void *)&gRootTable_root_0f_09_aF3_leaf, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_30_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2640] + (const void *)&gInstructions[2699] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2648] + (const void *)&gInstructions[2709] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2649] + (const void *)&gInstructions[2710] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_02_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2661] + (const void *)&gInstructions[2722] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_02_00_mprefix = @@ -11110,7 +11203,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_02_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_04_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2662] + (const void *)&gInstructions[2723] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_04_00_mprefix = @@ -11142,7 +11235,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_04_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_03_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2663] + (const void *)&gInstructions[2724] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_03_00_mprefix = @@ -11174,7 +11267,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_03_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_01_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2664] + (const void *)&gInstructions[2725] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_01_00_mprefix = @@ -11206,7 +11299,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_01_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_05_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2665] + (const void *)&gInstructions[2726] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_05_00_mprefix = @@ -11238,13 +11331,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_05_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2697] + (const void *)&gInstructions[2758] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2698] + (const void *)&gInstructions[2759] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_00_00_mprefix = @@ -11300,13 +11393,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2679] + (const void *)&gInstructions[2740] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2680] + (const void *)&gInstructions[2741] }; const ND_TABLE_MPREFIX gRootTable_root_0f_57_mprefix = @@ -11348,7 +11441,7 @@ const ND_TABLE_OPCODE gRootTable_root_0f_opcode = /* 15 */ (const void *)&gRootTable_root_0f_15_mprefix, /* 16 */ (const void *)&gRootTable_root_0f_16_modrmmod, /* 17 */ (const void *)&gRootTable_root_0f_17_modrmmod, - /* 18 */ (const void *)&gRootTable_root_0f_18_modrmmod, + /* 18 */ (const void *)&gRootTable_root_0f_18_feature, /* 19 */ (const void *)&gRootTable_root_0f_19_leaf, /* 1a */ (const void *)&gRootTable_root_0f_1a_feature, /* 1b */ (const void *)&gRootTable_root_0f_1b_feature, @@ -11583,88 +11676,388 @@ const ND_TABLE_OPCODE gRootTable_root_0f_opcode = } }; +const ND_TABLE_INSTRUCTION gRootTable_root_d4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[3] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_3f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[5] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_10_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[6] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_11_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[7] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_12_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[8] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_13_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[9] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_14_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[10] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_15_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[11] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[12] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[23] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[55] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[156] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[830] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1242] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1342] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2736] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_80_00_leaf, + /* 01 */ (const void *)&gRootTable_root_80_01_leaf, + /* 02 */ (const void *)&gRootTable_root_80_02_leaf, + /* 03 */ (const void *)&gRootTable_root_80_03_leaf, + /* 04 */ (const void *)&gRootTable_root_80_04_leaf, + /* 05 */ (const void *)&gRootTable_root_80_05_leaf, + /* 06 */ (const void *)&gRootTable_root_80_06_leaf, + /* 07 */ (const void *)&gRootTable_root_80_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[13] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[24] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[56] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[157] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[831] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1243] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1343] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2737] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_81_00_leaf, + /* 01 */ (const void *)&gRootTable_root_81_01_leaf, + /* 02 */ (const void *)&gRootTable_root_81_02_leaf, + /* 03 */ (const void *)&gRootTable_root_81_03_leaf, + /* 04 */ (const void *)&gRootTable_root_81_04_leaf, + /* 05 */ (const void *)&gRootTable_root_81_05_leaf, + /* 06 */ (const void *)&gRootTable_root_81_06_leaf, + /* 07 */ (const void *)&gRootTable_root_81_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[14] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[25] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[57] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[158] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[832] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1244] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1344] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2738] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_82_00_leaf, + /* 01 */ (const void *)&gRootTable_root_82_01_leaf, + /* 02 */ (const void *)&gRootTable_root_82_02_leaf, + /* 03 */ (const void *)&gRootTable_root_82_03_leaf, + /* 04 */ (const void *)&gRootTable_root_82_04_leaf, + /* 05 */ (const void *)&gRootTable_root_82_05_leaf, + /* 06 */ (const void *)&gRootTable_root_82_06_leaf, + /* 07 */ (const void *)&gRootTable_root_82_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[15] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[26] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[58] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[159] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[833] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1245] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1345] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2739] +}; + +const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_83_00_leaf, + /* 01 */ (const void *)&gRootTable_root_83_01_leaf, + /* 02 */ (const void *)&gRootTable_root_83_02_leaf, + /* 03 */ (const void *)&gRootTable_root_83_03_leaf, + /* 04 */ (const void *)&gRootTable_root_83_04_leaf, + /* 05 */ (const void *)&gRootTable_root_83_05_leaf, + /* 06 */ (const void *)&gRootTable_root_83_06_leaf, + /* 07 */ (const void *)&gRootTable_root_83_07_leaf, + } +}; + const ND_TABLE_INSTRUCTION gRootTable_root_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[15] + (const void *)&gInstructions[17] }; const ND_TABLE_INSTRUCTION gRootTable_root_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[16] + (const void *)&gInstructions[18] }; const ND_TABLE_INSTRUCTION gRootTable_root_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[17] + (const void *)&gInstructions[19] }; const ND_TABLE_INSTRUCTION gRootTable_root_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[18] + (const void *)&gInstructions[20] }; const ND_TABLE_INSTRUCTION gRootTable_root_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[19] + (const void *)&gInstructions[21] }; const ND_TABLE_INSTRUCTION gRootTable_root_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[20] + (const void *)&gInstructions[22] }; const ND_TABLE_INSTRUCTION gRootTable_root_20_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[47] + (const void *)&gInstructions[49] }; const ND_TABLE_INSTRUCTION gRootTable_root_21_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[48] + (const void *)&gInstructions[50] }; const ND_TABLE_INSTRUCTION gRootTable_root_22_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[49] + (const void *)&gInstructions[51] }; const ND_TABLE_INSTRUCTION gRootTable_root_23_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[50] + (const void *)&gInstructions[52] }; const ND_TABLE_INSTRUCTION gRootTable_root_24_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[51] + (const void *)&gInstructions[53] }; const ND_TABLE_INSTRUCTION gRootTable_root_25_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[52] + (const void *)&gInstructions[54] }; const ND_TABLE_INSTRUCTION gRootTable_root_63_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[62] + (const void *)&gInstructions[65] }; const ND_TABLE_INSTRUCTION gRootTable_root_63_64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[718] + (const void *)&gInstructions[738] }; const ND_TABLE_AUXILIARY gRootTable_root_63_auxiliary = @@ -11677,13 +12070,15 @@ const ND_TABLE_AUXILIARY gRootTable_root_63_auxiliary = /* 03 */ (const void *)&gRootTable_root_63_64_leaf, /* 04 */ ND_NULL, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_62_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[87] + (const void *)&gInstructions[91] }; const ND_TABLE_MODRM_MOD gRootTable_root_62_modrmmod = @@ -11698,49 +12093,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_62_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_e8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[107] + (const void *)&gInstructions[111] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[108] + (const void *)&gInstructions[112] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[110] + (const void *)&gInstructions[114] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[217] + (const void *)&gInstructions[237] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[426] + (const void *)&gInstructions[446] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[465] + (const void *)&gInstructions[485] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[469] + (const void *)&gInstructions[489] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1112] + (const void *)&gInstructions[1150] }; const ND_TABLE_MODRM_REG gRootTable_root_ff_mem_modrmreg = @@ -11761,31 +12156,31 @@ const ND_TABLE_MODRM_REG gRootTable_root_ff_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[108] + (const void *)&gInstructions[112] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[217] + (const void *)&gInstructions[237] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[426] + (const void *)&gInstructions[446] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[465] + (const void *)&gInstructions[485] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1112] + (const void *)&gInstructions[1150] }; const ND_TABLE_MODRM_REG gRootTable_root_ff_reg_modrmreg = @@ -11815,25 +12210,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_ff_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_9a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[109] + (const void *)&gInstructions[113] }; const ND_TABLE_INSTRUCTION gRootTable_root_98_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[111] + (const void *)&gInstructions[115] }; const ND_TABLE_INSTRUCTION gRootTable_root_98_ds64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[113] + (const void *)&gInstructions[117] }; const ND_TABLE_INSTRUCTION gRootTable_root_98_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[205] + (const void *)&gInstructions[225] }; const ND_TABLE_DSIZE gRootTable_root_98_dsize = @@ -11852,19 +12247,19 @@ const ND_TABLE_DSIZE gRootTable_root_98_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_99_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[112] + (const void *)&gInstructions[116] }; const ND_TABLE_INSTRUCTION gRootTable_root_99_ds64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[177] + (const void *)&gInstructions[197] }; const ND_TABLE_INSTRUCTION gRootTable_root_99_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[204] + (const void *)&gInstructions[224] }; const ND_TABLE_DSIZE gRootTable_root_99_dsize = @@ -11883,73 +12278,73 @@ const ND_TABLE_DSIZE gRootTable_root_99_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_f8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[115] + (const void *)&gInstructions[119] }; const ND_TABLE_INSTRUCTION gRootTable_root_fc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[116] + (const void *)&gInstructions[120] }; const ND_TABLE_INSTRUCTION gRootTable_root_fa_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[123] + (const void *)&gInstructions[127] }; const ND_TABLE_INSTRUCTION gRootTable_root_f5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[129] + (const void *)&gInstructions[133] }; const ND_TABLE_INSTRUCTION gRootTable_root_38_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[146] + (const void *)&gInstructions[150] }; const ND_TABLE_INSTRUCTION gRootTable_root_39_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[147] + (const void *)&gInstructions[151] }; const ND_TABLE_INSTRUCTION gRootTable_root_3a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[148] + (const void *)&gInstructions[152] }; const ND_TABLE_INSTRUCTION gRootTable_root_3b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[149] + (const void *)&gInstructions[153] }; const ND_TABLE_INSTRUCTION gRootTable_root_3c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[150] + (const void *)&gInstructions[154] }; const ND_TABLE_INSTRUCTION gRootTable_root_3d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[151] + (const void *)&gInstructions[155] }; const ND_TABLE_INSTRUCTION gRootTable_root_a6_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[158] + (const void *)&gInstructions[176] }; const ND_TABLE_INSTRUCTION gRootTable_root_a6_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[159] + (const void *)&gInstructions[177] }; const ND_TABLE_AUXILIARY gRootTable_root_a6_auxiliary = @@ -11962,19 +12357,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_a6_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_a6_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds32_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[161] + (const void *)&gInstructions[179] }; const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds32_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[162] + (const void *)&gInstructions[180] }; const ND_TABLE_AUXILIARY gRootTable_root_a7_ds32_auxiliary = @@ -11987,19 +12384,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_a7_ds32_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_a7_ds32_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds64_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[163] + (const void *)&gInstructions[181] }; const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds64_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[164] + (const void *)&gInstructions[182] }; const ND_TABLE_AUXILIARY gRootTable_root_a7_ds64_auxiliary = @@ -12012,19 +12411,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_a7_ds64_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_a7_ds64_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[166] + (const void *)&gInstructions[184] }; const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[167] + (const void *)&gInstructions[185] }; const ND_TABLE_AUXILIARY gRootTable_root_a7_ds16_auxiliary = @@ -12037,6 +12438,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_a7_ds16_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_a7_ds16_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -12056,73 +12459,73 @@ const ND_TABLE_DSIZE gRootTable_root_a7_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_27_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[206] + (const void *)&gInstructions[226] }; const ND_TABLE_INSTRUCTION gRootTable_root_2f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[207] + (const void *)&gInstructions[227] }; const ND_TABLE_INSTRUCTION gRootTable_root_48_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[208] + (const void *)&gInstructions[228] }; const ND_TABLE_INSTRUCTION gRootTable_root_49_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[209] + (const void *)&gInstructions[229] }; const ND_TABLE_INSTRUCTION gRootTable_root_4a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[210] + (const void *)&gInstructions[230] }; const ND_TABLE_INSTRUCTION gRootTable_root_4b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[211] + (const void *)&gInstructions[231] }; const ND_TABLE_INSTRUCTION gRootTable_root_4c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[212] + (const void *)&gInstructions[232] }; const ND_TABLE_INSTRUCTION gRootTable_root_4d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[213] + (const void *)&gInstructions[233] }; const ND_TABLE_INSTRUCTION gRootTable_root_4e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[214] + (const void *)&gInstructions[234] }; const ND_TABLE_INSTRUCTION gRootTable_root_4f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[215] + (const void *)&gInstructions[235] }; const ND_TABLE_INSTRUCTION gRootTable_root_fe_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[216] + (const void *)&gInstructions[236] }; const ND_TABLE_INSTRUCTION gRootTable_root_fe_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[425] + (const void *)&gInstructions[445] }; const ND_TABLE_MODRM_REG gRootTable_root_fe_modrmreg = @@ -12143,49 +12546,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_fe_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_f6_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[219] + (const void *)&gInstructions[239] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[406] + (const void *)&gInstructions[426] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[411] + (const void *)&gInstructions[431] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[726] + (const void *)&gInstructions[746] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[735] + (const void *)&gInstructions[755] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[792] + (const void *)&gInstructions[822] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1330] + (const void *)&gInstructions[1370] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1331] + (const void *)&gInstructions[1371] }; const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg = @@ -12206,49 +12609,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_f7_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[220] + (const void *)&gInstructions[240] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[407] + (const void *)&gInstructions[427] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[412] + (const void *)&gInstructions[432] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[727] + (const void *)&gInstructions[747] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[736] + (const void *)&gInstructions[756] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[793] + (const void *)&gInstructions[823] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1332] + (const void *)&gInstructions[1372] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1333] + (const void *)&gInstructions[1373] }; const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg = @@ -12269,55 +12672,55 @@ const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_c8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[238] + (const void *)&gInstructions[258] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[244] + (const void *)&gInstructions[264] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[275] + (const void *)&gInstructions[295] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[304] + (const void *)&gInstructions[324] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[346] + (const void *)&gInstructions[366] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[348] + (const void *)&gInstructions[368] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[349] + (const void *)&gInstructions[369] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[393] + (const void *)&gInstructions[413] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[394] + (const void *)&gInstructions[414] }; const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_06_modrmrm = @@ -12338,25 +12741,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_06_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[245] + (const void *)&gInstructions[265] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[253] + (const void *)&gInstructions[273] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[379] + (const void *)&gInstructions[399] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[385] + (const void *)&gInstructions[405] }; const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_04_modrmrm = @@ -12377,49 +12780,49 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_04_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[274] + (const void *)&gInstructions[294] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[347] + (const void *)&gInstructions[367] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[351] + (const void *)&gInstructions[371] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[353] + (const void *)&gInstructions[373] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[354] + (const void *)&gInstructions[374] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[355] + (const void *)&gInstructions[375] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[356] + (const void *)&gInstructions[376] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[395] + (const void *)&gInstructions[415] }; const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_07_modrmrm = @@ -12440,49 +12843,49 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_07_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[318] + (const void *)&gInstructions[338] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[321] + (const void *)&gInstructions[341] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[324] + (const void *)&gInstructions[344] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[325] + (const void *)&gInstructions[345] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[326] + (const void *)&gInstructions[346] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[327] + (const void *)&gInstructions[347] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[328] + (const void *)&gInstructions[348] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[329] + (const void *)&gInstructions[349] }; const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_05_modrmrm = @@ -12503,7 +12906,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_05_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[338] + (const void *)&gInstructions[358] }; const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_02_modrmrm = @@ -12524,13 +12927,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_02_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[367] + (const void *)&gInstructions[387] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[386] + (const void *)&gInstructions[406] }; const ND_TABLE_MODRM_REG gRootTable_root_d9_reg_modrmreg = @@ -12551,43 +12954,43 @@ const ND_TABLE_MODRM_REG gRootTable_root_d9_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[317] + (const void *)&gInstructions[337] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[322] + (const void *)&gInstructions[342] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[323] + (const void *)&gInstructions[343] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[342] + (const void *)&gInstructions[362] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[343] + (const void *)&gInstructions[363] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[357] + (const void *)&gInstructions[377] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[361] + (const void *)&gInstructions[381] }; const ND_TABLE_MODRM_REG gRootTable_root_d9_mem_modrmreg = @@ -12617,49 +13020,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_d9_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[246] + (const void *)&gInstructions[266] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[262] + (const void *)&gInstructions[282] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[268] + (const void *)&gInstructions[288] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[276] + (const void *)&gInstructions[296] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[281] + (const void *)&gInstructions[301] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[330] + (const void *)&gInstructions[350] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[369] + (const void *)&gInstructions[389] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[374] + (const void *)&gInstructions[394] }; const ND_TABLE_MODRM_REG gRootTable_root_d8_mem_modrmreg = @@ -12680,49 +13083,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d8_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[247] + (const void *)&gInstructions[267] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[263] + (const void *)&gInstructions[283] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[269] + (const void *)&gInstructions[289] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[277] + (const void *)&gInstructions[297] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[282] + (const void *)&gInstructions[302] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[331] + (const void *)&gInstructions[351] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[370] + (const void *)&gInstructions[390] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[375] + (const void *)&gInstructions[395] }; const ND_TABLE_MODRM_REG gRootTable_root_d8_reg_modrmreg = @@ -12752,49 +13155,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_d8_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[248] + (const void *)&gInstructions[268] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[264] + (const void *)&gInstructions[284] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[270] + (const void *)&gInstructions[290] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[278] + (const void *)&gInstructions[298] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[283] + (const void *)&gInstructions[303] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[332] + (const void *)&gInstructions[352] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[371] + (const void *)&gInstructions[391] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[376] + (const void *)&gInstructions[396] }; const ND_TABLE_MODRM_REG gRootTable_root_dc_mem_modrmreg = @@ -12815,49 +13218,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_dc_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[249] + (const void *)&gInstructions[269] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[265] + (const void *)&gInstructions[285] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[271] + (const void *)&gInstructions[291] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[279] + (const void *)&gInstructions[299] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[284] + (const void *)&gInstructions[304] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[333] + (const void *)&gInstructions[353] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[372] + (const void *)&gInstructions[392] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[377] + (const void *)&gInstructions[397] }; const ND_TABLE_MODRM_REG gRootTable_root_dc_reg_modrmreg = @@ -12887,19 +13290,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_dc_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[250] + (const void *)&gInstructions[270] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[272] + (const void *)&gInstructions[292] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[273] + (const void *)&gInstructions[293] }; const ND_TABLE_MODRM_RM gRootTable_root_de_reg_03_modrmrm = @@ -12920,31 +13323,31 @@ const ND_TABLE_MODRM_RM gRootTable_root_de_reg_03_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[280] + (const void *)&gInstructions[300] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[285] + (const void *)&gInstructions[305] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[334] + (const void *)&gInstructions[354] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[373] + (const void *)&gInstructions[393] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[378] + (const void *)&gInstructions[398] }; const ND_TABLE_MODRM_REG gRootTable_root_de_reg_modrmreg = @@ -12965,49 +13368,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_de_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[290] + (const void *)&gInstructions[310] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[292] + (const void *)&gInstructions[312] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[294] + (const void *)&gInstructions[314] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[296] + (const void *)&gInstructions[316] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[298] + (const void *)&gInstructions[318] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[303] + (const void *)&gInstructions[323] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[314] + (const void *)&gInstructions[334] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[316] + (const void *)&gInstructions[336] }; const ND_TABLE_MODRM_REG gRootTable_root_de_mem_modrmreg = @@ -13037,49 +13440,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_de_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[251] + (const void *)&gInstructions[271] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[252] + (const void *)&gInstructions[272] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[300] + (const void *)&gInstructions[320] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[301] + (const void *)&gInstructions[321] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[306] + (const void *)&gInstructions[326] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[308] + (const void *)&gInstructions[328] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[309] + (const void *)&gInstructions[329] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[312] + (const void *)&gInstructions[332] }; const ND_TABLE_MODRM_REG gRootTable_root_df_mem_modrmreg = @@ -13100,31 +13503,31 @@ const ND_TABLE_MODRM_REG gRootTable_root_df_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[267] + (const void *)&gInstructions[287] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[288] + (const void *)&gInstructions[308] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[345] + (const void *)&gInstructions[365] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[360] + (const void *)&gInstructions[380] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[368] + (const void *)&gInstructions[388] }; const ND_TABLE_MODRM_RM gRootTable_root_df_reg_04_modrmrm = @@ -13145,7 +13548,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_df_reg_04_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_07_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[350] + (const void *)&gInstructions[370] }; const ND_TABLE_MODRM_RM gRootTable_root_df_reg_07_modrmrm = @@ -13166,25 +13569,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_df_reg_07_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[365] + (const void *)&gInstructions[385] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[366] + (const void *)&gInstructions[386] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[382] + (const void *)&gInstructions[402] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[388] + (const void *)&gInstructions[408] }; const ND_TABLE_MODRM_REG gRootTable_root_df_reg_modrmreg = @@ -13214,31 +13617,31 @@ const ND_TABLE_MODRM_MOD gRootTable_root_df_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[254] + (const void *)&gInstructions[274] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[255] + (const void *)&gInstructions[275] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[256] + (const void *)&gInstructions[276] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[261] + (const void *)&gInstructions[281] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_05_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[384] + (const void *)&gInstructions[404] }; const ND_TABLE_MODRM_RM gRootTable_root_da_reg_05_modrmrm = @@ -13274,49 +13677,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_da_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[289] + (const void *)&gInstructions[309] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[291] + (const void *)&gInstructions[311] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[293] + (const void *)&gInstructions[313] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[295] + (const void *)&gInstructions[315] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[297] + (const void *)&gInstructions[317] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[302] + (const void *)&gInstructions[322] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[313] + (const void *)&gInstructions[333] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[315] + (const void *)&gInstructions[335] }; const ND_TABLE_MODRM_REG gRootTable_root_da_mem_modrmreg = @@ -13346,61 +13749,61 @@ const ND_TABLE_MODRM_MOD gRootTable_root_da_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[257] + (const void *)&gInstructions[277] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[258] + (const void *)&gInstructions[278] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[259] + (const void *)&gInstructions[279] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[260] + (const void *)&gInstructions[280] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[266] + (const void *)&gInstructions[286] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[335] + (const void *)&gInstructions[355] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[336] + (const void *)&gInstructions[356] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[337] + (const void *)&gInstructions[357] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[339] + (const void *)&gInstructions[359] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[340] + (const void *)&gInstructions[360] }; const ND_TABLE_MODRM_RM gRootTable_root_db_reg_04_modrmrm = @@ -13421,7 +13824,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_db_reg_04_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[381] + (const void *)&gInstructions[401] }; const ND_TABLE_MODRM_REG gRootTable_root_db_reg_modrmreg = @@ -13442,37 +13845,37 @@ const ND_TABLE_MODRM_REG gRootTable_root_db_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[299] + (const void *)&gInstructions[319] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[305] + (const void *)&gInstructions[325] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[307] + (const void *)&gInstructions[327] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[310] + (const void *)&gInstructions[330] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[319] + (const void *)&gInstructions[339] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[362] + (const void *)&gInstructions[382] }; const ND_TABLE_MODRM_REG gRootTable_root_db_mem_modrmreg = @@ -13502,37 +13905,37 @@ const ND_TABLE_MODRM_MOD gRootTable_root_db_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[287] + (const void *)&gInstructions[307] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[359] + (const void *)&gInstructions[379] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[364] + (const void *)&gInstructions[384] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[380] + (const void *)&gInstructions[400] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[383] + (const void *)&gInstructions[403] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[387] + (const void *)&gInstructions[407] }; const ND_TABLE_MODRM_REG gRootTable_root_dd_reg_modrmreg = @@ -13553,43 +13956,43 @@ const ND_TABLE_MODRM_REG gRootTable_root_dd_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[311] + (const void *)&gInstructions[331] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[320] + (const void *)&gInstructions[340] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[341] + (const void *)&gInstructions[361] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[344] + (const void *)&gInstructions[364] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[352] + (const void *)&gInstructions[372] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[358] + (const void *)&gInstructions[378] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[363] + (const void *)&gInstructions[383] }; const ND_TABLE_MODRM_REG gRootTable_root_dd_mem_modrmreg = @@ -13619,103 +14022,103 @@ const ND_TABLE_MODRM_MOD gRootTable_root_dd_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_f4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[402] + (const void *)&gInstructions[422] }; const ND_TABLE_INSTRUCTION gRootTable_root_69_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[409] + (const void *)&gInstructions[429] }; const ND_TABLE_INSTRUCTION gRootTable_root_6b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[410] + (const void *)&gInstructions[430] }; const ND_TABLE_INSTRUCTION gRootTable_root_e4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[413] + (const void *)&gInstructions[433] }; const ND_TABLE_INSTRUCTION gRootTable_root_e5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[414] + (const void *)&gInstructions[434] }; const ND_TABLE_INSTRUCTION gRootTable_root_ec_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[415] + (const void *)&gInstructions[435] }; const ND_TABLE_INSTRUCTION gRootTable_root_ed_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[416] + (const void *)&gInstructions[436] }; const ND_TABLE_INSTRUCTION gRootTable_root_40_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[417] + (const void *)&gInstructions[437] }; const ND_TABLE_INSTRUCTION gRootTable_root_41_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[418] + (const void *)&gInstructions[438] }; const ND_TABLE_INSTRUCTION gRootTable_root_42_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[419] + (const void *)&gInstructions[439] }; const ND_TABLE_INSTRUCTION gRootTable_root_43_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[420] + (const void *)&gInstructions[440] }; const ND_TABLE_INSTRUCTION gRootTable_root_44_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[421] + (const void *)&gInstructions[441] }; const ND_TABLE_INSTRUCTION gRootTable_root_45_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[422] + (const void *)&gInstructions[442] }; const ND_TABLE_INSTRUCTION gRootTable_root_46_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[423] + (const void *)&gInstructions[443] }; const ND_TABLE_INSTRUCTION gRootTable_root_47_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[424] + (const void *)&gInstructions[444] }; const ND_TABLE_INSTRUCTION gRootTable_root_6c_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[429] + (const void *)&gInstructions[449] }; const ND_TABLE_INSTRUCTION gRootTable_root_6c_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[430] + (const void *)&gInstructions[450] }; const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary = @@ -13728,19 +14131,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_6c_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[431] + (const void *)&gInstructions[451] }; const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[432] + (const void *)&gInstructions[452] }; const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary = @@ -13753,19 +14158,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_6d_None_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[437] + (const void *)&gInstructions[457] }; const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[438] + (const void *)&gInstructions[458] }; const ND_TABLE_AUXILIARY gRootTable_root_6d_ds16_auxiliary = @@ -13778,6 +14185,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_6d_ds16_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_6d_ds16_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -13797,43 +14206,43 @@ const ND_TABLE_DSIZE gRootTable_root_6d_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_cd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[439] + (const void *)&gInstructions[459] }; const ND_TABLE_INSTRUCTION gRootTable_root_f1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[440] + (const void *)&gInstructions[460] }; const ND_TABLE_INSTRUCTION gRootTable_root_cc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[441] + (const void *)&gInstructions[461] }; const ND_TABLE_INSTRUCTION gRootTable_root_ce_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[442] + (const void *)&gInstructions[462] }; const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[450] + (const void *)&gInstructions[470] }; const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[451] + (const void *)&gInstructions[471] }; const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[452] + (const void *)&gInstructions[472] }; const ND_TABLE_DSIZE gRootTable_root_cf_dsize = @@ -13852,31 +14261,31 @@ const ND_TABLE_DSIZE gRootTable_root_cf_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_76_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[454] + (const void *)&gInstructions[474] }; const ND_TABLE_INSTRUCTION gRootTable_root_72_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[456] + (const void *)&gInstructions[476] }; const ND_TABLE_INSTRUCTION gRootTable_root_e3_as16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[457] + (const void *)&gInstructions[477] }; const ND_TABLE_INSTRUCTION gRootTable_root_e3_as32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[458] + (const void *)&gInstructions[478] }; const ND_TABLE_INSTRUCTION gRootTable_root_e3_as64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[490] + (const void *)&gInstructions[510] }; const ND_TABLE_ASIZE gRootTable_root_e3_asize = @@ -13893,115 +14302,115 @@ const ND_TABLE_ASIZE gRootTable_root_e3_asize = const ND_TABLE_INSTRUCTION gRootTable_root_7c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[460] + (const void *)&gInstructions[480] }; const ND_TABLE_INSTRUCTION gRootTable_root_7e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[462] + (const void *)&gInstructions[482] }; const ND_TABLE_INSTRUCTION gRootTable_root_e9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[463] + (const void *)&gInstructions[483] }; const ND_TABLE_INSTRUCTION gRootTable_root_eb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[464] + (const void *)&gInstructions[484] }; const ND_TABLE_INSTRUCTION gRootTable_root_ea_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[468] + (const void *)&gInstructions[488] }; const ND_TABLE_INSTRUCTION gRootTable_root_77_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[471] + (const void *)&gInstructions[491] }; const ND_TABLE_INSTRUCTION gRootTable_root_73_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[473] + (const void *)&gInstructions[493] }; const ND_TABLE_INSTRUCTION gRootTable_root_7d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[475] + (const void *)&gInstructions[495] }; const ND_TABLE_INSTRUCTION gRootTable_root_7f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[477] + (const void *)&gInstructions[497] }; const ND_TABLE_INSTRUCTION gRootTable_root_71_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[479] + (const void *)&gInstructions[499] }; const ND_TABLE_INSTRUCTION gRootTable_root_7b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[481] + (const void *)&gInstructions[501] }; const ND_TABLE_INSTRUCTION gRootTable_root_79_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[483] + (const void *)&gInstructions[503] }; const ND_TABLE_INSTRUCTION gRootTable_root_75_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[485] + (const void *)&gInstructions[505] }; const ND_TABLE_INSTRUCTION gRootTable_root_70_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[487] + (const void *)&gInstructions[507] }; const ND_TABLE_INSTRUCTION gRootTable_root_7a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[489] + (const void *)&gInstructions[509] }; const ND_TABLE_INSTRUCTION gRootTable_root_78_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[492] + (const void *)&gInstructions[512] }; const ND_TABLE_INSTRUCTION gRootTable_root_74_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[494] + (const void *)&gInstructions[514] }; const ND_TABLE_INSTRUCTION gRootTable_root_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[564] + (const void *)&gInstructions[584] }; const ND_TABLE_INSTRUCTION gRootTable_root_c5_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[569] + (const void *)&gInstructions[589] }; const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod = @@ -14016,7 +14425,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_8d_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[571] + (const void *)&gInstructions[591] }; const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod = @@ -14031,13 +14440,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_c9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[572] + (const void *)&gInstructions[592] }; const ND_TABLE_INSTRUCTION gRootTable_root_c4_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[573] + (const void *)&gInstructions[593] }; const ND_TABLE_MODRM_MOD gRootTable_root_c4_modrmmod = @@ -14052,13 +14461,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c4_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_ac_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[585] + (const void *)&gInstructions[605] }; const ND_TABLE_INSTRUCTION gRootTable_root_ac_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[586] + (const void *)&gInstructions[606] }; const ND_TABLE_AUXILIARY gRootTable_root_ac_auxiliary = @@ -14071,19 +14480,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_ac_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_ac_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds32_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[587] + (const void *)&gInstructions[607] }; const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds32_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[588] + (const void *)&gInstructions[608] }; const ND_TABLE_AUXILIARY gRootTable_root_ad_ds32_auxiliary = @@ -14096,19 +14507,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_ad_ds32_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_ad_ds32_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds64_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[589] + (const void *)&gInstructions[609] }; const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds64_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[590] + (const void *)&gInstructions[610] }; const ND_TABLE_AUXILIARY gRootTable_root_ad_ds64_auxiliary = @@ -14121,19 +14534,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_ad_ds64_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_ad_ds64_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[591] + (const void *)&gInstructions[611] }; const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[592] + (const void *)&gInstructions[612] }; const ND_TABLE_AUXILIARY gRootTable_root_ad_ds16_auxiliary = @@ -14146,6 +14561,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_ad_ds16_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_ad_ds16_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -14165,55 +14582,55 @@ const ND_TABLE_DSIZE gRootTable_root_ad_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_e2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[593] + (const void *)&gInstructions[613] }; const ND_TABLE_INSTRUCTION gRootTable_root_e0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[594] + (const void *)&gInstructions[614] }; const ND_TABLE_INSTRUCTION gRootTable_root_e1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[595] + (const void *)&gInstructions[615] }; const ND_TABLE_INSTRUCTION gRootTable_root_88_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[624] + (const void *)&gInstructions[644] }; const ND_TABLE_INSTRUCTION gRootTable_root_89_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[625] + (const void *)&gInstructions[645] }; const ND_TABLE_INSTRUCTION gRootTable_root_8a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[626] + (const void *)&gInstructions[646] }; const ND_TABLE_INSTRUCTION gRootTable_root_8b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[627] + (const void *)&gInstructions[647] }; const ND_TABLE_INSTRUCTION gRootTable_root_8c_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[628] + (const void *)&gInstructions[648] }; const ND_TABLE_INSTRUCTION gRootTable_root_8c_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[629] + (const void *)&gInstructions[649] }; const ND_TABLE_MODRM_MOD gRootTable_root_8c_modrmmod = @@ -14228,13 +14645,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8c_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_8e_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[630] + (const void *)&gInstructions[650] }; const ND_TABLE_INSTRUCTION gRootTable_root_8e_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[631] + (const void *)&gInstructions[651] }; const ND_TABLE_MODRM_MOD gRootTable_root_8e_modrmmod = @@ -14249,127 +14666,127 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8e_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_a0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[632] + (const void *)&gInstructions[652] }; const ND_TABLE_INSTRUCTION gRootTable_root_a1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[633] + (const void *)&gInstructions[653] }; const ND_TABLE_INSTRUCTION gRootTable_root_a2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[634] + (const void *)&gInstructions[654] }; const ND_TABLE_INSTRUCTION gRootTable_root_a3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[635] + (const void *)&gInstructions[655] }; const ND_TABLE_INSTRUCTION gRootTable_root_b0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[636] + (const void *)&gInstructions[656] }; const ND_TABLE_INSTRUCTION gRootTable_root_b1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[637] + (const void *)&gInstructions[657] }; const ND_TABLE_INSTRUCTION gRootTable_root_b2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[638] + (const void *)&gInstructions[658] }; const ND_TABLE_INSTRUCTION gRootTable_root_b3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[639] + (const void *)&gInstructions[659] }; const ND_TABLE_INSTRUCTION gRootTable_root_b4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[640] + (const void *)&gInstructions[660] }; const ND_TABLE_INSTRUCTION gRootTable_root_b5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[641] + (const void *)&gInstructions[661] }; const ND_TABLE_INSTRUCTION gRootTable_root_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[642] + (const void *)&gInstructions[662] }; const ND_TABLE_INSTRUCTION gRootTable_root_b7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[643] + (const void *)&gInstructions[663] }; const ND_TABLE_INSTRUCTION gRootTable_root_b8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[644] + (const void *)&gInstructions[664] }; const ND_TABLE_INSTRUCTION gRootTable_root_b9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[645] + (const void *)&gInstructions[665] }; const ND_TABLE_INSTRUCTION gRootTable_root_ba_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[646] + (const void *)&gInstructions[666] }; const ND_TABLE_INSTRUCTION gRootTable_root_bb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[647] + (const void *)&gInstructions[667] }; const ND_TABLE_INSTRUCTION gRootTable_root_bc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[648] + (const void *)&gInstructions[668] }; const ND_TABLE_INSTRUCTION gRootTable_root_bd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[649] + (const void *)&gInstructions[669] }; const ND_TABLE_INSTRUCTION gRootTable_root_be_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[650] + (const void *)&gInstructions[670] }; const ND_TABLE_INSTRUCTION gRootTable_root_bf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[651] + (const void *)&gInstructions[671] }; const ND_TABLE_INSTRUCTION gRootTable_root_c6_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[652] + (const void *)&gInstructions[672] }; const ND_TABLE_MODRM_REG gRootTable_root_c6_mem_modrmreg = @@ -14390,13 +14807,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_c6_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[652] + (const void *)&gInstructions[672] }; const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2647] + (const void *)&gInstructions[2708] }; const ND_TABLE_MODRM_RM gRootTable_root_c6_reg_07_modrmrm = @@ -14441,7 +14858,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c6_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_c7_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[653] + (const void *)&gInstructions[673] }; const ND_TABLE_MODRM_REG gRootTable_root_c7_mem_modrmreg = @@ -14462,13 +14879,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_c7_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[653] + (const void *)&gInstructions[673] }; const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2650] + (const void *)&gInstructions[2711] }; const ND_TABLE_MODRM_RM gRootTable_root_c7_reg_07_modrmrm = @@ -14513,13 +14930,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_a4_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[702] + (const void *)&gInstructions[722] }; const ND_TABLE_INSTRUCTION gRootTable_root_a4_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[703] + (const void *)&gInstructions[723] }; const ND_TABLE_AUXILIARY gRootTable_root_a4_auxiliary = @@ -14532,19 +14949,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_a4_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_a4_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds32_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[706] + (const void *)&gInstructions[726] }; const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds32_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[707] + (const void *)&gInstructions[727] }; const ND_TABLE_AUXILIARY gRootTable_root_a5_ds32_auxiliary = @@ -14557,19 +14976,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_a5_ds32_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_a5_ds32_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds64_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[710] + (const void *)&gInstructions[730] }; const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds64_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[711] + (const void *)&gInstructions[731] }; const ND_TABLE_AUXILIARY gRootTable_root_a5_ds64_auxiliary = @@ -14582,19 +15003,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_a5_ds64_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_a5_ds64_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[714] + (const void *)&gInstructions[734] }; const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[715] + (const void *)&gInstructions[735] }; const ND_TABLE_AUXILIARY gRootTable_root_a5_ds16_auxiliary = @@ -14607,6 +15030,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_a5_ds16_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_a5_ds16_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -14626,19 +15051,19 @@ const ND_TABLE_DSIZE gRootTable_root_a5_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_90_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[791] + (const void *)&gInstructions[821] }; const ND_TABLE_INSTRUCTION gRootTable_root_90_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[851] + (const void *)&gInstructions[881] }; const ND_TABLE_INSTRUCTION gRootTable_root_90_rexb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2653] + (const void *)&gInstructions[2714] }; const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary = @@ -14651,79 +15076,81 @@ const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary = /* 03 */ ND_NULL, /* 04 */ (const void *)&gRootTable_root_90_aF3_leaf, /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[794] + (const void *)&gInstructions[824] }; const ND_TABLE_INSTRUCTION gRootTable_root_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[795] + (const void *)&gInstructions[825] }; const ND_TABLE_INSTRUCTION gRootTable_root_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[796] + (const void *)&gInstructions[826] }; const ND_TABLE_INSTRUCTION gRootTable_root_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[797] + (const void *)&gInstructions[827] }; const ND_TABLE_INSTRUCTION gRootTable_root_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[798] + (const void *)&gInstructions[828] }; const ND_TABLE_INSTRUCTION gRootTable_root_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[799] + (const void *)&gInstructions[829] }; const ND_TABLE_INSTRUCTION gRootTable_root_e6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[806] + (const void *)&gInstructions[836] }; const ND_TABLE_INSTRUCTION gRootTable_root_e7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[807] + (const void *)&gInstructions[837] }; const ND_TABLE_INSTRUCTION gRootTable_root_ee_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[808] + (const void *)&gInstructions[838] }; const ND_TABLE_INSTRUCTION gRootTable_root_ef_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[809] + (const void *)&gInstructions[839] }; const ND_TABLE_INSTRUCTION gRootTable_root_6e_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[810] + (const void *)&gInstructions[840] }; const ND_TABLE_INSTRUCTION gRootTable_root_6e_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[811] + (const void *)&gInstructions[841] }; const ND_TABLE_AUXILIARY gRootTable_root_6e_auxiliary = @@ -14736,19 +15163,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_6e_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_6e_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_6f_None_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[812] + (const void *)&gInstructions[842] }; const ND_TABLE_INSTRUCTION gRootTable_root_6f_None_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[813] + (const void *)&gInstructions[843] }; const ND_TABLE_AUXILIARY gRootTable_root_6f_None_auxiliary = @@ -14761,19 +15190,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_6f_None_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_6f_None_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_6f_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[814] + (const void *)&gInstructions[844] }; const ND_TABLE_INSTRUCTION gRootTable_root_6f_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[815] + (const void *)&gInstructions[845] }; const ND_TABLE_AUXILIARY gRootTable_root_6f_ds16_auxiliary = @@ -14786,6 +15217,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_6f_ds16_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_6f_ds16_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -14805,73 +15238,73 @@ const ND_TABLE_DSIZE gRootTable_root_6f_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[982] + (const void *)&gInstructions[1014] }; const ND_TABLE_INSTRUCTION gRootTable_root_17_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[983] + (const void *)&gInstructions[1015] }; const ND_TABLE_INSTRUCTION gRootTable_root_1f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[984] + (const void *)&gInstructions[1016] }; const ND_TABLE_INSTRUCTION gRootTable_root_58_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[985] + (const void *)&gInstructions[1017] }; const ND_TABLE_INSTRUCTION gRootTable_root_59_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[986] + (const void *)&gInstructions[1018] }; const ND_TABLE_INSTRUCTION gRootTable_root_5a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[987] + (const void *)&gInstructions[1019] }; const ND_TABLE_INSTRUCTION gRootTable_root_5b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[988] + (const void *)&gInstructions[1020] }; const ND_TABLE_INSTRUCTION gRootTable_root_5c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[989] + (const void *)&gInstructions[1021] }; const ND_TABLE_INSTRUCTION gRootTable_root_5d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[990] + (const void *)&gInstructions[1022] }; const ND_TABLE_INSTRUCTION gRootTable_root_5e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[991] + (const void *)&gInstructions[1023] }; const ND_TABLE_INSTRUCTION gRootTable_root_5f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[992] + (const void *)&gInstructions[1024] }; const ND_TABLE_INSTRUCTION gRootTable_root_8f_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[993] + (const void *)&gInstructions[1025] }; const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg = @@ -14892,13 +15325,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_61_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[994] + (const void *)&gInstructions[1026] }; const ND_TABLE_INSTRUCTION gRootTable_root_61_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[995] + (const void *)&gInstructions[1027] }; const ND_TABLE_DSIZE gRootTable_root_61_dsize = @@ -14917,19 +15350,19 @@ const ND_TABLE_DSIZE gRootTable_root_61_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[997] + (const void *)&gInstructions[1029] }; const ND_TABLE_INSTRUCTION gRootTable_root_9d_dds64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[998] + (const void *)&gInstructions[1030] }; const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[999] + (const void *)&gInstructions[1031] }; const ND_TABLE_DSIZE gRootTable_root_9d_dsize = @@ -14948,97 +15381,97 @@ const ND_TABLE_DSIZE gRootTable_root_9d_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1098] + (const void *)&gInstructions[1136] }; const ND_TABLE_INSTRUCTION gRootTable_root_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1099] + (const void *)&gInstructions[1137] }; const ND_TABLE_INSTRUCTION gRootTable_root_16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1100] + (const void *)&gInstructions[1138] }; const ND_TABLE_INSTRUCTION gRootTable_root_1e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1101] + (const void *)&gInstructions[1139] }; const ND_TABLE_INSTRUCTION gRootTable_root_50_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1102] + (const void *)&gInstructions[1140] }; const ND_TABLE_INSTRUCTION gRootTable_root_51_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1103] + (const void *)&gInstructions[1141] }; const ND_TABLE_INSTRUCTION gRootTable_root_52_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1104] + (const void *)&gInstructions[1142] }; const ND_TABLE_INSTRUCTION gRootTable_root_53_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1105] + (const void *)&gInstructions[1143] }; const ND_TABLE_INSTRUCTION gRootTable_root_54_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1106] + (const void *)&gInstructions[1144] }; const ND_TABLE_INSTRUCTION gRootTable_root_55_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1107] + (const void *)&gInstructions[1145] }; const ND_TABLE_INSTRUCTION gRootTable_root_56_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1108] + (const void *)&gInstructions[1146] }; const ND_TABLE_INSTRUCTION gRootTable_root_57_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1109] + (const void *)&gInstructions[1147] }; const ND_TABLE_INSTRUCTION gRootTable_root_68_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1110] + (const void *)&gInstructions[1148] }; const ND_TABLE_INSTRUCTION gRootTable_root_6a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1111] + (const void *)&gInstructions[1149] }; const ND_TABLE_INSTRUCTION gRootTable_root_60_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1113] + (const void *)&gInstructions[1151] }; const ND_TABLE_INSTRUCTION gRootTable_root_60_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1114] + (const void *)&gInstructions[1152] }; const ND_TABLE_DSIZE gRootTable_root_60_dsize = @@ -15057,19 +15490,19 @@ const ND_TABLE_DSIZE gRootTable_root_60_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1115] + (const void *)&gInstructions[1153] }; const ND_TABLE_INSTRUCTION gRootTable_root_9c_dds64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1116] + (const void *)&gInstructions[1154] }; const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1117] + (const void *)&gInstructions[1155] }; const ND_TABLE_DSIZE gRootTable_root_9c_dsize = @@ -15088,49 +15521,49 @@ const ND_TABLE_DSIZE gRootTable_root_9c_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_c0_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1121] + (const void *)&gInstructions[1159] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1129] + (const void *)&gInstructions[1167] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1157] + (const void *)&gInstructions[1196] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1163] + (const void *)&gInstructions[1202] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1182] + (const void *)&gInstructions[1221] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1189] + (const void *)&gInstructions[1228] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1246] + (const void *)&gInstructions[1285] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1255] + (const void *)&gInstructions[1294] }; const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg = @@ -15151,49 +15584,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_c1_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1122] + (const void *)&gInstructions[1160] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1130] + (const void *)&gInstructions[1168] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1158] + (const void *)&gInstructions[1197] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1164] + (const void *)&gInstructions[1203] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1183] + (const void *)&gInstructions[1222] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1190] + (const void *)&gInstructions[1229] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1247] + (const void *)&gInstructions[1286] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1256] + (const void *)&gInstructions[1295] }; const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg = @@ -15214,49 +15647,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_d0_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1123] + (const void *)&gInstructions[1161] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1131] + (const void *)&gInstructions[1169] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1159] + (const void *)&gInstructions[1198] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1165] + (const void *)&gInstructions[1204] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1184] + (const void *)&gInstructions[1223] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1191] + (const void *)&gInstructions[1230] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1248] + (const void *)&gInstructions[1287] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1257] + (const void *)&gInstructions[1296] }; const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg = @@ -15277,49 +15710,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_d1_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1124] + (const void *)&gInstructions[1162] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1132] + (const void *)&gInstructions[1170] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1160] + (const void *)&gInstructions[1199] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1166] + (const void *)&gInstructions[1205] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1185] + (const void *)&gInstructions[1224] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1192] + (const void *)&gInstructions[1231] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1249] + (const void *)&gInstructions[1288] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1258] + (const void *)&gInstructions[1297] }; const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg = @@ -15340,49 +15773,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_d2_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1125] + (const void *)&gInstructions[1163] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1133] + (const void *)&gInstructions[1171] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1161] + (const void *)&gInstructions[1200] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1167] + (const void *)&gInstructions[1206] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1186] + (const void *)&gInstructions[1225] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1193] + (const void *)&gInstructions[1232] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1250] + (const void *)&gInstructions[1289] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1259] + (const void *)&gInstructions[1298] }; const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg = @@ -15403,49 +15836,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_d3_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1126] + (const void *)&gInstructions[1164] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1134] + (const void *)&gInstructions[1172] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1162] + (const void *)&gInstructions[1201] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1168] + (const void *)&gInstructions[1207] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1187] + (const void *)&gInstructions[1226] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1194] + (const void *)&gInstructions[1233] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1251] + (const void *)&gInstructions[1290] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1260] + (const void *)&gInstructions[1299] }; const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg = @@ -15466,85 +15899,85 @@ const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_ca_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1151] + (const void *)&gInstructions[1190] }; const ND_TABLE_INSTRUCTION gRootTable_root_cb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1152] + (const void *)&gInstructions[1191] }; const ND_TABLE_INSTRUCTION gRootTable_root_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1153] + (const void *)&gInstructions[1192] }; const ND_TABLE_INSTRUCTION gRootTable_root_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1154] + (const void *)&gInstructions[1193] }; const ND_TABLE_INSTRUCTION gRootTable_root_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1181] + (const void *)&gInstructions[1220] }; const ND_TABLE_INSTRUCTION gRootTable_root_d6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1188] + (const void *)&gInstructions[1227] }; const ND_TABLE_INSTRUCTION gRootTable_root_18_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1197] + (const void *)&gInstructions[1236] }; const ND_TABLE_INSTRUCTION gRootTable_root_19_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1198] + (const void *)&gInstructions[1237] }; const ND_TABLE_INSTRUCTION gRootTable_root_1a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1199] + (const void *)&gInstructions[1238] }; const ND_TABLE_INSTRUCTION gRootTable_root_1b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1200] + (const void *)&gInstructions[1239] }; const ND_TABLE_INSTRUCTION gRootTable_root_1c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1201] + (const void *)&gInstructions[1240] }; const ND_TABLE_INSTRUCTION gRootTable_root_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1202] + (const void *)&gInstructions[1241] }; const ND_TABLE_INSTRUCTION gRootTable_root_ae_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1207] + (const void *)&gInstructions[1246] }; const ND_TABLE_INSTRUCTION gRootTable_root_ae_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1208] + (const void *)&gInstructions[1247] }; const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary = @@ -15557,19 +15990,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_ae_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1209] + (const void *)&gInstructions[1248] }; const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1210] + (const void *)&gInstructions[1249] }; const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary = @@ -15582,19 +16017,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_af_ds32_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1211] + (const void *)&gInstructions[1250] }; const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1212] + (const void *)&gInstructions[1251] }; const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary = @@ -15607,19 +16044,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_af_ds64_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1213] + (const void *)&gInstructions[1252] }; const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1214] + (const void *)&gInstructions[1253] }; const ND_TABLE_AUXILIARY gRootTable_root_af_ds16_auxiliary = @@ -15632,6 +16071,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds16_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_af_ds16_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -15651,31 +16092,31 @@ const ND_TABLE_DSIZE gRootTable_root_af_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_f9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1280] + (const void *)&gInstructions[1319] }; const ND_TABLE_INSTRUCTION gRootTable_root_fd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1281] + (const void *)&gInstructions[1320] }; const ND_TABLE_INSTRUCTION gRootTable_root_fb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1283] + (const void *)&gInstructions[1322] }; const ND_TABLE_INSTRUCTION gRootTable_root_aa_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1285] + (const void *)&gInstructions[1324] }; const ND_TABLE_INSTRUCTION gRootTable_root_aa_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1286] + (const void *)&gInstructions[1325] }; const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary = @@ -15688,19 +16129,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_aa_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1287] + (const void *)&gInstructions[1326] }; const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1288] + (const void *)&gInstructions[1327] }; const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary = @@ -15713,19 +16156,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_ab_ds32_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1289] + (const void *)&gInstructions[1328] }; const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1290] + (const void *)&gInstructions[1329] }; const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary = @@ -15738,19 +16183,21 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_ab_ds64_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1291] + (const void *)&gInstructions[1330] }; const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1292] + (const void *)&gInstructions[1331] }; const ND_TABLE_AUXILIARY gRootTable_root_ab_ds16_auxiliary = @@ -15763,6 +16210,8 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds16_auxiliary = /* 03 */ ND_NULL, /* 04 */ ND_NULL, /* 05 */ (const void *)&gRootTable_root_ab_ds16_rep_leaf, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, } }; @@ -15782,163 +16231,163 @@ const ND_TABLE_DSIZE gRootTable_root_ab_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_28_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1297] + (const void *)&gInstructions[1336] }; const ND_TABLE_INSTRUCTION gRootTable_root_29_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1298] + (const void *)&gInstructions[1337] }; const ND_TABLE_INSTRUCTION gRootTable_root_2a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1299] + (const void *)&gInstructions[1338] }; const ND_TABLE_INSTRUCTION gRootTable_root_2b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1300] + (const void *)&gInstructions[1339] }; const ND_TABLE_INSTRUCTION gRootTable_root_2c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1301] + (const void *)&gInstructions[1340] }; const ND_TABLE_INSTRUCTION gRootTable_root_2d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1302] + (const void *)&gInstructions[1341] }; const ND_TABLE_INSTRUCTION gRootTable_root_84_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1326] + (const void *)&gInstructions[1366] }; const ND_TABLE_INSTRUCTION gRootTable_root_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1327] + (const void *)&gInstructions[1367] }; const ND_TABLE_INSTRUCTION gRootTable_root_a8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1328] + (const void *)&gInstructions[1368] }; const ND_TABLE_INSTRUCTION gRootTable_root_a9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1329] + (const void *)&gInstructions[1369] }; const ND_TABLE_INSTRUCTION gRootTable_root_9b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2635] + (const void *)&gInstructions[2694] }; const ND_TABLE_INSTRUCTION gRootTable_root_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2651] + (const void *)&gInstructions[2712] }; const ND_TABLE_INSTRUCTION gRootTable_root_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2652] + (const void *)&gInstructions[2713] }; const ND_TABLE_INSTRUCTION gRootTable_root_91_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2654] + (const void *)&gInstructions[2715] }; const ND_TABLE_INSTRUCTION gRootTable_root_92_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2655] + (const void *)&gInstructions[2716] }; const ND_TABLE_INSTRUCTION gRootTable_root_93_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2656] + (const void *)&gInstructions[2717] }; const ND_TABLE_INSTRUCTION gRootTable_root_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2657] + (const void *)&gInstructions[2718] }; const ND_TABLE_INSTRUCTION gRootTable_root_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2658] + (const void *)&gInstructions[2719] }; const ND_TABLE_INSTRUCTION gRootTable_root_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2659] + (const void *)&gInstructions[2720] }; const ND_TABLE_INSTRUCTION gRootTable_root_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2660] + (const void *)&gInstructions[2721] }; const ND_TABLE_INSTRUCTION gRootTable_root_d7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2668] + (const void *)&gInstructions[2729] }; const ND_TABLE_INSTRUCTION gRootTable_root_30_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2669] + (const void *)&gInstructions[2730] }; const ND_TABLE_INSTRUCTION gRootTable_root_31_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2670] + (const void *)&gInstructions[2731] }; const ND_TABLE_INSTRUCTION gRootTable_root_32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2671] + (const void *)&gInstructions[2732] }; const ND_TABLE_INSTRUCTION gRootTable_root_33_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2672] + (const void *)&gInstructions[2733] }; const ND_TABLE_INSTRUCTION gRootTable_root_34_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2673] + (const void *)&gInstructions[2734] }; const ND_TABLE_INSTRUCTION gRootTable_root_35_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2674] + (const void *)&gInstructions[2735] }; const ND_TABLE_OPCODE gRootTable_root_opcode = diff --git a/bddisasm/include/table_vex.h b/bddisasm/include/table_vex.h index 64e7b9b..65d1f85 100644 --- a/bddisasm/include/table_vex.h +++ b/bddisasm/include/table_vex.h @@ -2,259 +2,856 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ + +// +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! +// + #ifndef TABLE_VEX_H #define TABLE_VEX_H -const ND_TABLE_INSTRUCTION gVexTable_root_02_f2_00_00_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_02_f2_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[59] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f2_00_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f2_00_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_f2_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_02_f2_00_l, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[67] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f7_00_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f7_00_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1234] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f7_02_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1293] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f7_01_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1302] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f7_03_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f7_03_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_f7_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_02_f7_00_l, + /* 01 */ (const void *)&gVexTable_root_02_f7_01_l, + /* 02 */ (const void *)&gVexTable_root_02_f7_02_l, + /* 03 */ (const void *)&gVexTable_root_02_f7_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[79] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f3_00_03_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f3_00_03_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[81] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f3_00_02_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f3_00_02_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[82] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f3_00_01_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f3_00_01_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gVexTable_root_02_f3_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_f3_00_01_l, + /* 02 */ (const void *)&gVexTable_root_02_f3_00_02_l, + /* 03 */ (const void *)&gVexTable_root_02_f3_00_03_l, + /* 04 */ ND_NULL, + /* 05 */ ND_NULL, + /* 06 */ ND_NULL, + /* 07 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_f3_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_02_f3_00_modrmreg, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[110] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f5_00_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f5_00_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[909] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f5_03_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[910] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_f5_02_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_f5_02_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_f5_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_02_f5_00_l, + /* 01 */ ND_NULL, + /* 02 */ (const void *)&gVexTable_root_02_f5_02_l, + /* 03 */ (const void *)&gVexTable_root_02_f5_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_e6_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[160] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_e6_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_e6_01_mem_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_e6_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_e6_01_mem_l, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_e6_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_e6_01_modrmmod, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_e2_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[161] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_e2_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_e2_01_mem_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_e2_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_e2_01_mem_l, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_e2_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_e2_01_modrmmod, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ee_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[162] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_ee_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_ee_01_mem_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_ee_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_ee_01_mem_l, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_ee_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_ee_01_modrmmod, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ec_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[163] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_ec_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_ec_01_mem_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_ec_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_ec_01_mem_l, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_ec_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_ec_01_modrmmod, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_e7_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[164] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_e7_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_e7_01_mem_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_e7_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_e7_01_mem_l, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_e7_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_e7_01_modrmmod, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_e3_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[165] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_e3_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_e3_01_mem_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_e3_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_e3_01_mem_l, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_e3_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_e3_01_modrmmod, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ef_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[166] +}; + +const ND_TABLE_VEX_L gVexTable_root_02_ef_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_ef_01_mem_00_leaf, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_ef_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_ef_01_mem_l, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_ef_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_ef_01_modrmmod, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_ed_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[57] + (const void *)&gInstructions[167] }; -const ND_TABLE_VEX_L gVexTable_root_02_f2_00_l = +const ND_TABLE_VEX_L gVexTable_root_02_ed_01_mem_l = { ND_ILUT_VEX_L, { - /* 00 */ (const void *)&gVexTable_root_02_f2_00_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_ed_01_mem_00_leaf, /* 01 */ ND_NULL, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_VEX_PP gVexTable_root_02_f2_pp = +const ND_TABLE_MODRM_MOD gVexTable_root_02_ed_01_modrmmod = { - ND_ILUT_VEX_PP, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexTable_root_02_f2_00_l, + /* 00 */ (const void *)&gVexTable_root_02_ed_01_mem_l, /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_ed_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_ed_01_modrmmod, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_00_00_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_02_e1_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[63] + (const void *)&gInstructions[168] }; -const ND_TABLE_VEX_L gVexTable_root_02_f7_00_l = +const ND_TABLE_VEX_L gVexTable_root_02_e1_01_mem_l = { ND_ILUT_VEX_L, { - /* 00 */ (const void *)&gVexTable_root_02_f7_00_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_e1_01_mem_00_leaf, /* 01 */ ND_NULL, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_02_00_leaf = +const ND_TABLE_MODRM_MOD gVexTable_root_02_e1_01_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1195] + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_e1_01_mem_l, + /* 01 */ ND_NULL, + } }; -const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l = +const ND_TABLE_VEX_PP gVexTable_root_02_e1_pp = { - ND_ILUT_VEX_L, + ND_ILUT_VEX_PP, { - /* 00 */ (const void *)&gVexTable_root_02_f7_02_00_leaf, - /* 01 */ ND_NULL, + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_e1_01_modrmmod, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_01_00_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_02_eb_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1254] + (const void *)&gInstructions[169] }; -const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l = +const ND_TABLE_VEX_L gVexTable_root_02_eb_01_mem_l = { ND_ILUT_VEX_L, { - /* 00 */ (const void *)&gVexTable_root_02_f7_01_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_eb_01_mem_00_leaf, /* 01 */ ND_NULL, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_03_00_leaf = +const ND_TABLE_MODRM_MOD gVexTable_root_02_eb_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_eb_01_mem_l, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_eb_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_eb_01_modrmmod, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_e9_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1263] + (const void *)&gInstructions[170] }; -const ND_TABLE_VEX_L gVexTable_root_02_f7_03_l = +const ND_TABLE_VEX_L gVexTable_root_02_e9_01_mem_l = { ND_ILUT_VEX_L, { - /* 00 */ (const void *)&gVexTable_root_02_f7_03_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_e9_01_mem_00_leaf, /* 01 */ ND_NULL, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_VEX_PP gVexTable_root_02_f7_pp = +const ND_TABLE_MODRM_MOD gVexTable_root_02_e9_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_e9_01_mem_l, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_e9_pp = { ND_ILUT_VEX_PP, { - /* 00 */ (const void *)&gVexTable_root_02_f7_00_l, - /* 01 */ (const void *)&gVexTable_root_02_f7_01_l, - /* 02 */ (const void *)&gVexTable_root_02_f7_02_l, - /* 03 */ (const void *)&gVexTable_root_02_f7_03_l, + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_e9_01_modrmmod, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_03_00_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_02_e5_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[75] + (const void *)&gInstructions[171] }; -const ND_TABLE_VEX_L gVexTable_root_02_f3_00_03_l = +const ND_TABLE_VEX_L gVexTable_root_02_e5_01_mem_l = { ND_ILUT_VEX_L, { - /* 00 */ (const void *)&gVexTable_root_02_f3_00_03_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_e5_01_mem_00_leaf, /* 01 */ ND_NULL, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_02_00_leaf = +const ND_TABLE_MODRM_MOD gVexTable_root_02_e5_01_modrmmod = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[77] + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_e5_01_mem_l, + /* 01 */ ND_NULL, + } }; -const ND_TABLE_VEX_L gVexTable_root_02_f3_00_02_l = +const ND_TABLE_VEX_PP gVexTable_root_02_e5_pp = { - ND_ILUT_VEX_L, + ND_ILUT_VEX_PP, { - /* 00 */ (const void *)&gVexTable_root_02_f3_00_02_00_leaf, - /* 01 */ ND_NULL, + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_e5_01_modrmmod, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_01_00_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_02_e0_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[78] + (const void *)&gInstructions[172] }; -const ND_TABLE_VEX_L gVexTable_root_02_f3_00_01_l = +const ND_TABLE_VEX_L gVexTable_root_02_e0_01_mem_l = { ND_ILUT_VEX_L, { - /* 00 */ (const void *)&gVexTable_root_02_f3_00_01_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_e0_01_mem_00_leaf, /* 01 */ ND_NULL, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_MODRM_REG gVexTable_root_02_f3_00_modrmreg = +const ND_TABLE_MODRM_MOD gVexTable_root_02_e0_01_modrmmod = { - ND_ILUT_MODRM_REG, + ND_ILUT_MODRM_MOD, { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_f3_00_01_l, - /* 02 */ (const void *)&gVexTable_root_02_f3_00_02_l, - /* 03 */ (const void *)&gVexTable_root_02_f3_00_03_l, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, + /* 00 */ (const void *)&gVexTable_root_02_e0_01_mem_l, + /* 01 */ ND_NULL, } }; -const ND_TABLE_VEX_PP gVexTable_root_02_f3_pp = +const ND_TABLE_VEX_PP gVexTable_root_02_e0_pp = { ND_ILUT_VEX_PP, { - /* 00 */ (const void *)&gVexTable_root_02_f3_00_modrmreg, - /* 01 */ ND_NULL, + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_e0_01_modrmmod, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_00_00_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_02_ea_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[106] + (const void *)&gInstructions[175] }; -const ND_TABLE_VEX_L gVexTable_root_02_f5_00_l = +const ND_TABLE_VEX_L gVexTable_root_02_ea_01_mem_l = { ND_ILUT_VEX_L, { - /* 00 */ (const void *)&gVexTable_root_02_f5_00_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_ea_01_mem_00_leaf, /* 01 */ ND_NULL, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_03_00_leaf = +const ND_TABLE_MODRM_MOD gVexTable_root_02_ea_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_ea_01_mem_l, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_ea_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_ea_01_modrmmod, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_e8_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[879] + (const void *)&gInstructions[186] }; -const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l = +const ND_TABLE_VEX_L gVexTable_root_02_e8_01_mem_l = { ND_ILUT_VEX_L, { - /* 00 */ (const void *)&gVexTable_root_02_f5_03_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_e8_01_mem_00_leaf, /* 01 */ ND_NULL, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_02_00_leaf = +const ND_TABLE_MODRM_MOD gVexTable_root_02_e8_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_e8_01_mem_l, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_e8_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_e8_01_modrmmod, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_e4_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[880] + (const void *)&gInstructions[191] }; -const ND_TABLE_VEX_L gVexTable_root_02_f5_02_l = +const ND_TABLE_VEX_L gVexTable_root_02_e4_01_mem_l = { ND_ILUT_VEX_L, { - /* 00 */ (const void *)&gVexTable_root_02_f5_02_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_e4_01_mem_00_leaf, /* 01 */ ND_NULL, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; -const ND_TABLE_VEX_PP gVexTable_root_02_f5_pp = +const ND_TABLE_MODRM_MOD gVexTable_root_02_e4_01_modrmmod = { - ND_ILUT_VEX_PP, + ND_ILUT_MODRM_MOD, { - /* 00 */ (const void *)&gVexTable_root_02_f5_00_l, + /* 00 */ (const void *)&gVexTable_root_02_e4_01_mem_l, /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_02_f5_02_l, - /* 03 */ (const void *)&gVexTable_root_02_f5_03_l, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_e4_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_e4_01_modrmmod, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, } }; const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_mem_00_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[570] + (const void *)&gInstructions[590] }; const ND_TABLE_VEX_W gVexTable_root_02_49_00_mem_00_00_w = @@ -295,7 +892,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_mem_modrmreg = const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_reg_00_00_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1337] + (const void *)&gInstructions[1377] }; const ND_TABLE_VEX_W gVexTable_root_02_49_00_reg_00_00_00_w = @@ -360,7 +957,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_00_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_49_01_mem_00_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1295] + (const void *)&gInstructions[1334] }; const ND_TABLE_VEX_W gVexTable_root_02_49_01_mem_00_00_w = @@ -410,7 +1007,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_49_03_reg_00_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1339] + (const void *)&gInstructions[1379] }; const ND_TABLE_VEX_W gVexTable_root_02_49_03_reg_00_00_w = @@ -471,7 +1068,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_49_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_f6_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[732] + (const void *)&gInstructions[752] }; const ND_TABLE_VEX_L gVexTable_root_02_f6_03_l = @@ -499,7 +1096,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_02_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1321] + (const void *)&gInstructions[1360] }; const ND_TABLE_VEX_W gVexTable_root_02_5c_02_reg_00_w = @@ -531,6 +1128,41 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5c_02_modrmmod = } }; +const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_03_reg_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1365] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_5c_03_reg_00_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_5c_03_reg_00_00_leaf, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_02_5c_03_reg_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_02_5c_03_reg_00_w, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_5c_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_5c_03_reg_l, + } +}; + const ND_TABLE_VEX_PP gVexTable_root_02_5c_pp = { ND_ILUT_VEX_PP, @@ -538,14 +1170,14 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5c_pp = /* 00 */ ND_NULL, /* 01 */ ND_NULL, /* 02 */ (const void *)&gVexTable_root_02_5c_02_modrmmod, - /* 03 */ ND_NULL, + /* 03 */ (const void *)&gVexTable_root_02_5c_03_modrmmod, } }; const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_03_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1322] + (const void *)&gInstructions[1361] }; const ND_TABLE_VEX_W gVexTable_root_02_5e_03_reg_00_w = @@ -580,7 +1212,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_02_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1323] + (const void *)&gInstructions[1362] }; const ND_TABLE_VEX_W gVexTable_root_02_5e_02_reg_00_w = @@ -615,7 +1247,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1324] + (const void *)&gInstructions[1363] }; const ND_TABLE_VEX_W gVexTable_root_02_5e_01_reg_00_w = @@ -650,7 +1282,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1325] + (const void *)&gInstructions[1364] }; const ND_TABLE_VEX_W gVexTable_root_02_5e_00_reg_00_w = @@ -696,7 +1328,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_03_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1335] + (const void *)&gInstructions[1375] }; const ND_TABLE_VEX_W gVexTable_root_02_4b_03_mem_00_w = @@ -731,7 +1363,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_01_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1336] + (const void *)&gInstructions[1376] }; const ND_TABLE_VEX_W gVexTable_root_02_4b_01_mem_00_w = @@ -766,7 +1398,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_02_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1338] + (const void *)&gInstructions[1378] }; const ND_TABLE_VEX_W gVexTable_root_02_4b_02_mem_00_w = @@ -812,7 +1444,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_4b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_de_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1373] + (const void *)&gInstructions[1413] }; const ND_TABLE_VEX_PP gVexTable_root_02_de_pp = @@ -829,7 +1461,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_de_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_df_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1375] + (const void *)&gInstructions[1415] }; const ND_TABLE_VEX_PP gVexTable_root_02_df_pp = @@ -846,7 +1478,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_df_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_dc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1377] + (const void *)&gInstructions[1417] }; const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp = @@ -863,7 +1495,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_dd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1379] + (const void *)&gInstructions[1419] }; const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp = @@ -880,7 +1512,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_db_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1380] + (const void *)&gInstructions[1420] }; const ND_TABLE_VEX_L gVexTable_root_02_db_01_l = @@ -905,10 +1537,69 @@ const ND_TABLE_VEX_PP gVexTable_root_02_db_pp = } }; +const ND_TABLE_INSTRUCTION gVexTable_root_02_b1_02_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1432] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_b1_02_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_b1_02_mem_00_leaf, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_b1_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_b1_02_mem_w, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b1_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1433] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_b1_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_b1_01_mem_00_leaf, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_b1_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_b1_01_mem_w, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_b1_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_b1_01_modrmmod, + /* 02 */ (const void *)&gVexTable_root_02_b1_02_modrmmod, + /* 03 */ ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gVexTable_root_02_1a_01_mem_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1398] + (const void *)&gInstructions[1440] }; const ND_TABLE_VEX_W gVexTable_root_02_1a_01_mem_01_w = @@ -954,7 +1645,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_5a_01_mem_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1404] + (const void *)&gInstructions[1446] }; const ND_TABLE_VEX_W gVexTable_root_02_5a_01_mem_01_w = @@ -1000,7 +1691,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_19_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1411] + (const void *)&gInstructions[1453] }; const ND_TABLE_VEX_W gVexTable_root_02_19_01_w = @@ -1026,7 +1717,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_19_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_18_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1413] + (const void *)&gInstructions[1455] }; const ND_TABLE_VEX_W gVexTable_root_02_18_01_w = @@ -1049,10 +1740,143 @@ const ND_TABLE_VEX_PP gVexTable_root_02_18_pp = } }; +const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_02_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1480] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_b0_02_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_b0_02_mem_00_leaf, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_b0_02_mem_w, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_01_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1481] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_b0_01_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_b0_01_mem_00_leaf, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_b0_01_mem_w, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_03_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1482] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_b0_03_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_b0_03_mem_00_leaf, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_b0_03_mem_w, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_00_mem_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1483] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_b0_00_mem_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_b0_00_mem_00_leaf, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_02_b0_00_mem_w, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_b0_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ (const void *)&gVexTable_root_02_b0_00_modrmmod, + /* 01 */ (const void *)&gVexTable_root_02_b0_01_modrmmod, + /* 02 */ (const void *)&gVexTable_root_02_b0_02_modrmmod, + /* 03 */ (const void *)&gVexTable_root_02_b0_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_72_02_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1485] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_72_02_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_72_02_00_leaf, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_72_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ ND_NULL, + /* 02 */ (const void *)&gVexTable_root_02_72_02_w, + /* 03 */ ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1451] + (const void *)&gInstructions[1498] }; const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w = @@ -1067,7 +1891,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w = const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1452] + (const void *)&gInstructions[1499] }; const ND_TABLE_VEX_W gVexTable_root_02_13_01_01_w = @@ -1104,13 +1928,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_13_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1575] + (const void *)&gInstructions[1622] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1578] + (const void *)&gInstructions[1625] }; const ND_TABLE_VEX_W gVexTable_root_02_98_01_w = @@ -1136,13 +1960,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_98_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1580] + (const void *)&gInstructions[1627] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1583] + (const void *)&gInstructions[1630] }; const ND_TABLE_VEX_W gVexTable_root_02_99_01_w = @@ -1168,13 +1992,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_99_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1585] + (const void *)&gInstructions[1632] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1588] + (const void *)&gInstructions[1635] }; const ND_TABLE_VEX_W gVexTable_root_02_a8_01_w = @@ -1200,13 +2024,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1590] + (const void *)&gInstructions[1637] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1593] + (const void *)&gInstructions[1640] }; const ND_TABLE_VEX_W gVexTable_root_02_a9_01_w = @@ -1232,13 +2056,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1595] + (const void *)&gInstructions[1642] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1598] + (const void *)&gInstructions[1645] }; const ND_TABLE_VEX_W gVexTable_root_02_b8_01_w = @@ -1264,13 +2088,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1600] + (const void *)&gInstructions[1647] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1603] + (const void *)&gInstructions[1650] }; const ND_TABLE_VEX_W gVexTable_root_02_b9_01_w = @@ -1296,13 +2120,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1615] + (const void *)&gInstructions[1662] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1618] + (const void *)&gInstructions[1665] }; const ND_TABLE_VEX_W gVexTable_root_02_96_01_w = @@ -1328,13 +2152,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_96_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1620] + (const void *)&gInstructions[1667] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1623] + (const void *)&gInstructions[1670] }; const ND_TABLE_VEX_W gVexTable_root_02_a6_01_w = @@ -1360,13 +2184,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1625] + (const void *)&gInstructions[1672] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1628] + (const void *)&gInstructions[1675] }; const ND_TABLE_VEX_W gVexTable_root_02_b6_01_w = @@ -1392,13 +2216,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1634] + (const void *)&gInstructions[1681] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1637] + (const void *)&gInstructions[1684] }; const ND_TABLE_VEX_W gVexTable_root_02_9a_01_w = @@ -1424,13 +2248,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1639] + (const void *)&gInstructions[1686] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1642] + (const void *)&gInstructions[1689] }; const ND_TABLE_VEX_W gVexTable_root_02_9b_01_w = @@ -1456,13 +2280,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1644] + (const void *)&gInstructions[1691] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1647] + (const void *)&gInstructions[1694] }; const ND_TABLE_VEX_W gVexTable_root_02_aa_01_w = @@ -1488,13 +2312,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_aa_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1649] + (const void *)&gInstructions[1696] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1652] + (const void *)&gInstructions[1699] }; const ND_TABLE_VEX_W gVexTable_root_02_ab_01_w = @@ -1520,13 +2344,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ab_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1654] + (const void *)&gInstructions[1701] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1657] + (const void *)&gInstructions[1704] }; const ND_TABLE_VEX_W gVexTable_root_02_ba_01_w = @@ -1552,13 +2376,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ba_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1659] + (const void *)&gInstructions[1706] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1662] + (const void *)&gInstructions[1709] }; const ND_TABLE_VEX_W gVexTable_root_02_bb_01_w = @@ -1584,13 +2408,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bb_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1664] + (const void *)&gInstructions[1711] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1667] + (const void *)&gInstructions[1714] }; const ND_TABLE_VEX_W gVexTable_root_02_97_01_w = @@ -1616,13 +2440,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_97_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1669] + (const void *)&gInstructions[1716] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1672] + (const void *)&gInstructions[1719] }; const ND_TABLE_VEX_W gVexTable_root_02_a7_01_w = @@ -1648,13 +2472,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1674] + (const void *)&gInstructions[1721] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1677] + (const void *)&gInstructions[1724] }; const ND_TABLE_VEX_W gVexTable_root_02_b7_01_w = @@ -1680,13 +2504,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1693] + (const void *)&gInstructions[1740] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1696] + (const void *)&gInstructions[1743] }; const ND_TABLE_VEX_W gVexTable_root_02_9c_01_w = @@ -1712,13 +2536,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1698] + (const void *)&gInstructions[1745] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1701] + (const void *)&gInstructions[1748] }; const ND_TABLE_VEX_W gVexTable_root_02_9d_01_w = @@ -1744,13 +2568,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1703] + (const void *)&gInstructions[1750] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1706] + (const void *)&gInstructions[1753] }; const ND_TABLE_VEX_W gVexTable_root_02_ac_01_w = @@ -1776,13 +2600,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ac_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1708] + (const void *)&gInstructions[1755] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1711] + (const void *)&gInstructions[1758] }; const ND_TABLE_VEX_W gVexTable_root_02_ad_01_w = @@ -1808,13 +2632,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ad_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1713] + (const void *)&gInstructions[1760] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1716] + (const void *)&gInstructions[1763] }; const ND_TABLE_VEX_W gVexTable_root_02_bc_01_w = @@ -1840,13 +2664,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bc_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1718] + (const void *)&gInstructions[1765] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1721] + (const void *)&gInstructions[1768] }; const ND_TABLE_VEX_W gVexTable_root_02_bd_01_w = @@ -1872,13 +2696,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bd_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1731] + (const void *)&gInstructions[1778] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1734] + (const void *)&gInstructions[1781] }; const ND_TABLE_VEX_W gVexTable_root_02_9e_01_w = @@ -1904,13 +2728,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1736] + (const void *)&gInstructions[1783] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1739] + (const void *)&gInstructions[1786] }; const ND_TABLE_VEX_W gVexTable_root_02_9f_01_w = @@ -1936,13 +2760,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1741] + (const void *)&gInstructions[1788] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1744] + (const void *)&gInstructions[1791] }; const ND_TABLE_VEX_W gVexTable_root_02_ae_01_w = @@ -1968,13 +2792,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ae_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1746] + (const void *)&gInstructions[1793] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1749] + (const void *)&gInstructions[1796] }; const ND_TABLE_VEX_W gVexTable_root_02_af_01_w = @@ -2000,13 +2824,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_af_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1751] + (const void *)&gInstructions[1798] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1754] + (const void *)&gInstructions[1801] }; const ND_TABLE_VEX_W gVexTable_root_02_be_01_w = @@ -2032,13 +2856,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_be_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1756] + (const void *)&gInstructions[1803] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1759] + (const void *)&gInstructions[1806] }; const ND_TABLE_VEX_W gVexTable_root_02_bf_01_w = @@ -2064,13 +2888,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bf_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1779] + (const void *)&gInstructions[1826] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1781] + (const void *)&gInstructions[1828] }; const ND_TABLE_VEX_W gVexTable_root_02_92_01_mem_w = @@ -2105,13 +2929,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_92_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1791] + (const void *)&gInstructions[1838] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1793] + (const void *)&gInstructions[1840] }; const ND_TABLE_VEX_W gVexTable_root_02_93_01_mem_w = @@ -2146,7 +2970,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_93_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_cf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1811] + (const void *)&gInstructions[1858] }; const ND_TABLE_VEX_W gVexTable_root_02_cf_01_w = @@ -2172,7 +2996,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_cf_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2d_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1833] + (const void *)&gInstructions[1880] }; const ND_TABLE_VEX_W gVexTable_root_02_2d_01_mem_w = @@ -2207,7 +3031,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2f_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1834] + (const void *)&gInstructions[1881] }; const ND_TABLE_VEX_W gVexTable_root_02_2f_01_mem_w = @@ -2242,7 +3066,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2c_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1835] + (const void *)&gInstructions[1882] }; const ND_TABLE_VEX_W gVexTable_root_02_2c_01_mem_w = @@ -2277,7 +3101,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2e_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1836] + (const void *)&gInstructions[1883] }; const ND_TABLE_VEX_W gVexTable_root_02_2e_01_mem_w = @@ -2312,7 +3136,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2a_01_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1924] + (const void *)&gInstructions[1971] }; const ND_TABLE_MODRM_MOD gVexTable_root_02_2a_01_modrmmod = @@ -2338,7 +3162,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_1c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2002] + (const void *)&gInstructions[2049] }; const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp = @@ -2355,7 +3179,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_1e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2004] + (const void *)&gInstructions[2051] }; const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp = @@ -2372,7 +3196,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_1d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2007] + (const void *)&gInstructions[2054] }; const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp = @@ -2389,7 +3213,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2013] + (const void *)&gInstructions[2060] }; const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp = @@ -2406,7 +3230,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2053] + (const void *)&gInstructions[2100] }; const ND_TABLE_VEX_W gVexTable_root_02_78_01_w = @@ -2432,7 +3256,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_78_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_58_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2056] + (const void *)&gInstructions[2103] }; const ND_TABLE_VEX_W gVexTable_root_02_58_01_w = @@ -2455,129 +3279,219 @@ const ND_TABLE_VEX_PP gVexTable_root_02_58_pp = } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_59_01_00_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_02_59_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2108] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_59_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_59_01_00_leaf, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_59_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_59_01_w, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_79_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2111] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_79_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_79_01_00_leaf, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_79_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_79_01_w, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_29_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2123] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_29_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_29_01_leaf, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_37_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2133] +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_37_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_37_01_leaf, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_50_03_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2158] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_50_03_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_50_03_00_leaf, + /* 01 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_50_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2061] + (const void *)&gInstructions[2160] }; -const ND_TABLE_VEX_W gVexTable_root_02_59_01_w = +const ND_TABLE_VEX_W gVexTable_root_02_50_02_w = { ND_ILUT_VEX_W, { - /* 00 */ (const void *)&gVexTable_root_02_59_01_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_50_02_00_leaf, /* 01 */ ND_NULL, } }; -const ND_TABLE_VEX_PP gVexTable_root_02_59_pp = +const ND_TABLE_INSTRUCTION gVexTable_root_02_50_01_00_leaf = { - ND_ILUT_VEX_PP, + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2163] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_50_01_w = +{ + ND_ILUT_VEX_W, { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_59_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, + /* 00 */ (const void *)&gVexTable_root_02_50_01_00_leaf, + /* 01 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_79_01_00_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_02_50_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2064] + (const void *)&gInstructions[2166] }; -const ND_TABLE_VEX_W gVexTable_root_02_79_01_w = +const ND_TABLE_VEX_W gVexTable_root_02_50_00_w = { ND_ILUT_VEX_W, { - /* 00 */ (const void *)&gVexTable_root_02_79_01_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_50_00_00_leaf, /* 01 */ ND_NULL, } }; -const ND_TABLE_VEX_PP gVexTable_root_02_79_pp = +const ND_TABLE_VEX_PP gVexTable_root_02_50_pp = { ND_ILUT_VEX_PP, { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_79_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, + /* 00 */ (const void *)&gVexTable_root_02_50_00_w, + /* 01 */ (const void *)&gVexTable_root_02_50_01_w, + /* 02 */ (const void *)&gVexTable_root_02_50_02_w, + /* 03 */ (const void *)&gVexTable_root_02_50_03_w, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_29_01_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_02_51_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2076] + (const void *)&gInstructions[2159] }; -const ND_TABLE_VEX_PP gVexTable_root_02_29_pp = +const ND_TABLE_VEX_W gVexTable_root_02_51_03_w = { - ND_ILUT_VEX_PP, + ND_ILUT_VEX_W, { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_29_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, + /* 00 */ (const void *)&gVexTable_root_02_51_03_00_leaf, + /* 01 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_37_01_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_02_51_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2086] + (const void *)&gInstructions[2161] }; -const ND_TABLE_VEX_PP gVexTable_root_02_37_pp = +const ND_TABLE_VEX_W gVexTable_root_02_51_02_w = { - ND_ILUT_VEX_PP, + ND_ILUT_VEX_W, { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_37_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, + /* 00 */ (const void *)&gVexTable_root_02_51_02_00_leaf, + /* 01 */ ND_NULL, } }; -const ND_TABLE_INSTRUCTION gVexTable_root_02_50_01_00_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_02_51_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2112] + (const void *)&gInstructions[2165] }; -const ND_TABLE_VEX_W gVexTable_root_02_50_01_w = +const ND_TABLE_VEX_W gVexTable_root_02_51_01_w = { ND_ILUT_VEX_W, { - /* 00 */ (const void *)&gVexTable_root_02_50_01_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_51_01_00_leaf, /* 01 */ ND_NULL, } }; -const ND_TABLE_VEX_PP gVexTable_root_02_50_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_50_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_51_01_00_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_02_51_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2114] + (const void *)&gInstructions[2167] }; -const ND_TABLE_VEX_W gVexTable_root_02_51_01_w = +const ND_TABLE_VEX_W gVexTable_root_02_51_00_w = { ND_ILUT_VEX_W, { - /* 00 */ (const void *)&gVexTable_root_02_51_01_00_leaf, + /* 00 */ (const void *)&gVexTable_root_02_51_00_00_leaf, /* 01 */ ND_NULL, } }; @@ -2586,17 +3500,17 @@ const ND_TABLE_VEX_PP gVexTable_root_02_51_pp = { ND_ILUT_VEX_PP, { - /* 00 */ ND_NULL, + /* 00 */ (const void *)&gVexTable_root_02_51_00_w, /* 01 */ (const void *)&gVexTable_root_02_51_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, + /* 02 */ (const void *)&gVexTable_root_02_51_02_w, + /* 03 */ (const void *)&gVexTable_root_02_51_03_w, } }; const ND_TABLE_INSTRUCTION gVexTable_root_02_52_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2116] + (const void *)&gInstructions[2169] }; const ND_TABLE_VEX_W gVexTable_root_02_52_01_w = @@ -2622,7 +3536,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_52_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_53_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2118] + (const void *)&gInstructions[2171] }; const ND_TABLE_VEX_W gVexTable_root_02_53_01_w = @@ -2648,7 +3562,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_53_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_36_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2123] + (const void *)&gInstructions[2176] }; const ND_TABLE_VEX_W gVexTable_root_02_36_01_01_w = @@ -2685,7 +3599,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_36_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2136] + (const void *)&gInstructions[2189] }; const ND_TABLE_VEX_W gVexTable_root_02_0d_01_w = @@ -2711,7 +3625,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2140] + (const void *)&gInstructions[2193] }; const ND_TABLE_VEX_W gVexTable_root_02_0c_01_w = @@ -2737,7 +3651,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_16_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2148] + (const void *)&gInstructions[2201] }; const ND_TABLE_VEX_W gVexTable_root_02_16_01_01_w = @@ -2774,13 +3688,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_16_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2178] + (const void *)&gInstructions[2235] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2180] + (const void *)&gInstructions[2237] }; const ND_TABLE_VEX_W gVexTable_root_02_90_01_mem_w = @@ -2815,13 +3729,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_90_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2182] + (const void *)&gInstructions[2239] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2184] + (const void *)&gInstructions[2241] }; const ND_TABLE_VEX_W gVexTable_root_02_91_01_mem_w = @@ -2856,7 +3770,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_91_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2188] + (const void *)&gInstructions[2245] }; const ND_TABLE_VEX_PP gVexTable_root_02_02_pp = @@ -2873,7 +3787,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_02_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2190] + (const void *)&gInstructions[2247] }; const ND_TABLE_VEX_PP gVexTable_root_02_03_pp = @@ -2890,7 +3804,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_03_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2197] + (const void *)&gInstructions[2254] }; const ND_TABLE_VEX_PP gVexTable_root_02_01_pp = @@ -2907,7 +3821,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_01_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_41_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2200] + (const void *)&gInstructions[2257] }; const ND_TABLE_VEX_L gVexTable_root_02_41_01_l = @@ -2935,7 +3849,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_41_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_06_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2202] + (const void *)&gInstructions[2259] }; const ND_TABLE_VEX_PP gVexTable_root_02_06_pp = @@ -2952,7 +3866,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_06_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_07_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2204] + (const void *)&gInstructions[2261] }; const ND_TABLE_VEX_PP gVexTable_root_02_07_pp = @@ -2969,7 +3883,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_07_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_05_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2205] + (const void *)&gInstructions[2262] }; const ND_TABLE_VEX_PP gVexTable_root_02_05_pp = @@ -2983,10 +3897,62 @@ const ND_TABLE_VEX_PP gVexTable_root_02_05_pp = } }; +const ND_TABLE_INSTRUCTION gVexTable_root_02_b5_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2291] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_b5_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_b5_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_b5_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_b5_01_w, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_b4_01_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2293] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_b4_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_b4_01_01_leaf, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_b4_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ ND_NULL, + /* 01 */ (const void *)&gVexTable_root_02_b4_01_w, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gVexTable_root_02_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2236] + (const void *)&gInstructions[2295] }; const ND_TABLE_VEX_PP gVexTable_root_02_04_pp = @@ -3003,13 +3969,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_04_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2239] + (const void *)&gInstructions[2298] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2241] + (const void *)&gInstructions[2300] }; const ND_TABLE_VEX_W gVexTable_root_02_8c_01_mem_w = @@ -3044,13 +4010,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2240] + (const void *)&gInstructions[2299] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2242] + (const void *)&gInstructions[2301] }; const ND_TABLE_VEX_W gVexTable_root_02_8e_01_mem_w = @@ -3085,7 +4051,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2244] + (const void *)&gInstructions[2303] }; const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp = @@ -3102,7 +4068,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2246] + (const void *)&gInstructions[2305] }; const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp = @@ -3119,7 +4085,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2253] + (const void *)&gInstructions[2312] }; const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp = @@ -3136,7 +4102,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2256] + (const void *)&gInstructions[2315] }; const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp = @@ -3153,7 +4119,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_38_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2258] + (const void *)&gInstructions[2317] }; const ND_TABLE_VEX_PP gVexTable_root_02_38_pp = @@ -3170,7 +4136,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_38_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_39_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2260] + (const void *)&gInstructions[2319] }; const ND_TABLE_VEX_PP gVexTable_root_02_39_pp = @@ -3187,7 +4153,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_39_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2267] + (const void *)&gInstructions[2326] }; const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp = @@ -3204,7 +4170,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2270] + (const void *)&gInstructions[2329] }; const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp = @@ -3221,13 +4187,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2291] + (const void *)&gInstructions[2350] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2292] + (const void *)&gInstructions[2351] }; const ND_TABLE_VEX_L gVexTable_root_02_21_01_l = @@ -3255,13 +4221,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_21_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2294] + (const void *)&gInstructions[2353] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2295] + (const void *)&gInstructions[2354] }; const ND_TABLE_VEX_L gVexTable_root_02_22_01_l = @@ -3289,13 +4255,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_22_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2297] + (const void *)&gInstructions[2356] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2298] + (const void *)&gInstructions[2357] }; const ND_TABLE_VEX_L gVexTable_root_02_20_01_l = @@ -3323,13 +4289,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_20_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2300] + (const void *)&gInstructions[2359] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2301] + (const void *)&gInstructions[2360] }; const ND_TABLE_VEX_L gVexTable_root_02_25_01_l = @@ -3357,13 +4323,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_25_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2303] + (const void *)&gInstructions[2362] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2304] + (const void *)&gInstructions[2363] }; const ND_TABLE_VEX_L gVexTable_root_02_23_01_l = @@ -3391,13 +4357,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_23_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2306] + (const void *)&gInstructions[2365] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2307] + (const void *)&gInstructions[2366] }; const ND_TABLE_VEX_L gVexTable_root_02_24_01_l = @@ -3425,13 +4391,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_24_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2317] + (const void *)&gInstructions[2376] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2318] + (const void *)&gInstructions[2377] }; const ND_TABLE_VEX_L gVexTable_root_02_31_01_l = @@ -3459,13 +4425,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_31_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2320] + (const void *)&gInstructions[2379] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2321] + (const void *)&gInstructions[2380] }; const ND_TABLE_VEX_L gVexTable_root_02_32_01_l = @@ -3493,13 +4459,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_32_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2323] + (const void *)&gInstructions[2382] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2324] + (const void *)&gInstructions[2383] }; const ND_TABLE_VEX_L gVexTable_root_02_30_01_l = @@ -3527,13 +4493,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_30_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2326] + (const void *)&gInstructions[2385] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2327] + (const void *)&gInstructions[2386] }; const ND_TABLE_VEX_L gVexTable_root_02_35_01_l = @@ -3561,13 +4527,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_35_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2329] + (const void *)&gInstructions[2388] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2330] + (const void *)&gInstructions[2389] }; const ND_TABLE_VEX_L gVexTable_root_02_33_01_l = @@ -3595,13 +4561,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_33_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2332] + (const void *)&gInstructions[2391] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2333] + (const void *)&gInstructions[2392] }; const ND_TABLE_VEX_L gVexTable_root_02_34_01_l = @@ -3629,7 +4595,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_34_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_28_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2335] + (const void *)&gInstructions[2394] }; const ND_TABLE_VEX_PP gVexTable_root_02_28_pp = @@ -3646,7 +4612,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_28_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2337] + (const void *)&gInstructions[2396] }; const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp = @@ -3663,7 +4629,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_40_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2343] + (const void *)&gInstructions[2402] }; const ND_TABLE_VEX_PP gVexTable_root_02_40_pp = @@ -3680,7 +4646,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_40_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2414] + (const void *)&gInstructions[2473] }; const ND_TABLE_VEX_PP gVexTable_root_02_00_pp = @@ -3697,7 +4663,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_00_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_08_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2422] + (const void *)&gInstructions[2481] }; const ND_TABLE_VEX_PP gVexTable_root_02_08_pp = @@ -3714,7 +4680,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_08_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2423] + (const void *)&gInstructions[2482] }; const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp = @@ -3731,7 +4697,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_09_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2424] + (const void *)&gInstructions[2483] }; const ND_TABLE_VEX_PP gVexTable_root_02_09_pp = @@ -3748,13 +4714,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_09_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2436] + (const void *)&gInstructions[2495] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2438] + (const void *)&gInstructions[2497] }; const ND_TABLE_VEX_W gVexTable_root_02_47_01_w = @@ -3780,7 +4746,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_47_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_46_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2451] + (const void *)&gInstructions[2510] }; const ND_TABLE_VEX_W gVexTable_root_02_46_01_w = @@ -3806,13 +4772,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_46_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2469] + (const void *)&gInstructions[2528] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2471] + (const void *)&gInstructions[2530] }; const ND_TABLE_VEX_W gVexTable_root_02_45_01_w = @@ -3838,7 +4804,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_45_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_17_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2495] + (const void *)&gInstructions[2554] }; const ND_TABLE_VEX_PP gVexTable_root_02_17_pp = @@ -3855,7 +4821,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_17_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2614] + (const void *)&gInstructions[2673] }; const ND_TABLE_VEX_W gVexTable_root_02_0f_01_w = @@ -3881,7 +4847,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2615] + (const void *)&gInstructions[2674] }; const ND_TABLE_VEX_W gVexTable_root_02_0e_01_w = @@ -4022,7 +4988,7 @@ const ND_TABLE_OPCODE gVexTable_root_02_opcode = /* 6f */ ND_NULL, /* 70 */ ND_NULL, /* 71 */ ND_NULL, - /* 72 */ ND_NULL, + /* 72 */ (const void *)&gVexTable_root_02_72_pp, /* 73 */ ND_NULL, /* 74 */ ND_NULL, /* 75 */ ND_NULL, @@ -4084,12 +5050,12 @@ const ND_TABLE_OPCODE gVexTable_root_02_opcode = /* ad */ (const void *)&gVexTable_root_02_ad_pp, /* ae */ (const void *)&gVexTable_root_02_ae_pp, /* af */ (const void *)&gVexTable_root_02_af_pp, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, + /* b0 */ (const void *)&gVexTable_root_02_b0_pp, + /* b1 */ (const void *)&gVexTable_root_02_b1_pp, /* b2 */ ND_NULL, /* b3 */ ND_NULL, - /* b4 */ ND_NULL, - /* b5 */ ND_NULL, + /* b4 */ (const void *)&gVexTable_root_02_b4_pp, + /* b5 */ (const void *)&gVexTable_root_02_b5_pp, /* b6 */ (const void *)&gVexTable_root_02_b6_pp, /* b7 */ (const void *)&gVexTable_root_02_b7_pp, /* b8 */ (const void *)&gVexTable_root_02_b8_pp, @@ -4132,22 +5098,22 @@ const ND_TABLE_OPCODE gVexTable_root_02_opcode = /* dd */ (const void *)&gVexTable_root_02_dd_pp, /* de */ (const void *)&gVexTable_root_02_de_pp, /* df */ (const void *)&gVexTable_root_02_df_pp, - /* e0 */ ND_NULL, - /* e1 */ ND_NULL, - /* e2 */ ND_NULL, - /* e3 */ ND_NULL, - /* e4 */ ND_NULL, - /* e5 */ ND_NULL, - /* e6 */ ND_NULL, - /* e7 */ ND_NULL, - /* e8 */ ND_NULL, - /* e9 */ ND_NULL, - /* ea */ ND_NULL, - /* eb */ ND_NULL, - /* ec */ ND_NULL, - /* ed */ ND_NULL, - /* ee */ ND_NULL, - /* ef */ ND_NULL, + /* e0 */ (const void *)&gVexTable_root_02_e0_pp, + /* e1 */ (const void *)&gVexTable_root_02_e1_pp, + /* e2 */ (const void *)&gVexTable_root_02_e2_pp, + /* e3 */ (const void *)&gVexTable_root_02_e3_pp, + /* e4 */ (const void *)&gVexTable_root_02_e4_pp, + /* e5 */ (const void *)&gVexTable_root_02_e5_pp, + /* e6 */ (const void *)&gVexTable_root_02_e6_pp, + /* e7 */ (const void *)&gVexTable_root_02_e7_pp, + /* e8 */ (const void *)&gVexTable_root_02_e8_pp, + /* e9 */ (const void *)&gVexTable_root_02_e9_pp, + /* ea */ (const void *)&gVexTable_root_02_ea_pp, + /* eb */ (const void *)&gVexTable_root_02_eb_pp, + /* ec */ (const void *)&gVexTable_root_02_ec_pp, + /* ed */ (const void *)&gVexTable_root_02_ed_pp, + /* ee */ (const void *)&gVexTable_root_02_ee_pp, + /* ef */ (const void *)&gVexTable_root_02_ef_pp, /* f0 */ ND_NULL, /* f1 */ ND_NULL, /* f2 */ (const void *)&gVexTable_root_02_f2_pp, @@ -4170,7 +5136,7 @@ const ND_TABLE_OPCODE gVexTable_root_02_opcode = const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[118] + (const void *)&gInstructions[122] }; const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_mem_modrmreg = @@ -4191,7 +5157,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_mem_modrmreg = const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1274] + (const void *)&gInstructions[1313] }; const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_reg_modrmreg = @@ -4221,7 +5187,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_02_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[119] + (const void *)&gInstructions[123] }; const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_mem_modrmreg = @@ -4242,7 +5208,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_mem_modrmreg = const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_02_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[218] + (const void *)&gInstructions[238] }; const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_reg_modrmreg = @@ -4272,13 +5238,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1831] + (const void *)&gInstructions[1878] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2603] + (const void *)&gInstructions[2662] }; const ND_TABLE_MODRM_REG gVexTable_root_01_ae_00_mem_modrmreg = @@ -4319,13 +5285,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ae_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[495] + (const void *)&gInstructions[515] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[496] + (const void *)&gInstructions[516] }; const ND_TABLE_VEX_W gVexTable_root_01_4a_01_reg_01_w = @@ -4360,13 +5326,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4a_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[497] + (const void *)&gInstructions[517] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[498] + (const void *)&gInstructions[518] }; const ND_TABLE_VEX_W gVexTable_root_01_4a_00_reg_01_w = @@ -4412,13 +5378,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_4a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[499] + (const void *)&gInstructions[519] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[500] + (const void *)&gInstructions[520] }; const ND_TABLE_VEX_W gVexTable_root_01_41_01_reg_01_w = @@ -4453,13 +5419,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_41_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[505] + (const void *)&gInstructions[525] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[506] + (const void *)&gInstructions[526] }; const ND_TABLE_VEX_W gVexTable_root_01_41_00_reg_01_w = @@ -4505,13 +5471,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_41_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[501] + (const void *)&gInstructions[521] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[502] + (const void *)&gInstructions[522] }; const ND_TABLE_VEX_W gVexTable_root_01_42_01_reg_01_w = @@ -4546,13 +5512,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_42_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[503] + (const void *)&gInstructions[523] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[504] + (const void *)&gInstructions[524] }; const ND_TABLE_VEX_W gVexTable_root_01_42_00_reg_01_w = @@ -4598,7 +5564,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_42_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_48_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[507] + (const void *)&gInstructions[527] }; const ND_TABLE_VEX_W gVexTable_root_01_48_00_reg_00_w = @@ -4644,7 +5610,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_48_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_49_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[508] + (const void *)&gInstructions[528] }; const ND_TABLE_VEX_W gVexTable_root_01_49_00_reg_00_w = @@ -4690,13 +5656,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_49_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[509] + (const void *)&gInstructions[529] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[514] + (const void *)&gInstructions[534] }; const ND_TABLE_VEX_W gVexTable_root_01_90_01_mem_00_w = @@ -4722,13 +5688,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[510] + (const void *)&gInstructions[530] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[515] + (const void *)&gInstructions[535] }; const ND_TABLE_VEX_W gVexTable_root_01_90_01_reg_00_w = @@ -4763,13 +5729,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_90_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[519] + (const void *)&gInstructions[539] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[524] + (const void *)&gInstructions[544] }; const ND_TABLE_VEX_W gVexTable_root_01_90_00_mem_00_w = @@ -4795,13 +5761,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_00_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[520] + (const void *)&gInstructions[540] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[525] + (const void *)&gInstructions[545] }; const ND_TABLE_VEX_W gVexTable_root_01_90_00_reg_00_w = @@ -4847,13 +5813,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_90_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[511] + (const void *)&gInstructions[531] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[516] + (const void *)&gInstructions[536] }; const ND_TABLE_VEX_W gVexTable_root_01_91_01_mem_00_w = @@ -4888,13 +5854,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_91_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[521] + (const void *)&gInstructions[541] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[526] + (const void *)&gInstructions[546] }; const ND_TABLE_VEX_W gVexTable_root_01_91_00_mem_00_w = @@ -4940,7 +5906,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_91_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_92_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[512] + (const void *)&gInstructions[532] }; const ND_TABLE_VEX_W gVexTable_root_01_92_01_reg_00_w = @@ -4975,13 +5941,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[517] + (const void *)&gInstructions[537] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[522] + (const void *)&gInstructions[542] }; const ND_TABLE_VEX_W gVexTable_root_01_92_03_reg_00_w = @@ -5016,7 +5982,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_92_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[527] + (const void *)&gInstructions[547] }; const ND_TABLE_VEX_W gVexTable_root_01_92_00_reg_00_w = @@ -5062,7 +6028,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_92_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_93_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[513] + (const void *)&gInstructions[533] }; const ND_TABLE_VEX_W gVexTable_root_01_93_01_reg_00_w = @@ -5097,13 +6063,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[518] + (const void *)&gInstructions[538] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[523] + (const void *)&gInstructions[543] }; const ND_TABLE_VEX_W gVexTable_root_01_93_03_reg_00_w = @@ -5138,7 +6104,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_93_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[528] + (const void *)&gInstructions[548] }; const ND_TABLE_VEX_W gVexTable_root_01_93_00_reg_00_w = @@ -5184,13 +6150,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_93_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[529] + (const void *)&gInstructions[549] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[530] + (const void *)&gInstructions[550] }; const ND_TABLE_VEX_W gVexTable_root_01_44_01_reg_00_w = @@ -5225,13 +6191,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_44_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[531] + (const void *)&gInstructions[551] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[532] + (const void *)&gInstructions[552] }; const ND_TABLE_VEX_W gVexTable_root_01_44_00_reg_00_w = @@ -5277,13 +6243,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_44_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[533] + (const void *)&gInstructions[553] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[534] + (const void *)&gInstructions[554] }; const ND_TABLE_VEX_W gVexTable_root_01_45_01_reg_01_w = @@ -5318,13 +6284,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_45_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[535] + (const void *)&gInstructions[555] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[540] + (const void *)&gInstructions[560] }; const ND_TABLE_VEX_W gVexTable_root_01_45_00_reg_01_w = @@ -5370,13 +6336,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_45_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[536] + (const void *)&gInstructions[556] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[537] + (const void *)&gInstructions[557] }; const ND_TABLE_VEX_W gVexTable_root_01_98_01_reg_00_w = @@ -5411,13 +6377,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_98_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[538] + (const void *)&gInstructions[558] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[539] + (const void *)&gInstructions[559] }; const ND_TABLE_VEX_W gVexTable_root_01_98_00_reg_00_w = @@ -5463,13 +6429,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_98_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[549] + (const void *)&gInstructions[569] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[550] + (const void *)&gInstructions[570] }; const ND_TABLE_VEX_W gVexTable_root_01_99_01_reg_00_w = @@ -5504,13 +6470,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_99_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[551] + (const void *)&gInstructions[571] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[552] + (const void *)&gInstructions[572] }; const ND_TABLE_VEX_W gVexTable_root_01_99_00_reg_00_w = @@ -5556,7 +6522,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_99_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[553] + (const void *)&gInstructions[573] }; const ND_TABLE_VEX_W gVexTable_root_01_4b_01_reg_01_w = @@ -5591,13 +6557,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4b_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[554] + (const void *)&gInstructions[574] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[555] + (const void *)&gInstructions[575] }; const ND_TABLE_VEX_W gVexTable_root_01_4b_00_reg_01_w = @@ -5643,13 +6609,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_4b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[556] + (const void *)&gInstructions[576] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[557] + (const void *)&gInstructions[577] }; const ND_TABLE_VEX_W gVexTable_root_01_46_01_reg_01_w = @@ -5684,13 +6650,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_46_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[558] + (const void *)&gInstructions[578] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[559] + (const void *)&gInstructions[579] }; const ND_TABLE_VEX_W gVexTable_root_01_46_00_reg_01_w = @@ -5736,13 +6702,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_46_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[560] + (const void *)&gInstructions[580] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[561] + (const void *)&gInstructions[581] }; const ND_TABLE_VEX_W gVexTable_root_01_47_01_reg_01_w = @@ -5777,13 +6743,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_47_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[562] + (const void *)&gInstructions[582] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[563] + (const void *)&gInstructions[583] }; const ND_TABLE_VEX_W gVexTable_root_01_47_00_reg_01_w = @@ -5829,25 +6795,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_47_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_58_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1361] + (const void *)&gInstructions[1401] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_58_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1364] + (const void *)&gInstructions[1404] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_58_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1366] + (const void *)&gInstructions[1406] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_58_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1369] + (const void *)&gInstructions[1409] }; const ND_TABLE_VEX_PP gVexTable_root_01_58_pp = @@ -5864,13 +6830,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_58_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1370] + (const void *)&gInstructions[1410] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1371] + (const void *)&gInstructions[1411] }; const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp = @@ -5887,13 +6853,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_55_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1385] + (const void *)&gInstructions[1425] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_55_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1387] + (const void *)&gInstructions[1427] }; const ND_TABLE_VEX_PP gVexTable_root_01_55_pp = @@ -5910,13 +6876,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_55_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_54_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1389] + (const void *)&gInstructions[1429] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_54_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1391] + (const void *)&gInstructions[1431] }; const ND_TABLE_VEX_PP gVexTable_root_01_54_pp = @@ -5933,25 +6899,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_54_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1415] + (const void *)&gInstructions[1457] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1418] + (const void *)&gInstructions[1460] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1420] + (const void *)&gInstructions[1462] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1423] + (const void *)&gInstructions[1465] }; const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp = @@ -5968,13 +6934,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1425] + (const void *)&gInstructions[1467] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1428] + (const void *)&gInstructions[1470] }; const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp = @@ -5991,13 +6957,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1432] + (const void *)&gInstructions[1474] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1433] + (const void *)&gInstructions[1475] }; const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l = @@ -6014,13 +6980,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1440] + (const void *)&gInstructions[1487] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1497] + (const void *)&gInstructions[1544] }; const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp = @@ -6037,19 +7003,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1436] + (const void *)&gInstructions[1478] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1460] + (const void *)&gInstructions[1507] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1508] + (const void *)&gInstructions[1555] }; const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp = @@ -6066,13 +7032,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1443] + (const void *)&gInstructions[1490] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1444] + (const void *)&gInstructions[1491] }; const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l = @@ -6089,13 +7055,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1462] + (const void *)&gInstructions[1509] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1463] + (const void *)&gInstructions[1510] }; const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l = @@ -6112,13 +7078,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1478] + (const void *)&gInstructions[1525] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1491] + (const void *)&gInstructions[1538] }; const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp = @@ -6135,13 +7101,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1476] + (const void *)&gInstructions[1523] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1494] + (const void *)&gInstructions[1541] }; const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp = @@ -6158,13 +7124,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1486] + (const void *)&gInstructions[1533] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1489] + (const void *)&gInstructions[1536] }; const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp = @@ -6181,13 +7147,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1513] + (const void *)&gInstructions[1560] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1518] + (const void *)&gInstructions[1565] }; const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp = @@ -6204,25 +7170,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1534] + (const void *)&gInstructions[1581] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1537] + (const void *)&gInstructions[1584] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1539] + (const void *)&gInstructions[1586] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1542] + (const void *)&gInstructions[1589] }; const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp = @@ -6239,13 +7205,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1812] + (const void *)&gInstructions[1859] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1813] + (const void *)&gInstructions[1860] }; const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp = @@ -6262,13 +7228,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1814] + (const void *)&gInstructions[1861] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1815] + (const void *)&gInstructions[1862] }; const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp = @@ -6285,7 +7251,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f0_03_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1830] + (const void *)&gInstructions[1877] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_f0_03_modrmmod = @@ -6311,7 +7277,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f7_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1832] + (const void *)&gInstructions[1879] }; const ND_TABLE_VEX_L gVexTable_root_01_f7_01_reg_l = @@ -6348,25 +7314,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1838] + (const void *)&gInstructions[1885] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1841] + (const void *)&gInstructions[1888] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1843] + (const void *)&gInstructions[1890] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1846] + (const void *)&gInstructions[1893] }; const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp = @@ -6383,25 +7349,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1853] + (const void *)&gInstructions[1900] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1856] + (const void *)&gInstructions[1903] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1858] + (const void *)&gInstructions[1905] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1861] + (const void *)&gInstructions[1908] }; const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp = @@ -6418,13 +7384,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_28_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1868] + (const void *)&gInstructions[1915] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_28_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1872] + (const void *)&gInstructions[1919] }; const ND_TABLE_VEX_PP gVexTable_root_01_28_pp = @@ -6441,13 +7407,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_28_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_29_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1869] + (const void *)&gInstructions[1916] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_29_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1873] + (const void *)&gInstructions[1920] }; const ND_TABLE_VEX_PP gVexTable_root_01_29_pp = @@ -6464,13 +7430,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_29_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1876] + (const void *)&gInstructions[1923] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1933] + (const void *)&gInstructions[1980] }; const ND_TABLE_VEX_W gVexTable_root_01_6e_01_00_wi = @@ -6507,13 +7473,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1877] + (const void *)&gInstructions[1924] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1934] + (const void *)&gInstructions[1981] }; const ND_TABLE_VEX_W gVexTable_root_01_7e_01_00_wi = @@ -6539,7 +7505,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_7e_01_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1935] + (const void *)&gInstructions[1982] }; const ND_TABLE_VEX_L gVexTable_root_01_7e_02_l = @@ -6567,13 +7533,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1881] + (const void *)&gInstructions[1928] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1882] + (const void *)&gInstructions[1929] }; const ND_TABLE_VEX_L gVexTable_root_01_12_03_l = @@ -6590,7 +7556,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_03_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1900] + (const void *)&gInstructions[1947] }; const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l = @@ -6607,7 +7573,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1917] + (const void *)&gInstructions[1964] }; const ND_TABLE_VEX_L gVexTable_root_01_12_00_mem_l = @@ -6633,7 +7599,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_00_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1913] + (const void *)&gInstructions[1960] }; const ND_TABLE_VEX_L gVexTable_root_01_12_01_mem_l = @@ -6659,7 +7625,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1952] + (const void *)&gInstructions[1999] }; const ND_TABLE_VEX_PP gVexTable_root_01_12_pp = @@ -6676,13 +7642,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_12_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1883] + (const void *)&gInstructions[1930] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1889] + (const void *)&gInstructions[1936] }; const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp = @@ -6699,13 +7665,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1884] + (const void *)&gInstructions[1931] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1890] + (const void *)&gInstructions[1937] }; const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp = @@ -6722,7 +7688,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_16_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1903] + (const void *)&gInstructions[1950] }; const ND_TABLE_VEX_L gVexTable_root_01_16_01_mem_l = @@ -6748,7 +7714,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1907] + (const void *)&gInstructions[1954] }; const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l = @@ -6765,7 +7731,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1910] + (const void *)&gInstructions[1957] }; const ND_TABLE_VEX_L gVexTable_root_01_16_00_reg_l = @@ -6791,7 +7757,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_00_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_16_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1950] + (const void *)&gInstructions[1997] }; const ND_TABLE_VEX_PP gVexTable_root_01_16_pp = @@ -6808,7 +7774,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_16_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_17_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1904] + (const void *)&gInstructions[1951] }; const ND_TABLE_VEX_L gVexTable_root_01_17_01_mem_l = @@ -6834,7 +7800,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_17_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_17_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1908] + (const void *)&gInstructions[1955] }; const ND_TABLE_VEX_L gVexTable_root_01_17_00_mem_l = @@ -6871,7 +7837,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_17_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_13_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1914] + (const void *)&gInstructions[1961] }; const ND_TABLE_VEX_L gVexTable_root_01_13_01_mem_l = @@ -6897,7 +7863,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_13_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_13_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1918] + (const void *)&gInstructions[1965] }; const ND_TABLE_VEX_L gVexTable_root_01_13_00_mem_l = @@ -6934,7 +7900,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_13_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_50_01_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1919] + (const void *)&gInstructions[1966] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod = @@ -6949,7 +7915,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_50_00_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1920] + (const void *)&gInstructions[1967] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_50_00_modrmmod = @@ -6975,7 +7941,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_50_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e7_01_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1922] + (const void *)&gInstructions[1969] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_e7_01_modrmmod = @@ -7001,7 +7967,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_01_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1926] + (const void *)&gInstructions[1973] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod = @@ -7016,7 +7982,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_00_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1928] + (const void *)&gInstructions[1975] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_00_modrmmod = @@ -7042,7 +8008,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1936] + (const void *)&gInstructions[1983] }; const ND_TABLE_VEX_L gVexTable_root_01_d6_01_l = @@ -7070,13 +8036,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1941] + (const void *)&gInstructions[1988] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1942] + (const void *)&gInstructions[1989] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod = @@ -7091,13 +8057,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1957] + (const void *)&gInstructions[2004] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1958] + (const void *)&gInstructions[2005] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod = @@ -7112,13 +8078,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_10_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1963] + (const void *)&gInstructions[2010] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_10_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1967] + (const void *)&gInstructions[2014] }; const ND_TABLE_VEX_PP gVexTable_root_01_10_pp = @@ -7135,13 +8101,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_10_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1943] + (const void *)&gInstructions[1990] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1944] + (const void *)&gInstructions[1991] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod = @@ -7156,13 +8122,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1959] + (const void *)&gInstructions[2006] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1960] + (const void *)&gInstructions[2007] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod = @@ -7177,13 +8143,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_11_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1964] + (const void *)&gInstructions[2011] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_11_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1968] + (const void *)&gInstructions[2015] }; const ND_TABLE_VEX_PP gVexTable_root_01_11_pp = @@ -7200,25 +8166,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_11_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_59_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1981] + (const void *)&gInstructions[2028] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_59_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1984] + (const void *)&gInstructions[2031] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_59_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1986] + (const void *)&gInstructions[2033] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_59_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1989] + (const void *)&gInstructions[2036] }; const ND_TABLE_VEX_PP gVexTable_root_01_59_pp = @@ -7235,13 +8201,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_59_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_56_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1994] + (const void *)&gInstructions[2041] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_56_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1996] + (const void *)&gInstructions[2043] }; const ND_TABLE_VEX_PP gVexTable_root_01_56_pp = @@ -7258,7 +8224,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_56_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2009] + (const void *)&gInstructions[2056] }; const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp = @@ -7275,7 +8241,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_63_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2011] + (const void *)&gInstructions[2058] }; const ND_TABLE_VEX_PP gVexTable_root_01_63_pp = @@ -7292,7 +8258,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_63_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_67_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2015] + (const void *)&gInstructions[2062] }; const ND_TABLE_VEX_PP gVexTable_root_01_67_pp = @@ -7309,7 +8275,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_67_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2017] + (const void *)&gInstructions[2064] }; const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp = @@ -7326,7 +8292,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fe_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2019] + (const void *)&gInstructions[2066] }; const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp = @@ -7343,7 +8309,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d4_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2021] + (const void *)&gInstructions[2068] }; const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp = @@ -7360,7 +8326,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ec_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2023] + (const void *)&gInstructions[2070] }; const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp = @@ -7377,7 +8343,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ed_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2025] + (const void *)&gInstructions[2072] }; const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp = @@ -7394,7 +8360,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_dc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2027] + (const void *)&gInstructions[2074] }; const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp = @@ -7411,7 +8377,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_dd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2029] + (const void *)&gInstructions[2076] }; const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp = @@ -7428,7 +8394,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2031] + (const void *)&gInstructions[2078] }; const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp = @@ -7445,7 +8411,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_db_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2034] + (const void *)&gInstructions[2081] }; const ND_TABLE_VEX_PP gVexTable_root_01_db_pp = @@ -7462,7 +8428,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_db_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_df_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2036] + (const void *)&gInstructions[2083] }; const ND_TABLE_VEX_PP gVexTable_root_01_df_pp = @@ -7479,7 +8445,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_df_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2041] + (const void *)&gInstructions[2088] }; const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp = @@ -7496,7 +8462,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2043] + (const void *)&gInstructions[2090] }; const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp = @@ -7513,7 +8479,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_74_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2072] + (const void *)&gInstructions[2119] }; const ND_TABLE_VEX_PP gVexTable_root_01_74_pp = @@ -7530,7 +8496,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_74_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_76_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2074] + (const void *)&gInstructions[2121] }; const ND_TABLE_VEX_PP gVexTable_root_01_76_pp = @@ -7547,7 +8513,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_76_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_75_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2078] + (const void *)&gInstructions[2125] }; const ND_TABLE_VEX_PP gVexTable_root_01_75_pp = @@ -7564,7 +8530,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_75_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_64_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2082] + (const void *)&gInstructions[2129] }; const ND_TABLE_VEX_PP gVexTable_root_01_64_pp = @@ -7581,7 +8547,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_64_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_66_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2084] + (const void *)&gInstructions[2131] }; const ND_TABLE_VEX_PP gVexTable_root_01_66_pp = @@ -7598,7 +8564,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_66_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_65_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2088] + (const void *)&gInstructions[2135] }; const ND_TABLE_VEX_PP gVexTable_root_01_65_pp = @@ -7615,7 +8581,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_65_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_c5_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2174] + (const void *)&gInstructions[2231] }; const ND_TABLE_VEX_L gVexTable_root_01_c5_01_reg_l = @@ -7652,7 +8618,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2217] + (const void *)&gInstructions[2274] }; const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l = @@ -7669,7 +8635,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2218] + (const void *)&gInstructions[2275] }; const ND_TABLE_VEX_L gVexTable_root_01_c4_01_reg_l = @@ -7706,7 +8672,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2238] + (const void *)&gInstructions[2297] }; const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp = @@ -7723,7 +8689,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ee_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2249] + (const void *)&gInstructions[2308] }; const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp = @@ -7740,7 +8706,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_de_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2251] + (const void *)&gInstructions[2310] }; const ND_TABLE_VEX_PP gVexTable_root_01_de_pp = @@ -7757,7 +8723,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_de_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ea_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2263] + (const void *)&gInstructions[2322] }; const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp = @@ -7774,7 +8740,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_da_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2265] + (const void *)&gInstructions[2324] }; const ND_TABLE_VEX_PP gVexTable_root_01_da_pp = @@ -7791,7 +8757,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_da_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d7_01_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2279] + (const void *)&gInstructions[2338] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_d7_01_modrmmod = @@ -7817,7 +8783,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e4_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2339] + (const void *)&gInstructions[2398] }; const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp = @@ -7834,7 +8800,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2341] + (const void *)&gInstructions[2400] }; const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp = @@ -7851,7 +8817,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2346] + (const void *)&gInstructions[2405] }; const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp = @@ -7868,7 +8834,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f4_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2349] + (const void *)&gInstructions[2408] }; const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp = @@ -7885,7 +8851,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_eb_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2354] + (const void *)&gInstructions[2413] }; const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp = @@ -7902,7 +8868,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2380] + (const void *)&gInstructions[2439] }; const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp = @@ -7919,19 +8885,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_70_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2417] + (const void *)&gInstructions[2476] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_70_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2419] + (const void *)&gInstructions[2478] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_70_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2421] + (const void *)&gInstructions[2480] }; const ND_TABLE_VEX_PP gVexTable_root_01_70_pp = @@ -7948,19 +8914,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_70_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2427] + (const void *)&gInstructions[2486] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2446] + (const void *)&gInstructions[2505] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2460] + (const void *)&gInstructions[2519] }; const ND_TABLE_MODRM_REG gVexTable_root_01_72_01_reg_modrmreg = @@ -8001,7 +8967,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_72_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2428] + (const void *)&gInstructions[2487] }; const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp = @@ -8018,25 +8984,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2430] + (const void *)&gInstructions[2489] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2433] + (const void *)&gInstructions[2492] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2463] + (const void *)&gInstructions[2522] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2466] + (const void *)&gInstructions[2525] }; const ND_TABLE_MODRM_REG gVexTable_root_01_73_01_reg_modrmreg = @@ -8077,7 +9043,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_73_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2434] + (const void *)&gInstructions[2493] }; const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp = @@ -8094,19 +9060,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2442] + (const void *)&gInstructions[2501] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2456] + (const void *)&gInstructions[2515] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2475] + (const void *)&gInstructions[2534] }; const ND_TABLE_MODRM_REG gVexTable_root_01_71_01_reg_modrmreg = @@ -8147,7 +9113,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_71_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2443] + (const void *)&gInstructions[2502] }; const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp = @@ -8164,7 +9130,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2447] + (const void *)&gInstructions[2506] }; const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp = @@ -8181,7 +9147,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2457] + (const void *)&gInstructions[2516] }; const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp = @@ -8198,7 +9164,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2461] + (const void *)&gInstructions[2520] }; const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp = @@ -8215,7 +9181,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2467] + (const void *)&gInstructions[2526] }; const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp = @@ -8232,7 +9198,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2476] + (const void *)&gInstructions[2535] }; const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp = @@ -8249,7 +9215,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2478] + (const void *)&gInstructions[2537] }; const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp = @@ -8266,7 +9232,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fa_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2480] + (const void *)&gInstructions[2539] }; const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp = @@ -8283,7 +9249,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fb_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2482] + (const void *)&gInstructions[2541] }; const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp = @@ -8300,7 +9266,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2484] + (const void *)&gInstructions[2543] }; const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp = @@ -8317,7 +9283,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2486] + (const void *)&gInstructions[2545] }; const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp = @@ -8334,7 +9300,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2488] + (const void *)&gInstructions[2547] }; const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp = @@ -8351,7 +9317,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2490] + (const void *)&gInstructions[2549] }; const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp = @@ -8368,7 +9334,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2492] + (const void *)&gInstructions[2551] }; const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp = @@ -8385,7 +9351,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_68_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2505] + (const void *)&gInstructions[2564] }; const ND_TABLE_VEX_PP gVexTable_root_01_68_pp = @@ -8402,7 +9368,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_68_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2507] + (const void *)&gInstructions[2566] }; const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp = @@ -8419,7 +9385,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2509] + (const void *)&gInstructions[2568] }; const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp = @@ -8436,7 +9402,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_69_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2511] + (const void *)&gInstructions[2570] }; const ND_TABLE_VEX_PP gVexTable_root_01_69_pp = @@ -8453,7 +9419,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_69_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_60_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2513] + (const void *)&gInstructions[2572] }; const ND_TABLE_VEX_PP gVexTable_root_01_60_pp = @@ -8470,7 +9436,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_60_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_62_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2515] + (const void *)&gInstructions[2574] }; const ND_TABLE_VEX_PP gVexTable_root_01_62_pp = @@ -8487,7 +9453,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_62_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2517] + (const void *)&gInstructions[2576] }; const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp = @@ -8504,7 +9470,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_61_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2519] + (const void *)&gInstructions[2578] }; const ND_TABLE_VEX_PP gVexTable_root_01_61_pp = @@ -8521,7 +9487,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_61_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ef_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2520] + (const void *)&gInstructions[2579] }; const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp = @@ -8538,13 +9504,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_53_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2536] + (const void *)&gInstructions[2595] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_53_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2538] + (const void *)&gInstructions[2597] }; const ND_TABLE_VEX_PP gVexTable_root_01_53_pp = @@ -8561,13 +9527,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_53_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_52_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2564] + (const void *)&gInstructions[2623] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_52_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2566] + (const void *)&gInstructions[2625] }; const ND_TABLE_VEX_PP gVexTable_root_01_52_pp = @@ -8584,13 +9550,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_52_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2590] + (const void *)&gInstructions[2649] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2592] + (const void *)&gInstructions[2651] }; const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp = @@ -8607,25 +9573,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_51_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2594] + (const void *)&gInstructions[2653] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_51_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2597] + (const void *)&gInstructions[2656] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_51_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2599] + (const void *)&gInstructions[2658] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_51_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2602] + (const void *)&gInstructions[2661] }; const ND_TABLE_VEX_PP gVexTable_root_01_51_pp = @@ -8642,25 +9608,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_51_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2605] + (const void *)&gInstructions[2664] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2608] + (const void *)&gInstructions[2667] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2610] + (const void *)&gInstructions[2669] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2613] + (const void *)&gInstructions[2672] }; const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp = @@ -8677,13 +9643,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2617] + (const void *)&gInstructions[2676] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2620] + (const void *)&gInstructions[2679] }; const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp = @@ -8700,13 +9666,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_15_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2622] + (const void *)&gInstructions[2681] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_15_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2624] + (const void *)&gInstructions[2683] }; const ND_TABLE_VEX_PP gVexTable_root_01_15_pp = @@ -8723,13 +9689,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_15_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_14_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2626] + (const void *)&gInstructions[2685] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_14_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2628] + (const void *)&gInstructions[2687] }; const ND_TABLE_VEX_PP gVexTable_root_01_14_pp = @@ -8746,13 +9712,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_14_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_57_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2630] + (const void *)&gInstructions[2689] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_57_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2632] + (const void *)&gInstructions[2691] }; const ND_TABLE_VEX_PP gVexTable_root_01_57_pp = @@ -8769,13 +9735,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_57_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2633] + (const void *)&gInstructions[2692] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2634] + (const void *)&gInstructions[2693] }; const ND_TABLE_VEX_L gVexTable_root_01_77_00_l = @@ -9066,13 +10032,13 @@ const ND_TABLE_OPCODE gVexTable_root_01_opcode = const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[541] + (const void *)&gInstructions[561] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[544] + (const void *)&gInstructions[564] }; const ND_TABLE_VEX_W gVexTable_root_03_32_01_reg_00_w = @@ -9118,13 +10084,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_32_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[542] + (const void *)&gInstructions[562] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[543] + (const void *)&gInstructions[563] }; const ND_TABLE_VEX_W gVexTable_root_03_33_01_reg_00_w = @@ -9170,13 +10136,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_33_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[545] + (const void *)&gInstructions[565] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[548] + (const void *)&gInstructions[568] }; const ND_TABLE_VEX_W gVexTable_root_03_30_01_reg_00_w = @@ -9222,13 +10188,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_30_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[546] + (const void *)&gInstructions[566] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[547] + (const void *)&gInstructions[567] }; const ND_TABLE_VEX_W gVexTable_root_03_31_01_reg_00_w = @@ -9274,7 +10240,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_31_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_f0_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1169] + (const void *)&gInstructions[1208] }; const ND_TABLE_VEX_L gVexTable_root_03_f0_03_l = @@ -9302,7 +10268,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_f0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_df_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1381] + (const void *)&gInstructions[1421] }; const ND_TABLE_VEX_L gVexTable_root_03_df_01_l = @@ -9330,7 +10296,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_df_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1394] + (const void *)&gInstructions[1436] }; const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp = @@ -9347,7 +10313,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1395] + (const void *)&gInstructions[1437] }; const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp = @@ -9364,7 +10330,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_4b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1396] + (const void *)&gInstructions[1438] }; const ND_TABLE_VEX_W gVexTable_root_03_4b_01_w = @@ -9390,7 +10356,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_4a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1397] + (const void *)&gInstructions[1439] }; const ND_TABLE_VEX_W gVexTable_root_03_4a_01_w = @@ -9416,7 +10382,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1465] + (const void *)&gInstructions[1512] }; const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w = @@ -9431,7 +10397,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w = const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1466] + (const void *)&gInstructions[1513] }; const ND_TABLE_VEX_W gVexTable_root_03_1d_01_01_w = @@ -9468,7 +10434,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_1d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_41_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1544] + (const void *)&gInstructions[1591] }; const ND_TABLE_VEX_L gVexTable_root_03_41_01_l = @@ -9496,7 +10462,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_41_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_40_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1545] + (const void *)&gInstructions[1592] }; const ND_TABLE_VEX_PP gVexTable_root_03_40_pp = @@ -9513,7 +10479,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_40_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_19_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1552] + (const void *)&gInstructions[1599] }; const ND_TABLE_VEX_W gVexTable_root_03_19_01_01_w = @@ -9550,7 +10516,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_19_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_39_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1557] + (const void *)&gInstructions[1604] }; const ND_TABLE_VEX_W gVexTable_root_03_39_01_01_w = @@ -9587,7 +10553,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_39_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1564] + (const void *)&gInstructions[1611] }; const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l = @@ -9604,7 +10570,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1565] + (const void *)&gInstructions[1612] }; const ND_TABLE_VEX_L gVexTable_root_03_17_01_reg_l = @@ -9641,13 +10607,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_17_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1606] + (const void *)&gInstructions[1653] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1607] + (const void *)&gInstructions[1654] }; const ND_TABLE_VEX_W gVexTable_root_03_69_01_w = @@ -9673,13 +10639,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_69_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1608] + (const void *)&gInstructions[1655] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1609] + (const void *)&gInstructions[1656] }; const ND_TABLE_VEX_W gVexTable_root_03_68_01_w = @@ -9705,13 +10671,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_68_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1610] + (const void *)&gInstructions[1657] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1611] + (const void *)&gInstructions[1658] }; const ND_TABLE_VEX_W gVexTable_root_03_6b_01_w = @@ -9737,13 +10703,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1612] + (const void *)&gInstructions[1659] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1613] + (const void *)&gInstructions[1660] }; const ND_TABLE_VEX_W gVexTable_root_03_6a_01_w = @@ -9769,13 +10735,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1629] + (const void *)&gInstructions[1676] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1630] + (const void *)&gInstructions[1677] }; const ND_TABLE_VEX_W gVexTable_root_03_5d_01_w = @@ -9801,13 +10767,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1631] + (const void *)&gInstructions[1678] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1632] + (const void *)&gInstructions[1679] }; const ND_TABLE_VEX_W gVexTable_root_03_5c_01_w = @@ -9833,13 +10799,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1678] + (const void *)&gInstructions[1725] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1679] + (const void *)&gInstructions[1726] }; const ND_TABLE_VEX_W gVexTable_root_03_5f_01_w = @@ -9865,13 +10831,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1680] + (const void *)&gInstructions[1727] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1681] + (const void *)&gInstructions[1728] }; const ND_TABLE_VEX_W gVexTable_root_03_5e_01_w = @@ -9897,13 +10863,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1682] + (const void *)&gInstructions[1729] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1683] + (const void *)&gInstructions[1730] }; const ND_TABLE_VEX_W gVexTable_root_03_6d_01_w = @@ -9929,13 +10895,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1684] + (const void *)&gInstructions[1731] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1685] + (const void *)&gInstructions[1732] }; const ND_TABLE_VEX_W gVexTable_root_03_6c_01_w = @@ -9961,13 +10927,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1686] + (const void *)&gInstructions[1733] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1687] + (const void *)&gInstructions[1734] }; const ND_TABLE_VEX_W gVexTable_root_03_6f_01_w = @@ -9993,13 +10959,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1688] + (const void *)&gInstructions[1735] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1689] + (const void *)&gInstructions[1736] }; const ND_TABLE_VEX_W gVexTable_root_03_6e_01_w = @@ -10025,13 +10991,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1722] + (const void *)&gInstructions[1769] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1723] + (const void *)&gInstructions[1770] }; const ND_TABLE_VEX_W gVexTable_root_03_79_01_w = @@ -10057,13 +11023,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_79_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1724] + (const void *)&gInstructions[1771] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1725] + (const void *)&gInstructions[1772] }; const ND_TABLE_VEX_W gVexTable_root_03_78_01_w = @@ -10089,13 +11055,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_78_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1726] + (const void *)&gInstructions[1773] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1727] + (const void *)&gInstructions[1774] }; const ND_TABLE_VEX_W gVexTable_root_03_7b_01_w = @@ -10121,13 +11087,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1728] + (const void *)&gInstructions[1775] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1729] + (const void *)&gInstructions[1776] }; const ND_TABLE_VEX_W gVexTable_root_03_7a_01_w = @@ -10153,13 +11119,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1760] + (const void *)&gInstructions[1807] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1761] + (const void *)&gInstructions[1808] }; const ND_TABLE_VEX_W gVexTable_root_03_7d_01_w = @@ -10185,13 +11151,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1762] + (const void *)&gInstructions[1809] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1763] + (const void *)&gInstructions[1810] }; const ND_TABLE_VEX_W gVexTable_root_03_7c_01_w = @@ -10217,13 +11183,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1764] + (const void *)&gInstructions[1811] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1765] + (const void *)&gInstructions[1812] }; const ND_TABLE_VEX_W gVexTable_root_03_7f_01_w = @@ -10249,13 +11215,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1766] + (const void *)&gInstructions[1813] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1767] + (const void *)&gInstructions[1814] }; const ND_TABLE_VEX_W gVexTable_root_03_7e_01_w = @@ -10281,7 +11247,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_cf_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1807] + (const void *)&gInstructions[1854] }; const ND_TABLE_VEX_W gVexTable_root_03_cf_01_w = @@ -10307,7 +11273,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_cf_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_ce_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1809] + (const void *)&gInstructions[1856] }; const ND_TABLE_VEX_W gVexTable_root_03_ce_01_w = @@ -10333,7 +11299,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_ce_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_18_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1816] + (const void *)&gInstructions[1863] }; const ND_TABLE_VEX_W gVexTable_root_03_18_01_01_w = @@ -10370,7 +11336,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_18_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_38_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1821] + (const void *)&gInstructions[1868] }; const ND_TABLE_VEX_W gVexTable_root_03_38_01_01_w = @@ -10407,7 +11373,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_38_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1828] + (const void *)&gInstructions[1875] }; const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l = @@ -10424,7 +11390,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1829] + (const void *)&gInstructions[1876] }; const ND_TABLE_VEX_L gVexTable_root_03_21_01_reg_l = @@ -10461,7 +11427,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_21_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_42_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1973] + (const void *)&gInstructions[2020] }; const ND_TABLE_VEX_PP gVexTable_root_03_42_pp = @@ -10478,7 +11444,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_42_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2033] + (const void *)&gInstructions[2080] }; const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp = @@ -10495,7 +11461,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_02_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2044] + (const void *)&gInstructions[2091] }; const ND_TABLE_VEX_W gVexTable_root_03_02_01_w = @@ -10521,7 +11487,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_02_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_4c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2049] + (const void *)&gInstructions[2096] }; const ND_TABLE_VEX_W gVexTable_root_03_4c_01_w = @@ -10547,7 +11513,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2050] + (const void *)&gInstructions[2097] }; const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp = @@ -10564,7 +11530,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_44_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2066] + (const void *)&gInstructions[2113] }; const ND_TABLE_VEX_PP gVexTable_root_03_44_pp = @@ -10581,7 +11547,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_44_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_61_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2079] + (const void *)&gInstructions[2126] }; const ND_TABLE_VEX_L gVexTable_root_03_61_01_l = @@ -10609,7 +11575,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_61_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_60_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2080] + (const void *)&gInstructions[2127] }; const ND_TABLE_VEX_L gVexTable_root_03_60_01_l = @@ -10637,7 +11603,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_60_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_63_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2089] + (const void *)&gInstructions[2136] }; const ND_TABLE_VEX_L gVexTable_root_03_63_01_l = @@ -10665,7 +11631,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_63_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_62_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2090] + (const void *)&gInstructions[2137] }; const ND_TABLE_VEX_L gVexTable_root_03_62_01_l = @@ -10693,7 +11659,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_62_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_06_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2119] + (const void *)&gInstructions[2172] }; const ND_TABLE_VEX_W gVexTable_root_03_06_01_01_w = @@ -10730,7 +11696,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_06_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_46_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2120] + (const void *)&gInstructions[2173] }; const ND_TABLE_VEX_W gVexTable_root_03_46_01_01_w = @@ -10767,13 +11733,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_46_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2130] + (const void *)&gInstructions[2183] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2131] + (const void *)&gInstructions[2184] }; const ND_TABLE_VEX_W gVexTable_root_03_49_01_w = @@ -10799,13 +11765,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_49_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2132] + (const void *)&gInstructions[2185] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2133] + (const void *)&gInstructions[2186] }; const ND_TABLE_VEX_W gVexTable_root_03_48_01_w = @@ -10831,7 +11797,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_48_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_05_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2137] + (const void *)&gInstructions[2190] }; const ND_TABLE_VEX_W gVexTable_root_03_05_01_w = @@ -10857,7 +11823,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_05_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_04_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2141] + (const void *)&gInstructions[2194] }; const ND_TABLE_VEX_W gVexTable_root_03_04_01_w = @@ -10883,7 +11849,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_04_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_01_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2145] + (const void *)&gInstructions[2198] }; const ND_TABLE_VEX_W gVexTable_root_03_01_01_01_w = @@ -10920,7 +11886,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_01_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_00_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2151] + (const void *)&gInstructions[2204] }; const ND_TABLE_VEX_W gVexTable_root_03_00_01_01_w = @@ -10957,7 +11923,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_00_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2165] + (const void *)&gInstructions[2218] }; const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l = @@ -10974,7 +11940,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2166] + (const void *)&gInstructions[2219] }; const ND_TABLE_VEX_L gVexTable_root_03_14_01_reg_l = @@ -11008,44 +11974,85 @@ const ND_TABLE_VEX_PP gVexTable_root_03_14_pp = } }; -const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_00_00_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_mem_00_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2222] +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_mem_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2226] +}; + +const ND_TABLE_VEX_W gVexTable_root_03_16_01_mem_00_wi = +{ + ND_ILUT_VEX_WI, + { + /* 00 */ (const void *)&gVexTable_root_03_16_01_mem_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_16_01_mem_00_01_leaf, + } +}; + +const ND_TABLE_VEX_L gVexTable_root_03_16_01_mem_l = +{ + ND_ILUT_VEX_L, + { + /* 00 */ (const void *)&gVexTable_root_03_16_01_mem_00_wi, + /* 01 */ ND_NULL, + /* 02 */ ND_NULL, + /* 03 */ ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2168] + (const void *)&gInstructions[2223] }; -const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_00_01_leaf = +const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2170] + (const void *)&gInstructions[2227] }; -const ND_TABLE_VEX_W gVexTable_root_03_16_01_00_wi = +const ND_TABLE_VEX_W gVexTable_root_03_16_01_reg_00_wi = { ND_ILUT_VEX_WI, { - /* 00 */ (const void *)&gVexTable_root_03_16_01_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_16_01_00_01_leaf, + /* 00 */ (const void *)&gVexTable_root_03_16_01_reg_00_00_leaf, + /* 01 */ (const void *)&gVexTable_root_03_16_01_reg_00_01_leaf, } }; -const ND_TABLE_VEX_L gVexTable_root_03_16_01_l = +const ND_TABLE_VEX_L gVexTable_root_03_16_01_reg_l = { ND_ILUT_VEX_L, { - /* 00 */ (const void *)&gVexTable_root_03_16_01_00_wi, + /* 00 */ (const void *)&gVexTable_root_03_16_01_reg_00_wi, /* 01 */ ND_NULL, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } }; +const ND_TABLE_MODRM_MOD gVexTable_root_03_16_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexTable_root_03_16_01_mem_l, + /* 01 */ (const void *)&gVexTable_root_03_16_01_reg_l, + } +}; + const ND_TABLE_VEX_PP gVexTable_root_03_16_pp = { ND_ILUT_VEX_PP, { /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_16_01_l, + /* 01 */ (const void *)&gVexTable_root_03_16_01_modrmmod, /* 02 */ ND_NULL, /* 03 */ ND_NULL, } @@ -11054,7 +12061,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_16_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2175] + (const void *)&gInstructions[2232] }; const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l = @@ -11071,7 +12078,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2176] + (const void *)&gInstructions[2233] }; const ND_TABLE_VEX_L gVexTable_root_03_15_01_reg_l = @@ -11108,7 +12115,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_15_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2209] + (const void *)&gInstructions[2266] }; const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l = @@ -11125,7 +12132,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2210] + (const void *)&gInstructions[2267] }; const ND_TABLE_VEX_L gVexTable_root_03_20_01_reg_l = @@ -11162,13 +12169,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_20_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2212] + (const void *)&gInstructions[2269] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2214] + (const void *)&gInstructions[2271] }; const ND_TABLE_VEX_W gVexTable_root_03_22_01_00_wi = @@ -11205,7 +12212,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_22_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_09_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2551] + (const void *)&gInstructions[2610] }; const ND_TABLE_VEX_PP gVexTable_root_03_09_pp = @@ -11222,7 +12229,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_09_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_08_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2552] + (const void *)&gInstructions[2611] }; const ND_TABLE_VEX_PP gVexTable_root_03_08_pp = @@ -11239,7 +12246,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_08_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2553] + (const void *)&gInstructions[2612] }; const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp = @@ -11256,7 +12263,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2554] + (const void *)&gInstructions[2613] }; const ND_TABLE_VEX_PP gVexTable_root_03_0a_pp = diff --git a/bddisasm/include/table_xop.h b/bddisasm/include/table_xop.h index 511747c..7f6f0ca 100644 --- a/bddisasm/include/table_xop.h +++ b/bddisasm/include/table_xop.h @@ -2,25 +2,30 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ + +// +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! +// + #ifndef TABLE_XOP_H #define TABLE_XOP_H const ND_TABLE_INSTRUCTION gXopTable_root_0a_10_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[64] + (const void *)&gInstructions[68] }; const ND_TABLE_INSTRUCTION gXopTable_root_0a_12_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[600] + (const void *)&gInstructions[620] }; const ND_TABLE_INSTRUCTION gXopTable_root_0a_12_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[601] + (const void *)&gInstructions[621] }; const ND_TABLE_MODRM_REG gXopTable_root_0a_12_modrmreg = @@ -304,43 +309,43 @@ const ND_TABLE_OPCODE gXopTable_root_0a_opcode = const ND_TABLE_INSTRUCTION gXopTable_root_09_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[65] + (const void *)&gInstructions[69] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_01_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[67] + (const void *)&gInstructions[71] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_01_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[69] + (const void *)&gInstructions[73] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_01_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[74] + (const void *)&gInstructions[78] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_01_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[76] + (const void *)&gInstructions[80] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1319] + (const void *)&gInstructions[1358] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1343] + (const void *)&gInstructions[1383] }; const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg = @@ -361,13 +366,13 @@ const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg = const ND_TABLE_INSTRUCTION gXopTable_root_09_02_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[66] + (const void *)&gInstructions[70] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[68] + (const void *)&gInstructions[72] }; const ND_TABLE_MODRM_REG gXopTable_root_09_02_modrmreg = @@ -388,13 +393,13 @@ const ND_TABLE_MODRM_REG gXopTable_root_09_02_modrmreg = const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[582] + (const void *)&gInstructions[602] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1270] + (const void *)&gInstructions[1309] }; const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg = @@ -424,127 +429,127 @@ const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod = const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1774] + (const void *)&gInstructions[1821] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1775] + (const void *)&gInstructions[1822] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1776] + (const void *)&gInstructions[1823] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1777] + (const void *)&gInstructions[1824] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2185] + (const void *)&gInstructions[2242] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2186] + (const void *)&gInstructions[2243] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2187] + (const void *)&gInstructions[2244] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2189] + (const void *)&gInstructions[2246] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2191] + (const void *)&gInstructions[2248] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2192] + (const void *)&gInstructions[2249] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2193] + (const void *)&gInstructions[2250] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2194] + (const void *)&gInstructions[2251] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2195] + (const void *)&gInstructions[2252] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2196] + (const void *)&gInstructions[2253] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2198] + (const void *)&gInstructions[2255] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2199] + (const void *)&gInstructions[2256] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2201] + (const void *)&gInstructions[2258] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2203] + (const void *)&gInstructions[2260] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2206] + (const void *)&gInstructions[2263] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2368] + (const void *)&gInstructions[2427] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2369] + (const void *)&gInstructions[2428] }; const ND_TABLE_VEX_W gXopTable_root_09_90_w = @@ -559,13 +564,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_90_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2371] + (const void *)&gInstructions[2430] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2372] + (const void *)&gInstructions[2431] }; const ND_TABLE_VEX_W gXopTable_root_09_92_w = @@ -580,13 +585,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_92_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2374] + (const void *)&gInstructions[2433] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2375] + (const void *)&gInstructions[2434] }; const ND_TABLE_VEX_W gXopTable_root_09_93_w = @@ -601,13 +606,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_93_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2377] + (const void *)&gInstructions[2436] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2378] + (const void *)&gInstructions[2437] }; const ND_TABLE_VEX_W gXopTable_root_09_91_w = @@ -622,13 +627,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_91_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2385] + (const void *)&gInstructions[2444] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2386] + (const void *)&gInstructions[2445] }; const ND_TABLE_VEX_W gXopTable_root_09_98_w = @@ -643,13 +648,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_98_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2387] + (const void *)&gInstructions[2446] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2388] + (const void *)&gInstructions[2447] }; const ND_TABLE_VEX_W gXopTable_root_09_9a_w = @@ -664,13 +669,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9a_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2389] + (const void *)&gInstructions[2448] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2390] + (const void *)&gInstructions[2449] }; const ND_TABLE_VEX_W gXopTable_root_09_9b_w = @@ -685,13 +690,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9b_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2391] + (const void *)&gInstructions[2450] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2392] + (const void *)&gInstructions[2451] }; const ND_TABLE_VEX_W gXopTable_root_09_99_w = @@ -706,13 +711,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_99_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2393] + (const void *)&gInstructions[2452] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2394] + (const void *)&gInstructions[2453] }; const ND_TABLE_VEX_W gXopTable_root_09_94_w = @@ -727,13 +732,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_94_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2395] + (const void *)&gInstructions[2454] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2406] + (const void *)&gInstructions[2465] }; const ND_TABLE_VEX_W gXopTable_root_09_95_w = @@ -748,13 +753,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_95_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2396] + (const void *)&gInstructions[2455] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2397] + (const void *)&gInstructions[2456] }; const ND_TABLE_VEX_W gXopTable_root_09_96_w = @@ -769,13 +774,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_96_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2404] + (const void *)&gInstructions[2463] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2405] + (const void *)&gInstructions[2464] }; const ND_TABLE_VEX_W gXopTable_root_09_97_w = @@ -1053,13 +1058,13 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode = const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2067] + (const void *)&gInstructions[2114] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2068] + (const void *)&gInstructions[2115] }; const ND_TABLE_VEX_W gXopTable_root_08_a2_w = @@ -1074,133 +1079,133 @@ const ND_TABLE_VEX_W gXopTable_root_08_a2_w = const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2097] + (const void *)&gInstructions[2144] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2098] + (const void *)&gInstructions[2145] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2103] + (const void *)&gInstructions[2150] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2104] + (const void *)&gInstructions[2151] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2105] + (const void *)&gInstructions[2152] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2106] + (const void *)&gInstructions[2153] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2107] + (const void *)&gInstructions[2154] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2108] + (const void *)&gInstructions[2155] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2221] + (const void *)&gInstructions[2278] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2222] + (const void *)&gInstructions[2279] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2223] + (const void *)&gInstructions[2280] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2224] + (const void *)&gInstructions[2281] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2225] + (const void *)&gInstructions[2282] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2226] + (const void *)&gInstructions[2283] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2227] + (const void *)&gInstructions[2284] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2228] + (const void *)&gInstructions[2285] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2229] + (const void *)&gInstructions[2286] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2230] + (const void *)&gInstructions[2287] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2231] + (const void *)&gInstructions[2288] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2232] + (const void *)&gInstructions[2289] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2357] + (const void *)&gInstructions[2416] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2358] + (const void *)&gInstructions[2417] }; const ND_TABLE_VEX_W gXopTable_root_08_a3_w = @@ -1215,25 +1220,25 @@ const ND_TABLE_VEX_W gXopTable_root_08_a3_w = const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2367] + (const void *)&gInstructions[2426] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2370] + (const void *)&gInstructions[2429] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2373] + (const void *)&gInstructions[2432] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2376] + (const void *)&gInstructions[2435] }; const ND_TABLE_OPCODE gXopTable_root_08_opcode = diff --git a/bddisasm/include/tabledefs.h b/bddisasm/include/tabledefs.h index f746270..7fff2b9 100644 --- a/bddisasm/include/tabledefs.h +++ b/bddisasm/include/tabledefs.h @@ -42,16 +42,19 @@ typedef enum _ND_ILUT_TYPE #define ND_ILUT_INDEX_MOD_MEM 0 #define ND_ILUT_INDEX_MOD_REG 1 +// Mandatory prefixes. #define ND_ILUT_INDEX_MAN_PREF_NONE 0 #define ND_ILUT_INDEX_MAN_PREF_66 1 #define ND_ILUT_INDEX_MAN_PREF_F3 2 #define ND_ILUT_INDEX_MAN_PREF_F2 3 +// Operating mode. #define ND_ILUT_INDEX_MODE_NONE 0 #define ND_ILUT_INDEX_MODE_16 1 #define ND_ILUT_INDEX_MODE_32 2 #define ND_ILUT_INDEX_MODE_64 3 +// Operand size. #define ND_ILUT_INDEX_DSIZE_NONE 0 #define ND_ILUT_INDEX_DSIZE_16 1 #define ND_ILUT_INDEX_DSIZE_32 2 @@ -59,22 +62,27 @@ typedef enum _ND_ILUT_TYPE #define ND_ILUT_INDEX_DSIZE_DEF64 4 #define ND_ILUT_INDEX_DSIZE_F64 5 +// Address size. #define ND_ILUT_INDEX_ASIZE_NONE 0 #define ND_ILUT_INDEX_ASIZE_16 1 #define ND_ILUT_INDEX_ASIZE_32 2 #define ND_ILUT_INDEX_ASIZE_64 3 +// Misc conditions. #define ND_ILUT_INDEX_AUX_NONE 0 #define ND_ILUT_INDEX_AUX_REXB 1 #define ND_ILUT_INDEX_AUX_REXW 2 #define ND_ILUT_INDEX_AUX_O64 3 #define ND_ILUT_INDEX_AUX_F3 4 #define ND_ILUT_INDEX_AUX_REP 5 +#define ND_ILUT_INDEX_AUX_RIPREL 6 +// Specific features for instructions that map on the wide NOP space. #define ND_ILUT_FEATURE_NONE 0 #define ND_ILUT_FEATURE_MPX 1 #define ND_ILUT_FEATURE_CET 2 #define ND_ILUT_FEATURE_CLDEMOTE 3 +#define ND_ILUT_FEATURE_PITI 4 @@ -126,7 +134,7 @@ typedef struct _ND_TABLE_MPREFIX typedef struct _ND_TABLE_AUXILIARY { ND_UINT32 Type; - const void *Table[6]; + const void *Table[8]; } ND_TABLE_AUXILIARY, *PND_TABLE_AUXILIARY; typedef struct _ND_TABLE_VENDOR @@ -138,7 +146,7 @@ typedef struct _ND_TABLE_VENDOR typedef struct _ND_TABLE_FEATURE { ND_UINT32 Type; - const void *Table[4]; + const void *Table[8]; } ND_TABLE_FEATURE; typedef struct _ND_TABLE_DSIZE @@ -319,6 +327,7 @@ typedef enum _ND_OPERAND_SIZE_SPEC ND_OPS_t, // Tile register size, can be up to 1K. ND_OPS_384, // 384 bit Key Locker handle. ND_OPS_512, // 512 bit Key Locker handle. + ND_OPS_4096, // 4096 bit MSR address/value table, used by RDMSRLIST/WRMSRLIST. // Stack sizes - indicates number of words. Also, hybrid sizes - sizes where from a large register (say 32 bit GPR) // only a smaller amount of data is used (for example, 8 bit). ND_OPS_v2, @@ -443,13 +452,15 @@ typedef enum _ND_OPERAND_TYPE_SPEC ND_OPT_SSE_XMM7, // Implicit memory operands. - ND_OPT_MEM_rAX, - ND_OPT_MEM_rCX, - ND_OPT_MEM_rBX_AL, - ND_OPT_MEM_rDI, - ND_OPT_MEM_SHS, - ND_OPT_MEM_SHSP, + ND_OPT_MEM_rAX, // [rAX] + ND_OPT_MEM_rCX, // [rCX] + ND_OPT_MEM_rBX_AL, // [rBX + AL] + ND_OPT_MEM_rDI, // [rDI] + ND_OPT_MEM_SHS, // Shadow stack. + ND_OPT_MEM_SHSP, // Shadow stack pointed by the SSP. ND_OPT_MEM_SHS0, + ND_OPT_MEM_SMSRT, // Source MSR table, encoded in [RSI]. + ND_OPT_MEM_DMSRT, // Destination MSR table, encoded in [RDI]. // Special immediates. ND_OPT_Im2z, diff --git a/bddisasm_test/test_all.py b/bddisasm_test/test_all.py index f58cefb..44eb73b 100644 --- a/bddisasm_test/test_all.py +++ b/bddisasm_test/test_all.py @@ -65,66 +65,77 @@ def test_dir(dir): global total_tests global failed_tests - for f in glob.glob('%s\\*' % dir): - if -1 == f.find('.'): - if 0 < f.find('_16'): - mod = '-b16' - elif 0 < f.find('_32'): - mod = '-b32' - else: - mod = '-b64' - if 0 < f.find('_r0'): - mod += ' -k' - if 0 < f.find('_skip'): - mod += ' -skip16' - - print(' * Running test case %s...' % f) - os.system('disasm -exi %s -f %s >%s.temp' % (mod, f, f)) - try: - res = open('%s.result' % f).read() - except: - print(' ! No result file provided for test %s!' % f) - - try: - tmp = open('%s.temp' % f).read() - except: - print(' ! No result produced by test %s!' % f) + for f in glob.glob('%s\\*.test' % dir): + base, _ = os.path.splitext(f) + + tst_file = f + res_file = base + '.result' + tmp_file = base + '.temp' + + if 0 < f.find('_16'): + mod = '-b16' + elif 0 < f.find('_32'): + mod = '-b32' + else: + mod = '-b64' + if 0 < f.find('_r0'): + mod += ' -k' - total_tests += 1 - if not compare_results(res, tmp): - print(' **** FAILED! ****') - failed_tests += 1 - else: - print(' * Passed.') - - for f in glob.glob('%s\\*_decoded.bin' % dir): - os.remove(f) - for f in glob.glob('%s\\*.temp' % dir): - os.remove(f) + if 0 < f.find('_skip'): + mod += ' -skip16' + + print(' * Running test case %s...' % f) + os.system('disasm -exi %s -f %s >%s' % (mod, tst_file, tmp_file)) + try: + res = open(res_file).read() + except: + print(' ! No result file provided for test %s!' % tst_file) + + try: + tmp = open(tmp_file).read() + except: + print(' ! No result produced by test %s!' % tst_file) + + total_tests += 1 + if not compare_results(res, tmp): + print(' **** FAILED! ****') + failed_tests += 1 + else: + print(' * Passed.') + + # Cleanup. + os.remove(tmp_file) def regenerate(dir): - for f in glob.glob('%s\\*' % dir): - if -1 == f.find('.'): - if 0 < f.find('_16'): - mod = '-b16' - elif 0 < f.find('_32'): - mod = '-b32' - else: - mod = '-b64' - if 0 < f.find('_r0'): - mod += ' -k' - if 0 < f.find('_skip'): - mod += ' -skip16' + for f in glob.glob('%s\\*.test' % dir): + base, _ = os.path.splitext(f) + + tst_file = f + res_file = base + '.result' + + if 0 < f.find('_16'): + mod = '-b16' + elif 0 < f.find('_32'): + mod = '-b32' + else: + mod = '-b64' + if 0 < f.find('_r0'): + mod += ' -k' + if 0 < f.find('_skip'): + mod += ' -skip16' - print(' * Regenerating test case %s...' % f) - os.system('disasm -exi %s -f %s >%s.result' % (mod, f, f)) - - for f in glob.glob('%s\\*_decoded.bin' % dir): - os.remove(f) + print(' * Regenerating test case %s...' % tst_file) + os.system('disasm -exi %s -f %s >%s' % (mod, tst_file, res_file)) -for dn in glob.glob("*"): - if not os.path.isdir(dn): - continue - print('Testing %s...' % dn) - test_dir(dn) -print("Ran %d tests, %d failed" % (total_tests, failed_tests)) \ No newline at end of file +if __name__ == "__main__": + for dn in glob.glob("x86\\*"): + if not os.path.isdir(dn): + continue + if "regenerate" in sys.argv: + print('Regenerating %s...' % dn) + regenerate(dn) + else: + print('Testing %s...' % dn) + test_dir(dn) + + print("Ran %d tests, %d failed" % (total_tests, failed_tests)) diff --git a/bddisasm_test/amx/amx1_64.asm b/bddisasm_test/x86/amx/amx1_64.asm similarity index 94% rename from bddisasm_test/amx/amx1_64.asm rename to bddisasm_test/x86/amx/amx1_64.asm index 81e0f68..27418e2 100644 --- a/bddisasm_test/amx/amx1_64.asm +++ b/bddisasm_test/x86/amx/amx1_64.asm @@ -21,3 +21,5 @@ db 0xc4, 0xe2, 0x78, 0x49, 0xC0 ; TILERELEASE db 0xc4, 0xe2, 0x7b, 0x49, 0xC0 ; TILEZERO tmm0 db 0xc4, 0xe2, 0x7b, 0x49, 0xf8 ; TILEZERO tmm7 + + db 0xc4, 0xe2, 0x7b, 0x5C, 0xF4 ; TDPFP16PS tmm6, tmm4, tmm0 \ No newline at end of file diff --git a/bddisasm_test/amx/amx1_64.result b/bddisasm_test/x86/amx/amx1_64.result similarity index 93% rename from bddisasm_test/amx/amx1_64.result rename to bddisasm_test/x86/amx/amx1_64.result index 2a5251b..cdca84c 100644 --- a/bddisasm_test/amx/amx1_64.result +++ b/bddisasm_test/x86/amx/amx1_64.result @@ -277,3 +277,21 @@ BND: no, BHINT: no, DNT: no Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 7, RegCount: 1 +0000000000000062 c4e27b5cf4 TDPFP16PS tmm6, tmm4, tmm0 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: AMX-FP16, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 21 + Exception class: AMX, exception type: AMX-E4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 4, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/amx/amx1_64 b/bddisasm_test/x86/amx/amx1_64.test similarity index 62% rename from bddisasm_test/amx/amx1_64 rename to bddisasm_test/x86/amx/amx1_64.test index 035ed72bbbbed5c64abc255faaeba81a2803b4a2..f2fc6bb7d21dd16657ac288b7636c7d1ade176c9 100644 GIT binary patch delta 10 RcmYdFpOD0Q*!Vn03cu)?EnA( literal 0 HcmV?d00001 diff --git a/bddisasm_test/x86/avx/avxneconvert_64.asm b/bddisasm_test/x86/avx/avxneconvert_64.asm new file mode 100644 index 0000000..d474fd1 --- /dev/null +++ b/bddisasm_test/x86/avx/avxneconvert_64.asm @@ -0,0 +1,20 @@ + bits 64 + + db 0xc4, 0xe2, 0x7a, 0xb1, 0x00 ; VBCSTNEBF162PS xmm0, word [rax] + db 0xc4, 0xe2, 0x7e, 0xb1, 0x00 ; VBCSTNEBF162PS ymm0, word [rax] + db 0xc4, 0xe2, 0x79, 0xb1, 0x00 ; VBCSTNESH2PS xmm0, word [rax] + db 0xc4, 0xe2, 0x7d, 0xb1, 0x00 ; VBCSTNESH2PS ymm0, word [rax] + db 0xc4, 0xe2, 0x7a, 0xb0, 0x00 ; VCVTNEEBF162PS xmm0, xmmword [rax] + db 0xc4, 0xe2, 0x7e, 0xb0, 0x00 ; VCVTNEEBF162PS ymm0, ymmword [rax] + db 0xc4, 0xe2, 0x79, 0xb0, 0x00 ; VCVTNEEPH2PS xmm0, xmmword [rax] + db 0xc4, 0xe2, 0x7d, 0xb0, 0x00 ; VCVTNEEPH2PS ymm0, ymmword [rax] + db 0xc4, 0xe2, 0x7b, 0xb0, 0x00 ; VCVTNEOBF162PS xmm0, xmmword [rax] + db 0xc4, 0xe2, 0x7f, 0xb0, 0x00 ; VCVTNEOBF162PS ymm0, ymmword [rax] + db 0xc4, 0xe2, 0x78, 0xb0, 0x00 ; VCVTNEOPH2PS xmm0, xmmword [rax] + db 0xc4, 0xe2, 0x7c, 0xb0, 0x00 ; VCVTNEOPH2PS ymm0, ymmword [rax] + + db 0xc4, 0xe2, 0x7a, 0x72, 0xC1 ; VCVTNEPS2BF16 xmm0, xmm1 + db 0xc4, 0xe2, 0x7e, 0x72, 0xC1 ; VCVTNEPS2BF16 ymm0, ymm1 + db 0xc4, 0xe2, 0x7a, 0x72, 0x00 ; VCVTNEPS2BF16 xmm0, [rax] + db 0xc4, 0xe2, 0x7e, 0x72, 0x00 ; VCVTNEPS2BF16 ymm0, [rax] + \ No newline at end of file diff --git a/bddisasm_test/x86/avx/avxneconvert_64.result b/bddisasm_test/x86/avx/avxneconvert_64.result new file mode 100644 index 0000000..db7fa54 --- /dev/null +++ b/bddisasm_test/x86/avx/avxneconvert_64.result @@ -0,0 +1,286 @@ +0000000000000000 c4e27ab100 VBCSTNEBF162PS xmm0, word ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 0, + +0000000000000005 c4e27eb100 VBCSTNEBF162PS ymm0, word ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 0, + +000000000000000A c4e279b100 VBCSTNESH2PS xmm0, word ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 0, + +000000000000000F c4e27db100 VBCSTNESH2PS ymm0, word ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 0, + +0000000000000014 c4e27ab000 VCVTNEEBF162PS xmm0, xmmword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 0, + +0000000000000019 c4e27eb000 VCVTNEEBF162PS ymm0, ymmword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 0, + +000000000000001E c4e279b000 VCVTNEEPH2PS xmm0, xmmword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 0, + +0000000000000023 c4e27db000 VCVTNEEPH2PS ymm0, ymmword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 0, + +0000000000000028 c4e27bb000 VCVTNEOBF162PS xmm0, xmmword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 0, + +000000000000002D c4e27fb000 VCVTNEOBF162PS ymm0, ymmword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 0, + +0000000000000032 c4e278b000 VCVTNEOPH2PS xmm0, xmmword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 0, + +0000000000000037 c4e27cb000 VCVTNEOPH2PS ymm0, ymmword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 0, + +000000000000003C c4e27a72c1 VCVTNEPS2BF16 xmm0, xmm1 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1 + +0000000000000041 c4e27e72c1 VCVTNEPS2BF16 ymm0, ymm1 + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 1, RegCount: 1 + +0000000000000046 c4e27a7200 VCVTNEPS2BF16 xmm0, xmmword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 0, + +000000000000004B c4e27e7200 VCVTNEPS2BF16 ymm0, ymmword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVXNECONVERT, Ins cat: AVXNECONVERT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 5 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 0, + diff --git a/bddisasm_test/x86/avx/avxneconvert_64.test b/bddisasm_test/x86/avx/avxneconvert_64.test new file mode 100644 index 0000000000000000000000000000000000000000..e7eab5129b4133d12e1c4e70396b98da12fe9cc7 GIT binary patch literal 80 zcmWm4$qfJ?3quW{go%!dPb?DH(zU!kyp@v#i6l$nNMX9FR L)RbzfO?{saC4?$v literal 0 HcmV?d00001 diff --git a/bddisasm_test/avx/f16c_64.asm b/bddisasm_test/x86/avx/f16c_64.asm similarity index 100% rename from bddisasm_test/avx/f16c_64.asm rename to bddisasm_test/x86/avx/f16c_64.asm diff --git a/bddisasm_test/avx/f16c_64.result b/bddisasm_test/x86/avx/f16c_64.result similarity index 100% rename from bddisasm_test/avx/f16c_64.result rename to bddisasm_test/x86/avx/f16c_64.result diff --git a/bddisasm_test/avx/f16c_64 b/bddisasm_test/x86/avx/f16c_64.test similarity index 100% rename from bddisasm_test/avx/f16c_64 rename to bddisasm_test/x86/avx/f16c_64.test diff --git a/bddisasm_test/avx/fma4_64.asm b/bddisasm_test/x86/avx/fma4_64.asm similarity index 100% rename from bddisasm_test/avx/fma4_64.asm rename to bddisasm_test/x86/avx/fma4_64.asm diff --git a/bddisasm_test/avx/fma4_64.result b/bddisasm_test/x86/avx/fma4_64.result similarity index 100% rename from bddisasm_test/avx/fma4_64.result rename to bddisasm_test/x86/avx/fma4_64.result diff --git a/bddisasm_test/avx/fma4_64 b/bddisasm_test/x86/avx/fma4_64.test similarity index 100% rename from bddisasm_test/avx/fma4_64 rename to bddisasm_test/x86/avx/fma4_64.test diff --git a/bddisasm_test/avx/fma_64.asm b/bddisasm_test/x86/avx/fma_64.asm similarity index 100% rename from bddisasm_test/avx/fma_64.asm rename to bddisasm_test/x86/avx/fma_64.asm diff --git a/bddisasm_test/avx/fma_64.result b/bddisasm_test/x86/avx/fma_64.result similarity index 100% rename from bddisasm_test/avx/fma_64.result rename to bddisasm_test/x86/avx/fma_64.result diff --git a/bddisasm_test/avx/fma_64 b/bddisasm_test/x86/avx/fma_64.test similarity index 100% rename from bddisasm_test/avx/fma_64 rename to bddisasm_test/x86/avx/fma_64.test diff --git a/bddisasm_test/avx512/avx512bitalg_64.asm b/bddisasm_test/x86/avx512/avx512bitalg_64.asm similarity index 100% rename from bddisasm_test/avx512/avx512bitalg_64.asm rename to bddisasm_test/x86/avx512/avx512bitalg_64.asm diff --git a/bddisasm_test/avx512/avx512bitalg_64.result b/bddisasm_test/x86/avx512/avx512bitalg_64.result similarity index 100% rename from bddisasm_test/avx512/avx512bitalg_64.result rename to bddisasm_test/x86/avx512/avx512bitalg_64.result diff --git a/bddisasm_test/avx512/avx512bitalg_64 b/bddisasm_test/x86/avx512/avx512bitalg_64.test similarity index 100% rename from bddisasm_test/avx512/avx512bitalg_64 rename to bddisasm_test/x86/avx512/avx512bitalg_64.test diff --git a/bddisasm_test/avx512/avx512bw_64.asm b/bddisasm_test/x86/avx512/avx512bw_64.asm similarity index 100% rename from bddisasm_test/avx512/avx512bw_64.asm rename to bddisasm_test/x86/avx512/avx512bw_64.asm diff --git a/bddisasm_test/avx512/avx512bw_64.result b/bddisasm_test/x86/avx512/avx512bw_64.result similarity index 99% rename from bddisasm_test/avx512/avx512bw_64.result rename to bddisasm_test/x86/avx512/avx512bw_64.result index 94f88c2..cebada5 100644 --- a/bddisasm_test/avx512/avx512bw_64.result +++ b/bddisasm_test/x86/avx512/avx512bw_64.result @@ -26460,8 +26460,8 @@ Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -0000000000002287 62f37d0814d10a VPEXTRB ecx, xmm2, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +0000000000002287 62f37d0814d10a VPEXTRB rcx, xmm2, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 EVEX Tuple Type: Tuple 1 scalar, 8 bit @@ -26475,12 +26475,12 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -000000000000228E 62f37d0814d10a VPEXTRB ecx, xmm2, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +000000000000228E 62f37d0814d10a VPEXTRB rcx, xmm2, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 EVEX Tuple Type: Tuple 1 scalar, 8 bit @@ -26494,12 +26494,12 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -0000000000002295 c4e37914d10a VPEXTRB ecx, xmm2, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +0000000000002295 c4e37914d10a VPEXTRB rcx, xmm2, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: AVX, Ins cat: AVX, CET tracked: no CPUID leaf: 0x00000001, reg: ecx, bit: 28 Exception class: SSE/VEX, exception type: 5 @@ -26512,12 +26512,12 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -000000000000229B c4e37914d10a VPEXTRB ecx, xmm2, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +000000000000229B c4e37914d10a VPEXTRB rcx, xmm2, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: AVX, Ins cat: AVX, CET tracked: no CPUID leaf: 0x00000001, reg: ecx, bit: 28 Exception class: SSE/VEX, exception type: 5 @@ -26530,12 +26530,12 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -00000000000022A1 62f37d0815c10a VPEXTRW ecx, xmm0, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +00000000000022A1 62f37d0815c10a VPEXTRW rcx, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 EVEX Tuple Type: Tuple 1 scalar, 16 bit @@ -26549,12 +26549,12 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -00000000000022A8 c5f9c5c80a VPEXTRW ecx, xmm0, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +00000000000022A8 c5f9c5c80a VPEXTRW rcx, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: AVX, Ins cat: AVX, CET tracked: no CPUID leaf: 0x00000001, reg: ecx, bit: 28 Exception class: SSE/VEX, exception type: 5 @@ -26567,12 +26567,12 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -00000000000022AD c5f9c5c80a VPEXTRW ecx, xmm0, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +00000000000022AD c5f9c5c80a VPEXTRW rcx, xmm0, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: AVX, Ins cat: AVX, CET tracked: no CPUID leaf: 0x00000001, reg: ecx, bit: 28 Exception class: SSE/VEX, exception type: 5 @@ -26585,7 +26585,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I @@ -26646,8 +26646,8 @@ Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -00000000000022CE 62f37d0815d10a VPEXTRW ecx, xmm2, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +00000000000022CE 62f37d0815d10a VPEXTRW rcx, xmm2, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30 EVEX Tuple Type: Tuple 1 scalar, 16 bit @@ -26661,12 +26661,12 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -00000000000022D5 c5f9c5ca0a VPEXTRW ecx, xmm2, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +00000000000022D5 c5f9c5ca0a VPEXTRW rcx, xmm2, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: AVX, Ins cat: AVX, CET tracked: no CPUID leaf: 0x00000001, reg: ecx, bit: 28 Exception class: SSE/VEX, exception type: 5 @@ -26679,12 +26679,12 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -00000000000022DA c5f9c5ca0a VPEXTRW ecx, xmm2, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +00000000000022DA c5f9c5ca0a VPEXTRW rcx, xmm2, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: AVX, Ins cat: AVX, CET tracked: no CPUID leaf: 0x00000001, reg: ecx, bit: 28 Exception class: SSE/VEX, exception type: 5 @@ -26697,7 +26697,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I diff --git a/bddisasm_test/avx512/avx512bw_64 b/bddisasm_test/x86/avx512/avx512bw_64.test similarity index 100% rename from bddisasm_test/avx512/avx512bw_64 rename to bddisasm_test/x86/avx512/avx512bw_64.test diff --git a/bddisasm_test/avx512/avx512cd_64.asm b/bddisasm_test/x86/avx512/avx512cd_64.asm similarity index 100% rename from bddisasm_test/avx512/avx512cd_64.asm rename to bddisasm_test/x86/avx512/avx512cd_64.asm diff --git a/bddisasm_test/avx512/avx512cd_64.result b/bddisasm_test/x86/avx512/avx512cd_64.result similarity index 100% rename from bddisasm_test/avx512/avx512cd_64.result rename to bddisasm_test/x86/avx512/avx512cd_64.result diff --git a/bddisasm_test/avx512/avx512cd_64 b/bddisasm_test/x86/avx512/avx512cd_64.test similarity index 100% rename from bddisasm_test/avx512/avx512cd_64 rename to bddisasm_test/x86/avx512/avx512cd_64.test diff --git a/bddisasm_test/avx512/avx512dq_64.asm b/bddisasm_test/x86/avx512/avx512dq_64.asm similarity index 100% rename from bddisasm_test/avx512/avx512dq_64.asm rename to bddisasm_test/x86/avx512/avx512dq_64.asm diff --git a/bddisasm_test/avx512/avx512dq_64.result b/bddisasm_test/x86/avx512/avx512dq_64.result similarity index 99% rename from bddisasm_test/avx512/avx512dq_64.result rename to bddisasm_test/x86/avx512/avx512dq_64.result index 49944d1..4d5a808 100644 --- a/bddisasm_test/avx512/avx512dq_64.result +++ b/bddisasm_test/x86/avx512/avx512dq_64.result @@ -22975,8 +22975,8 @@ Operand: 3, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0xfffffffffffffffc, -0000000000001D20 c4e37916d10a VPEXTRD ecx, xmm2, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +0000000000001D20 c4e37916d10a VPEXTRD rcx, xmm2, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: AVX, Ins cat: AVX, CET tracked: no CPUID leaf: 0x00000001, reg: ecx, bit: 28 Exception class: SSE/VEX, exception type: 5 @@ -22989,12 +22989,12 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -0000000000001D26 c4e37916d10a VPEXTRD ecx, xmm2, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +0000000000001D26 c4e37916d10a VPEXTRD rcx, xmm2, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: AVX, Ins cat: AVX, CET tracked: no CPUID leaf: 0x00000001, reg: ecx, bit: 28 Exception class: SSE/VEX, exception type: 5 @@ -23007,7 +23007,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I diff --git a/bddisasm_test/avx512/avx512dq_64 b/bddisasm_test/x86/avx512/avx512dq_64.test similarity index 100% rename from bddisasm_test/avx512/avx512dq_64 rename to bddisasm_test/x86/avx512/avx512dq_64.test diff --git a/bddisasm_test/avx512/avx512er_64.asm b/bddisasm_test/x86/avx512/avx512er_64.asm similarity index 100% rename from bddisasm_test/avx512/avx512er_64.asm rename to bddisasm_test/x86/avx512/avx512er_64.asm diff --git a/bddisasm_test/avx512/avx512er_64.result b/bddisasm_test/x86/avx512/avx512er_64.result similarity index 100% rename from bddisasm_test/avx512/avx512er_64.result rename to bddisasm_test/x86/avx512/avx512er_64.result diff --git a/bddisasm_test/avx512/avx512er_64 b/bddisasm_test/x86/avx512/avx512er_64.test similarity index 100% rename from bddisasm_test/avx512/avx512er_64 rename to bddisasm_test/x86/avx512/avx512er_64.test diff --git a/bddisasm_test/avx512/avx512f_64.asm b/bddisasm_test/x86/avx512/avx512f_64.asm similarity index 100% rename from bddisasm_test/avx512/avx512f_64.asm rename to bddisasm_test/x86/avx512/avx512f_64.asm diff --git a/bddisasm_test/avx512/avx512f_64.result b/bddisasm_test/x86/avx512/avx512f_64.result similarity index 100% rename from bddisasm_test/avx512/avx512f_64.result rename to bddisasm_test/x86/avx512/avx512f_64.result diff --git a/bddisasm_test/avx512/avx512f_64 b/bddisasm_test/x86/avx512/avx512f_64.test similarity index 100% rename from bddisasm_test/avx512/avx512f_64 rename to bddisasm_test/x86/avx512/avx512f_64.test diff --git a/bddisasm_test/avx512/avx512fma_64.asm b/bddisasm_test/x86/avx512/avx512fma_64.asm similarity index 100% rename from bddisasm_test/avx512/avx512fma_64.asm rename to bddisasm_test/x86/avx512/avx512fma_64.asm diff --git a/bddisasm_test/avx512/avx512fma_64.result b/bddisasm_test/x86/avx512/avx512fma_64.result similarity index 100% rename from bddisasm_test/avx512/avx512fma_64.result rename to bddisasm_test/x86/avx512/avx512fma_64.result diff --git a/bddisasm_test/avx512/avx512fma_64 b/bddisasm_test/x86/avx512/avx512fma_64.test similarity index 100% rename from bddisasm_test/avx512/avx512fma_64 rename to bddisasm_test/x86/avx512/avx512fma_64.test diff --git a/bddisasm_test/avx512/avx512fp16_32.result b/bddisasm_test/x86/avx512/avx512fp16_32.result similarity index 100% rename from bddisasm_test/avx512/avx512fp16_32.result rename to bddisasm_test/x86/avx512/avx512fp16_32.result diff --git a/bddisasm_test/avx512/avx512fp16_32 b/bddisasm_test/x86/avx512/avx512fp16_32.test similarity index 100% rename from bddisasm_test/avx512/avx512fp16_32 rename to bddisasm_test/x86/avx512/avx512fp16_32.test diff --git a/bddisasm_test/avx512/avx512fp16_64.result b/bddisasm_test/x86/avx512/avx512fp16_64.result similarity index 100% rename from bddisasm_test/avx512/avx512fp16_64.result rename to bddisasm_test/x86/avx512/avx512fp16_64.result diff --git a/bddisasm_test/avx512/avx512fp16_64 b/bddisasm_test/x86/avx512/avx512fp16_64.test similarity index 100% rename from bddisasm_test/avx512/avx512fp16_64 rename to bddisasm_test/x86/avx512/avx512fp16_64.test diff --git a/bddisasm_test/avx512/avx512pf_64.asm b/bddisasm_test/x86/avx512/avx512pf_64.asm similarity index 100% rename from bddisasm_test/avx512/avx512pf_64.asm rename to bddisasm_test/x86/avx512/avx512pf_64.asm diff --git a/bddisasm_test/avx512/avx512pf_64.result b/bddisasm_test/x86/avx512/avx512pf_64.result similarity index 100% rename from bddisasm_test/avx512/avx512pf_64.result rename to bddisasm_test/x86/avx512/avx512pf_64.result diff --git a/bddisasm_test/avx512/avx512pf_64 b/bddisasm_test/x86/avx512/avx512pf_64.test similarity index 100% rename from bddisasm_test/avx512/avx512pf_64 rename to bddisasm_test/x86/avx512/avx512pf_64.test diff --git a/bddisasm_test/avx512/avx512vbmi_64.asm b/bddisasm_test/x86/avx512/avx512vbmi_64.asm similarity index 100% rename from bddisasm_test/avx512/avx512vbmi_64.asm rename to bddisasm_test/x86/avx512/avx512vbmi_64.asm diff --git a/bddisasm_test/avx512/avx512vbmi_64.result b/bddisasm_test/x86/avx512/avx512vbmi_64.result similarity index 100% rename from bddisasm_test/avx512/avx512vbmi_64.result rename to bddisasm_test/x86/avx512/avx512vbmi_64.result diff --git a/bddisasm_test/avx512/avx512vbmi_64 b/bddisasm_test/x86/avx512/avx512vbmi_64.test similarity index 100% rename from bddisasm_test/avx512/avx512vbmi_64 rename to bddisasm_test/x86/avx512/avx512vbmi_64.test diff --git a/bddisasm_test/avx512/avx512vnni_64.asm b/bddisasm_test/x86/avx512/avx512vnni_64.asm similarity index 100% rename from bddisasm_test/avx512/avx512vnni_64.asm rename to bddisasm_test/x86/avx512/avx512vnni_64.asm diff --git a/bddisasm_test/avx512/avx512vnni_64.result b/bddisasm_test/x86/avx512/avx512vnni_64.result similarity index 100% rename from bddisasm_test/avx512/avx512vnni_64.result rename to bddisasm_test/x86/avx512/avx512vnni_64.result diff --git a/bddisasm_test/avx512/avx512vnni_64 b/bddisasm_test/x86/avx512/avx512vnni_64.test similarity index 100% rename from bddisasm_test/avx512/avx512vnni_64 rename to bddisasm_test/x86/avx512/avx512vnni_64.test diff --git a/bddisasm_test/basic/address_16.asm b/bddisasm_test/x86/basic/address_16.asm similarity index 100% rename from bddisasm_test/basic/address_16.asm rename to bddisasm_test/x86/basic/address_16.asm diff --git a/bddisasm_test/basic/address_16.result b/bddisasm_test/x86/basic/address_16.result similarity index 100% rename from bddisasm_test/basic/address_16.result rename to bddisasm_test/x86/basic/address_16.result diff --git a/bddisasm_test/basic/address_16 b/bddisasm_test/x86/basic/address_16.test similarity index 100% rename from bddisasm_test/basic/address_16 rename to bddisasm_test/x86/basic/address_16.test diff --git a/bddisasm_test/basic/address_32.asm b/bddisasm_test/x86/basic/address_32.asm similarity index 100% rename from bddisasm_test/basic/address_32.asm rename to bddisasm_test/x86/basic/address_32.asm diff --git a/bddisasm_test/basic/address_32.result b/bddisasm_test/x86/basic/address_32.result similarity index 100% rename from bddisasm_test/basic/address_32.result rename to bddisasm_test/x86/basic/address_32.result diff --git a/bddisasm_test/basic/address_32 b/bddisasm_test/x86/basic/address_32.test similarity index 100% rename from bddisasm_test/basic/address_32 rename to bddisasm_test/x86/basic/address_32.test diff --git a/bddisasm_test/basic/address_64.asm b/bddisasm_test/x86/basic/address_64.asm similarity index 100% rename from bddisasm_test/basic/address_64.asm rename to bddisasm_test/x86/basic/address_64.asm diff --git a/bddisasm_test/basic/address_64.result b/bddisasm_test/x86/basic/address_64.result similarity index 100% rename from bddisasm_test/basic/address_64.result rename to bddisasm_test/x86/basic/address_64.result diff --git a/bddisasm_test/basic/address_64 b/bddisasm_test/x86/basic/address_64.test similarity index 100% rename from bddisasm_test/basic/address_64 rename to bddisasm_test/x86/basic/address_64.test diff --git a/bddisasm_test/basic/aes_64.asm b/bddisasm_test/x86/basic/aes_64.asm similarity index 100% rename from bddisasm_test/basic/aes_64.asm rename to bddisasm_test/x86/basic/aes_64.asm diff --git a/bddisasm_test/basic/aes_64.result b/bddisasm_test/x86/basic/aes_64.result similarity index 100% rename from bddisasm_test/basic/aes_64.result rename to bddisasm_test/x86/basic/aes_64.result diff --git a/bddisasm_test/basic/aes_64 b/bddisasm_test/x86/basic/aes_64.test similarity index 100% rename from bddisasm_test/basic/aes_64 rename to bddisasm_test/x86/basic/aes_64.test diff --git a/bddisasm_test/basic/basic1_64.asm b/bddisasm_test/x86/basic/basic1_64.asm similarity index 100% rename from bddisasm_test/basic/basic1_64.asm rename to bddisasm_test/x86/basic/basic1_64.asm diff --git a/bddisasm_test/basic/basic1_64.result b/bddisasm_test/x86/basic/basic1_64.result similarity index 100% rename from bddisasm_test/basic/basic1_64.result rename to bddisasm_test/x86/basic/basic1_64.result diff --git a/bddisasm_test/basic/basic1_64 b/bddisasm_test/x86/basic/basic1_64.test similarity index 100% rename from bddisasm_test/basic/basic1_64 rename to bddisasm_test/x86/basic/basic1_64.test diff --git a/bddisasm_test/basic/basic2_64.asm b/bddisasm_test/x86/basic/basic2_64.asm similarity index 100% rename from bddisasm_test/basic/basic2_64.asm rename to bddisasm_test/x86/basic/basic2_64.asm diff --git a/bddisasm_test/basic/basic2_64.result b/bddisasm_test/x86/basic/basic2_64.result similarity index 100% rename from bddisasm_test/basic/basic2_64.result rename to bddisasm_test/x86/basic/basic2_64.result diff --git a/bddisasm_test/basic/basic2_64 b/bddisasm_test/x86/basic/basic2_64.test similarity index 100% rename from bddisasm_test/basic/basic2_64 rename to bddisasm_test/x86/basic/basic2_64.test diff --git a/bddisasm_test/basic/bmi_64.asm b/bddisasm_test/x86/basic/bmi_64.asm similarity index 100% rename from bddisasm_test/basic/bmi_64.asm rename to bddisasm_test/x86/basic/bmi_64.asm diff --git a/bddisasm_test/basic/bmi_64.result b/bddisasm_test/x86/basic/bmi_64.result similarity index 100% rename from bddisasm_test/basic/bmi_64.result rename to bddisasm_test/x86/basic/bmi_64.result diff --git a/bddisasm_test/basic/bmi_64 b/bddisasm_test/x86/basic/bmi_64.test similarity index 100% rename from bddisasm_test/basic/bmi_64 rename to bddisasm_test/x86/basic/bmi_64.test diff --git a/bddisasm_test/basic/branch_16.asm b/bddisasm_test/x86/basic/branch_16.asm similarity index 100% rename from bddisasm_test/basic/branch_16.asm rename to bddisasm_test/x86/basic/branch_16.asm diff --git a/bddisasm_test/basic/branch_16.result b/bddisasm_test/x86/basic/branch_16.result similarity index 100% rename from bddisasm_test/basic/branch_16.result rename to bddisasm_test/x86/basic/branch_16.result diff --git a/bddisasm_test/basic/branch_16 b/bddisasm_test/x86/basic/branch_16.test similarity index 100% rename from bddisasm_test/basic/branch_16 rename to bddisasm_test/x86/basic/branch_16.test diff --git a/bddisasm_test/basic/branch_32.asm b/bddisasm_test/x86/basic/branch_32.asm similarity index 100% rename from bddisasm_test/basic/branch_32.asm rename to bddisasm_test/x86/basic/branch_32.asm diff --git a/bddisasm_test/basic/branch_32.result b/bddisasm_test/x86/basic/branch_32.result similarity index 100% rename from bddisasm_test/basic/branch_32.result rename to bddisasm_test/x86/basic/branch_32.result diff --git a/bddisasm_test/basic/branch_32 b/bddisasm_test/x86/basic/branch_32.test similarity index 100% rename from bddisasm_test/basic/branch_32 rename to bddisasm_test/x86/basic/branch_32.test diff --git a/bddisasm_test/basic/branch_64.asm b/bddisasm_test/x86/basic/branch_64.asm similarity index 100% rename from bddisasm_test/basic/branch_64.asm rename to bddisasm_test/x86/basic/branch_64.asm diff --git a/bddisasm_test/basic/branch_64.result b/bddisasm_test/x86/basic/branch_64.result similarity index 100% rename from bddisasm_test/basic/branch_64.result rename to bddisasm_test/x86/basic/branch_64.result diff --git a/bddisasm_test/basic/branch_64 b/bddisasm_test/x86/basic/branch_64.test similarity index 100% rename from bddisasm_test/basic/branch_64 rename to bddisasm_test/x86/basic/branch_64.test diff --git a/bddisasm_test/basic/cet_64.asm b/bddisasm_test/x86/basic/cet_64.asm similarity index 100% rename from bddisasm_test/basic/cet_64.asm rename to bddisasm_test/x86/basic/cet_64.asm diff --git a/bddisasm_test/basic/cet_64.result b/bddisasm_test/x86/basic/cet_64.result similarity index 100% rename from bddisasm_test/basic/cet_64.result rename to bddisasm_test/x86/basic/cet_64.result diff --git a/bddisasm_test/basic/cet_64 b/bddisasm_test/x86/basic/cet_64.test similarity index 100% rename from bddisasm_test/basic/cet_64 rename to bddisasm_test/x86/basic/cet_64.test diff --git a/bddisasm_test/basic/enqcmd_64.asm b/bddisasm_test/x86/basic/enqcmd_64.asm similarity index 100% rename from bddisasm_test/basic/enqcmd_64.asm rename to bddisasm_test/x86/basic/enqcmd_64.asm diff --git a/bddisasm_test/basic/enqcmd_64.result b/bddisasm_test/x86/basic/enqcmd_64.result similarity index 100% rename from bddisasm_test/basic/enqcmd_64.result rename to bddisasm_test/x86/basic/enqcmd_64.result diff --git a/bddisasm_test/basic/enqcmd_64 b/bddisasm_test/x86/basic/enqcmd_64.test similarity index 100% rename from bddisasm_test/basic/enqcmd_64 rename to bddisasm_test/x86/basic/enqcmd_64.test diff --git a/bddisasm_test/basic/fpu_64.asm b/bddisasm_test/x86/basic/fpu_64.asm similarity index 100% rename from bddisasm_test/basic/fpu_64.asm rename to bddisasm_test/x86/basic/fpu_64.asm diff --git a/bddisasm_test/basic/fpu_64.result b/bddisasm_test/x86/basic/fpu_64.result similarity index 100% rename from bddisasm_test/basic/fpu_64.result rename to bddisasm_test/x86/basic/fpu_64.result diff --git a/bddisasm_test/basic/fpu_64 b/bddisasm_test/x86/basic/fpu_64.test similarity index 100% rename from bddisasm_test/basic/fpu_64 rename to bddisasm_test/x86/basic/fpu_64.test diff --git a/bddisasm_test/basic/gfni_64.asm b/bddisasm_test/x86/basic/gfni_64.asm similarity index 100% rename from bddisasm_test/basic/gfni_64.asm rename to bddisasm_test/x86/basic/gfni_64.asm diff --git a/bddisasm_test/basic/gfni_64.result b/bddisasm_test/x86/basic/gfni_64.result similarity index 100% rename from bddisasm_test/basic/gfni_64.result rename to bddisasm_test/x86/basic/gfni_64.result diff --git a/bddisasm_test/basic/gfni_64 b/bddisasm_test/x86/basic/gfni_64.test similarity index 100% rename from bddisasm_test/basic/gfni_64 rename to bddisasm_test/x86/basic/gfni_64.test diff --git a/bddisasm_test/basic/invlpgb_64.asm b/bddisasm_test/x86/basic/invlpgb_64.asm similarity index 100% rename from bddisasm_test/basic/invlpgb_64.asm rename to bddisasm_test/x86/basic/invlpgb_64.asm diff --git a/bddisasm_test/basic/invlpgb_64.result b/bddisasm_test/x86/basic/invlpgb_64.result similarity index 100% rename from bddisasm_test/basic/invlpgb_64.result rename to bddisasm_test/x86/basic/invlpgb_64.result diff --git a/bddisasm_test/basic/invlpgb_64 b/bddisasm_test/x86/basic/invlpgb_64.test similarity index 100% rename from bddisasm_test/basic/invlpgb_64 rename to bddisasm_test/x86/basic/invlpgb_64.test diff --git a/bddisasm_test/basic/misc_16.asm b/bddisasm_test/x86/basic/misc_16.asm similarity index 100% rename from bddisasm_test/basic/misc_16.asm rename to bddisasm_test/x86/basic/misc_16.asm diff --git a/bddisasm_test/basic/misc_16.result b/bddisasm_test/x86/basic/misc_16.result similarity index 100% rename from bddisasm_test/basic/misc_16.result rename to bddisasm_test/x86/basic/misc_16.result diff --git a/bddisasm_test/basic/misc_16 b/bddisasm_test/x86/basic/misc_16.test similarity index 100% rename from bddisasm_test/basic/misc_16 rename to bddisasm_test/x86/basic/misc_16.test diff --git a/bddisasm_test/basic/misc_32.asm b/bddisasm_test/x86/basic/misc_32.asm similarity index 100% rename from bddisasm_test/basic/misc_32.asm rename to bddisasm_test/x86/basic/misc_32.asm diff --git a/bddisasm_test/basic/misc_32.result b/bddisasm_test/x86/basic/misc_32.result similarity index 100% rename from bddisasm_test/basic/misc_32.result rename to bddisasm_test/x86/basic/misc_32.result diff --git a/bddisasm_test/basic/misc_32 b/bddisasm_test/x86/basic/misc_32.test similarity index 100% rename from bddisasm_test/basic/misc_32 rename to bddisasm_test/x86/basic/misc_32.test diff --git a/bddisasm_test/basic/misc_64.asm b/bddisasm_test/x86/basic/misc_64.asm similarity index 100% rename from bddisasm_test/basic/misc_64.asm rename to bddisasm_test/x86/basic/misc_64.asm diff --git a/bddisasm_test/basic/misc_64.result b/bddisasm_test/x86/basic/misc_64.result similarity index 100% rename from bddisasm_test/basic/misc_64.result rename to bddisasm_test/x86/basic/misc_64.result diff --git a/bddisasm_test/basic/misc_64 b/bddisasm_test/x86/basic/misc_64.test similarity index 100% rename from bddisasm_test/basic/misc_64 rename to bddisasm_test/x86/basic/misc_64.test diff --git a/bddisasm_test/basic/mpx_64.asm b/bddisasm_test/x86/basic/mpx_64.asm similarity index 100% rename from bddisasm_test/basic/mpx_64.asm rename to bddisasm_test/x86/basic/mpx_64.asm diff --git a/bddisasm_test/basic/mpx_64.result b/bddisasm_test/x86/basic/mpx_64.result similarity index 100% rename from bddisasm_test/basic/mpx_64.result rename to bddisasm_test/x86/basic/mpx_64.result diff --git a/bddisasm_test/basic/mpx_64 b/bddisasm_test/x86/basic/mpx_64.test similarity index 100% rename from bddisasm_test/basic/mpx_64 rename to bddisasm_test/x86/basic/mpx_64.test diff --git a/bddisasm_test/basic/prefixes_64.asm b/bddisasm_test/x86/basic/prefixes_64.asm similarity index 100% rename from bddisasm_test/basic/prefixes_64.asm rename to bddisasm_test/x86/basic/prefixes_64.asm diff --git a/bddisasm_test/basic/prefixes_64.result b/bddisasm_test/x86/basic/prefixes_64.result similarity index 100% rename from bddisasm_test/basic/prefixes_64.result rename to bddisasm_test/x86/basic/prefixes_64.result diff --git a/bddisasm_test/basic/prefixes_64 b/bddisasm_test/x86/basic/prefixes_64.test similarity index 100% rename from bddisasm_test/basic/prefixes_64 rename to bddisasm_test/x86/basic/prefixes_64.test diff --git a/bddisasm_test/basic/sha_64.asm b/bddisasm_test/x86/basic/sha_64.asm similarity index 100% rename from bddisasm_test/basic/sha_64.asm rename to bddisasm_test/x86/basic/sha_64.asm diff --git a/bddisasm_test/basic/sha_64.result b/bddisasm_test/x86/basic/sha_64.result similarity index 100% rename from bddisasm_test/basic/sha_64.result rename to bddisasm_test/x86/basic/sha_64.result diff --git a/bddisasm_test/basic/sha_64 b/bddisasm_test/x86/basic/sha_64.test similarity index 100% rename from bddisasm_test/basic/sha_64 rename to bddisasm_test/x86/basic/sha_64.test diff --git a/bddisasm_test/basic/snp_64.asm b/bddisasm_test/x86/basic/snp_64.asm similarity index 100% rename from bddisasm_test/basic/snp_64.asm rename to bddisasm_test/x86/basic/snp_64.asm diff --git a/bddisasm_test/basic/snp_64.result b/bddisasm_test/x86/basic/snp_64.result similarity index 100% rename from bddisasm_test/basic/snp_64.result rename to bddisasm_test/x86/basic/snp_64.result diff --git a/bddisasm_test/basic/snp_64 b/bddisasm_test/x86/basic/snp_64.test similarity index 100% rename from bddisasm_test/basic/snp_64 rename to bddisasm_test/x86/basic/snp_64.test diff --git a/bddisasm_test/basic/stack_16.asm b/bddisasm_test/x86/basic/stack_16.asm similarity index 100% rename from bddisasm_test/basic/stack_16.asm rename to bddisasm_test/x86/basic/stack_16.asm diff --git a/bddisasm_test/basic/stack_16.result b/bddisasm_test/x86/basic/stack_16.result similarity index 100% rename from bddisasm_test/basic/stack_16.result rename to bddisasm_test/x86/basic/stack_16.result diff --git a/bddisasm_test/basic/stack_16 b/bddisasm_test/x86/basic/stack_16.test similarity index 100% rename from bddisasm_test/basic/stack_16 rename to bddisasm_test/x86/basic/stack_16.test diff --git a/bddisasm_test/basic/stack_32.asm b/bddisasm_test/x86/basic/stack_32.asm similarity index 100% rename from bddisasm_test/basic/stack_32.asm rename to bddisasm_test/x86/basic/stack_32.asm diff --git a/bddisasm_test/basic/stack_32.result b/bddisasm_test/x86/basic/stack_32.result similarity index 100% rename from bddisasm_test/basic/stack_32.result rename to bddisasm_test/x86/basic/stack_32.result diff --git a/bddisasm_test/basic/stack_32 b/bddisasm_test/x86/basic/stack_32.test similarity index 100% rename from bddisasm_test/basic/stack_32 rename to bddisasm_test/x86/basic/stack_32.test diff --git a/bddisasm_test/basic/stack_64.asm b/bddisasm_test/x86/basic/stack_64.asm similarity index 100% rename from bddisasm_test/basic/stack_64.asm rename to bddisasm_test/x86/basic/stack_64.asm diff --git a/bddisasm_test/basic/stack_64.result b/bddisasm_test/x86/basic/stack_64.result similarity index 100% rename from bddisasm_test/basic/stack_64.result rename to bddisasm_test/x86/basic/stack_64.result diff --git a/bddisasm_test/basic/stack_64 b/bddisasm_test/x86/basic/stack_64.test similarity index 100% rename from bddisasm_test/basic/stack_64 rename to bddisasm_test/x86/basic/stack_64.test diff --git a/bddisasm_test/basic/svm_64.asm b/bddisasm_test/x86/basic/svm_64.asm similarity index 100% rename from bddisasm_test/basic/svm_64.asm rename to bddisasm_test/x86/basic/svm_64.asm diff --git a/bddisasm_test/basic/svm_64.result b/bddisasm_test/x86/basic/svm_64.result similarity index 100% rename from bddisasm_test/basic/svm_64.result rename to bddisasm_test/x86/basic/svm_64.result diff --git a/bddisasm_test/basic/svm_64 b/bddisasm_test/x86/basic/svm_64.test similarity index 100% rename from bddisasm_test/basic/svm_64 rename to bddisasm_test/x86/basic/svm_64.test diff --git a/bddisasm_test/basic/system_16.asm b/bddisasm_test/x86/basic/system_16.asm similarity index 100% rename from bddisasm_test/basic/system_16.asm rename to bddisasm_test/x86/basic/system_16.asm diff --git a/bddisasm_test/basic/system_16.result b/bddisasm_test/x86/basic/system_16.result similarity index 100% rename from bddisasm_test/basic/system_16.result rename to bddisasm_test/x86/basic/system_16.result diff --git a/bddisasm_test/basic/system_16 b/bddisasm_test/x86/basic/system_16.test similarity index 100% rename from bddisasm_test/basic/system_16 rename to bddisasm_test/x86/basic/system_16.test diff --git a/bddisasm_test/basic/system_32.asm b/bddisasm_test/x86/basic/system_32.asm similarity index 100% rename from bddisasm_test/basic/system_32.asm rename to bddisasm_test/x86/basic/system_32.asm diff --git a/bddisasm_test/basic/system_32.result b/bddisasm_test/x86/basic/system_32.result similarity index 100% rename from bddisasm_test/basic/system_32.result rename to bddisasm_test/x86/basic/system_32.result diff --git a/bddisasm_test/basic/system_32 b/bddisasm_test/x86/basic/system_32.test similarity index 100% rename from bddisasm_test/basic/system_32 rename to bddisasm_test/x86/basic/system_32.test diff --git a/bddisasm_test/basic/system_64.asm b/bddisasm_test/x86/basic/system_64.asm similarity index 100% rename from bddisasm_test/basic/system_64.asm rename to bddisasm_test/x86/basic/system_64.asm diff --git a/bddisasm_test/basic/system_64.result b/bddisasm_test/x86/basic/system_64.result similarity index 100% rename from bddisasm_test/basic/system_64.result rename to bddisasm_test/x86/basic/system_64.result diff --git a/bddisasm_test/basic/system_64 b/bddisasm_test/x86/basic/system_64.test similarity index 100% rename from bddisasm_test/basic/system_64 rename to bddisasm_test/x86/basic/system_64.test diff --git a/bddisasm_test/basic/tsx_64.asm b/bddisasm_test/x86/basic/tsx_64.asm similarity index 100% rename from bddisasm_test/basic/tsx_64.asm rename to bddisasm_test/x86/basic/tsx_64.asm diff --git a/bddisasm_test/basic/tsx_64.result b/bddisasm_test/x86/basic/tsx_64.result similarity index 100% rename from bddisasm_test/basic/tsx_64.result rename to bddisasm_test/x86/basic/tsx_64.result diff --git a/bddisasm_test/basic/tsx_64 b/bddisasm_test/x86/basic/tsx_64.test similarity index 100% rename from bddisasm_test/basic/tsx_64 rename to bddisasm_test/x86/basic/tsx_64.test diff --git a/bddisasm_test/basic/vmx_64.asm b/bddisasm_test/x86/basic/vmx_64.asm similarity index 100% rename from bddisasm_test/basic/vmx_64.asm rename to bddisasm_test/x86/basic/vmx_64.asm diff --git a/bddisasm_test/basic/vmx_64.result b/bddisasm_test/x86/basic/vmx_64.result similarity index 100% rename from bddisasm_test/basic/vmx_64.result rename to bddisasm_test/x86/basic/vmx_64.result diff --git a/bddisasm_test/basic/vmx_64 b/bddisasm_test/x86/basic/vmx_64.test similarity index 100% rename from bddisasm_test/basic/vmx_64 rename to bddisasm_test/x86/basic/vmx_64.test diff --git a/bddisasm_test/cet/cet_32.asm b/bddisasm_test/x86/cet/cet_32.asm similarity index 100% rename from bddisasm_test/cet/cet_32.asm rename to bddisasm_test/x86/cet/cet_32.asm diff --git a/bddisasm_test/cet/cet_32.result b/bddisasm_test/x86/cet/cet_32.result similarity index 100% rename from bddisasm_test/cet/cet_32.result rename to bddisasm_test/x86/cet/cet_32.result diff --git a/bddisasm_test/cet/cet_32 b/bddisasm_test/x86/cet/cet_32.test similarity index 100% rename from bddisasm_test/cet/cet_32 rename to bddisasm_test/x86/cet/cet_32.test diff --git a/bddisasm_test/cet/cet_64.asm b/bddisasm_test/x86/cet/cet_64.asm similarity index 100% rename from bddisasm_test/cet/cet_64.asm rename to bddisasm_test/x86/cet/cet_64.asm diff --git a/bddisasm_test/cet/cet_64.result b/bddisasm_test/x86/cet/cet_64.result similarity index 100% rename from bddisasm_test/cet/cet_64.result rename to bddisasm_test/x86/cet/cet_64.result diff --git a/bddisasm_test/cet/cet_64 b/bddisasm_test/x86/cet/cet_64.test similarity index 100% rename from bddisasm_test/cet/cet_64 rename to bddisasm_test/x86/cet/cet_64.test diff --git a/bddisasm_test/cet/dnt_32.asm b/bddisasm_test/x86/cet/dnt_32.asm similarity index 100% rename from bddisasm_test/cet/dnt_32.asm rename to bddisasm_test/x86/cet/dnt_32.asm diff --git a/bddisasm_test/cet/dnt_32.result b/bddisasm_test/x86/cet/dnt_32.result similarity index 100% rename from bddisasm_test/cet/dnt_32.result rename to bddisasm_test/x86/cet/dnt_32.result diff --git a/bddisasm_test/cet/dnt_32 b/bddisasm_test/x86/cet/dnt_32.test similarity index 100% rename from bddisasm_test/cet/dnt_32 rename to bddisasm_test/x86/cet/dnt_32.test diff --git a/bddisasm_test/cet/dnt_64.asm b/bddisasm_test/x86/cet/dnt_64.asm similarity index 100% rename from bddisasm_test/cet/dnt_64.asm rename to bddisasm_test/x86/cet/dnt_64.asm diff --git a/bddisasm_test/cet/dnt_64.result b/bddisasm_test/x86/cet/dnt_64.result similarity index 100% rename from bddisasm_test/cet/dnt_64.result rename to bddisasm_test/x86/cet/dnt_64.result diff --git a/bddisasm_test/cet/dnt_64 b/bddisasm_test/x86/cet/dnt_64.test similarity index 100% rename from bddisasm_test/cet/dnt_64 rename to bddisasm_test/x86/cet/dnt_64.test diff --git a/bddisasm_test/x86/cmpccxadd/cmpccxadd_64.asm b/bddisasm_test/x86/cmpccxadd/cmpccxadd_64.asm new file mode 100644 index 0000000..7bb9a3e --- /dev/null +++ b/bddisasm_test/x86/cmpccxadd/cmpccxadd_64.asm @@ -0,0 +1,49 @@ + bits 64 + + db 0xC4, 0x02, 0x79, 0xE0, 0x00 + db 0xC4, 0x02, 0xF9, 0xE0, 0x00 + + db 0xC4, 0x02, 0x79, 0xE1, 0x00 + db 0xC4, 0x02, 0xF9, 0xE1, 0x00 + + db 0xC4, 0x02, 0x79, 0xE2, 0x00 + db 0xC4, 0x02, 0xF9, 0xE2, 0x00 + + db 0xC4, 0x02, 0x79, 0xE3, 0x00 + db 0xC4, 0x02, 0xF9, 0xE3, 0x00 + + db 0xC4, 0x02, 0x79, 0xE4, 0x00 + db 0xC4, 0x02, 0xF9, 0xE4, 0x00 + + db 0xC4, 0x02, 0x79, 0xE5, 0x00 + db 0xC4, 0x02, 0xF9, 0xE5, 0x00 + + db 0xC4, 0x02, 0x79, 0xE6, 0x00 + db 0xC4, 0x02, 0xF9, 0xE6, 0x00 + + db 0xC4, 0x02, 0x79, 0xE7, 0x00 + db 0xC4, 0x02, 0xF9, 0xE7, 0x00 + + db 0xC4, 0x02, 0x79, 0xE8, 0x00 + db 0xC4, 0x02, 0xF9, 0xE8, 0x00 + + db 0xC4, 0x02, 0x79, 0xE9, 0x00 + db 0xC4, 0x02, 0xF9, 0xE9, 0x00 + + db 0xC4, 0x02, 0x79, 0xEA, 0x00 + db 0xC4, 0x02, 0xF9, 0xEA, 0x00 + + db 0xC4, 0x02, 0x79, 0xEB, 0x00 + db 0xC4, 0x02, 0xF9, 0xEB, 0x00 + + db 0xC4, 0x02, 0x79, 0xEC, 0x00 + db 0xC4, 0x02, 0xF9, 0xEC, 0x00 + + db 0xC4, 0x02, 0x79, 0xED, 0x00 + db 0xC4, 0x02, 0xF9, 0xED, 0x00 + + db 0xC4, 0x02, 0x79, 0xEE, 0x00 + db 0xC4, 0x02, 0xF9, 0xEE, 0x00 + + db 0xC4, 0x02, 0x79, 0xEF, 0x00 + db 0xC4, 0x02, 0xF9, 0xEF, 0x00 \ No newline at end of file diff --git a/bddisasm_test/x86/cmpccxadd/cmpccxadd_64.result b/bddisasm_test/x86/cmpccxadd/cmpccxadd_64.result new file mode 100644 index 0000000..0c3dff8 --- /dev/null +++ b/bddisasm_test/x86/cmpccxadd/cmpccxadd_64.result @@ -0,0 +1,704 @@ +0000000000000000 c40279e000 CMPOXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000005 c402f9e000 CMPOXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000000A c40279e100 CMPNOXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000F c402f9e100 CMPNOXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000014 c40279e200 CMPCXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000019 c402f9e200 CMPCXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000001E c40279e300 CMPNCXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000023 c402f9e300 CMPNCXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000028 c40279e400 CMPZXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000002D c402f9e400 CMPZXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000032 c40279e500 CMPNZXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000037 c402f9e500 CMPNZXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000003C c40279e600 CMPBEXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000041 c402f9e600 CMPBEXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000046 c40279e700 CMPNBEXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000004B c402f9e700 CMPNBEXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000050 c40279e800 CMPSXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000055 c402f9e800 CMPSXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000005A c40279e900 CMPNSXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000005F c402f9e900 CMPNSXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000064 c40279ea00 CMPPXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000069 c402f9ea00 CMPPXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000006E c40279eb00 CMPNPXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000073 c402f9eb00 CMPNPXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000078 c40279ec00 CMPLXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000007D c402f9ec00 CMPLXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000082 c40279ed00 CMPNLXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000087 c402f9ed00 CMPNLXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000008C c40279ee00 CMPLEXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000091 c402f9ee00 CMPLEXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000096 c40279ef00 CMPNLEXADD dword ptr [r8], r8d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000009B c402f9ef00 CMPNLEXADD qword ptr [r8], r8, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: CMPCCXADD, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 7 + Exception class: EVEX, exception type: E6NF + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 8, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 8, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/x86/cmpccxadd/cmpccxadd_64.test b/bddisasm_test/x86/cmpccxadd/cmpccxadd_64.test new file mode 100644 index 0000000000000000000000000000000000000000..54d79b4945aad2aa24dcae64268efe147d6c7b53 GIT binary patch literal 160 zcmWm0xeb6Y00c0Ut#7{!!v8~RI^@Q3E$O>jK4dUtG-NVlHe@kmHDohnH{>wnG~_bm MHsmqnHKbYVeh)BA(EtDd literal 0 HcmV?d00001 diff --git a/bddisasm_test/fred/fred_64.asm b/bddisasm_test/x86/fred/fred_64.asm similarity index 100% rename from bddisasm_test/fred/fred_64.asm rename to bddisasm_test/x86/fred/fred_64.asm diff --git a/bddisasm_test/fred/fred_64.result b/bddisasm_test/x86/fred/fred_64.result similarity index 100% rename from bddisasm_test/fred/fred_64.result rename to bddisasm_test/x86/fred/fred_64.result diff --git a/bddisasm_test/fred/fred_64 b/bddisasm_test/x86/fred/fred_64.test similarity index 100% rename from bddisasm_test/fred/fred_64 rename to bddisasm_test/x86/fred/fred_64.test diff --git a/bddisasm_test/kl/kl_64.asm b/bddisasm_test/x86/kl/kl_64.asm similarity index 100% rename from bddisasm_test/kl/kl_64.asm rename to bddisasm_test/x86/kl/kl_64.asm diff --git a/bddisasm_test/kl/kl_64.result b/bddisasm_test/x86/kl/kl_64.result similarity index 100% rename from bddisasm_test/kl/kl_64.result rename to bddisasm_test/x86/kl/kl_64.result diff --git a/bddisasm_test/kl/kl_64 b/bddisasm_test/x86/kl/kl_64.test similarity index 100% rename from bddisasm_test/kl/kl_64 rename to bddisasm_test/x86/kl/kl_64.test diff --git a/bddisasm_test/x86/msr/msr_64.asm b/bddisasm_test/x86/msr/msr_64.asm new file mode 100644 index 0000000..2a96790 --- /dev/null +++ b/bddisasm_test/x86/msr/msr_64.asm @@ -0,0 +1,5 @@ + bits 64 + + db 0xF2, 0x0F, 0x01, 0xC6 ; RDMSRLIST + db 0xF3, 0x0F, 0x01, 0xC6 ; WRMSRLIST + db 0x0F, 0x01, 0xC6 ; WRMSRNS \ No newline at end of file diff --git a/bddisasm_test/x86/msr/msr_64.result b/bddisasm_test/x86/msr/msr_64.result new file mode 100644 index 0000000..2425a59 --- /dev/null +++ b/bddisasm_test/x86/msr/msr_64.result @@ -0,0 +1,56 @@ +0000000000000000 f20f01c6 RDMSRLIST + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MSRLIST, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 27 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 512, RawSize: 512, Encoding: S, + Base: 6, + Operand: 1, Acc: -W, Type: Memory, Size: 512, RawSize: 512, Encoding: S, + Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000004 f30f01c6 WRMSRLIST + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: MSRLIST, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 27 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 512, RawSize: 512, Encoding: S, + Base: 6, + Operand: 1, Acc: R-, Type: Memory, Size: 512, RawSize: 512, Encoding: S, + Base: 7, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + +0000000000000008 0f01c6 WRMSRNS + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: WRMSRNS, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 19 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1 + diff --git a/bddisasm_test/x86/msr/msr_64.test b/bddisasm_test/x86/msr/msr_64.test new file mode 100644 index 0000000..81baf59 --- /dev/null +++ b/bddisasm_test/x86/msr/msr_64.test @@ -0,0 +1 @@ +òÆóÆÆ \ No newline at end of file diff --git a/bddisasm_test/x86/prefetchit/prefetchit_32.asm b/bddisasm_test/x86/prefetchit/prefetchit_32.asm new file mode 100644 index 0000000..2a2401d --- /dev/null +++ b/bddisasm_test/x86/prefetchit/prefetchit_32.asm @@ -0,0 +1,4 @@ + bits 32 + + db 0x0F, 0x18, 0x38 ; NOP dword ptr [eax] + db 0x0F, 0x18, 0x3D, 0x90, 0x90, 0x90, 0x90 ; NOP dword ptr [0x90909090] \ No newline at end of file diff --git a/bddisasm_test/x86/prefetchit/prefetchit_32.result b/bddisasm_test/x86/prefetchit/prefetchit_32.result new file mode 100644 index 0000000..56466cf --- /dev/null +++ b/bddisasm_test/x86/prefetchit/prefetchit_32.result @@ -0,0 +1,30 @@ +0000000000000000 0f1838 NOP dword ptr [eax] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: PPRO, Ins cat: WIDENOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + +0000000000000003 0f183d90909090 NOP dword ptr [0x90909090] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: PPRO, Ins cat: WIDENOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Displacement: 0xffffffff90909090, + diff --git a/bddisasm_test/x86/prefetchit/prefetchit_32.test b/bddisasm_test/x86/prefetchit/prefetchit_32.test new file mode 100644 index 0000000..49b03a5 --- /dev/null +++ b/bddisasm_test/x86/prefetchit/prefetchit_32.test @@ -0,0 +1 @@ +8= \ No newline at end of file diff --git a/bddisasm_test/x86/prefetchit/prefetchit_64.asm b/bddisasm_test/x86/prefetchit/prefetchit_64.asm new file mode 100644 index 0000000..4eb9412 --- /dev/null +++ b/bddisasm_test/x86/prefetchit/prefetchit_64.asm @@ -0,0 +1,11 @@ + bits 64 + + db 0x0F, 0x18, 0xF8 ; NOP eax + db 0x0F, 0x18, 0x38 ; NOP dword ptr [rax] + db 0x0F, 0x18, 0x3D, 0x90, 0x90, 0x90, 0x90 ; PREFETCHIT0 byte ptr [rel 0xffffffff9090909d] + db 0x67, 0x0F, 0x18, 0x3D, 0x90, 0x90, 0x90, 0x90 ; PREFETCHIT0 byte ptr [rel 0x909090a5] + + db 0x0F, 0x18, 0xF0 ; NOP eax + db 0x0F, 0x18, 0x30 ; NOP dword ptr [rax] + db 0x0F, 0x18, 0x35, 0x90, 0x90, 0x90, 0x90 ; PREFETCHIT1 byte ptr [rel 0xffffffff909090b2] + db 0x67, 0x0F, 0x18, 0x35, 0x90, 0x90, 0x90, 0x90 ; PREFETCHIT1 byte ptr [rel 0x909090ba] \ No newline at end of file diff --git a/bddisasm_test/x86/prefetchit/prefetchit_64.result b/bddisasm_test/x86/prefetchit/prefetchit_64.result new file mode 100644 index 0000000..f9f01c4 --- /dev/null +++ b/bddisasm_test/x86/prefetchit/prefetchit_64.result @@ -0,0 +1,122 @@ +0000000000000000 0f18f8 NOP eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PPRO, Ins cat: WIDENOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000003 0f1838 NOP dword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PPRO, Ins cat: WIDENOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + +0000000000000006 0f183d90909090 PREFETCHIT0 byte ptr [rel 0xffffffff9090909d] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PREFETCHITI, Ins cat: PREFETCH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Memory, Size: 1, RawSize: 1, Encoding: M, RIP relative: yes, + Segment: 3, Displacement: 0xffffffff90909090, + +000000000000000D 670f183d90909090 PREFETCHIT0 byte ptr [rel 0x909090a5] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: PREFETCHITI, Ins cat: PREFETCH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Memory, Size: 1, RawSize: 1, Encoding: M, RIP relative: yes, + Segment: 3, Displacement: 0xffffffff90909090, + +0000000000000015 0f18f0 NOP eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PPRO, Ins cat: WIDENOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000018 0f1830 NOP dword ptr [rax] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PPRO, Ins cat: WIDENOP, CET tracked: no + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + +000000000000001B 0f183590909090 PREFETCHIT1 byte ptr [rel 0xffffffff909090b2] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: PREFETCHITI, Ins cat: PREFETCH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Memory, Size: 1, RawSize: 1, Encoding: M, RIP relative: yes, + Segment: 3, Displacement: 0xffffffff90909090, + +0000000000000022 670f183590909090 PREFETCHIT1 byte ptr [rel 0x909090ba] + DSIZE: 32, ASIZE: 32, VLEN: - + ISA Set: PREFETCHITI, Ins cat: PREFETCH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 14 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Memory, Size: 1, RawSize: 1, Encoding: M, RIP relative: yes, + Segment: 3, Displacement: 0xffffffff90909090, + diff --git a/bddisasm_test/x86/prefetchit/prefetchit_64.test b/bddisasm_test/x86/prefetchit/prefetchit_64.test new file mode 100644 index 0000000..d6d4619 --- /dev/null +++ b/bddisasm_test/x86/prefetchit/prefetchit_64.test @@ -0,0 +1 @@ +ø8=g=ð05g5 \ No newline at end of file diff --git a/bddisasm_test/x86/rao-int/raoint_64.asm b/bddisasm_test/x86/rao-int/raoint_64.asm new file mode 100644 index 0000000..c1e15dc --- /dev/null +++ b/bddisasm_test/x86/rao-int/raoint_64.asm @@ -0,0 +1,29 @@ + bits 64 + + db 0x0F, 0x38, 0xFC, 0x00 ; AADD dword ptr [rax], eax + db 0x0F, 0x38, 0xFC, 0x40, 0x00 ; AADD dword ptr [rax+0x0], eax + db 0x0F, 0x38, 0xFC, 0x80, 0x00, 0x00, 0x00, 0x00 ; AADD dword ptr [rax+0x0], eax + db 0x48, 0x0F, 0x38, 0xFC, 0x00 ; AADD qword ptr [rax], rax + db 0x48, 0x0F, 0x38, 0xFC, 0x40, 0x00 ; AADD qword ptr [rax+0x0], rax + db 0x48, 0x0F, 0x38, 0xFC, 0x80, 0x00, 0x00, 0x00, 0x00 ; AADD qword ptr [rax+0x0], rax + + db 0x66, 0x0F, 0x38, 0xFC, 0x00 ; AAND dword ptr [rax], eax + db 0x66, 0x0F, 0x38, 0xFC, 0x40, 0x00 ; AAND dword ptr [rax+0x0], eax + db 0x66, 0x0F, 0x38, 0xFC, 0x80, 0x00, 0x00, 0x00, 0x00 ; AAND dword ptr [rax+0x0], eax + db 0x66, 0x48, 0x0F, 0x38, 0xFC, 0x00 ; AAND qword ptr [rax], rax + db 0x66, 0x48, 0x0F, 0x38, 0xFC, 0x40, 0x00 ; AAND qword ptr [rax+0x0], rax + db 0x66, 0x48, 0x0F, 0x38, 0xFC, 0x80, 0x00, 0x00, 0x00, 0x00 ; AAND qword ptr [rax+0x0], rax + + db 0xF2, 0x0F, 0x38, 0xFC, 0x00 ; AOR dword ptr [rax], eax + db 0xF2, 0x0F, 0x38, 0xFC, 0x40, 0x00 ; AOR dword ptr [rax+0x0], eax + db 0xF2, 0x0F, 0x38, 0xFC, 0x80, 0x00, 0x00, 0x00, 0x00 ; AOR dword ptr [rax+0x0], eax + db 0xF2, 0x48, 0x0F, 0x38, 0xFC, 0x00 ; AOR qword ptr [rax], rax + db 0xF2, 0x48, 0x0F, 0x38, 0xFC, 0x40, 0x00 ; AOR qword ptr [rax+0x0], rax + db 0xF2, 0x48, 0x0F, 0x38, 0xFC, 0x80, 0x00, 0x00, 0x00, 0x00 ; AOR qword ptr [rax+0x0], rax + + db 0xF3, 0x0F, 0x38, 0xFC, 0x00 ; AXOR dword ptr [rax], eax + db 0xF3, 0x0F, 0x38, 0xFC, 0x40, 0x00 ; AXOR dword ptr [rax+0x0], eax + db 0xF3, 0x0F, 0x38, 0xFC, 0x80, 0x00, 0x00, 0x00, 0x00 ; AXOR dword ptr [rax+0x0], eax + db 0xF3, 0x48, 0x0F, 0x38, 0xFC, 0x00 ; AXOR qword ptr [rax], rax + db 0xF3, 0x48, 0x0F, 0x38, 0xFC, 0x40, 0x00 ; AXOR qword ptr [rax+0x0], rax + db 0xF3, 0x48, 0x0F, 0x38, 0xFC, 0x80, 0x00, 0x00, 0x00, 0x00 ; AXOR qword ptr [rax+0x0], rax \ No newline at end of file diff --git a/bddisasm_test/x86/rao-int/raoint_64.result b/bddisasm_test/x86/rao-int/raoint_64.result new file mode 100644 index 0000000..de6ebd2 --- /dev/null +++ b/bddisasm_test/x86/rao-int/raoint_64.result @@ -0,0 +1,408 @@ +0000000000000000 0f38fc00 AADD dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000004 0f38fc4000 AADD dword ptr [rax+0x0], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000009 0f38fc8000000000 AADD dword ptr [rax+0x0], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000011 480f38fc00 AADD qword ptr [rax], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000016 480f38fc4000 AADD qword ptr [rax+0x0], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000001C 480f38fc8000000000 AADD qword ptr [rax+0x0], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000025 660f38fc00 AAND dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000002A 660f38fc4000 AAND dword ptr [rax+0x0], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000030 660f38fc8000000000 AAND dword ptr [rax+0x0], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000039 66480f38fc00 AAND qword ptr [rax], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000003F 66480f38fc4000 AAND qword ptr [rax+0x0], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000046 66480f38fc8000000000 AAND qword ptr [rax+0x0], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000050 f20f38fc00 AOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000055 f20f38fc4000 AOR dword ptr [rax+0x0], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000005B f20f38fc8000000000 AOR dword ptr [rax+0x0], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000064 f2480f38fc00 AOR qword ptr [rax], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000006A f2480f38fc4000 AOR qword ptr [rax+0x0], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000071 f2480f38fc8000000000 AOR qword ptr [rax+0x0], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000007B f30f38fc00 AXOR dword ptr [rax], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000080 f30f38fc4000 AXOR dword ptr [rax+0x0], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000086 f30f38fc8000000000 AXOR dword ptr [rax+0x0], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000008F f3480f38fc00 AXOR qword ptr [rax], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000095 f3480f38fc4000 AXOR qword ptr [rax+0x0], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000009C f3480f38fc8000000000 AXOR qword ptr [rax+0x0], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: RAOINT, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 0, Displacement: 0x0000000000000000, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/x86/rao-int/raoint_64.test b/bddisasm_test/x86/rao-int/raoint_64.test new file mode 100644 index 0000000000000000000000000000000000000000..682861bf36d0307a158119732152cbfe01b55264 GIT binary patch literal 166 zcmXAfu?+wq48!<!$7_8&8N1cZdVnBq*%^Xygv%`JK_91v TU>xa5%Al`PLokl?CS}kcnYuM= literal 0 HcmV?d00001 diff --git a/bddisasm_test/simd/3dnow_64.asm b/bddisasm_test/x86/simd/3dnow_64.asm similarity index 100% rename from bddisasm_test/simd/3dnow_64.asm rename to bddisasm_test/x86/simd/3dnow_64.asm diff --git a/bddisasm_test/simd/3dnow_64.result b/bddisasm_test/x86/simd/3dnow_64.result similarity index 100% rename from bddisasm_test/simd/3dnow_64.result rename to bddisasm_test/x86/simd/3dnow_64.result diff --git a/bddisasm_test/simd/3dnow_64 b/bddisasm_test/x86/simd/3dnow_64.test similarity index 100% rename from bddisasm_test/simd/3dnow_64 rename to bddisasm_test/x86/simd/3dnow_64.test diff --git a/bddisasm_test/simd/mmx_64.asm b/bddisasm_test/x86/simd/mmx_64.asm similarity index 100% rename from bddisasm_test/simd/mmx_64.asm rename to bddisasm_test/x86/simd/mmx_64.asm diff --git a/bddisasm_test/simd/mmx_64.result b/bddisasm_test/x86/simd/mmx_64.result similarity index 100% rename from bddisasm_test/simd/mmx_64.result rename to bddisasm_test/x86/simd/mmx_64.result diff --git a/bddisasm_test/simd/mmx_64 b/bddisasm_test/x86/simd/mmx_64.test similarity index 100% rename from bddisasm_test/simd/mmx_64 rename to bddisasm_test/x86/simd/mmx_64.test diff --git a/bddisasm_test/simd/sse2_64.asm b/bddisasm_test/x86/simd/sse2_64.asm similarity index 100% rename from bddisasm_test/simd/sse2_64.asm rename to bddisasm_test/x86/simd/sse2_64.asm diff --git a/bddisasm_test/simd/sse2_64.result b/bddisasm_test/x86/simd/sse2_64.result similarity index 99% rename from bddisasm_test/simd/sse2_64.result rename to bddisasm_test/x86/simd/sse2_64.result index c60a2a1..14c0b04 100644 --- a/bddisasm_test/simd/sse2_64.result +++ b/bddisasm_test/x86/simd/sse2_64.result @@ -366,8 +366,8 @@ Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1 Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 -0000000000000063 660f50c7 MOVMSKPD eax, xmm7 - DSIZE: 32, ASIZE: 64, VLEN: 128 +0000000000000063 660f50c7 MOVMSKPD rax, xmm7 + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no CPUID leaf: 0x00000001, reg: edx, bit: 26 Exception class: SSE/VEX, exception type: 7 @@ -380,7 +380,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 0000000000000067 66410f51fd SQRTPD xmm7, xmm13 @@ -1564,8 +1564,8 @@ Segment: 3, Base: 3, Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -00000000000001BF 660fc5d70a PEXTRW edx, xmm7, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +00000000000001BF 660fc5d70a PEXTRW rdx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: SSE2, Ins cat: SSE, CET tracked: no CPUID leaf: 0x00000001, reg: edx, bit: 26 Exception class: SSE/VEX, exception type: 5 @@ -1578,7 +1578,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I @@ -1736,8 +1736,8 @@ Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 -00000000000001F2 660fd7d7 PMOVMSKB edx, xmm7 - DSIZE: 32, ASIZE: 64, VLEN: 128 +00000000000001F2 660fd7d7 PMOVMSKB rdx, xmm7 + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: SSE2, Ins cat: SSE, CET tracked: no CPUID leaf: 0x00000001, reg: edx, bit: 26 Exception class: SSE/VEX, exception type: 7 @@ -1750,7 +1750,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 00000000000001F6 66410fd8fd PSUBUSB xmm7, xmm13 @@ -2818,8 +2818,8 @@ Segment: 3, Base: 3, Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 -0000000000000313 660f50c7 MOVMSKPD eax, xmm7 - DSIZE: 32, ASIZE: 64, VLEN: 128 +0000000000000313 660f50c7 MOVMSKPD rax, xmm7 + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: SSE2, Ins cat: DATAXFER, CET tracked: no CPUID leaf: 0x00000001, reg: edx, bit: 26 Exception class: SSE/VEX, exception type: 7 @@ -2832,7 +2832,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 0000000000000317 660f513b SQRTPD xmm7, xmmword ptr [rbx] @@ -4068,8 +4068,8 @@ Segment: 3, Base: 3, Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -000000000000043B 660fc5d70a PEXTRW edx, xmm7, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +000000000000043B 660fc5d70a PEXTRW rdx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: SSE2, Ins cat: SSE, CET tracked: no CPUID leaf: 0x00000001, reg: edx, bit: 26 Exception class: SSE/VEX, exception type: 5 @@ -4082,7 +4082,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I @@ -4247,8 +4247,8 @@ Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: MMX, RegSize: 8, RegId: 0, RegCount: 1 -0000000000000467 660fd7d7 PMOVMSKB edx, xmm7 - DSIZE: 32, ASIZE: 64, VLEN: 128 +0000000000000467 660fd7d7 PMOVMSKB rdx, xmm7 + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: SSE2, Ins cat: SSE, CET tracked: no CPUID leaf: 0x00000001, reg: edx, bit: 26 Exception class: SSE/VEX, exception type: 7 @@ -4261,7 +4261,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 000000000000046B 660fd83b PSUBUSB xmm7, xmmword ptr [rbx] diff --git a/bddisasm_test/simd/sse2_64 b/bddisasm_test/x86/simd/sse2_64.test similarity index 100% rename from bddisasm_test/simd/sse2_64 rename to bddisasm_test/x86/simd/sse2_64.test diff --git a/bddisasm_test/simd/sse3_64.asm b/bddisasm_test/x86/simd/sse3_64.asm similarity index 100% rename from bddisasm_test/simd/sse3_64.asm rename to bddisasm_test/x86/simd/sse3_64.asm diff --git a/bddisasm_test/simd/sse3_64.result b/bddisasm_test/x86/simd/sse3_64.result similarity index 100% rename from bddisasm_test/simd/sse3_64.result rename to bddisasm_test/x86/simd/sse3_64.result diff --git a/bddisasm_test/simd/sse3_64 b/bddisasm_test/x86/simd/sse3_64.test similarity index 100% rename from bddisasm_test/simd/sse3_64 rename to bddisasm_test/x86/simd/sse3_64.test diff --git a/bddisasm_test/simd/sse4_64.asm b/bddisasm_test/x86/simd/sse4_64.asm similarity index 100% rename from bddisasm_test/simd/sse4_64.asm rename to bddisasm_test/x86/simd/sse4_64.asm diff --git a/bddisasm_test/simd/sse4_64.result b/bddisasm_test/x86/simd/sse4_64.result similarity index 99% rename from bddisasm_test/simd/sse4_64.result rename to bddisasm_test/x86/simd/sse4_64.result index 72de39d..2c68a65 100644 --- a/bddisasm_test/simd/sse4_64.result +++ b/bddisasm_test/x86/simd/sse4_64.result @@ -778,8 +778,8 @@ Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -000000000000010C 660f3a14fa0a PEXTRB edx, xmm7, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +000000000000010C 660f3a14fa0a PEXTRB rdx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: SSE4, Ins cat: SSE, CET tracked: no CPUID leaf: 0x00000001, reg: ecx, bit: 19 Exception class: SSE/VEX, exception type: 5 @@ -792,7 +792,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I @@ -815,8 +815,8 @@ Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -0000000000000118 660fc5d70a PEXTRW edx, xmm7, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +0000000000000118 660fc5d70a PEXTRW rdx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: SSE2, Ins cat: SSE, CET tracked: no CPUID leaf: 0x00000001, reg: edx, bit: 26 Exception class: SSE/VEX, exception type: 5 @@ -829,12 +829,12 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -000000000000011D 660f3a16fa0a PEXTRD edx, xmm7, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +000000000000011D 660f3a16fa0a PEXTRD rdx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: SSE4, Ins cat: SSE, CET tracked: no CPUID leaf: 0x00000001, reg: ecx, bit: 19 Exception class: SSE/VEX, exception type: 5 @@ -847,7 +847,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I @@ -1960,8 +1960,8 @@ Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -000000000000026E 660f3a14fa0a PEXTRB edx, xmm7, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +000000000000026E 660f3a14fa0a PEXTRB rdx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: SSE4, Ins cat: SSE, CET tracked: no CPUID leaf: 0x00000001, reg: ecx, bit: 19 Exception class: SSE/VEX, exception type: 5 @@ -1974,7 +1974,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I @@ -1997,8 +1997,8 @@ Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -000000000000027A 660fc5d70a PEXTRW edx, xmm7, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +000000000000027A 660fc5d70a PEXTRW rdx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: SSE2, Ins cat: SSE, CET tracked: no CPUID leaf: 0x00000001, reg: edx, bit: 26 Exception class: SSE/VEX, exception type: 5 @@ -2011,12 +2011,12 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I -000000000000027F 660f3a16fa0a PEXTRD edx, xmm7, 0x0a - DSIZE: 32, ASIZE: 64, VLEN: 128 +000000000000027F 660f3a16fa0a PEXTRD rdx, xmm7, 0x0a + DSIZE: 64, ASIZE: 64, VLEN: 128 ISA Set: SSE4, Ins cat: SSE, CET tracked: no CPUID leaf: 0x00000001, reg: ecx, bit: 19 Exception class: SSE/VEX, exception type: 5 @@ -2029,7 +2029,7 @@ REP: no, REPcc: no, LOCK: no HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no - Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1 Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I diff --git a/bddisasm_test/simd/sse4_64 b/bddisasm_test/x86/simd/sse4_64.test similarity index 100% rename from bddisasm_test/simd/sse4_64 rename to bddisasm_test/x86/simd/sse4_64.test diff --git a/bddisasm_test/special/amx_64_skip.asm b/bddisasm_test/x86/special/amx_64_skip.asm similarity index 100% rename from bddisasm_test/special/amx_64_skip.asm rename to bddisasm_test/x86/special/amx_64_skip.asm diff --git a/bddisasm_test/special/amx_64_skip.result b/bddisasm_test/x86/special/amx_64_skip.result similarity index 100% rename from bddisasm_test/special/amx_64_skip.result rename to bddisasm_test/x86/special/amx_64_skip.result diff --git a/bddisasm_test/special/amx_64_skip b/bddisasm_test/x86/special/amx_64_skip.test similarity index 100% rename from bddisasm_test/special/amx_64_skip rename to bddisasm_test/x86/special/amx_64_skip.test diff --git a/bddisasm_test/special/avx2gather_1_64_skip.asm b/bddisasm_test/x86/special/avx2gather_1_64_skip.asm similarity index 100% rename from bddisasm_test/special/avx2gather_1_64_skip.asm rename to bddisasm_test/x86/special/avx2gather_1_64_skip.asm diff --git a/bddisasm_test/special/avx2gather_1_64_skip.result b/bddisasm_test/x86/special/avx2gather_1_64_skip.result similarity index 100% rename from bddisasm_test/special/avx2gather_1_64_skip.result rename to bddisasm_test/x86/special/avx2gather_1_64_skip.result diff --git a/bddisasm_test/special/avx2gather_1_64_skip b/bddisasm_test/x86/special/avx2gather_1_64_skip.test similarity index 100% rename from bddisasm_test/special/avx2gather_1_64_skip rename to bddisasm_test/x86/special/avx2gather_1_64_skip.test diff --git a/bddisasm_test/special/avx2gather_2_64_skip.asm b/bddisasm_test/x86/special/avx2gather_2_64_skip.asm similarity index 100% rename from bddisasm_test/special/avx2gather_2_64_skip.asm rename to bddisasm_test/x86/special/avx2gather_2_64_skip.asm diff --git a/bddisasm_test/special/avx2gather_2_64_skip.result b/bddisasm_test/x86/special/avx2gather_2_64_skip.result similarity index 100% rename from bddisasm_test/special/avx2gather_2_64_skip.result rename to bddisasm_test/x86/special/avx2gather_2_64_skip.result diff --git a/bddisasm_test/special/avx2gather_2_64_skip b/bddisasm_test/x86/special/avx2gather_2_64_skip.test similarity index 100% rename from bddisasm_test/special/avx2gather_2_64_skip rename to bddisasm_test/x86/special/avx2gather_2_64_skip.test diff --git a/bddisasm_test/special/avx2gather_3_64_skip.asm b/bddisasm_test/x86/special/avx2gather_3_64_skip.asm similarity index 100% rename from bddisasm_test/special/avx2gather_3_64_skip.asm rename to bddisasm_test/x86/special/avx2gather_3_64_skip.asm diff --git a/bddisasm_test/special/avx2gather_3_64_skip.result b/bddisasm_test/x86/special/avx2gather_3_64_skip.result similarity index 100% rename from bddisasm_test/special/avx2gather_3_64_skip.result rename to bddisasm_test/x86/special/avx2gather_3_64_skip.result diff --git a/bddisasm_test/special/avx2gather_3_64_skip b/bddisasm_test/x86/special/avx2gather_3_64_skip.test similarity index 100% rename from bddisasm_test/special/avx2gather_3_64_skip rename to bddisasm_test/x86/special/avx2gather_3_64_skip.test diff --git a/bddisasm_test/special/cr8_32.asm b/bddisasm_test/x86/special/cr8_32.asm similarity index 100% rename from bddisasm_test/special/cr8_32.asm rename to bddisasm_test/x86/special/cr8_32.asm diff --git a/bddisasm_test/special/cr8_32.result b/bddisasm_test/x86/special/cr8_32.result similarity index 100% rename from bddisasm_test/special/cr8_32.result rename to bddisasm_test/x86/special/cr8_32.result diff --git a/bddisasm_test/special/cr8_32 b/bddisasm_test/x86/special/cr8_32.test similarity index 100% rename from bddisasm_test/special/cr8_32 rename to bddisasm_test/x86/special/cr8_32.test diff --git a/bddisasm_test/special/ignorew_evex_32.result b/bddisasm_test/x86/special/ignorew_evex_32.result similarity index 100% rename from bddisasm_test/special/ignorew_evex_32.result rename to bddisasm_test/x86/special/ignorew_evex_32.result diff --git a/bddisasm_test/special/ignorew_evex_32 b/bddisasm_test/x86/special/ignorew_evex_32.test similarity index 100% rename from bddisasm_test/special/ignorew_evex_32 rename to bddisasm_test/x86/special/ignorew_evex_32.test diff --git a/bddisasm_test/special/ignorew_evex_64.result b/bddisasm_test/x86/special/ignorew_evex_64.result similarity index 100% rename from bddisasm_test/special/ignorew_evex_64.result rename to bddisasm_test/x86/special/ignorew_evex_64.result diff --git a/bddisasm_test/special/ignorew_evex_64 b/bddisasm_test/x86/special/ignorew_evex_64.test similarity index 100% rename from bddisasm_test/special/ignorew_evex_64 rename to bddisasm_test/x86/special/ignorew_evex_64.test diff --git a/bddisasm_test/special/invalid_32_skip.asm b/bddisasm_test/x86/special/invalid_32_skip.asm similarity index 100% rename from bddisasm_test/special/invalid_32_skip.asm rename to bddisasm_test/x86/special/invalid_32_skip.asm diff --git a/bddisasm_test/special/invalid_32_skip.result b/bddisasm_test/x86/special/invalid_32_skip.result similarity index 100% rename from bddisasm_test/special/invalid_32_skip.result rename to bddisasm_test/x86/special/invalid_32_skip.result diff --git a/bddisasm_test/special/invalid_32_skip b/bddisasm_test/x86/special/invalid_32_skip.test similarity index 100% rename from bddisasm_test/special/invalid_32_skip rename to bddisasm_test/x86/special/invalid_32_skip.test diff --git a/bddisasm_test/special/invalid_64_skip.asm b/bddisasm_test/x86/special/invalid_64_skip.asm similarity index 100% rename from bddisasm_test/special/invalid_64_skip.asm rename to bddisasm_test/x86/special/invalid_64_skip.asm diff --git a/bddisasm_test/special/invalid_64_skip.result b/bddisasm_test/x86/special/invalid_64_skip.result similarity index 100% rename from bddisasm_test/special/invalid_64_skip.result rename to bddisasm_test/x86/special/invalid_64_skip.result diff --git a/bddisasm_test/special/invalid_64_skip b/bddisasm_test/x86/special/invalid_64_skip.test similarity index 100% rename from bddisasm_test/special/invalid_64_skip rename to bddisasm_test/x86/special/invalid_64_skip.test diff --git a/bddisasm_test/special/invalid_evex_64_skip.asm b/bddisasm_test/x86/special/invalid_evex_64_skip.asm similarity index 100% rename from bddisasm_test/special/invalid_evex_64_skip.asm rename to bddisasm_test/x86/special/invalid_evex_64_skip.asm diff --git a/bddisasm_test/special/invalid_evex_64_skip.result b/bddisasm_test/x86/special/invalid_evex_64_skip.result similarity index 100% rename from bddisasm_test/special/invalid_evex_64_skip.result rename to bddisasm_test/x86/special/invalid_evex_64_skip.result diff --git a/bddisasm_test/special/invalid_evex_64_skip b/bddisasm_test/x86/special/invalid_evex_64_skip.test similarity index 100% rename from bddisasm_test/special/invalid_evex_64_skip rename to bddisasm_test/x86/special/invalid_evex_64_skip.test diff --git a/bddisasm_test/special/long_64.asm b/bddisasm_test/x86/special/long_64.asm similarity index 100% rename from bddisasm_test/special/long_64.asm rename to bddisasm_test/x86/special/long_64.asm diff --git a/bddisasm_test/special/long_64.result b/bddisasm_test/x86/special/long_64.result similarity index 100% rename from bddisasm_test/special/long_64.result rename to bddisasm_test/x86/special/long_64.result diff --git a/bddisasm_test/special/long_64 b/bddisasm_test/x86/special/long_64.test similarity index 100% rename from bddisasm_test/special/long_64 rename to bddisasm_test/x86/special/long_64.test diff --git a/bddisasm_test/special/movcrdr_64.asm b/bddisasm_test/x86/special/movcrdr_64.asm similarity index 100% rename from bddisasm_test/special/movcrdr_64.asm rename to bddisasm_test/x86/special/movcrdr_64.asm diff --git a/bddisasm_test/special/movcrdr_64.result b/bddisasm_test/x86/special/movcrdr_64.result similarity index 100% rename from bddisasm_test/special/movcrdr_64.result rename to bddisasm_test/x86/special/movcrdr_64.result diff --git a/bddisasm_test/special/movcrdr_64 b/bddisasm_test/x86/special/movcrdr_64.test similarity index 100% rename from bddisasm_test/special/movcrdr_64 rename to bddisasm_test/x86/special/movcrdr_64.test diff --git a/bddisasm_test/special/only_32.asm b/bddisasm_test/x86/special/only_32.asm similarity index 100% rename from bddisasm_test/special/only_32.asm rename to bddisasm_test/x86/special/only_32.asm diff --git a/bddisasm_test/special/only_32.result b/bddisasm_test/x86/special/only_32.result similarity index 99% rename from bddisasm_test/special/only_32.result rename to bddisasm_test/x86/special/only_32.result index e8a17a8..70328dd 100644 --- a/bddisasm_test/special/only_32.result +++ b/bddisasm_test/x86/special/only_32.result @@ -79,7 +79,7 @@ HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1 - Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, + Operand: 1, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: S, Stack: yes, Segment: 2, Base: 4, 0000000000000008 16 PUSH ss diff --git a/bddisasm_test/special/only_32 b/bddisasm_test/x86/special/only_32.test similarity index 100% rename from bddisasm_test/special/only_32 rename to bddisasm_test/x86/special/only_32.test diff --git a/bddisasm_test/special/only_64.asm b/bddisasm_test/x86/special/only_64.asm similarity index 100% rename from bddisasm_test/special/only_64.asm rename to bddisasm_test/x86/special/only_64.asm diff --git a/bddisasm_test/special/only_64.result b/bddisasm_test/x86/special/only_64.result similarity index 100% rename from bddisasm_test/special/only_64.result rename to bddisasm_test/x86/special/only_64.result diff --git a/bddisasm_test/special/only_64 b/bddisasm_test/x86/special/only_64.test similarity index 100% rename from bddisasm_test/special/only_64 rename to bddisasm_test/x86/special/only_64.test diff --git a/bddisasm_test/special/regressions_32.asm b/bddisasm_test/x86/special/regressions_32.asm similarity index 100% rename from bddisasm_test/special/regressions_32.asm rename to bddisasm_test/x86/special/regressions_32.asm diff --git a/bddisasm_test/special/regressions_32.result b/bddisasm_test/x86/special/regressions_32.result similarity index 100% rename from bddisasm_test/special/regressions_32.result rename to bddisasm_test/x86/special/regressions_32.result diff --git a/bddisasm_test/special/regressions_32 b/bddisasm_test/x86/special/regressions_32.test similarity index 100% rename from bddisasm_test/special/regressions_32 rename to bddisasm_test/x86/special/regressions_32.test diff --git a/bddisasm_test/special/regressions_64.asm b/bddisasm_test/x86/special/regressions_64.asm similarity index 100% rename from bddisasm_test/special/regressions_64.asm rename to bddisasm_test/x86/special/regressions_64.asm diff --git a/bddisasm_test/special/regressions_64.result b/bddisasm_test/x86/special/regressions_64.result similarity index 100% rename from bddisasm_test/special/regressions_64.result rename to bddisasm_test/x86/special/regressions_64.result diff --git a/bddisasm_test/special/regressions_64 b/bddisasm_test/x86/special/regressions_64.test similarity index 100% rename from bddisasm_test/special/regressions_64 rename to bddisasm_test/x86/special/regressions_64.test diff --git a/bddisasm_test/tdx/tdx_64.asm b/bddisasm_test/x86/tdx/tdx_64.asm similarity index 100% rename from bddisasm_test/tdx/tdx_64.asm rename to bddisasm_test/x86/tdx/tdx_64.asm diff --git a/bddisasm_test/tdx/tdx_64.result b/bddisasm_test/x86/tdx/tdx_64.result similarity index 100% rename from bddisasm_test/tdx/tdx_64.result rename to bddisasm_test/x86/tdx/tdx_64.result diff --git a/bddisasm_test/tdx/tdx_64 b/bddisasm_test/x86/tdx/tdx_64.test similarity index 100% rename from bddisasm_test/tdx/tdx_64 rename to bddisasm_test/x86/tdx/tdx_64.test diff --git a/bddisasm_test/uintr/uintr_64.asm b/bddisasm_test/x86/uintr/uintr_64.asm similarity index 100% rename from bddisasm_test/uintr/uintr_64.asm rename to bddisasm_test/x86/uintr/uintr_64.asm diff --git a/bddisasm_test/uintr/uintr_64.result b/bddisasm_test/x86/uintr/uintr_64.result similarity index 100% rename from bddisasm_test/uintr/uintr_64.result rename to bddisasm_test/x86/uintr/uintr_64.result diff --git a/bddisasm_test/uintr/uintr_64 b/bddisasm_test/x86/uintr/uintr_64.test similarity index 100% rename from bddisasm_test/uintr/uintr_64 rename to bddisasm_test/x86/uintr/uintr_64.test diff --git a/bindings/pybddisasm/setup.py b/bindings/pybddisasm/setup.py index 7e4dd34..b5d9333 100644 --- a/bindings/pybddisasm/setup.py +++ b/bindings/pybddisasm/setup.py @@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution from codecs import open VERSION = (0, 1, 3) -LIBRARY_VERSION = (1, 34, 18) +LIBRARY_VERSION = (1, 35, 0) LIBRARY_INSTRUX_SIZE = 856 packages = ['pybddisasm'] diff --git a/disasmtool/disasmtool.c b/disasmtool/disasmtool.c index b0f4c2c..ab0493e 100644 --- a/disasmtool/disasmtool.c +++ b/disasmtool/disasmtool.c @@ -101,6 +101,7 @@ const char* set_to_string( case ND_SET_AES: return "AES"; case ND_SET_AMD: return "AMD"; case ND_SET_AMXBF16: return "AMX-BF16"; + case ND_SET_AMXFP16: return "AMX-FP16"; case ND_SET_AMXINT8: return "AMX-INT8"; case ND_SET_AMXTILE: return "AMX-TILE"; case ND_SET_AVX: return "AVX"; @@ -123,7 +124,10 @@ const char* set_to_string( case ND_SET_AVX512VP2INTERSECT: return "AVX512VP2INTERSECT"; case ND_SET_AVX512VPOPCNTDQ: return "AVX512VPOPCNTDQ"; case ND_SET_AVX512FP16: return "AVX512FP16"; + case ND_SET_AVXIFMA: return "AVXIFMA"; + case ND_SET_AVXNECONVERT: return "AVXNECONVERT"; case ND_SET_AVXVNNI: return "AVXVNNI"; + case ND_SET_AVXVNNIINT8: return "AVXVNNIINT8"; case ND_SET_BMI1: return "BMI1"; case ND_SET_BMI2: return "BMI2"; case ND_SET_CET_SS: return "CET_SS"; @@ -133,6 +137,7 @@ const char* set_to_string( case ND_SET_CLFSHOPT: return "CLFSHOPT"; case ND_SET_CLWB: return "CLWB"; case ND_SET_CLZERO: return "CLZERO"; + case ND_SET_CMPCCXADD: return "CMPCCXADD"; case ND_SET_CMPXCHG16B: return "CMPXCHG16B"; case ND_SET_CYRIX: return "CYRIX"; case ND_SET_CYRIX_SMM: return "CYRIX_SMM"; @@ -165,6 +170,7 @@ const char* set_to_string( case ND_SET_MOVDIR64B: return "MOVDIR64B"; case ND_SET_MOVDIRI: return "MOVDIRI"; case ND_SET_MPX: return "MPX"; + case ND_SET_MSRLIST: return "MSRLIST"; case ND_SET_MWAITT: return "MWAITT"; case ND_SET_PAUSE: return "PAUSE"; case ND_SET_PCLMULQDQ: return "PCLMULQDQ"; @@ -173,8 +179,10 @@ const char* set_to_string( case ND_SET_PKU: return "PKU"; case ND_SET_POPCNT: return "POPCNT"; case ND_SET_PPRO: return "PPRO"; + case ND_SET_PREFETCHITI: return "PREFETCHITI"; case ND_SET_PREFETCH_NOP: return "PREFETCH_NOP"; case ND_SET_PTWRITE: return "PTWRITE"; + case ND_SET_RAOINT: return "RAOINT"; case ND_SET_RDPID: return "RDPID"; case ND_SET_RDPMC: return "RDPMC"; case ND_SET_RDPRU: return "RDPRU"; @@ -208,6 +216,7 @@ const char* set_to_string( case ND_SET_VTX: return "VTX"; case ND_SET_WAITPKG: return "WAITPKG"; case ND_SET_WBNOINVD: return "WBNOINVD"; + case ND_SET_WRMSRNS: return "WRMSRNS"; case ND_SET_X87: return "X87"; case ND_SET_XOP: return "XOP"; case ND_SET_XSAVE: return "XSAVE"; @@ -240,7 +249,10 @@ const char* category_to_string( case ND_CAT_AVX512VBMI: return "AVX512VBMI"; case ND_CAT_AVX512VP2INTERSECT: return "AVX512VP2INTERSECT"; case ND_CAT_AVX512FP16: return "AVX512FP16"; + case ND_CAT_AVXIFMA: return "AVXIFMA"; case ND_CAT_AVXVNNI: return "AVXVNNI"; + case ND_CAT_AVXVNNIINT8: return "AVXVNNIINT8"; + case ND_CAT_AVXNECONVERT: return "AVXNECONVERT"; case ND_CAT_BITBYTE: return "BITBYTE"; case ND_CAT_BLEND: return "BLEND"; case ND_CAT_BMI1: return "BMI1"; @@ -250,6 +262,7 @@ const char* category_to_string( case ND_CAT_CET: return "CET"; case ND_CAT_CLDEMOTE: return "CLDEMOTE"; case ND_CAT_CMOV: return "CMOV"; + case ND_CAT_CMPCCXADD: return "CMPCCXADD"; case ND_CAT_COMPRESS: return "COMPRESS"; case ND_CAT_COND_BR: return "COND_BR"; case ND_CAT_CONFLICT: return "CONFLICT"; @@ -290,6 +303,7 @@ const char* category_to_string( case ND_CAT_PREFETCH: return "PREFETCH"; case ND_CAT_PTWRITE: return "PTWRITE"; case ND_CAT_PUSH: return "PUSH"; + case ND_CAT_RAOINT: return "RAO-INT"; case ND_CAT_RDPID: return "RDPID"; case ND_CAT_RDRAND: return "RDRAND"; case ND_CAT_RDSEED: return "RDSEED"; @@ -1790,7 +1804,7 @@ int main( printf(" -r rip use the provided RIP\n"); printf(" -b[16|32|64] set decoding mode; default is 16\n"); printf(" -v[intel|amd|cyrix|mpx|any] set preferred vendor\n"); - printf(" -t[none|all|mpx|cet|cldm] set preferred feature mode; default is all\n"); + printf(" -t[none|all|mpx|cet|cldm|piti] set preferred feature mode; default is all\n"); printf(" -s \"ins\" search for the given instructions\n"); printf(" -nv don't print disassembly\n"); printf(" -iv display statistics\n"); @@ -1961,6 +1975,15 @@ int main( feat |= ND_FEAT_CLDEMOTE; } + else if (0 == strcmp(argv[i], "-tpiti")) + { + if (feat == ND_FEAT_ALL) + { + feat = 0; + } + + feat |= ND_FEAT_PITI; + } else if (0 == strcmp(argv[i], "-tnone")) { feat = ND_FEAT_NONE; diff --git a/disasmtool_lix/dumpers.cpp b/disasmtool_lix/dumpers.cpp index b74d9c2..b0a95e0 100644 --- a/disasmtool_lix/dumpers.cpp +++ b/disasmtool_lix/dumpers.cpp @@ -1547,6 +1547,44 @@ std::string ins_class_to_str(const ND_INS_CLASS cls) case ND_INS_TESTUI: return "testui"; case ND_INS_UIRET: return "uiret"; case ND_INS_SENDUIPI: return "senduipi"; + case ND_INS_AADD: return "aadd"; + case ND_INS_AAND: return "aand"; + case ND_INS_AOR: return "aor"; + case ND_INS_AXOR: return "axor"; + case ND_INS_CMPBEXADD: return "cmpbexadd"; + case ND_INS_CMPCXADD: return "cmpcxadd"; + case ND_INS_CMPLEXADD: return "cmplexadd"; + case ND_INS_CMPLXADD: return "cmplxadd"; + case ND_INS_CMPNBEXADD: return "cmpnbexadd"; + case ND_INS_CMPNCXADD: return "cmpncxadd"; + case ND_INS_CMPNLEXADD: return "cmpnlexadd"; + case ND_INS_CMPNLXADD: return "cmpnlxadd"; + case ND_INS_CMPNOXADD: return "cmpnoxadd"; + case ND_INS_CMPNPXADD: return "cmpnpxadd"; + case ND_INS_CMPNSXADD: return "cmpnsxadd"; + case ND_INS_CMPNZXADD: return "cmpnzxadd"; + case ND_INS_CMPOXADD: return "cmpoxadd"; + case ND_INS_CMPPXADD: return "cmppxadd"; + case ND_INS_CMPSXADD: return "cmpsxadd"; + case ND_INS_CMPZXADD: return "cmpzxadd"; + case ND_INS_PREFETCHIT0: return "prefetchit0"; + case ND_INS_PREFETCHIT1: return "prefetchit1"; + case ND_INS_RDMSRLIST: return "rdmsrlist"; + case ND_INS_TDPFP16PS: return "tdpfp16ps"; + case ND_INS_VBCSTNEBF162PS: return "vbcstnebf162ps"; + case ND_INS_VBCSTNESH2PS: return "vbcstnesh2ps"; + case ND_INS_VCVTNEEBF162PS: return "vcvtneebf162ps"; + case ND_INS_VCVTNEEPH2PS: return "vcvtneeph2ps"; + case ND_INS_VCVTNEOBF162PS: return "vcvtneobf162ps"; + case ND_INS_VCVTNEOPH2PS: return "vcvtneoph2ps"; + case ND_INS_VPDPBSSD: return "vpdpbssd"; + case ND_INS_VPDPBSSDS: return "vpdpbssds"; + case ND_INS_VPDPBSUD: return "vpdpbsud"; + case ND_INS_VPDPBSUDS: return "vpdpbsuds"; + case ND_INS_VPDPBUUD: return "vpdpbuud"; + case ND_INS_VPDPBUUDS: return "vpdpbuuds"; + case ND_INS_WRMSRLIST: return "wrmsrlist"; + case ND_INS_WRMSRNS: return "wrmsrns"; default: return "unhandled!"; } @@ -1661,6 +1699,11 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category) case ND_CAT_X87_ALU: return "x87_alu"; case ND_CAT_XOP: return "xop"; case ND_CAT_XSAVE: return "xsave"; + case ND_CAT_AVXIFMA: return "avxifma"; + case ND_CAT_AVXVNNIINT8: return "avxvnniint8"; + case ND_CAT_AVXNECONVERT: return "avxneconvert"; + case ND_CAT_CMPCCXADD: return "cmpccxass"; + case ND_CAT_RAOINT: return "rao-int"; } return ""; @@ -1788,6 +1831,15 @@ std::string ins_set_to_str(ND_INS_SET ins_set) case ND_SET_XSAVE: return "xsave"; case ND_SET_XSAVEC: return "xsavec"; case ND_SET_XSAVES: return "xsaves"; + case ND_SET_AMXFP16: return "AMX-FP16"; + case ND_SET_AVXIFMA: return "avxifma"; + case ND_SET_AVXNECONVERT: return "avxneconvert"; + case ND_SET_AVXVNNIINT8: return "avxvnniint8"; + case ND_SET_CMPCCXADD: return "cmpccxadd"; + case ND_SET_MSRLIST: return "msrlist"; + case ND_SET_PREFETCHITI: return "prefetchiti"; + case ND_SET_RAOINT: return "raoint"; + case ND_SET_WRMSRNS: return "wrmsrns"; } return ""; diff --git a/disasmtool_lix/dumpers.cpp.bak b/disasmtool_lix/dumpers.cpp.bak new file mode 100644 index 0000000..b74d9c2 --- /dev/null +++ b/disasmtool_lix/dumpers.cpp.bak @@ -0,0 +1,1933 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#include "disasm.hpp" + + +std::string enc_mode_to_str(const uint8_t enc_mode) +{ + switch (enc_mode) { + case ND_ENCM_LEGACY: return "legacy"; + case ND_ENCM_XOP: return "xop"; + case ND_ENCM_VEX: return "vex"; + case ND_ENCM_EVEX: return "evex"; + } + + return ""; +} + + +std::string op_enc_to_str(const ND_OPERAND_ENCODING Encoding) +{ + switch (Encoding) { + case ND_OPE_NP: return "NP"; + case ND_OPE_R: return "R"; + case ND_OPE_M: return "M"; + case ND_OPE_V: return "V"; + case ND_OPE_O: return "O"; + case ND_OPE_I: return "I"; + case ND_OPE_D: return "D"; + case ND_OPE_C: return "C"; + case ND_OPE_1: return "1"; + case ND_OPE_A: return "A"; + case ND_OPE_L: return "L"; + case ND_OPE_E: return "E"; + case ND_OPE_S: return "S"; + default: return ""; + } +} + + +std::string op_type_to_str(const ND_OPERAND_TYPE type) +{ + switch(type) { + case ND_OP_NOT_PRESENT: + return "not_present"; + case ND_OP_REG: + return "register"; + case ND_OP_MEM: + return "memory"; + case ND_OP_IMM: + return "immediate"; + case ND_OP_OFFS: + return "offset"; + case ND_OP_ADDR: + return "address"; + case ND_OP_CONST: + return "const"; + case ND_OP_BANK: + return "bank"; + } + + return ""; +} + + +std::string ins_class_to_str(const ND_INS_CLASS cls) +{ + switch (cls) { + case ND_INS_INVALID: return "invalid"; + case ND_INS_AAA: return "aaa"; + case ND_INS_AAD: return "aad"; + case ND_INS_AAM: return "aam"; + case ND_INS_AAS: return "aas"; + case ND_INS_ADC: return "adc"; + case ND_INS_ADCX: return "adcx"; + case ND_INS_ADD: return "add"; + case ND_INS_ADDPD: return "addpd"; + case ND_INS_ADDPS: return "addps"; + case ND_INS_ADDSD: return "addsd"; + case ND_INS_ADDSS: return "addss"; + case ND_INS_ADDSUBPD: return "addsubpd"; + case ND_INS_ADDSUBPS: return "addsubps"; + case ND_INS_ADOX: return "adox"; + case ND_INS_AESDEC: return "aesdec"; + case ND_INS_AESDEC128KL: return "aesdec128kl"; + case ND_INS_AESDEC256KL: return "aesdec256kl"; + case ND_INS_AESDECWIDE128KL: return "aesdecwide128kl"; + case ND_INS_AESDECWIDE256KL: return "aesdecwide256kl"; + case ND_INS_AESDECLAST: return "aesdeclast"; + case ND_INS_AESENC: return "aesenc"; + case ND_INS_AESENC128KL: return "aesenc128kl"; + case ND_INS_AESENC256KL: return "aesenc256kl"; + case ND_INS_AESENCWIDE128KL: return "aesencwide128kl"; + case ND_INS_AESENCWIDE256KL: return "aesencwide256kl"; + case ND_INS_AESENCLAST: return "aesenclast"; + case ND_INS_AESIMC: return "aesimc"; + case ND_INS_AESKEYGENASSIST: return "aeskeygenassist"; + case ND_INS_ALTINST: return "altinst"; + case ND_INS_AND: return "and"; + case ND_INS_ANDN: return "andn"; + case ND_INS_ANDNPD: return "andnpd"; + case ND_INS_ANDNPS: return "andnps"; + case ND_INS_ANDPD: return "andpd"; + case ND_INS_ANDPS: return "andps"; + case ND_INS_ARPL: return "arpl"; + case ND_INS_BEXTR: return "bextr"; + case ND_INS_BLCFILL: return "blcfill"; + case ND_INS_BLCI: return "blci"; + case ND_INS_BLCIC: return "blcic"; + case ND_INS_BLCMSK: return "blcmsk"; + case ND_INS_BLCS: return "blcs"; + case ND_INS_BLENDPD: return "blendpd"; + case ND_INS_BLENDPS: return "blendps"; + case ND_INS_BLENDVPD: return "blendvpd"; + case ND_INS_BLENDVPS: return "blendvps"; + case ND_INS_BLSFILL: return "blsfill"; + case ND_INS_BLSI: return "blsi"; + case ND_INS_BLSIC: return "blsic"; + case ND_INS_BLSMSK: return "blsmsk"; + case ND_INS_BLSR: return "blsr"; + case ND_INS_BNDCL: return "bndcl"; + case ND_INS_BNDCN: return "bndcn"; + case ND_INS_BNDCU: return "bndcu"; + case ND_INS_BNDLDX: return "bndldx"; + case ND_INS_BNDMK: return "bndmk"; + case ND_INS_BNDMOV: return "bndmov"; + case ND_INS_BNDSTX: return "bndstx"; + case ND_INS_BOUND: return "bound"; + case ND_INS_BSF: return "bsf"; + case ND_INS_BSR: return "bsr"; + case ND_INS_BSWAP: return "bswap"; + case ND_INS_BT: return "bt"; + case ND_INS_BTC: return "btc"; + case ND_INS_BTR: return "btr"; + case ND_INS_BTS: return "bts"; + case ND_INS_BZHI: return "bzhi"; + case ND_INS_CALLFD: return "callfd"; + case ND_INS_CALLFI: return "callfi"; + case ND_INS_CALLNI: return "callni"; + case ND_INS_CALLNR: return "callnr"; + case ND_INS_CBW: return "cbw"; + case ND_INS_CDQ: return "cdq"; + case ND_INS_CDQE: return "cdqe"; + case ND_INS_CLAC: return "clac"; + case ND_INS_CLC: return "clc"; + case ND_INS_CLD: return "cld"; + case ND_INS_CLDEMOTE: return "cldemote"; + case ND_INS_CLEVICT0: return "clevict0"; + case ND_INS_CLEVICT1: return "clevict1"; + case ND_INS_CLFLUSH: return "clflush"; + case ND_INS_CLFLUSHOPT: return "clflushopt"; + case ND_INS_CLGI: return "clgi"; + case ND_INS_CLI: return "cli"; + case ND_INS_CLRSSBSY: return "clrssbsy"; + case ND_INS_CLTS: return "clts"; + case ND_INS_CLWB: return "clwb"; + case ND_INS_CLZERO: return "clzero"; + case ND_INS_CMC: return "cmc"; + case ND_INS_CMOVcc: return "cmovcc"; + case ND_INS_CMP: return "cmp"; + case ND_INS_CMPPD: return "cmppd"; + case ND_INS_CMPPS: return "cmpps"; + case ND_INS_CMPS: return "cmps"; + case ND_INS_CMPSD: return "cmpsd"; + case ND_INS_CMPSS: return "cmpss"; + case ND_INS_CMPXCHG: return "cmpxchg"; + case ND_INS_CMPXCHG16B: return "cmpxchg16b"; + case ND_INS_CMPXCHG8B: return "cmpxchg8b"; + case ND_INS_COMISD: return "comisd"; + case ND_INS_COMISS: return "comiss"; + case ND_INS_CPUID: return "cpuid"; + case ND_INS_CPU_READ: return "cpuread"; + case ND_INS_CPU_WRITE: return "cpuwrite"; + case ND_INS_CQO: return "cqo"; + case ND_INS_CRC32: return "crc32"; + case ND_INS_CVTDQ2PD: return "cvtdq2pd"; + case ND_INS_CVTDQ2PS: return "cvtdq2ps"; + case ND_INS_CVTPD2DQ: return "cvtpd2dq"; + case ND_INS_CVTPD2PI: return "cvtpd2pi"; + case ND_INS_CVTPD2PS: return "cvtpd2ps"; + case ND_INS_CVTPI2PD: return "cvtpi2pd"; + case ND_INS_CVTPI2PS: return "cvtpi2ps"; + case ND_INS_CVTPS2DQ: return "cvtps2dq"; + case ND_INS_CVTPS2PD: return "cvtps2pd"; + case ND_INS_CVTPS2PI: return "cvtps2pi"; + case ND_INS_CVTSD2SI: return "cvtsd2si"; + case ND_INS_CVTSD2SS: return "cvtsd2ss"; + case ND_INS_CVTSI2SD: return "cvtsi2sd"; + case ND_INS_CVTSI2SS: return "cvtsi2ss"; + case ND_INS_CVTSS2SD: return "cvtss2sd"; + case ND_INS_CVTSS2SI: return "cvtss2si"; + case ND_INS_CVTTPD2DQ: return "cvttpd2dq"; + case ND_INS_CVTTPD2PI: return "cvttpd2pi"; + case ND_INS_CVTTPS2DQ: return "cvttps2dq"; + case ND_INS_CVTTPS2PI: return "cvttps2pi"; + case ND_INS_CVTTSD2SI: return "cvttsd2si"; + case ND_INS_CVTTSS2SI: return "cvttss2si"; + case ND_INS_CWD: return "cwd"; + case ND_INS_CWDE: return "cwde"; + case ND_INS_DAA: return "daa"; + case ND_INS_DAS: return "das"; + case ND_INS_DEC: return "dec"; + case ND_INS_DELAY: return "delay"; + case ND_INS_DIV: return "div"; + case ND_INS_DIVPD: return "divpd"; + case ND_INS_DIVPS: return "divps"; + case ND_INS_DIVSD: return "divsd"; + case ND_INS_DIVSS: return "divss"; + case ND_INS_DMINT: return "dmint"; + case ND_INS_DPPD: return "dppd"; + case ND_INS_DPPS: return "dpps"; + case ND_INS_EMMS: return "emms"; + case ND_INS_ENCLS: return "encls"; + case ND_INS_ENCLU: return "enclu"; + case ND_INS_ENCLV: return "enclv"; + case ND_INS_ENCODEKEY128: return "encodekey128"; + case ND_INS_ENCODEKEY256: return "encodekey256"; + case ND_INS_ENDBR: return "endbr"; + case ND_INS_ENQCMD: return "enqcmd"; + case ND_INS_ENQCMDS: return "enqcmds"; + case ND_INS_ENTER: return "enter"; + case ND_INS_ERETS: return "erets"; + case ND_INS_ERETU: return "eretu"; + case ND_INS_EXTRACTPS: return "extractps"; + case ND_INS_EXTRQ: return "extrq"; + case ND_INS_F2XM1: return "f2xm1"; + case ND_INS_FABS: return "fabs"; + case ND_INS_FADD: return "fadd"; + case ND_INS_FADDP: return "faddp"; + case ND_INS_FBLD: return "fbld"; + case ND_INS_FBSTP: return "fbstp"; + case ND_INS_FCHS: return "fchs"; + case ND_INS_FCMOVB: return "fcmovb"; + case ND_INS_FCMOVBE: return "fcmovbe"; + case ND_INS_FCMOVE: return "fcmove"; + case ND_INS_FCMOVNB: return "fcmovnb"; + case ND_INS_FCMOVNBE: return "fcmovnbe"; + case ND_INS_FCMOVNE: return "fcmovne"; + case ND_INS_FCMOVNU: return "fcmovnu"; + case ND_INS_FCMOVU: return "fcmovu"; + case ND_INS_FCOM: return "fcom"; + case ND_INS_FCOMI: return "fcomi"; + case ND_INS_FCOMIP: return "fcomip"; + case ND_INS_FCOMP: return "fcomp"; + case ND_INS_FCOMPP: return "fcompp"; + case ND_INS_FCOS: return "fcos"; + case ND_INS_FDECSTP: return "fdecstp"; + case ND_INS_FDIV: return "fdiv"; + case ND_INS_FDIVP: return "fdivp"; + case ND_INS_FDIVR: return "fdivr"; + case ND_INS_FDIVRP: return "fdivrp"; + case ND_INS_FEMMS: return "femms"; + case ND_INS_FFREE: return "ffree"; + case ND_INS_FFREEP: return "ffreep"; + case ND_INS_FIADD: return "fiadd"; + case ND_INS_FICOM: return "ficom"; + case ND_INS_FICOMP: return "ficomp"; + case ND_INS_FIDIV: return "fidiv"; + case ND_INS_FIDIVR: return "fidivr"; + case ND_INS_FILD: return "fild"; + case ND_INS_FIMUL: return "fimul"; + case ND_INS_FINCSTP: return "fincstp"; + case ND_INS_FIST: return "fist"; + case ND_INS_FISTP: return "fistp"; + case ND_INS_FISTTP: return "fisttp"; + case ND_INS_FISUB: return "fisub"; + case ND_INS_FISUBR: return "fisubr"; + case ND_INS_FLD: return "fld"; + case ND_INS_FLD1: return "fld1"; + case ND_INS_FLDCW: return "fldcw"; + case ND_INS_FLDENV: return "fldenv"; + case ND_INS_FLDL2E: return "fldl2e"; + case ND_INS_FLDL2T: return "fldl2t"; + case ND_INS_FLDLG2: return "fldlg2"; + case ND_INS_FLDLN2: return "fldln2"; + case ND_INS_FLDPI: return "fldpi"; + case ND_INS_FLDZ: return "fldz"; + case ND_INS_FMUL: return "fmul"; + case ND_INS_FMULP: return "fmulp"; + case ND_INS_FNCLEX: return "fnclex"; + case ND_INS_FNDISI: return "fndisi"; + case ND_INS_FNINIT: return "fninit"; + case ND_INS_FNOP: return "fnop"; + case ND_INS_FNSAVE: return "fnsave"; + case ND_INS_FNSTCW: return "fnstcw"; + case ND_INS_FNSTENV: return "fnstenv"; + case ND_INS_FNSTSW: return "fnstsw"; + case ND_INS_FPATAN: return "fpatan"; + case ND_INS_FPREM: return "fprem"; + case ND_INS_FPREM1: return "fprem1"; + case ND_INS_FPTAN: return "fptan"; + case ND_INS_FRINEAR: return "frinear"; + case ND_INS_FRNDINT: return "frndint"; + case ND_INS_FRSTOR: return "frstor"; + case ND_INS_FSCALE: return "fscale"; + case ND_INS_FSIN: return "fsin"; + case ND_INS_FSINCOS: return "fsincos"; + case ND_INS_FSQRT: return "fsqrt"; + case ND_INS_FST: return "fst"; + case ND_INS_FSTDW: return "fstdw"; + case ND_INS_FSTP: return "fstp"; + case ND_INS_FSTPNCE: return "fstpnce"; + case ND_INS_FSTSG: return "fstsg"; + case ND_INS_FSUB: return "fsub"; + case ND_INS_FSUBP: return "fsubp"; + case ND_INS_FSUBR: return "fsubr"; + case ND_INS_FSUBRP: return "fsubrp"; + case ND_INS_FTST: return "ftst"; + case ND_INS_FUCOM: return "fucom"; + case ND_INS_FUCOMI: return "fucomi"; + case ND_INS_FUCOMIP: return "fucomip"; + case ND_INS_FUCOMP: return "fucomp"; + case ND_INS_FUCOMPP: return "fucompp"; + case ND_INS_FXAM: return "fxam"; + case ND_INS_FXCH: return "fxch"; + case ND_INS_FXRSTOR: return "fxrstor"; + case ND_INS_FXRSTOR64: return "fxrstor64"; + case ND_INS_FXSAVE: return "fxsave"; + case ND_INS_FXSAVE64: return "fxsave64"; + case ND_INS_FXTRACT: return "fxtract"; + case ND_INS_FYL2X: return "fyl2x"; + case ND_INS_FYL2XP1: return "fyl2xp1"; + case ND_INS_GETSEC: return "getsec"; + case ND_INS_GF2P8AFFINEINVQB: return "gf2p8affineinvqb"; + case ND_INS_GF2P8AFFINEQB: return "gf2p8affineqb"; + case ND_INS_GF2P8MULB: return "gf2p8mulb"; + case ND_INS_HADDPD: return "haddpd"; + case ND_INS_HADDPS: return "haddps"; + case ND_INS_HLT: return "hlt"; + case ND_INS_HSUBPD: return "hsubpd"; + case ND_INS_HSUBPS: return "hsubps"; + case ND_INS_IDIV: return "idiv"; + case ND_INS_IMUL: return "imul"; + case ND_INS_IN: return "in"; + case ND_INS_INC: return "inc"; + case ND_INS_INCSSP: return "incssp"; + case ND_INS_INS: return "ins"; + case ND_INS_INSERTPS: return "insertps"; + case ND_INS_INSERTQ: return "insertq"; + case ND_INS_INT: return "int"; + case ND_INS_INT1: return "int1"; + case ND_INS_INT3: return "int3"; + case ND_INS_INTO: return "into"; + case ND_INS_INVD: return "invd"; + case ND_INS_INVEPT: return "invept"; + case ND_INS_INVLPG: return "invlpg"; + case ND_INS_INVLPGA: return "invlpga"; + case ND_INS_INVLPGB: return "invlpgb"; + case ND_INS_INVPCID: return "invpcid"; + case ND_INS_INVVPID: return "invvpid"; + case ND_INS_IRET: return "iret"; + case ND_INS_JMPE: return "jmpe"; + case ND_INS_JMPFD: return "jmpfd"; + case ND_INS_JMPFI: return "jmpfi"; + case ND_INS_JMPNI: return "jmpni"; + case ND_INS_JMPNR: return "jmpnr"; + case ND_INS_Jcc: return "jcc"; + case ND_INS_JrCXZ: return "jrcxz"; + case ND_INS_KADD: return "kadd"; + case ND_INS_KAND: return "kand"; + case ND_INS_KANDN: return "kandn"; + case ND_INS_KMERGE2L1H: return "kmerge2l1h"; + case ND_INS_KMERGE2L1L: return "kmerge2l1l"; + case ND_INS_KMOV: return "kmov"; + case ND_INS_KNOT: return "knot"; + case ND_INS_KOR: return "kor"; + case ND_INS_KORTEST: return "kortest"; + case ND_INS_KSHIFTL: return "kshiftl"; + case ND_INS_KSHIFTR: return "kshiftr"; + case ND_INS_KTEST: return "ktest"; + case ND_INS_KUNPCKBW: return "kunpckbw"; + case ND_INS_KUNPCKDQ: return "kunpckdq"; + case ND_INS_KUNPCKWD: return "kunpckwd"; + case ND_INS_KXNOR: return "kxnor"; + case ND_INS_KXOR: return "kxor"; + case ND_INS_LAHF: return "lahf"; + case ND_INS_LAR: return "lar"; + case ND_INS_LDDQU: return "lddqu"; + case ND_INS_LDMXCSR: return "ldmxcsr"; + case ND_INS_LDS: return "lds"; + case ND_INS_LDTILECFG: return "ldtilecfg"; + case ND_INS_LEA: return "lea"; + case ND_INS_LEAVE: return "leave"; + case ND_INS_LES: return "les"; + case ND_INS_LFENCE: return "lfence"; + case ND_INS_LFS: return "lfs"; + case ND_INS_LGDT: return "lgdt"; + case ND_INS_LGS: return "lgs"; + case ND_INS_LIDT: return "lidt"; + case ND_INS_LKGS: return "lkgs"; + case ND_INS_LLDT: return "lldt"; + case ND_INS_LLWPCB: return "llwpcb"; + case ND_INS_LMSW: return "lmsw"; + case ND_INS_LOADIWKEY: return "loadiwkey"; + case ND_INS_LODS: return "lods"; + case ND_INS_LOOP: return "loop"; + case ND_INS_LOOPNZ: return "loopnz"; + case ND_INS_LOOPZ: return "loopz"; + case ND_INS_LSL: return "lsl"; + case ND_INS_LSS: return "lss"; + case ND_INS_LTR: return "ltr"; + case ND_INS_LWPINS: return "lwpins"; + case ND_INS_LWPVAL: return "lwpval"; + case ND_INS_LZCNT: return "lzcnt"; + case ND_INS_MASKMOVDQU: return "maskmovdqu"; + case ND_INS_MASKMOVQ: return "maskmovq"; + case ND_INS_MAXPD: return "maxpd"; + case ND_INS_MAXPS: return "maxps"; + case ND_INS_MAXSD: return "maxsd"; + case ND_INS_MAXSS: return "maxss"; + case ND_INS_MCOMMIT: return "mcommit"; + case ND_INS_MFENCE: return "mfence"; + case ND_INS_MINPD: return "minpd"; + case ND_INS_MINPS: return "minps"; + case ND_INS_MINSD: return "minsd"; + case ND_INS_MINSS: return "minss"; + case ND_INS_MONITOR: return "monitor"; + case ND_INS_MONITORX: return "monitorx"; + case ND_INS_MONTMUL: return "montmul"; + case ND_INS_MOV: return "mov"; + case ND_INS_MOVAPD: return "movapd"; + case ND_INS_MOVAPS: return "movaps"; + case ND_INS_MOVBE: return "movbe"; + case ND_INS_MOVD: return "movd"; + case ND_INS_MOVDDUP: return "movddup"; + case ND_INS_MOVDIR64B: return "movdir64b"; + case ND_INS_MOVDIRI: return "movdiri"; + case ND_INS_MOVDQ2Q: return "movdq2q"; + case ND_INS_MOVDQA: return "movdqa"; + case ND_INS_MOVDQU: return "movdqu"; + case ND_INS_MOVHLPS: return "movhlps"; + case ND_INS_MOVHPD: return "movhpd"; + case ND_INS_MOVHPS: return "movhps"; + case ND_INS_MOVLHPS: return "movlhps"; + case ND_INS_MOVLPD: return "movlpd"; + case ND_INS_MOVLPS: return "movlps"; + case ND_INS_MOVMSKPD: return "movmskpd"; + case ND_INS_MOVMSKPS: return "movmskps"; + case ND_INS_MOVNTDQ: return "movntdq"; + case ND_INS_MOVNTDQA: return "movntdqa"; + case ND_INS_MOVNTI: return "movnti"; + case ND_INS_MOVNTPD: return "movntpd"; + case ND_INS_MOVNTPS: return "movntps"; + case ND_INS_MOVNTQ: return "movntq"; + case ND_INS_MOVNTSD: return "movntsd"; + case ND_INS_MOVNTSS: return "movntss"; + case ND_INS_MOVQ: return "movq"; + case ND_INS_MOVQ2DQ: return "movq2dq"; + case ND_INS_MOVS: return "movs"; + case ND_INS_MOVSD: return "movsd"; + case ND_INS_MOVSHDUP: return "movshdup"; + case ND_INS_MOVSLDUP: return "movsldup"; + case ND_INS_MOVSS: return "movss"; + case ND_INS_MOVSX: return "movsx"; + case ND_INS_MOVSXD: return "movsxd"; + case ND_INS_MOVUPD: return "movupd"; + case ND_INS_MOVUPS: return "movups"; + case ND_INS_MOVZX: return "movzx"; + case ND_INS_MOV_CR: return "movcr"; + case ND_INS_MOV_DR: return "movdr"; + case ND_INS_MOV_TR: return "movtr"; + case ND_INS_MPSADBW: return "mpsadbw"; + case ND_INS_MUL: return "mul"; + case ND_INS_MULPD: return "mulpd"; + case ND_INS_MULPS: return "mulps"; + case ND_INS_MULSD: return "mulsd"; + case ND_INS_MULSS: return "mulss"; + case ND_INS_MULX: return "mulx"; + case ND_INS_MWAIT: return "mwait"; + case ND_INS_MWAITX: return "mwaitx"; + case ND_INS_NEG: return "neg"; + case ND_INS_NOP: return "nop"; + case ND_INS_NOT: return "not"; + case ND_INS_OR: return "or"; + case ND_INS_ORPD: return "orpd"; + case ND_INS_ORPS: return "orps"; + case ND_INS_OUT: return "out"; + case ND_INS_OUTS: return "outs"; + case ND_INS_PABSB: return "pabsb"; + case ND_INS_PABSD: return "pabsd"; + case ND_INS_PABSW: return "pabsw"; + case ND_INS_PACKSSDW: return "packssdw"; + case ND_INS_PACKSSWB: return "packsswb"; + case ND_INS_PACKUSDW: return "packusdw"; + case ND_INS_PACKUSWB: return "packuswb"; + case ND_INS_PADDB: return "paddb"; + case ND_INS_PADDD: return "paddd"; + case ND_INS_PADDQ: return "paddq"; + case ND_INS_PADDSB: return "paddsb"; + case ND_INS_PADDSW: return "paddsw"; + case ND_INS_PADDUSB: return "paddusb"; + case ND_INS_PADDUSW: return "paddusw"; + case ND_INS_PADDW: return "paddw"; + case ND_INS_PALIGNR: return "palignr"; + case ND_INS_PAND: return "pand"; + case ND_INS_PANDN: return "pandn"; + case ND_INS_PAUSE: return "pause"; + case ND_INS_PAVGB: return "pavgb"; + case ND_INS_PAVGUSB: return "pavgusb"; + case ND_INS_PAVGW: return "pavgw"; + case ND_INS_PBLENDVB: return "pblendvb"; + case ND_INS_PBLENDW: return "pblendw"; + case ND_INS_PCLMULQDQ: return "pclmulqdq"; + case ND_INS_PCMPEQB: return "pcmpeqb"; + case ND_INS_PCMPEQD: return "pcmpeqd"; + case ND_INS_PCMPEQQ: return "pcmpeqq"; + case ND_INS_PCMPEQW: return "pcmpeqw"; + case ND_INS_PCMPESTRI: return "pcmpestri"; + case ND_INS_PCMPESTRM: return "pcmpestrm"; + case ND_INS_PCMPGTB: return "pcmpgtb"; + case ND_INS_PCMPGTD: return "pcmpgtd"; + case ND_INS_PCMPGTQ: return "pcmpgtq"; + case ND_INS_PCMPGTW: return "pcmpgtw"; + case ND_INS_PCMPISTRI: return "pcmpistri"; + case ND_INS_PCMPISTRM: return "pcmpistrm"; + case ND_INS_PCONFIG: return "pconfig"; + case ND_INS_PDEP: return "pdep"; + case ND_INS_PEXT: return "pext"; + case ND_INS_PEXTRB: return "pextrb"; + case ND_INS_PEXTRD: return "pextrd"; + case ND_INS_PEXTRQ: return "pextrq"; + case ND_INS_PEXTRW: return "pextrw"; + case ND_INS_PF2ID: return "pf2id"; + case ND_INS_PF2IW: return "pf2iw"; + case ND_INS_PFACC: return "pfacc"; + case ND_INS_PFADD: return "pfadd"; + case ND_INS_PFCMPEQ: return "pfcmpeq"; + case ND_INS_PFCMPGE: return "pfcmpge"; + case ND_INS_PFCMPGT: return "pfcmpgt"; + case ND_INS_PFMAX: return "pfmax"; + case ND_INS_PFMIN: return "pfmin"; + case ND_INS_PFMUL: return "pfmul"; + case ND_INS_PFNACC: return "pfnacc"; + case ND_INS_PFPNACC: return "pfpnacc"; + case ND_INS_PFRCP: return "pfrcp"; + case ND_INS_PFRCPIT1: return "pfrcpit1"; + case ND_INS_PFRCPIT2: return "pfrcpit2"; + case ND_INS_PFRCPV: return "pfrcpv"; + case ND_INS_PFRSQIT1: return "pfrsqit1"; + case ND_INS_PFRSQRT: return "pfrsqrt"; + case ND_INS_PFRSQRTV: return "pfrsqrtv"; + case ND_INS_PFSUB: return "pfsub"; + case ND_INS_PFSUBR: return "pfsubr"; + case ND_INS_PHADDD: return "phaddd"; + case ND_INS_PHADDSW: return "phaddsw"; + case ND_INS_PHADDW: return "phaddw"; + case ND_INS_PHMINPOSUW: return "phminposuw"; + case ND_INS_PHSUBD: return "phsubd"; + case ND_INS_PHSUBSW: return "phsubsw"; + case ND_INS_PHSUBW: return "phsubw"; + case ND_INS_PI2FD: return "pi2fd"; + case ND_INS_PI2FW: return "pi2fw"; + case ND_INS_PINSRB: return "pinsrb"; + case ND_INS_PINSRD: return "pinsrd"; + case ND_INS_PINSRQ: return "pinsrq"; + case ND_INS_PINSRW: return "pinsrw"; + case ND_INS_PMADDUBSW: return "pmaddubsw"; + case ND_INS_PMADDWD: return "pmaddwd"; + case ND_INS_PMAXSB: return "pmaxsb"; + case ND_INS_PMAXSD: return "pmaxsd"; + case ND_INS_PMAXSW: return "pmaxsw"; + case ND_INS_PMAXUB: return "pmaxub"; + case ND_INS_PMAXUD: return "pmaxud"; + case ND_INS_PMAXUW: return "pmaxuw"; + case ND_INS_PMINSB: return "pminsb"; + case ND_INS_PMINSD: return "pminsd"; + case ND_INS_PMINSW: return "pminsw"; + case ND_INS_PMINUB: return "pminub"; + case ND_INS_PMINUD: return "pminud"; + case ND_INS_PMINUW: return "pminuw"; + case ND_INS_PMOVMSKB: return "pmovmskb"; + case ND_INS_PMOVSXBD: return "pmovsxbd"; + case ND_INS_PMOVSXBQ: return "pmovsxbq"; + case ND_INS_PMOVSXBW: return "pmovsxbw"; + case ND_INS_PMOVSXDQ: return "pmovsxdq"; + case ND_INS_PMOVSXWD: return "pmovsxwd"; + case ND_INS_PMOVSXWQ: return "pmovsxwq"; + case ND_INS_PMOVZXBD: return "pmovzxbd"; + case ND_INS_PMOVZXBQ: return "pmovzxbq"; + case ND_INS_PMOVZXBW: return "pmovzxbw"; + case ND_INS_PMOVZXDQ: return "pmovzxdq"; + case ND_INS_PMOVZXWD: return "pmovzxwd"; + case ND_INS_PMOVZXWQ: return "pmovzxwq"; + case ND_INS_PMULDQ: return "pmuldq"; + case ND_INS_PMULHRSW: return "pmulhrsw"; + case ND_INS_PMULHRW: return "pmulhrw"; + case ND_INS_PMULHUW: return "pmulhuw"; + case ND_INS_PMULHW: return "pmulhw"; + case ND_INS_PMULLD: return "pmulld"; + case ND_INS_PMULLW: return "pmullw"; + case ND_INS_PMULUDQ: return "pmuludq"; + case ND_INS_POP: return "pop"; + case ND_INS_POPA: return "popa"; + case ND_INS_POPAD: return "popad"; + case ND_INS_POPCNT: return "popcnt"; + case ND_INS_POPF: return "popf"; + case ND_INS_POR: return "por"; + case ND_INS_PREFETCH: return "prefetch"; + case ND_INS_PREFETCHE: return "prefetche"; + case ND_INS_PREFETCHM: return "prefetchm"; + case ND_INS_PREFETCHNTA: return "prefetchnta"; + case ND_INS_PREFETCHT0: return "prefetcht0"; + case ND_INS_PREFETCHT1: return "prefetcht1"; + case ND_INS_PREFETCHT2: return "prefetcht2"; + case ND_INS_PREFETCHW: return "prefetchw"; + case ND_INS_PREFETCHWT1: return "prefetchwt1"; + case ND_INS_PSADBW: return "psadbw"; + case ND_INS_PSHUFB: return "pshufb"; + case ND_INS_PSHUFD: return "pshufd"; + case ND_INS_PSHUFHW: return "pshufhw"; + case ND_INS_PSHUFLW: return "pshuflw"; + case ND_INS_PSHUFW: return "pshufw"; + case ND_INS_PSIGNB: return "psignb"; + case ND_INS_PSIGND: return "psignd"; + case ND_INS_PSIGNW: return "psignw"; + case ND_INS_PSLLD: return "pslld"; + case ND_INS_PSLLDQ: return "pslldq"; + case ND_INS_PSLLQ: return "psllq"; + case ND_INS_PSLLW: return "psllw"; + case ND_INS_PSMASH: return "psmash"; + case ND_INS_PSRAD: return "psrad"; + case ND_INS_PSRAW: return "psraw"; + case ND_INS_PSRLD: return "psrld"; + case ND_INS_PSRLDQ: return "psrldq"; + case ND_INS_PSRLQ: return "psrlq"; + case ND_INS_PSRLW: return "psrlw"; + case ND_INS_PSUBB: return "psubb"; + case ND_INS_PSUBD: return "psubd"; + case ND_INS_PSUBQ: return "psubq"; + case ND_INS_PSUBSB: return "psubsb"; + case ND_INS_PSUBSW: return "psubsw"; + case ND_INS_PSUBUSB: return "psubusb"; + case ND_INS_PSUBUSW: return "psubusw"; + case ND_INS_PSUBW: return "psubw"; + case ND_INS_PSWAPD: return "pswapd"; + case ND_INS_PTEST: return "ptest"; + case ND_INS_PTWRITE: return "ptwrite"; + case ND_INS_PUNPCKHBW: return "punpckhbw"; + case ND_INS_PUNPCKHDQ: return "punpckhdq"; + case ND_INS_PUNPCKHQDQ: return "punpckhqdq"; + case ND_INS_PUNPCKHWD: return "punpckhwd"; + case ND_INS_PUNPCKLBW: return "punpcklbw"; + case ND_INS_PUNPCKLDQ: return "punpckldq"; + case ND_INS_PUNPCKLQDQ: return "punpcklqdq"; + case ND_INS_PUNPCKLWD: return "punpcklwd"; + case ND_INS_PUSH: return "push"; + case ND_INS_PUSHA: return "pusha"; + case ND_INS_PUSHAD: return "pushad"; + case ND_INS_PUSHF: return "pushf"; + case ND_INS_PVALIDATE: return "pvalidate"; + case ND_INS_PXOR: return "pxor"; + case ND_INS_RCL: return "rcl"; + case ND_INS_RCPPS: return "rcpps"; + case ND_INS_RCPSS: return "rcpss"; + case ND_INS_RCR: return "rcr"; + case ND_INS_RDFSBASE: return "rdfsbase"; + case ND_INS_RDGSBASE: return "rdgsbase"; + case ND_INS_RDMSR: return "rdmsr"; + case ND_INS_RDPID: return "rdpid"; + case ND_INS_RDPKRU: return "rdpkru"; + case ND_INS_RDPMC: return "rdpmc"; + case ND_INS_RDPRU: return "rdpru"; + case ND_INS_RDRAND: return "rdrand"; + case ND_INS_RDSEED: return "rdseed"; + case ND_INS_RDSHR: return "rdshr"; + case ND_INS_RDTSC: return "rdtsc"; + case ND_INS_RDTSCP: return "rdtscp"; + case ND_INS_RETF: return "retf"; + case ND_INS_RETN: return "retn"; + case ND_INS_RMPADJUST: return "rmpadjust"; + case ND_INS_RMPUPDATE: return "rmpupdate"; + case ND_INS_ROL: return "rol"; + case ND_INS_ROR: return "ror"; + case ND_INS_RORX: return "rorx"; + case ND_INS_ROUNDPD: return "roundpd"; + case ND_INS_ROUNDPS: return "roundps"; + case ND_INS_ROUNDSD: return "roundsd"; + case ND_INS_ROUNDSS: return "roundss"; + case ND_INS_RSDC: return "rsdc"; + case ND_INS_RSLDT: return "rsldt"; + case ND_INS_RSM: return "rsm"; + case ND_INS_RSQRTPS: return "rsqrtps"; + case ND_INS_RSQRTSS: return "rsqrtss"; + case ND_INS_RSSSP: return "rsssp"; + case ND_INS_RSTORSSP: return "rstorssp"; + case ND_INS_RSTS: return "rsts"; + case ND_INS_SAHF: return "sahf"; + case ND_INS_SAL: return "sal"; + case ND_INS_SALC: return "salc"; + case ND_INS_SAR: return "sar"; + case ND_INS_SARX: return "sarx"; + case ND_INS_SAVEPREVSSP: return "saveprevssp"; + case ND_INS_SBB: return "sbb"; + case ND_INS_SCAS: return "scas"; + case ND_INS_SEAMOPS: return "seamops"; + case ND_INS_SEAMCALL: return "seamcall"; + case ND_INS_SEAMRET: return "seamret"; + case ND_INS_SERIALIZE: return "serialize"; + case ND_INS_SETSSBSY: return "setssbsy"; + case ND_INS_SETcc: return "setcc"; + case ND_INS_SFENCE: return "sfence"; + case ND_INS_SGDT: return "sgdt"; + case ND_INS_SHA1MSG1: return "sha1msg1"; + case ND_INS_SHA1MSG2: return "sha1msg2"; + case ND_INS_SHA1NEXTE: return "sha1nexte"; + case ND_INS_SHA1RNDS4: return "sha1rnds4"; + case ND_INS_SHA256MSG1: return "sha256msg1"; + case ND_INS_SHA256MSG2: return "sha256msg2"; + case ND_INS_SHA256RNDS2: return "sha256rnds2"; + case ND_INS_SHL: return "shl"; + case ND_INS_SHLD: return "shld"; + case ND_INS_SHLX: return "shlx"; + case ND_INS_SHR: return "shr"; + case ND_INS_SHRD: return "shrd"; + case ND_INS_SHRX: return "shrx"; + case ND_INS_SHUFPD: return "shufpd"; + case ND_INS_SHUFPS: return "shufps"; + case ND_INS_SIDT: return "sidt"; + case ND_INS_SKINIT: return "skinit"; + case ND_INS_SLDT: return "sldt"; + case ND_INS_SLWPCB: return "slwpcb"; + case ND_INS_SMINT: return "smint"; + case ND_INS_SMSW: return "smsw"; + case ND_INS_SPFLT: return "spflt"; + case ND_INS_SQRTPD: return "sqrtpd"; + case ND_INS_SQRTPS: return "sqrtps"; + case ND_INS_SQRTSD: return "sqrtsd"; + case ND_INS_SQRTSS: return "sqrtss"; + case ND_INS_STAC: return "stac"; + case ND_INS_STC: return "stc"; + case ND_INS_STD: return "std"; + case ND_INS_STGI: return "stgi"; + case ND_INS_STI: return "sti"; + case ND_INS_STMXCSR: return "stmxcsr"; + case ND_INS_STOS: return "stos"; + case ND_INS_STR: return "str"; + case ND_INS_STTILECFG: return "sttilecfg"; + case ND_INS_SUB: return "sub"; + case ND_INS_SUBPD: return "subpd"; + case ND_INS_SUBPS: return "subps"; + case ND_INS_SUBSD: return "subsd"; + case ND_INS_SUBSS: return "subss"; + case ND_INS_SVDC: return "svdc"; + case ND_INS_SVLDT: return "svldt"; + case ND_INS_SVTS: return "svts"; + case ND_INS_SWAPGS: return "swapgs"; + case ND_INS_SYSCALL: return "syscall"; + case ND_INS_SYSENTER: return "sysenter"; + case ND_INS_SYSEXIT: return "sysexit"; + case ND_INS_SYSRET: return "sysret"; + case ND_INS_T1MSKC: return "t1mskc"; + case ND_INS_TDCALL: return "tdcall"; + case ND_INS_TDPBF16PS: return "tdpbf16ps"; + case ND_INS_TDPBSSD: return "tdpbssd"; + case ND_INS_TDPBSUD: return "tdpbsud"; + case ND_INS_TDPBUSD: return "tdpbusd"; + case ND_INS_TDPBUUD: return "tdpbuud"; + case ND_INS_TEST: return "test"; + case ND_INS_TILELOADD: return "tileloadd"; + case ND_INS_TILELOADDT1: return "tileloaddt1"; + case ND_INS_TILERELEASE: return "tilerelease"; + case ND_INS_TILESTORED: return "tilestored"; + case ND_INS_TILEZERO: return "tilezero"; + case ND_INS_TLBSYNC: return "tlbsync"; + case ND_INS_TPAUSE: return "tpause"; + case ND_INS_TZCNT: return "tzcnt"; + case ND_INS_TZMSK: return "tzmsk"; + case ND_INS_UCOMISD: return "ucomisd"; + case ND_INS_UCOMISS: return "ucomiss"; + case ND_INS_UD0: return "ud0"; + case ND_INS_UD1: return "ud1"; + case ND_INS_UD2: return "ud2"; + case ND_INS_UMONITOR: return "umonitor"; + case ND_INS_UMWAIT: return "umwait"; + case ND_INS_UNPCKHPD: return "unpckhpd"; + case ND_INS_UNPCKHPS: return "unpckhps"; + case ND_INS_UNPCKLPD: return "unpcklpd"; + case ND_INS_UNPCKLPS: return "unpcklps"; + case ND_INS_V4FMADDPS: return "v4fmaddps"; + case ND_INS_V4FMADDSS: return "v4fmaddss"; + case ND_INS_V4FNMADDPS: return "v4fnmaddps"; + case ND_INS_V4FNMADDSS: return "v4fnmaddss"; + case ND_INS_VADDPD: return "vaddpd"; + case ND_INS_VADDPS: return "vaddps"; + case ND_INS_VADDSD: return "vaddsd"; + case ND_INS_VADDSS: return "vaddss"; + case ND_INS_VADDSUBPD: return "vaddsubpd"; + case ND_INS_VADDSUBPS: return "vaddsubps"; + case ND_INS_VAESDEC: return "vaesdec"; + case ND_INS_VAESDECLAST: return "vaesdeclast"; + case ND_INS_VAESENC: return "vaesenc"; + case ND_INS_VAESENCLAST: return "vaesenclast"; + case ND_INS_VAESIMC: return "vaesimc"; + case ND_INS_VAESKEYGENASSIST: return "vaeskeygenassist"; + case ND_INS_VALIGND: return "valignd"; + case ND_INS_VALIGNQ: return "valignq"; + case ND_INS_VANDNPD: return "vandnpd"; + case ND_INS_VANDNPS: return "vandnps"; + case ND_INS_VANDPD: return "vandpd"; + case ND_INS_VANDPS: return "vandps"; + case ND_INS_VBLENDMPD: return "vblendmpd"; + case ND_INS_VBLENDMPS: return "vblendmps"; + case ND_INS_VBLENDPD: return "vblendpd"; + case ND_INS_VBLENDPS: return "vblendps"; + case ND_INS_VBLENDVPD: return "vblendvpd"; + case ND_INS_VBLENDVPS: return "vblendvps"; + case ND_INS_VBROADCASTF128: return "vbroadcastf128"; + case ND_INS_VBROADCASTF32X2: return "vbroadcastf32x2"; + case ND_INS_VBROADCASTF32X4: return "vbroadcastf32x4"; + case ND_INS_VBROADCASTF32X8: return "vbroadcastf32x8"; + case ND_INS_VBROADCASTF64X2: return "vbroadcastf64x2"; + case ND_INS_VBROADCASTF64X4: return "vbroadcastf64x4"; + case ND_INS_VBROADCASTI128: return "vbroadcasti128"; + case ND_INS_VBROADCASTI32X2: return "vbroadcasti32x2"; + case ND_INS_VBROADCASTI32X4: return "vbroadcasti32x4"; + case ND_INS_VBROADCASTI32X8: return "vbroadcasti32x8"; + case ND_INS_VBROADCASTI64X2: return "vbroadcasti64x2"; + case ND_INS_VBROADCASTI64X4: return "vbroadcasti64x4"; + case ND_INS_VBROADCASTSD: return "vbroadcastsd"; + case ND_INS_VBROADCASTSS: return "vbroadcastss"; + case ND_INS_VCMPPD: return "vcmppd"; + case ND_INS_VCMPPS: return "vcmpps"; + case ND_INS_VCMPSD: return "vcmpsd"; + case ND_INS_VCMPSS: return "vcmpss"; + case ND_INS_VCOMISD: return "vcomisd"; + case ND_INS_VCOMISS: return "vcomiss"; + case ND_INS_VCOMPRESSPD: return "vcompresspd"; + case ND_INS_VCOMPRESSPS: return "vcompressps"; + case ND_INS_VCVTDQ2PD: return "vcvtdq2pd"; + case ND_INS_VCVTDQ2PS: return "vcvtdq2ps"; + case ND_INS_VCVTNE2PS2BF16: return "vcvtne2ps2bf16"; + case ND_INS_VCVTNEPS2BF16: return "vcvtneps2bf16"; + case ND_INS_VCVTPD2DQ: return "vcvtpd2dq"; + case ND_INS_VCVTPD2PS: return "vcvtpd2ps"; + case ND_INS_VCVTPD2QQ: return "vcvtpd2qq"; + case ND_INS_VCVTPD2UDQ: return "vcvtpd2udq"; + case ND_INS_VCVTPD2UQQ: return "vcvtpd2uqq"; + case ND_INS_VCVTPH2PS: return "vcvtph2ps"; + case ND_INS_VCVTPS2DQ: return "vcvtps2dq"; + case ND_INS_VCVTPS2PD: return "vcvtps2pd"; + case ND_INS_VCVTPS2PH: return "vcvtps2ph"; + case ND_INS_VCVTPS2QQ: return "vcvtps2qq"; + case ND_INS_VCVTPS2UDQ: return "vcvtps2udq"; + case ND_INS_VCVTPS2UQQ: return "vcvtps2uqq"; + case ND_INS_VCVTQQ2PD: return "vcvtqq2pd"; + case ND_INS_VCVTQQ2PS: return "vcvtqq2ps"; + case ND_INS_VCVTSD2SI: return "vcvtsd2si"; + case ND_INS_VCVTSD2SS: return "vcvtsd2ss"; + case ND_INS_VCVTSD2USI: return "vcvtsd2usi"; + case ND_INS_VCVTSI2SD: return "vcvtsi2sd"; + case ND_INS_VCVTSI2SS: return "vcvtsi2ss"; + case ND_INS_VCVTSS2SD: return "vcvtss2sd"; + case ND_INS_VCVTSS2SI: return "vcvtss2si"; + case ND_INS_VCVTSS2USI: return "vcvtss2usi"; + case ND_INS_VCVTTPD2DQ: return "vcvttpd2dq"; + case ND_INS_VCVTTPD2QQ: return "vcvttpd2qq"; + case ND_INS_VCVTTPD2UDQ: return "vcvttpd2udq"; + case ND_INS_VCVTTPD2UQQ: return "vcvttpd2uqq"; + case ND_INS_VCVTTPS2DQ: return "vcvttps2dq"; + case ND_INS_VCVTTPS2QQ: return "vcvttps2qq"; + case ND_INS_VCVTTPS2UDQ: return "vcvttps2udq"; + case ND_INS_VCVTTPS2UQQ: return "vcvttps2uqq"; + case ND_INS_VCVTTSD2SI: return "vcvttsd2si"; + case ND_INS_VCVTTSD2USI: return "vcvttsd2usi"; + case ND_INS_VCVTTSS2SI: return "vcvttss2si"; + case ND_INS_VCVTTSS2USI: return "vcvttss2usi"; + case ND_INS_VCVTUDQ2PD: return "vcvtudq2pd"; + case ND_INS_VCVTUDQ2PS: return "vcvtudq2ps"; + case ND_INS_VCVTUQQ2PD: return "vcvtuqq2pd"; + case ND_INS_VCVTUQQ2PS: return "vcvtuqq2ps"; + case ND_INS_VCVTUSI2SD: return "vcvtusi2sd"; + case ND_INS_VCVTUSI2SS: return "vcvtusi2ss"; + case ND_INS_VDBPSADBW: return "vdbpsadbw"; + case ND_INS_VDIVPD: return "vdivpd"; + case ND_INS_VDIVPS: return "vdivps"; + case ND_INS_VDIVSD: return "vdivsd"; + case ND_INS_VDIVSS: return "vdivss"; + case ND_INS_VDPBF16PS: return "vdpbf16ps"; + case ND_INS_VDPPD: return "vdppd"; + case ND_INS_VDPPS: return "vdpps"; + case ND_INS_VERR: return "verr"; + case ND_INS_VERW: return "verw"; + case ND_INS_VEXP2PD: return "vexp2pd"; + case ND_INS_VEXP2PS: return "vexp2ps"; + case ND_INS_VEXPANDPD: return "vexpandpd"; + case ND_INS_VEXPANDPS: return "vexpandps"; + case ND_INS_VEXTRACTF128: return "vextractf128"; + case ND_INS_VEXTRACTF32X4: return "vextractf32x4"; + case ND_INS_VEXTRACTF32X8: return "vextractf32x8"; + case ND_INS_VEXTRACTF64X2: return "vextractf64x2"; + case ND_INS_VEXTRACTF64X4: return "vextractf64x4"; + case ND_INS_VEXTRACTI128: return "vextracti128"; + case ND_INS_VEXTRACTI32X4: return "vextracti32x4"; + case ND_INS_VEXTRACTI32X8: return "vextracti32x8"; + case ND_INS_VEXTRACTI64X2: return "vextracti64x2"; + case ND_INS_VEXTRACTI64X4: return "vextracti64x4"; + case ND_INS_VEXTRACTPS: return "vextractps"; + case ND_INS_VFIXUPIMMPD: return "vfixupimmpd"; + case ND_INS_VFIXUPIMMPS: return "vfixupimmps"; + case ND_INS_VFIXUPIMMSD: return "vfixupimmsd"; + case ND_INS_VFIXUPIMMSS: return "vfixupimmss"; + case ND_INS_VFMADD132PD: return "vfmadd132pd"; + case ND_INS_VFMADD132PS: return "vfmadd132ps"; + case ND_INS_VFMADD132SD: return "vfmadd132sd"; + case ND_INS_VFMADD132SS: return "vfmadd132ss"; + case ND_INS_VFMADD213PD: return "vfmadd213pd"; + case ND_INS_VFMADD213PS: return "vfmadd213ps"; + case ND_INS_VFMADD213SD: return "vfmadd213sd"; + case ND_INS_VFMADD213SS: return "vfmadd213ss"; + case ND_INS_VFMADD231PD: return "vfmadd231pd"; + case ND_INS_VFMADD231PS: return "vfmadd231ps"; + case ND_INS_VFMADD231SD: return "vfmadd231sd"; + case ND_INS_VFMADD231SS: return "vfmadd231ss"; + case ND_INS_VFMADDPD: return "vfmaddpd"; + case ND_INS_VFMADDPS: return "vfmaddps"; + case ND_INS_VFMADDSD: return "vfmaddsd"; + case ND_INS_VFMADDSS: return "vfmaddss"; + case ND_INS_VFMADDSUB132PD: return "vfmaddsub132pd"; + case ND_INS_VFMADDSUB132PS: return "vfmaddsub132ps"; + case ND_INS_VFMADDSUB213PD: return "vfmaddsub213pd"; + case ND_INS_VFMADDSUB213PS: return "vfmaddsub213ps"; + case ND_INS_VFMADDSUB231PD: return "vfmaddsub231pd"; + case ND_INS_VFMADDSUB231PS: return "vfmaddsub231ps"; + case ND_INS_VFMADDSUBPD: return "vfmaddsubpd"; + case ND_INS_VFMADDSUBPS: return "vfmaddsubps"; + case ND_INS_VFMSUB132PD: return "vfmsub132pd"; + case ND_INS_VFMSUB132PS: return "vfmsub132ps"; + case ND_INS_VFMSUB132SD: return "vfmsub132sd"; + case ND_INS_VFMSUB132SS: return "vfmsub132ss"; + case ND_INS_VFMSUB213PD: return "vfmsub213pd"; + case ND_INS_VFMSUB213PS: return "vfmsub213ps"; + case ND_INS_VFMSUB213SD: return "vfmsub213sd"; + case ND_INS_VFMSUB213SS: return "vfmsub213ss"; + case ND_INS_VFMSUB231PD: return "vfmsub231pd"; + case ND_INS_VFMSUB231PS: return "vfmsub231ps"; + case ND_INS_VFMSUB231SD: return "vfmsub231sd"; + case ND_INS_VFMSUB231SS: return "vfmsub231ss"; + case ND_INS_VFMSUBADD132PD: return "vfmsubadd132pd"; + case ND_INS_VFMSUBADD132PS: return "vfmsubadd132ps"; + case ND_INS_VFMSUBADD213PD: return "vfmsubadd213pd"; + case ND_INS_VFMSUBADD213PS: return "vfmsubadd213ps"; + case ND_INS_VFMSUBADD231PD: return "vfmsubadd231pd"; + case ND_INS_VFMSUBADD231PS: return "vfmsubadd231ps"; + case ND_INS_VFMSUBADDPD: return "vfmsubaddpd"; + case ND_INS_VFMSUBADDPS: return "vfmsubaddps"; + case ND_INS_VFMSUBPD: return "vfmsubpd"; + case ND_INS_VFMSUBPS: return "vfmsubps"; + case ND_INS_VFMSUBSD: return "vfmsubsd"; + case ND_INS_VFMSUBSS: return "vfmsubss"; + case ND_INS_VFNMADD132PD: return "vfnmadd132pd"; + case ND_INS_VFNMADD132PS: return "vfnmadd132ps"; + case ND_INS_VFNMADD132SD: return "vfnmadd132sd"; + case ND_INS_VFNMADD132SS: return "vfnmadd132ss"; + case ND_INS_VFNMADD213PD: return "vfnmadd213pd"; + case ND_INS_VFNMADD213PS: return "vfnmadd213ps"; + case ND_INS_VFNMADD213SD: return "vfnmadd213sd"; + case ND_INS_VFNMADD213SS: return "vfnmadd213ss"; + case ND_INS_VFNMADD231PD: return "vfnmadd231pd"; + case ND_INS_VFNMADD231PS: return "vfnmadd231ps"; + case ND_INS_VFNMADD231SD: return "vfnmadd231sd"; + case ND_INS_VFNMADD231SS: return "vfnmadd231ss"; + case ND_INS_VFNMADDPD: return "vfnmaddpd"; + case ND_INS_VFNMADDPS: return "vfnmaddps"; + case ND_INS_VFNMADDSD: return "vfnmaddsd"; + case ND_INS_VFNMADDSS: return "vfnmaddss"; + case ND_INS_VFNMSUB132PD: return "vfnmsub132pd"; + case ND_INS_VFNMSUB132PS: return "vfnmsub132ps"; + case ND_INS_VFNMSUB132SD: return "vfnmsub132sd"; + case ND_INS_VFNMSUB132SS: return "vfnmsub132ss"; + case ND_INS_VFNMSUB213PD: return "vfnmsub213pd"; + case ND_INS_VFNMSUB213PS: return "vfnmsub213ps"; + case ND_INS_VFNMSUB213SD: return "vfnmsub213sd"; + case ND_INS_VFNMSUB213SS: return "vfnmsub213ss"; + case ND_INS_VFNMSUB231PD: return "vfnmsub231pd"; + case ND_INS_VFNMSUB231PS: return "vfnmsub231ps"; + case ND_INS_VFNMSUB231SD: return "vfnmsub231sd"; + case ND_INS_VFNMSUB231SS: return "vfnmsub231ss"; + case ND_INS_VFNMSUBPD: return "vfnmsubpd"; + case ND_INS_VFNMSUBPS: return "vfnmsubps"; + case ND_INS_VFNMSUBSD: return "vfnmsubsd"; + case ND_INS_VFNMSUBSS: return "vfnmsubss"; + case ND_INS_VFPCLASSPD: return "vfpclasspd"; + case ND_INS_VFPCLASSPS: return "vfpclassps"; + case ND_INS_VFPCLASSSD: return "vfpclasssd"; + case ND_INS_VFPCLASSSS: return "vfpclassss"; + case ND_INS_VFRCZPD: return "vfrczpd"; + case ND_INS_VFRCZPS: return "vfrczps"; + case ND_INS_VFRCZSD: return "vfrczsd"; + case ND_INS_VFRCZSS: return "vfrczss"; + case ND_INS_VGATHERDPD: return "vgatherdpd"; + case ND_INS_VGATHERDPS: return "vgatherdps"; + case ND_INS_VGATHERPF0DPD: return "vgatherpf0dpd"; + case ND_INS_VGATHERPF0DPS: return "vgatherpf0dps"; + case ND_INS_VGATHERPF0QPD: return "vgatherpf0qpd"; + case ND_INS_VGATHERPF0QPS: return "vgatherpf0qps"; + case ND_INS_VGATHERPF1DPD: return "vgatherpf1dpd"; + case ND_INS_VGATHERPF1DPS: return "vgatherpf1dps"; + case ND_INS_VGATHERPF1QPD: return "vgatherpf1qpd"; + case ND_INS_VGATHERPF1QPS: return "vgatherpf1qps"; + case ND_INS_VGATHERQPD: return "vgatherqpd"; + case ND_INS_VGATHERQPS: return "vgatherqps"; + case ND_INS_VGETEXPPD: return "vgetexppd"; + case ND_INS_VGETEXPPS: return "vgetexpps"; + case ND_INS_VGETEXPSD: return "vgetexpsd"; + case ND_INS_VGETEXPSS: return "vgetexpss"; + case ND_INS_VGETMANTPD: return "vgetmantpd"; + case ND_INS_VGETMANTPS: return "vgetmantps"; + case ND_INS_VGETMANTSD: return "vgetmantsd"; + case ND_INS_VGETMANTSS: return "vgetmantss"; + case ND_INS_VGF2P8AFFINEINVQB: return "vgf2p8affineinvqb"; + case ND_INS_VGF2P8AFFINEQB: return "vgf2p8affineqb"; + case ND_INS_VGF2P8MULB: return "vgf2p8mulb"; + case ND_INS_VHADDPD: return "vhaddpd"; + case ND_INS_VHADDPS: return "vhaddps"; + case ND_INS_VHSUBPD: return "vhsubpd"; + case ND_INS_VHSUBPS: return "vhsubps"; + case ND_INS_VINSERTF128: return "vinsertf128"; + case ND_INS_VINSERTF32X4: return "vinsertf32x4"; + case ND_INS_VINSERTF32X8: return "vinsertf32x8"; + case ND_INS_VINSERTF64X2: return "vinsertf64x2"; + case ND_INS_VINSERTF64X4: return "vinsertf64x4"; + case ND_INS_VINSERTI128: return "vinserti128"; + case ND_INS_VINSERTI32X4: return "vinserti32x4"; + case ND_INS_VINSERTI32X8: return "vinserti32x8"; + case ND_INS_VINSERTI64X2: return "vinserti64x2"; + case ND_INS_VINSERTI64X4: return "vinserti64x4"; + case ND_INS_VINSERTPS: return "vinsertps"; + case ND_INS_VLDDQU: return "vlddqu"; + case ND_INS_VLDMXCSR: return "vldmxcsr"; + case ND_INS_VMASKMOVDQU: return "vmaskmovdqu"; + case ND_INS_VMASKMOVPD: return "vmaskmovpd"; + case ND_INS_VMASKMOVPS: return "vmaskmovps"; + case ND_INS_VMAXPD: return "vmaxpd"; + case ND_INS_VMAXPS: return "vmaxps"; + case ND_INS_VMAXSD: return "vmaxsd"; + case ND_INS_VMAXSS: return "vmaxss"; + case ND_INS_VMCALL: return "vmcall"; + case ND_INS_VMCLEAR: return "vmclear"; + case ND_INS_VMFUNC: return "vmfunc"; + case ND_INS_VMGEXIT: return "vmgexit"; + case ND_INS_VMINPD: return "vminpd"; + case ND_INS_VMINPS: return "vminps"; + case ND_INS_VMINSD: return "vminsd"; + case ND_INS_VMINSS: return "vminss"; + case ND_INS_VMLAUNCH: return "vmlaunch"; + case ND_INS_VMLOAD: return "vmload"; + case ND_INS_VMMCALL: return "vmmcall"; + case ND_INS_VMOVAPD: return "vmovapd"; + case ND_INS_VMOVAPS: return "vmovaps"; + case ND_INS_VMOVD: return "vmovd"; + case ND_INS_VMOVDDUP: return "vmovddup"; + case ND_INS_VMOVDQA: return "vmovdqa"; + case ND_INS_VMOVDQA32: return "vmovdqa32"; + case ND_INS_VMOVDQA64: return "vmovdqa64"; + case ND_INS_VMOVDQU: return "vmovdqu"; + case ND_INS_VMOVDQU16: return "vmovdqu16"; + case ND_INS_VMOVDQU32: return "vmovdqu32"; + case ND_INS_VMOVDQU64: return "vmovdqu64"; + case ND_INS_VMOVDQU8: return "vmovdqu8"; + case ND_INS_VMOVHLPS: return "vmovhlps"; + case ND_INS_VMOVHPD: return "vmovhpd"; + case ND_INS_VMOVHPS: return "vmovhps"; + case ND_INS_VMOVLHPS: return "vmovlhps"; + case ND_INS_VMOVLPD: return "vmovlpd"; + case ND_INS_VMOVLPS: return "vmovlps"; + case ND_INS_VMOVMSKPD: return "vmovmskpd"; + case ND_INS_VMOVMSKPS: return "vmovmskps"; + case ND_INS_VMOVNTDQ: return "vmovntdq"; + case ND_INS_VMOVNTDQA: return "vmovntdqa"; + case ND_INS_VMOVNTPD: return "vmovntpd"; + case ND_INS_VMOVNTPS: return "vmovntps"; + case ND_INS_VMOVQ: return "vmovq"; + case ND_INS_VMOVSD: return "vmovsd"; + case ND_INS_VMOVSHDUP: return "vmovshdup"; + case ND_INS_VMOVSLDUP: return "vmovsldup"; + case ND_INS_VMOVSS: return "vmovss"; + case ND_INS_VMOVUPD: return "vmovupd"; + case ND_INS_VMOVUPS: return "vmovups"; + case ND_INS_VMPSADBW: return "vmpsadbw"; + case ND_INS_VMPTRLD: return "vmptrld"; + case ND_INS_VMPTRST: return "vmptrst"; + case ND_INS_VMREAD: return "vmread"; + case ND_INS_VMRESUME: return "vmresume"; + case ND_INS_VMRUN: return "vmrun"; + case ND_INS_VMSAVE: return "vmsave"; + case ND_INS_VMULPD: return "vmulpd"; + case ND_INS_VMULPS: return "vmulps"; + case ND_INS_VMULSD: return "vmulsd"; + case ND_INS_VMULSS: return "vmulss"; + case ND_INS_VMWRITE: return "vmwrite"; + case ND_INS_VMXOFF: return "vmxoff"; + case ND_INS_VMXON: return "vmxon"; + case ND_INS_VORPD: return "vorpd"; + case ND_INS_VORPS: return "vorps"; + case ND_INS_VP2INTERSECTD: return "vp2intersectd"; + case ND_INS_VP2INTERSECTQ: return "vp2intersectq"; + case ND_INS_VP4DPWSSD: return "vp4dpwssd"; + case ND_INS_VP4DPWSSDS: return "vp4dpwssds"; + case ND_INS_VPABSB: return "vpabsb"; + case ND_INS_VPABSD: return "vpabsd"; + case ND_INS_VPABSQ: return "vpabsq"; + case ND_INS_VPABSW: return "vpabsw"; + case ND_INS_VPACKSSDW: return "vpackssdw"; + case ND_INS_VPACKSSWB: return "vpacksswb"; + case ND_INS_VPACKUSDW: return "vpackusdw"; + case ND_INS_VPACKUSWB: return "vpackuswb"; + case ND_INS_VPADDB: return "vpaddb"; + case ND_INS_VPADDD: return "vpaddd"; + case ND_INS_VPADDQ: return "vpaddq"; + case ND_INS_VPADDSB: return "vpaddsb"; + case ND_INS_VPADDSW: return "vpaddsw"; + case ND_INS_VPADDUSB: return "vpaddusb"; + case ND_INS_VPADDUSW: return "vpaddusw"; + case ND_INS_VPADDW: return "vpaddw"; + case ND_INS_VPALIGNR: return "vpalignr"; + case ND_INS_VPAND: return "vpand"; + case ND_INS_VPANDD: return "vpandd"; + case ND_INS_VPANDN: return "vpandn"; + case ND_INS_VPANDND: return "vpandnd"; + case ND_INS_VPANDNQ: return "vpandnq"; + case ND_INS_VPANDQ: return "vpandq"; + case ND_INS_VPAVGB: return "vpavgb"; + case ND_INS_VPAVGW: return "vpavgw"; + case ND_INS_VPBLENDD: return "vpblendd"; + case ND_INS_VPBLENDMB: return "vpblendmb"; + case ND_INS_VPBLENDMD: return "vpblendmd"; + case ND_INS_VPBLENDMQ: return "vpblendmq"; + case ND_INS_VPBLENDMW: return "vpblendmw"; + case ND_INS_VPBLENDVB: return "vpblendvb"; + case ND_INS_VPBLENDW: return "vpblendw"; + case ND_INS_VPBROADCASTB: return "vpbroadcastb"; + case ND_INS_VPBROADCASTD: return "vpbroadcastd"; + case ND_INS_VPBROADCASTMB2Q: return "vpbroadcastmb2q"; + case ND_INS_VPBROADCASTMW2D: return "vpbroadcastmw2d"; + case ND_INS_VPBROADCASTQ: return "vpbroadcastq"; + case ND_INS_VPBROADCASTW: return "vpbroadcastw"; + case ND_INS_VPCLMULQDQ: return "vpclmulqdq"; + case ND_INS_VPCMOV: return "vpcmov"; + case ND_INS_VPCMPB: return "vpcmpb"; + case ND_INS_VPCMPD: return "vpcmpd"; + case ND_INS_VPCMPEQB: return "vpcmpeqb"; + case ND_INS_VPCMPEQD: return "vpcmpeqd"; + case ND_INS_VPCMPEQQ: return "vpcmpeqq"; + case ND_INS_VPCMPEQW: return "vpcmpeqw"; + case ND_INS_VPCMPESTRI: return "vpcmpestri"; + case ND_INS_VPCMPESTRM: return "vpcmpestrm"; + case ND_INS_VPCMPGTB: return "vpcmpgtb"; + case ND_INS_VPCMPGTD: return "vpcmpgtd"; + case ND_INS_VPCMPGTQ: return "vpcmpgtq"; + case ND_INS_VPCMPGTW: return "vpcmpgtw"; + case ND_INS_VPCMPISTRI: return "vpcmpistri"; + case ND_INS_VPCMPISTRM: return "vpcmpistrm"; + case ND_INS_VPCMPQ: return "vpcmpq"; + case ND_INS_VPCMPUB: return "vpcmpub"; + case ND_INS_VPCMPUD: return "vpcmpud"; + case ND_INS_VPCMPUQ: return "vpcmpuq"; + case ND_INS_VPCMPUW: return "vpcmpuw"; + case ND_INS_VPCMPW: return "vpcmpw"; + case ND_INS_VPCOMB: return "vpcomb"; + case ND_INS_VPCOMD: return "vpcomd"; + case ND_INS_VPCOMPRESSB: return "vpcompressb"; + case ND_INS_VPCOMPRESSD: return "vpcompressd"; + case ND_INS_VPCOMPRESSQ: return "vpcompressq"; + case ND_INS_VPCOMPRESSW: return "vpcompressw"; + case ND_INS_VPCOMQ: return "vpcomq"; + case ND_INS_VPCOMUB: return "vpcomub"; + case ND_INS_VPCOMUD: return "vpcomud"; + case ND_INS_VPCOMUQ: return "vpcomuq"; + case ND_INS_VPCOMUW: return "vpcomuw"; + case ND_INS_VPCOMW: return "vpcomw"; + case ND_INS_VPCONFLICTD: return "vpconflictd"; + case ND_INS_VPCONFLICTQ: return "vpconflictq"; + case ND_INS_VPDPBUSD: return "vpdpbusd"; + case ND_INS_VPDPBUSDS: return "vpdpbusds"; + case ND_INS_VPDPWSSD: return "vpdpwssd"; + case ND_INS_VPDPWSSDS: return "vpdpwssds"; + case ND_INS_VPERM2F128: return "vperm2f128"; + case ND_INS_VPERM2I128: return "vperm2i128"; + case ND_INS_VPERMB: return "vpermb"; + case ND_INS_VPERMD: return "vpermd"; + case ND_INS_VPERMI2B: return "vpermi2b"; + case ND_INS_VPERMI2D: return "vpermi2d"; + case ND_INS_VPERMI2PD: return "vpermi2pd"; + case ND_INS_VPERMI2PS: return "vpermi2ps"; + case ND_INS_VPERMI2Q: return "vpermi2q"; + case ND_INS_VPERMI2W: return "vpermi2w"; + case ND_INS_VPERMIL2PD: return "vpermil2pd"; + case ND_INS_VPERMIL2PS: return "vpermil2ps"; + case ND_INS_VPERMILPD: return "vpermilpd"; + case ND_INS_VPERMILPS: return "vpermilps"; + case ND_INS_VPERMPD: return "vpermpd"; + case ND_INS_VPERMPS: return "vpermps"; + case ND_INS_VPERMQ: return "vpermq"; + case ND_INS_VPERMT2B: return "vpermt2b"; + case ND_INS_VPERMT2D: return "vpermt2d"; + case ND_INS_VPERMT2PD: return "vpermt2pd"; + case ND_INS_VPERMT2PS: return "vpermt2ps"; + case ND_INS_VPERMT2Q: return "vpermt2q"; + case ND_INS_VPERMT2W: return "vpermt2w"; + case ND_INS_VPERMW: return "vpermw"; + case ND_INS_VPEXPANDB: return "vpexpandb"; + case ND_INS_VPEXPANDD: return "vpexpandd"; + case ND_INS_VPEXPANDQ: return "vpexpandq"; + case ND_INS_VPEXPANDW: return "vpexpandw"; + case ND_INS_VPEXTRB: return "vpextrb"; + case ND_INS_VPEXTRD: return "vpextrd"; + case ND_INS_VPEXTRQ: return "vpextrq"; + case ND_INS_VPEXTRW: return "vpextrw"; + case ND_INS_VPGATHERDD: return "vpgatherdd"; + case ND_INS_VPGATHERDQ: return "vpgatherdq"; + case ND_INS_VPGATHERQD: return "vpgatherqd"; + case ND_INS_VPGATHERQQ: return "vpgatherqq"; + case ND_INS_VPHADDBD: return "vphaddbd"; + case ND_INS_VPHADDBQ: return "vphaddbq"; + case ND_INS_VPHADDBW: return "vphaddbw"; + case ND_INS_VPHADDD: return "vphaddd"; + case ND_INS_VPHADDDQ: return "vphadddq"; + case ND_INS_VPHADDSW: return "vphaddsw"; + case ND_INS_VPHADDUBD: return "vphaddubd"; + case ND_INS_VPHADDUBQ: return "vphaddubq"; + case ND_INS_VPHADDUBW: return "vphaddubw"; + case ND_INS_VPHADDUDQ: return "vphaddudq"; + case ND_INS_VPHADDUWD: return "vphadduwd"; + case ND_INS_VPHADDUWQ: return "vphadduwq"; + case ND_INS_VPHADDW: return "vphaddw"; + case ND_INS_VPHADDWD: return "vphaddwd"; + case ND_INS_VPHADDWQ: return "vphaddwq"; + case ND_INS_VPHMINPOSUW: return "vphminposuw"; + case ND_INS_VPHSUBBW: return "vphsubbw"; + case ND_INS_VPHSUBD: return "vphsubd"; + case ND_INS_VPHSUBDQ: return "vphsubdq"; + case ND_INS_VPHSUBSW: return "vphsubsw"; + case ND_INS_VPHSUBW: return "vphsubw"; + case ND_INS_VPHSUBWD: return "vphsubwd"; + case ND_INS_VPINSRB: return "vpinsrb"; + case ND_INS_VPINSRD: return "vpinsrd"; + case ND_INS_VPINSRQ: return "vpinsrq"; + case ND_INS_VPINSRW: return "vpinsrw"; + case ND_INS_VPLZCNTD: return "vplzcntd"; + case ND_INS_VPLZCNTQ: return "vplzcntq"; + case ND_INS_VPMACSDD: return "vpmacsdd"; + case ND_INS_VPMACSDQH: return "vpmacsdqh"; + case ND_INS_VPMACSDQL: return "vpmacsdql"; + case ND_INS_VPMACSSDD: return "vpmacssdd"; + case ND_INS_VPMACSSDQH: return "vpmacssdqh"; + case ND_INS_VPMACSSDQL: return "vpmacssdql"; + case ND_INS_VPMACSSWD: return "vpmacsswd"; + case ND_INS_VPMACSSWW: return "vpmacssww"; + case ND_INS_VPMACSWD: return "vpmacswd"; + case ND_INS_VPMACSWW: return "vpmacsww"; + case ND_INS_VPMADCSSWD: return "vpmadcsswd"; + case ND_INS_VPMADCSWD: return "vpmadcswd"; + case ND_INS_VPMADD52HUQ: return "vpmadd52huq"; + case ND_INS_VPMADD52LUQ: return "vpmadd52luq"; + case ND_INS_VPMADDUBSW: return "vpmaddubsw"; + case ND_INS_VPMADDWD: return "vpmaddwd"; + case ND_INS_VPMASKMOVD: return "vpmaskmovd"; + case ND_INS_VPMASKMOVQ: return "vpmaskmovq"; + case ND_INS_VPMAXSB: return "vpmaxsb"; + case ND_INS_VPMAXSD: return "vpmaxsd"; + case ND_INS_VPMAXSQ: return "vpmaxsq"; + case ND_INS_VPMAXSW: return "vpmaxsw"; + case ND_INS_VPMAXUB: return "vpmaxub"; + case ND_INS_VPMAXUD: return "vpmaxud"; + case ND_INS_VPMAXUQ: return "vpmaxuq"; + case ND_INS_VPMAXUW: return "vpmaxuw"; + case ND_INS_VPMINSB: return "vpminsb"; + case ND_INS_VPMINSD: return "vpminsd"; + case ND_INS_VPMINSQ: return "vpminsq"; + case ND_INS_VPMINSW: return "vpminsw"; + case ND_INS_VPMINUB: return "vpminub"; + case ND_INS_VPMINUD: return "vpminud"; + case ND_INS_VPMINUQ: return "vpminuq"; + case ND_INS_VPMINUW: return "vpminuw"; + case ND_INS_VPMOVB2M: return "vpmovb2m"; + case ND_INS_VPMOVD2M: return "vpmovd2m"; + case ND_INS_VPMOVDB: return "vpmovdb"; + case ND_INS_VPMOVDW: return "vpmovdw"; + case ND_INS_VPMOVM2B: return "vpmovm2b"; + case ND_INS_VPMOVM2D: return "vpmovm2d"; + case ND_INS_VPMOVM2Q: return "vpmovm2q"; + case ND_INS_VPMOVM2W: return "vpmovm2w"; + case ND_INS_VPMOVMSKB: return "vpmovmskb"; + case ND_INS_VPMOVQ2M: return "vpmovq2m"; + case ND_INS_VPMOVQB: return "vpmovqb"; + case ND_INS_VPMOVQD: return "vpmovqd"; + case ND_INS_VPMOVQW: return "vpmovqw"; + case ND_INS_VPMOVSDB: return "vpmovsdb"; + case ND_INS_VPMOVSDW: return "vpmovsdw"; + case ND_INS_VPMOVSQB: return "vpmovsqb"; + case ND_INS_VPMOVSQD: return "vpmovsqd"; + case ND_INS_VPMOVSQW: return "vpmovsqw"; + case ND_INS_VPMOVSWB: return "vpmovswb"; + case ND_INS_VPMOVSXBD: return "vpmovsxbd"; + case ND_INS_VPMOVSXBQ: return "vpmovsxbq"; + case ND_INS_VPMOVSXBW: return "vpmovsxbw"; + case ND_INS_VPMOVSXDQ: return "vpmovsxdq"; + case ND_INS_VPMOVSXWD: return "vpmovsxwd"; + case ND_INS_VPMOVSXWQ: return "vpmovsxwq"; + case ND_INS_VPMOVUSDB: return "vpmovusdb"; + case ND_INS_VPMOVUSDW: return "vpmovusdw"; + case ND_INS_VPMOVUSQB: return "vpmovusqb"; + case ND_INS_VPMOVUSQD: return "vpmovusqd"; + case ND_INS_VPMOVUSQW: return "vpmovusqw"; + case ND_INS_VPMOVUSWB: return "vpmovuswb"; + case ND_INS_VPMOVW2M: return "vpmovw2m"; + case ND_INS_VPMOVWB: return "vpmovwb"; + case ND_INS_VPMOVZXBD: return "vpmovzxbd"; + case ND_INS_VPMOVZXBQ: return "vpmovzxbq"; + case ND_INS_VPMOVZXBW: return "vpmovzxbw"; + case ND_INS_VPMOVZXDQ: return "vpmovzxdq"; + case ND_INS_VPMOVZXWD: return "vpmovzxwd"; + case ND_INS_VPMOVZXWQ: return "vpmovzxwq"; + case ND_INS_VPMULDQ: return "vpmuldq"; + case ND_INS_VPMULHRSW: return "vpmulhrsw"; + case ND_INS_VPMULHUW: return "vpmulhuw"; + case ND_INS_VPMULHW: return "vpmulhw"; + case ND_INS_VPMULLD: return "vpmulld"; + case ND_INS_VPMULLQ: return "vpmullq"; + case ND_INS_VPMULLW: return "vpmullw"; + case ND_INS_VPMULTISHIFTQB: return "vpmultishiftqb"; + case ND_INS_VPMULUDQ: return "vpmuludq"; + case ND_INS_VPOPCNTB: return "vpopcntb"; + case ND_INS_VPOPCNTD: return "vpopcntd"; + case ND_INS_VPOPCNTQ: return "vpopcntq"; + case ND_INS_VPOPCNTW: return "vpopcntw"; + case ND_INS_VPOR: return "vpor"; + case ND_INS_VPORD: return "vpord"; + case ND_INS_VPORQ: return "vporq"; + case ND_INS_VPPERM: return "vpperm"; + case ND_INS_VPROLD: return "vprold"; + case ND_INS_VPROLQ: return "vprolq"; + case ND_INS_VPROLVD: return "vprolvd"; + case ND_INS_VPROLVQ: return "vprolvq"; + case ND_INS_VPRORD: return "vprord"; + case ND_INS_VPRORQ: return "vprorq"; + case ND_INS_VPRORVD: return "vprorvd"; + case ND_INS_VPRORVQ: return "vprorvq"; + case ND_INS_VPROTB: return "vprotb"; + case ND_INS_VPROTD: return "vprotd"; + case ND_INS_VPROTQ: return "vprotq"; + case ND_INS_VPROTW: return "vprotw"; + case ND_INS_VPSADBW: return "vpsadbw"; + case ND_INS_VPSCATTERDD: return "vpscatterdd"; + case ND_INS_VPSCATTERDQ: return "vpscatterdq"; + case ND_INS_VPSCATTERQD: return "vpscatterqd"; + case ND_INS_VPSCATTERQQ: return "vpscatterqq"; + case ND_INS_VPSHAB: return "vpshab"; + case ND_INS_VPSHAD: return "vpshad"; + case ND_INS_VPSHAQ: return "vpshaq"; + case ND_INS_VPSHAW: return "vpshaw"; + case ND_INS_VPSHLB: return "vpshlb"; + case ND_INS_VPSHLD: return "vpshld"; + case ND_INS_VPSHLDD: return "vpshldd"; + case ND_INS_VPSHLDQ: return "vpshldq"; + case ND_INS_VPSHLDVD: return "vpshldvd"; + case ND_INS_VPSHLDVQ: return "vpshldvq"; + case ND_INS_VPSHLDVW: return "vpshldvw"; + case ND_INS_VPSHLDW: return "vpshldw"; + case ND_INS_VPSHLQ: return "vpshlq"; + case ND_INS_VPSHLW: return "vpshlw"; + case ND_INS_VPSHRDD: return "vpshrdd"; + case ND_INS_VPSHRDQ: return "vpshrdq"; + case ND_INS_VPSHRDVD: return "vpshrdvd"; + case ND_INS_VPSHRDVQ: return "vpshrdvq"; + case ND_INS_VPSHRDVW: return "vpshrdvw"; + case ND_INS_VPSHRDW: return "vpshrdw"; + case ND_INS_VPSHUFB: return "vpshufb"; + case ND_INS_VPSHUFBITQMB: return "vpshufbitqmb"; + case ND_INS_VPSHUFD: return "vpshufd"; + case ND_INS_VPSHUFHW: return "vpshufhw"; + case ND_INS_VPSHUFLW: return "vpshuflw"; + case ND_INS_VPSIGNB: return "vpsignb"; + case ND_INS_VPSIGND: return "vpsignd"; + case ND_INS_VPSIGNW: return "vpsignw"; + case ND_INS_VPSLLD: return "vpslld"; + case ND_INS_VPSLLDQ: return "vpslldq"; + case ND_INS_VPSLLQ: return "vpsllq"; + case ND_INS_VPSLLVD: return "vpsllvd"; + case ND_INS_VPSLLVQ: return "vpsllvq"; + case ND_INS_VPSLLVW: return "vpsllvw"; + case ND_INS_VPSLLW: return "vpsllw"; + case ND_INS_VPSRAD: return "vpsrad"; + case ND_INS_VPSRAQ: return "vpsraq"; + case ND_INS_VPSRAVD: return "vpsravd"; + case ND_INS_VPSRAVQ: return "vpsravq"; + case ND_INS_VPSRAVW: return "vpsravw"; + case ND_INS_VPSRAW: return "vpsraw"; + case ND_INS_VPSRLD: return "vpsrld"; + case ND_INS_VPSRLDQ: return "vpsrldq"; + case ND_INS_VPSRLQ: return "vpsrlq"; + case ND_INS_VPSRLVD: return "vpsrlvd"; + case ND_INS_VPSRLVQ: return "vpsrlvq"; + case ND_INS_VPSRLVW: return "vpsrlvw"; + case ND_INS_VPSRLW: return "vpsrlw"; + case ND_INS_VPSUBB: return "vpsubb"; + case ND_INS_VPSUBD: return "vpsubd"; + case ND_INS_VPSUBQ: return "vpsubq"; + case ND_INS_VPSUBSB: return "vpsubsb"; + case ND_INS_VPSUBSW: return "vpsubsw"; + case ND_INS_VPSUBUSB: return "vpsubusb"; + case ND_INS_VPSUBUSW: return "vpsubusw"; + case ND_INS_VPSUBW: return "vpsubw"; + case ND_INS_VPTERNLOGD: return "vpternlogd"; + case ND_INS_VPTERNLOGQ: return "vpternlogq"; + case ND_INS_VPTEST: return "vptest"; + case ND_INS_VPTESTMB: return "vptestmb"; + case ND_INS_VPTESTMD: return "vptestmd"; + case ND_INS_VPTESTMQ: return "vptestmq"; + case ND_INS_VPTESTMW: return "vptestmw"; + case ND_INS_VPTESTNMB: return "vptestnmb"; + case ND_INS_VPTESTNMD: return "vptestnmd"; + case ND_INS_VPTESTNMQ: return "vptestnmq"; + case ND_INS_VPTESTNMW: return "vptestnmw"; + case ND_INS_VPUNPCKHBW: return "vpunpckhbw"; + case ND_INS_VPUNPCKHDQ: return "vpunpckhdq"; + case ND_INS_VPUNPCKHQDQ: return "vpunpckhqdq"; + case ND_INS_VPUNPCKHWD: return "vpunpckhwd"; + case ND_INS_VPUNPCKLBW: return "vpunpcklbw"; + case ND_INS_VPUNPCKLDQ: return "vpunpckldq"; + case ND_INS_VPUNPCKLQDQ: return "vpunpcklqdq"; + case ND_INS_VPUNPCKLWD: return "vpunpcklwd"; + case ND_INS_VPXOR: return "vpxor"; + case ND_INS_VPXORD: return "vpxord"; + case ND_INS_VPXORQ: return "vpxorq"; + case ND_INS_VRANGEPD: return "vrangepd"; + case ND_INS_VRANGEPS: return "vrangeps"; + case ND_INS_VRANGESD: return "vrangesd"; + case ND_INS_VRANGESS: return "vrangess"; + case ND_INS_VRCP14PD: return "vrcp14pd"; + case ND_INS_VRCP14PS: return "vrcp14ps"; + case ND_INS_VRCP14SD: return "vrcp14sd"; + case ND_INS_VRCP14SS: return "vrcp14ss"; + case ND_INS_VRCP28PD: return "vrcp28pd"; + case ND_INS_VRCP28PS: return "vrcp28ps"; + case ND_INS_VRCP28SD: return "vrcp28sd"; + case ND_INS_VRCP28SS: return "vrcp28ss"; + case ND_INS_VRCPPS: return "vrcpps"; + case ND_INS_VRCPSS: return "vrcpss"; + case ND_INS_VREDUCEPD: return "vreducepd"; + case ND_INS_VREDUCEPS: return "vreduceps"; + case ND_INS_VREDUCESD: return "vreducesd"; + case ND_INS_VREDUCESS: return "vreducess"; + case ND_INS_VRNDSCALEPD: return "vrndscalepd"; + case ND_INS_VRNDSCALEPS: return "vrndscaleps"; + case ND_INS_VRNDSCALESD: return "vrndscalesd"; + case ND_INS_VRNDSCALESS: return "vrndscaless"; + case ND_INS_VROUNDPD: return "vroundpd"; + case ND_INS_VROUNDPS: return "vroundps"; + case ND_INS_VROUNDSD: return "vroundsd"; + case ND_INS_VROUNDSS: return "vroundss"; + case ND_INS_VRSQRT14PD: return "vrsqrt14pd"; + case ND_INS_VRSQRT14PS: return "vrsqrt14ps"; + case ND_INS_VRSQRT14SD: return "vrsqrt14sd"; + case ND_INS_VRSQRT14SS: return "vrsqrt14ss"; + case ND_INS_VRSQRT28PD: return "vrsqrt28pd"; + case ND_INS_VRSQRT28PS: return "vrsqrt28ps"; + case ND_INS_VRSQRT28SD: return "vrsqrt28sd"; + case ND_INS_VRSQRT28SS: return "vrsqrt28ss"; + case ND_INS_VRSQRTPS: return "vrsqrtps"; + case ND_INS_VRSQRTSS: return "vrsqrtss"; + case ND_INS_VSCALEFPD: return "vscalefpd"; + case ND_INS_VSCALEFPS: return "vscalefps"; + case ND_INS_VSCALEFSD: return "vscalefsd"; + case ND_INS_VSCALEFSS: return "vscalefss"; + case ND_INS_VSCATTERDPD: return "vscatterdpd"; + case ND_INS_VSCATTERDPS: return "vscatterdps"; + case ND_INS_VSCATTERPF0DPD: return "vscatterpf0dpd"; + case ND_INS_VSCATTERPF0DPS: return "vscatterpf0dps"; + case ND_INS_VSCATTERPF0QPD: return "vscatterpf0qpd"; + case ND_INS_VSCATTERPF0QPS: return "vscatterpf0qps"; + case ND_INS_VSCATTERPF1DPD: return "vscatterpf1dpd"; + case ND_INS_VSCATTERPF1DPS: return "vscatterpf1dps"; + case ND_INS_VSCATTERPF1QPD: return "vscatterpf1qpd"; + case ND_INS_VSCATTERPF1QPS: return "vscatterpf1qps"; + case ND_INS_VSCATTERQPD: return "vscatterqpd"; + case ND_INS_VSCATTERQPS: return "vscatterqps"; + case ND_INS_VSHUFF32X4: return "vshuff32x4"; + case ND_INS_VSHUFF64X2: return "vshuff64x2"; + case ND_INS_VSHUFI32X4: return "vshufi32x4"; + case ND_INS_VSHUFI64X2: return "vshufi64x2"; + case ND_INS_VSHUFPD: return "vshufpd"; + case ND_INS_VSHUFPS: return "vshufps"; + case ND_INS_VSQRTPD: return "vsqrtpd"; + case ND_INS_VSQRTPS: return "vsqrtps"; + case ND_INS_VSQRTSD: return "vsqrtsd"; + case ND_INS_VSQRTSS: return "vsqrtss"; + case ND_INS_VSTMXCSR: return "vstmxcsr"; + case ND_INS_VSUBPD: return "vsubpd"; + case ND_INS_VSUBPS: return "vsubps"; + case ND_INS_VSUBSD: return "vsubsd"; + case ND_INS_VSUBSS: return "vsubss"; + case ND_INS_VTESTPD: return "vtestpd"; + case ND_INS_VTESTPS: return "vtestps"; + case ND_INS_VUCOMISD: return "vucomisd"; + case ND_INS_VUCOMISS: return "vucomiss"; + case ND_INS_VUNPCKHPD: return "vunpckhpd"; + case ND_INS_VUNPCKHPS: return "vunpckhps"; + case ND_INS_VUNPCKLPD: return "vunpcklpd"; + case ND_INS_VUNPCKLPS: return "vunpcklps"; + case ND_INS_VXORPD: return "vxorpd"; + case ND_INS_VXORPS: return "vxorps"; + case ND_INS_VZEROALL: return "vzeroall"; + case ND_INS_VZEROUPPER: return "vzeroupper"; + case ND_INS_WAIT: return "wait"; + case ND_INS_WBINVD: return "wbinvd"; + case ND_INS_WBNOINVD: return "wbnoinvd"; + case ND_INS_WRFSBASE: return "wrfsbase"; + case ND_INS_WRGSBASE: return "wrgsbase"; + case ND_INS_WRMSR: return "wrmsr"; + case ND_INS_WRPKRU: return "wrpkru"; + case ND_INS_WRSHR: return "wrshr"; + case ND_INS_WRSS: return "wrss"; + case ND_INS_WRUSS: return "wruss"; + case ND_INS_XABORT: return "xabort"; + case ND_INS_XADD: return "xadd"; + case ND_INS_XBEGIN: return "xbegin"; + case ND_INS_XCHG: return "xchg"; + case ND_INS_XCRYPTCBC: return "xcryptcbc"; + case ND_INS_XCRYPTCFB: return "xcryptcfb"; + case ND_INS_XCRYPTCTR: return "xcryptctr"; + case ND_INS_XCRYPTECB: return "xcryptecb"; + case ND_INS_XCRYPTOFB: return "xcryptofb"; + case ND_INS_XEND: return "xend"; + case ND_INS_XGETBV: return "xgetbv"; + case ND_INS_XLATB: return "xlatb"; + case ND_INS_XOR: return "xor"; + case ND_INS_XORPD: return "xorpd"; + case ND_INS_XORPS: return "xorps"; + case ND_INS_XRESLDTRK: return "xresldtrik"; + case ND_INS_XRSTOR: return "xrstor"; + case ND_INS_XRSTORS: return "xrstors"; + case ND_INS_XSAVE: return "xsave"; + case ND_INS_XSAVEC: return "xsavec"; + case ND_INS_XSAVEOPT: return "xsaveopt"; + case ND_INS_XSAVES: return "xsaves"; + case ND_INS_XSETBV: return "xsetbv"; + case ND_INS_XSHA1: return "xsha1"; + case ND_INS_XSHA256: return "xsha256"; + case ND_INS_XSUSLDTRK: return "xsusldtrk"; + case ND_INS_XSTORE: return "xstore"; + case ND_INS_XTEST: return "xtest"; + case ND_INS_HRESET: return "hreset"; + case ND_INS_CLUI: return "clui"; + case ND_INS_STUI: return "stui"; + case ND_INS_TESTUI: return "testui"; + case ND_INS_UIRET: return "uiret"; + case ND_INS_SENDUIPI: return "senduipi"; + default: return "unhandled!"; + } + + return ""; +} + + +std::string ins_cat_to_str(ND_INS_CATEGORY category) +{ + switch (category) { + case ND_CAT_INVALID: return "invalid"; + case ND_CAT_3DNOW: return "3dnow"; + case ND_CAT_AES: return "aes"; + case ND_CAT_AESKL: return "aeskl"; + case ND_CAT_AMX: return "amx"; + case ND_CAT_ARITH: return "arith"; + case ND_CAT_AVX: return "avx"; + case ND_CAT_AVX2: return "avx2"; + case ND_CAT_AVX2GATHER: return "avx2gather"; + case ND_CAT_AVX512: return "avx512"; + case ND_CAT_AVX512BF16: return "avx512bf16"; + case ND_CAT_AVX512VBMI: return "avx512vbmi"; + case ND_CAT_AVX512VP2INTERSECT: return "avx512vp2intersect"; + case ND_CAT_AVX512FP16: return "avx512fp16"; + case ND_CAT_AVXVNNI: return "avxvnni"; + case ND_CAT_BITBYTE: return "bitbyte"; + case ND_CAT_BLEND: return "blend"; + case ND_CAT_BMI1: return "bmi1"; + case ND_CAT_BMI2: return "bmi2"; + case ND_CAT_BROADCAST: return "broadcast"; + case ND_CAT_CALL: return "call"; + case ND_CAT_CET: return "cet"; + case ND_CAT_CLDEMOTE: return "cldemote"; + case ND_CAT_CMOV: return "cmov"; + case ND_CAT_COMPRESS: return "compress"; + case ND_CAT_COND_BR: return "cond_br"; + case ND_CAT_CONFLICT: return "conflict"; + case ND_CAT_CONVERT: return "convert"; + case ND_CAT_DATAXFER: return "dataxfer"; + case ND_CAT_DECIMAL: return "decimal"; + case ND_CAT_ENQCMD: return "enqcmd"; + case ND_CAT_EXPAND: return "expand"; + case ND_CAT_FLAGOP: return "flagop"; + case ND_CAT_FMA4: return "fma4"; + case ND_CAT_GATHER: return "gather"; + case ND_CAT_GFNI: return "gfni"; + case ND_CAT_HRESET: return "hreset"; + case ND_CAT_I386: return "i386"; + case ND_CAT_IFMA: return "ifma"; + case ND_CAT_INTERRUPT: return "interrupt"; + case ND_CAT_IO: return "io"; + case ND_CAT_IOSTRINGOP: return "iostringop"; + case ND_CAT_KL: return "kl"; + case ND_CAT_KMASK: return "kmask"; + case ND_CAT_KNL: return "knl"; + case ND_CAT_LKGS: return "lkgs"; + case ND_CAT_LOGIC: return "logic"; + case ND_CAT_LOGICAL: return "logical"; + case ND_CAT_LOGICAL_FP: return "logical_fp"; + case ND_CAT_LWP: return "lwp"; + case ND_CAT_LZCNT: return "lzcnt"; + case ND_CAT_MISC: return "misc"; + case ND_CAT_MMX: return "mmx"; + case ND_CAT_MOVDIR64B: return "movdir64b"; + case ND_CAT_MOVDIRI: return "movdiri"; + case ND_CAT_MPX: return "mpx"; + case ND_CAT_NOP: return "nop"; + case ND_CAT_PADLOCK: return "padlock"; + case ND_CAT_PCLMULQDQ: return "pclmulqdq"; + case ND_CAT_PCONFIG: return "pconfig"; + case ND_CAT_POP: return "pop"; + case ND_CAT_PREFETCH: return "prefetch"; + case ND_CAT_PTWRITE: return "ptwrite"; + case ND_CAT_PUSH: return "push"; + case ND_CAT_RDPID: return "rdpid"; + case ND_CAT_RDRAND: return "rdrand"; + case ND_CAT_RDSEED: return "rdseed"; + case ND_CAT_RDWRFSGS: return "rdwrfsgs"; + case ND_CAT_RET: return "ret"; + case ND_CAT_ROTATE: return "rotate"; + case ND_CAT_SCATTER: return "scatter"; + case ND_CAT_SEGOP: return "segop"; + case ND_CAT_SEMAPHORE: return "semaphore"; + case ND_CAT_SGX: return "sgx"; + case ND_CAT_SHA: return "sha"; + case ND_CAT_SHIFT: return "shift"; + case ND_CAT_SMAP: return "smap"; + case ND_CAT_SSE: return "sse"; + case ND_CAT_SSE2: return "sse2"; + case ND_CAT_STRINGOP: return "stringop"; + case ND_CAT_STTNI: return "sttni"; + case ND_CAT_SYSCALL: return "syscall"; + case ND_CAT_SYSRET: return "sysret"; + case ND_CAT_SYSTEM: return "system"; + case ND_CAT_TDX: return "tdx"; + case ND_CAT_UD: return "ud"; + case ND_CAT_UINTR: return "uintr"; + case ND_CAT_UNCOND_BR: return "uncond_br"; + case ND_CAT_UNKNOWN: return "unknown"; + case ND_CAT_VAES: return "vaes"; + case ND_CAT_VFMA: return "vfma"; + case ND_CAT_VFMAPS: return "vfmaps"; + case ND_CAT_VNNI: return "vnni"; + case ND_CAT_VNNIW: return "vnniw"; + case ND_CAT_VPCLMULQDQ: return "vpclmulqdq"; + case ND_CAT_VPOPCNT: return "vpopcnt"; + case ND_CAT_VTX: return "vtx"; + case ND_CAT_WAITPKG: return "waitpkg"; + case ND_CAT_WBNOINVD: return "wbnoinvd"; + case ND_CAT_WIDE_KL: return "wide_kl"; + case ND_CAT_WIDENOP: return "widenop"; + case ND_CAT_X87_ALU: return "x87_alu"; + case ND_CAT_XOP: return "xop"; + case ND_CAT_XSAVE: return "xsave"; + } + + return ""; +} + + +std::string ins_set_to_str(ND_INS_SET ins_set) +{ + switch (ins_set) { + case ND_SET_INVALID: return "invalid"; + case ND_SET_3DNOW: return "3dnow"; + case ND_SET_ADX: return "adx"; + case ND_SET_AES: return "aes"; + case ND_SET_AMD: return "amd"; + case ND_SET_AMXBF16: return "amxbf16"; + case ND_SET_AMXINT8: return "amxint8"; + case ND_SET_AMXTILE: return "amxtile"; + case ND_SET_AVX: return "avx"; + case ND_SET_AVX2: return "avx2"; + case ND_SET_AVX2GATHER: return "avx2gather"; + case ND_SET_AVX5124FMAPS: return "avx5124fmaps"; + case ND_SET_AVX5124VNNIW: return "avx5124vnniw"; + case ND_SET_AVX512BF16: return "avx512bf16"; + case ND_SET_AVX512BITALG: return "avx512bitalg"; + case ND_SET_AVX512BW: return "avx512bw"; + case ND_SET_AVX512CD: return "avx512cd"; + case ND_SET_AVX512DQ: return "avx512dq"; + case ND_SET_AVX512ER: return "avx512er"; + case ND_SET_AVX512F: return "avx512f"; + case ND_SET_AVX512IFMA: return "avx512ifma"; + case ND_SET_AVX512PF: return "avx512pf"; + case ND_SET_AVX512VBMI: return "avx512vbmi"; + case ND_SET_AVX512VBMI2: return "avx512vbmi2"; + case ND_SET_AVX512VNNI: return "avx512vnni"; + case ND_SET_AVX512VP2INTERSECT: return "avx512vp2intersect"; + case ND_SET_AVX512VPOPCNTDQ: return "avx512vpopcntdq"; + case ND_SET_AVX512FP16: return "avx512fp16"; + case ND_SET_AVXVNNI: return "avxvnni"; + case ND_SET_BMI1: return "bmi1"; + case ND_SET_BMI2: return "bmi2"; + case ND_SET_CET_SS: return "cet_ss"; + case ND_SET_CET_IBT: return "cet_ibt"; + case ND_SET_CLDEMOTE: return "cldemote"; + case ND_SET_CLFSH: return "clfsh"; + case ND_SET_CLFSHOPT: return "clfshopt"; + case ND_SET_CLWB: return "clwb"; + case ND_SET_CLZERO: return "clzero"; + case ND_SET_CMPXCHG16B: return "cmpxchg16b"; + case ND_SET_CYRIX: return "cyrix"; + case ND_SET_CYRIX_SMM: return "cyrix_smm"; + case ND_SET_ENQCMD: return "enqcmd"; + case ND_SET_F16C: return "f16c"; + case ND_SET_FMA: return "fma"; + case ND_SET_FMA4: return "fma4"; + case ND_SET_FRED: return "fred"; + case ND_SET_FXSAVE: return "fxsave"; + case ND_SET_GFNI: return "gfni"; + case ND_SET_HRESET: return "hreset"; + case ND_SET_I186: return "i186"; + case ND_SET_INVLPGB: return "invlpgb"; + case ND_SET_I286PROT: return "i286prot"; + case ND_SET_I286REAL: return "i286real"; + case ND_SET_I386: return "i386"; + case ND_SET_I486: return "i486"; + case ND_SET_I486REAL: return "i486real"; + case ND_SET_I64: return "i64"; + case ND_SET_I86: return "i86"; + case ND_SET_INVPCID: return "invpcid"; + case ND_SET_KL: return "kl"; + case ND_SET_LKGS: return "lkgs"; + case ND_SET_LONGMODE: return "longmode"; + case ND_SET_LWP: return "lwp"; + case ND_SET_LZCNT: return "lzcnt"; + case ND_SET_MCOMMIT: return "mcommit"; + case ND_SET_MMX: return "mmx"; + case ND_SET_MOVBE: return "movbe"; + case ND_SET_MOVDIR64B: return "movdir64b"; + case ND_SET_MOVDIRI: return "movdiri"; + case ND_SET_MPX: return "mpx"; + case ND_SET_MWAITT: return "mwaitt"; + case ND_SET_PAUSE: return "pause"; + case ND_SET_PCLMULQDQ: return "pclmulqdq"; + case ND_SET_PCONFIG: return "pconfig"; + case ND_SET_PENTIUMREAL: return "pentiumreal"; + case ND_SET_PKU: return "pku"; + case ND_SET_POPCNT: return "popcnt"; + case ND_SET_PPRO: return "ppro"; + case ND_SET_PREFETCH_NOP: return "prefetch_nop"; + case ND_SET_PTWRITE: return "ptwrite"; + case ND_SET_RDPID: return "rdpid"; + case ND_SET_RDPMC: return "rdpmc"; + case ND_SET_RDPRU: return "rdpru"; + case ND_SET_RDRAND: return "rdrand"; + case ND_SET_RDSEED: return "rdseed"; + case ND_SET_RDTSCP: return "rdtscp"; + case ND_SET_RDWRFSGS: return "rdwrfsgs"; + case ND_SET_SERIALIZE: return "serialize"; + case ND_SET_SGX: return "sgx"; + case ND_SET_SHA: return "sha"; + case ND_SET_SMAP: return "smap"; + case ND_SET_SMX: return "smx"; + case ND_SET_SNP: return "snp"; + case ND_SET_SSE: return "sse"; + case ND_SET_SSE2: return "sse2"; + case ND_SET_SSE3: return "sse3"; + case ND_SET_SSE4: return "sse4"; + case ND_SET_SSE42: return "sse42"; + case ND_SET_SSE4A: return "sse4a"; + case ND_SET_SSSE3: return "ssse3"; + case ND_SET_SVM: return "svm"; + case ND_SET_TBM: return "tbm"; + case ND_SET_TDX: return "tdx"; + case ND_SET_TSX: return "tsx"; + case ND_SET_TSXLDTRK: return "tsxldtrk"; + case ND_SET_UD: return "ud"; + case ND_SET_UINTR: return "uintr"; + case ND_SET_UNKNOWN: return "unknown"; + case ND_SET_VAES: return "vaes"; + case ND_SET_VPCLMULQDQ: return "vpclmulqdq"; + case ND_SET_VTX: return "vtx"; + case ND_SET_WAITPKG: return "waitpkg"; + case ND_SET_WBNOINVD: return "wbnoinvd"; + case ND_SET_X87: return "x87"; + case ND_SET_XOP: return "xop"; + case ND_SET_XSAVE: return "xsave"; + case ND_SET_XSAVEC: return "xsavec"; + case ND_SET_XSAVES: return "xsaves"; + } + + return ""; +} + + +std::string reg_to_str(const int reg, const ND_REG_TYPE type) +{ + switch (type) { + case ND_REG_NOT_PRESENT: + return "not_preset"; + + case ND_REG_GPR: + switch (reg) { + case NDR_RAX: return "rax"; + case NDR_RCX: return "rcx"; + case NDR_RDX: return "rdx"; + case NDR_RBX: return "rbx"; + case NDR_RSP: return "rsp"; + case NDR_RBP: return "rbp"; + case NDR_RSI: return "rsi"; + case NDR_RDI: return "rdi"; + case NDR_R8: return "r8"; + case NDR_R9: return "r9"; + case NDR_R10: return "r10"; + case NDR_R11: return "r11"; + case NDR_R12: return "r12"; + case NDR_R13: return "r13"; + case NDR_R14: return "r14"; + case NDR_R15: return "r15"; + } + + return ""; + + case ND_REG_SEG: + switch (reg) { + case NDR_ES: return "es"; + case NDR_CS: return "cs"; + case NDR_SS: return "ss"; + case NDR_DS: return "ds"; + case NDR_FS: return "fs"; + case NDR_GS: return "gs"; + case NDR_INV6: return "inv6"; + case NDR_INV7: return "inv7"; + } + + return ""; + + case ND_REG_FPU: + return "fpu"; + case ND_REG_MMX: + return "mmx"; + case ND_REG_SSE: + return "sse"; + case ND_REG_CR: + return "cr"; + case ND_REG_DR: + return "dr"; + case ND_REG_TR: + return "tr"; + case ND_REG_BND: + return "bnd"; + case ND_REG_MSK: + return "msk"; + case ND_REG_TILE: + return "tile"; + case ND_REG_MSR: + return "msr"; + case ND_REG_XCR: + return "xcr"; + case ND_REG_SYS: + return "sys"; + case ND_REG_X87: + return "x87"; + case ND_REG_MXCSR: + return "mxcsr"; + case ND_REG_PKRU: + return "pkru"; + case ND_REG_SSP: + return "ssp"; + case ND_REG_FLG: + return "flg"; + case ND_REG_RIP: + return "rip"; + case ND_REG_UIF: + return "uif"; + } + + return ""; +} + + +std::string reg_type_to_str(const ND_REG_TYPE type) +{ + switch (type) { + case ND_REG_NOT_PRESENT: + return "present"; + case ND_REG_GPR: + return "gpr"; + case ND_REG_SEG: + return "seg"; + case ND_REG_FPU: + return "fpu"; + case ND_REG_MMX: + return "mmx"; + case ND_REG_SSE: + return "sse"; + case ND_REG_CR: + return "cr"; + case ND_REG_DR: + return "dr"; + case ND_REG_TR: + return "tr"; + case ND_REG_BND: + return "bnd"; + case ND_REG_MSK: + return "msk"; + case ND_REG_TILE: + return "tile"; + case ND_REG_MSR: + return "msr"; + case ND_REG_XCR: + return "xcr"; + case ND_REG_SYS: + return "sys"; + case ND_REG_X87: + return "x87"; + case ND_REG_MXCSR: + return "mxcsr"; + case ND_REG_PKRU: + return "pkru"; + case ND_REG_SSP: + return "ssp"; + case ND_REG_FLG: + return "flg"; + case ND_REG_RIP: + return "rip"; + case ND_REG_UIF: + return "uif"; + } + + return ""; +} diff --git a/inc/bddisasm.h b/inc/bddisasm.h index 884274f..492c975 100644 --- a/inc/bddisasm.h +++ b/inc/bddisasm.h @@ -39,6 +39,7 @@ #define ND_FEAT_MPX 0x01 // MPX support enabled. #define ND_FEAT_CET 0x02 // CET support enabled. #define ND_FEAT_CLDEMOTE 0x04 // CLDEMOTE support enabled. +#define ND_FEAT_PITI 0x08 // PREFETCHITI support enabled. #define ND_FEAT_ALL 0xFF // Decode as if all features are enabled. This is default. // @@ -632,6 +633,7 @@ typedef enum _ND_EX_TYPE_SSE_AVX ND_EXT_11, ND_EXT_12, ND_EXT_13, + ND_EXT_14, } ND_EX_TYPE_SSE_AVX; diff --git a/inc/constants.h b/inc/constants.h index ca1389c..7f853fe 100644 --- a/inc/constants.h +++ b/inc/constants.h @@ -2,9 +2,9 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ - + // -// This file was auto-generated by generate_tables.py from defs.dat. DO NOT MODIFY! +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! // #ifndef CONSTANTS_H @@ -16,7 +16,9 @@ typedef enum _ND_INS_CLASS ND_INS_INVALID = 0, ND_INS_AAA, ND_INS_AAD, + ND_INS_AADD, ND_INS_AAM, + ND_INS_AAND, ND_INS_AAS, ND_INS_ADC, ND_INS_ADCX, @@ -49,7 +51,9 @@ typedef enum _ND_INS_CLASS ND_INS_ANDNPS, ND_INS_ANDPD, ND_INS_ANDPS, + ND_INS_AOR, ND_INS_ARPL, + ND_INS_AXOR, ND_INS_BEXTR, ND_INS_BLCFILL, ND_INS_BLCI, @@ -106,14 +110,30 @@ typedef enum _ND_INS_CLASS ND_INS_CMC, ND_INS_CMOVcc, ND_INS_CMP, + ND_INS_CMPBEXADD, + ND_INS_CMPCXADD, + ND_INS_CMPLEXADD, + ND_INS_CMPLXADD, + ND_INS_CMPNBEXADD, + ND_INS_CMPNCXADD, + ND_INS_CMPNLEXADD, + ND_INS_CMPNLXADD, + ND_INS_CMPNOXADD, + ND_INS_CMPNPXADD, + ND_INS_CMPNSXADD, + ND_INS_CMPNZXADD, + ND_INS_CMPOXADD, ND_INS_CMPPD, ND_INS_CMPPS, + ND_INS_CMPPXADD, ND_INS_CMPS, ND_INS_CMPSD, ND_INS_CMPSS, + ND_INS_CMPSXADD, ND_INS_CMPXCHG, ND_INS_CMPXCHG16B, ND_INS_CMPXCHG8B, + ND_INS_CMPZXADD, ND_INS_COMISD, ND_INS_COMISS, ND_INS_CPUID, @@ -546,6 +566,8 @@ typedef enum _ND_INS_CLASS ND_INS_POR, ND_INS_PREFETCH, ND_INS_PREFETCHE, + ND_INS_PREFETCHIT0, + ND_INS_PREFETCHIT1, ND_INS_PREFETCHM, ND_INS_PREFETCHNTA, ND_INS_PREFETCHT0, @@ -605,6 +627,7 @@ typedef enum _ND_INS_CLASS ND_INS_RDFSBASE, ND_INS_RDGSBASE, ND_INS_RDMSR, + ND_INS_RDMSRLIST, ND_INS_RDPID, ND_INS_RDPKRU, ND_INS_RDPMC, @@ -706,6 +729,7 @@ typedef enum _ND_INS_CLASS ND_INS_TDPBSUD, ND_INS_TDPBUSD, ND_INS_TDPBUUD, + ND_INS_TDPFP16PS, ND_INS_TEST, ND_INS_TESTUI, ND_INS_TILELOADD, @@ -753,6 +777,8 @@ typedef enum _ND_INS_CLASS ND_INS_VANDNPS, ND_INS_VANDPD, ND_INS_VANDPS, + ND_INS_VBCSTNEBF162PS, + ND_INS_VBCSTNESH2PS, ND_INS_VBLENDMPD, ND_INS_VBLENDMPS, ND_INS_VBLENDPD, @@ -788,6 +814,10 @@ typedef enum _ND_INS_CLASS ND_INS_VCVTDQ2PH, ND_INS_VCVTDQ2PS, ND_INS_VCVTNE2PS2BF16, + ND_INS_VCVTNEEBF162PS, + ND_INS_VCVTNEEPH2PS, + ND_INS_VCVTNEOBF162PS, + ND_INS_VCVTNEOPH2PS, ND_INS_VCVTNEPS2BF16, ND_INS_VCVTPD2DQ, ND_INS_VCVTPD2PH, @@ -1214,8 +1244,14 @@ typedef enum _ND_INS_CLASS ND_INS_VPCOMW, ND_INS_VPCONFLICTD, ND_INS_VPCONFLICTQ, + ND_INS_VPDPBSSD, + ND_INS_VPDPBSSDS, + ND_INS_VPDPBSUD, + ND_INS_VPDPBSUDS, ND_INS_VPDPBUSD, ND_INS_VPDPBUSDS, + ND_INS_VPDPBUUD, + ND_INS_VPDPBUUDS, ND_INS_VPDPWSSD, ND_INS_VPDPWSSDS, ND_INS_VPERM2F128, @@ -1567,6 +1603,8 @@ typedef enum _ND_INS_CLASS ND_INS_WRFSBASE, ND_INS_WRGSBASE, ND_INS_WRMSR, + ND_INS_WRMSRLIST, + ND_INS_WRMSRNS, ND_INS_WRPKRU, ND_INS_WRSHR, ND_INS_WRSS, @@ -1611,6 +1649,7 @@ typedef enum _ND_INS_SET ND_SET_AES, ND_SET_AMD, ND_SET_AMXBF16, + ND_SET_AMXFP16, ND_SET_AMXINT8, ND_SET_AMXTILE, ND_SET_AVX, @@ -1633,7 +1672,10 @@ typedef enum _ND_INS_SET ND_SET_AVX512VNNI, ND_SET_AVX512VP2INTERSECT, ND_SET_AVX512VPOPCNTDQ, + ND_SET_AVXIFMA, + ND_SET_AVXNECONVERT, ND_SET_AVXVNNI, + ND_SET_AVXVNNIINT8, ND_SET_BMI1, ND_SET_BMI2, ND_SET_CET_IBT, @@ -1643,6 +1685,7 @@ typedef enum _ND_INS_SET ND_SET_CLFSHOPT, ND_SET_CLWB, ND_SET_CLZERO, + ND_SET_CMPCCXADD, ND_SET_CMPXCHG16B, ND_SET_CYRIX, ND_SET_CYRIX_SMM, @@ -1675,6 +1718,7 @@ typedef enum _ND_INS_SET ND_SET_MOVDIR64B, ND_SET_MOVDIRI, ND_SET_MPX, + ND_SET_MSRLIST, ND_SET_MWAITT, ND_SET_PAUSE, ND_SET_PCLMULQDQ, @@ -1683,8 +1727,10 @@ typedef enum _ND_INS_SET ND_SET_PKU, ND_SET_POPCNT, ND_SET_PPRO, + ND_SET_PREFETCHITI, ND_SET_PREFETCH_NOP, ND_SET_PTWRITE, + ND_SET_RAOINT, ND_SET_RDPID, ND_SET_RDPMC, ND_SET_RDPRU, @@ -1718,6 +1764,7 @@ typedef enum _ND_INS_SET ND_SET_VTX, ND_SET_WAITPKG, ND_SET_WBNOINVD, + ND_SET_WRMSRNS, ND_SET_X87, ND_SET_XOP, ND_SET_XSAVE, @@ -1743,7 +1790,10 @@ typedef enum _ND_INS_TYPE ND_CAT_AVX512FP16, ND_CAT_AVX512VBMI, ND_CAT_AVX512VP2INTERSECT, + ND_CAT_AVXIFMA, + ND_CAT_AVXNECONVERT, ND_CAT_AVXVNNI, + ND_CAT_AVXVNNIINT8, ND_CAT_BITBYTE, ND_CAT_BLEND, ND_CAT_BMI1, @@ -1753,6 +1803,7 @@ typedef enum _ND_INS_TYPE ND_CAT_CET, ND_CAT_CLDEMOTE, ND_CAT_CMOV, + ND_CAT_CMPCCXADD, ND_CAT_COMPRESS, ND_CAT_COND_BR, ND_CAT_CONFLICT, @@ -1793,6 +1844,7 @@ typedef enum _ND_INS_TYPE ND_CAT_PREFETCH, ND_CAT_PTWRITE, ND_CAT_PUSH, + ND_CAT_RAOINT, ND_CAT_RDPID, ND_CAT_RDRAND, ND_CAT_RDSEED, diff --git a/inc/cpuidflags.h b/inc/cpuidflags.h index 94c4005..b4028e9 100644 --- a/inc/cpuidflags.h +++ b/inc/cpuidflags.h @@ -2,6 +2,11 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ + +// +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! +// + #ifndef CPUID_FLAGS_H #define CPUID_FLAGS_H @@ -89,11 +94,20 @@ #define ND_CFF_AVX512FP16 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 23) #define ND_CFF_AMXTILE ND_CFF(0x00000007, 0x00000000, NDR_EDX, 24) #define ND_CFF_AMXINT8 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 25) +#define ND_CFF_RAOINT ND_CFF(0x00000007, 0x00000001, NDR_EAX, 3) #define ND_CFF_AVXVNNI ND_CFF(0x00000007, 0x00000001, NDR_EAX, 4) #define ND_CFF_AVX512BF16 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 5) +#define ND_CFF_CMPCCXADD ND_CFF(0x00000007, 0x00000001, NDR_EAX, 7) #define ND_CFF_FRED ND_CFF(0x00000007, 0x00000001, NDR_EAX, 17) #define ND_CFF_LKGS ND_CFF(0x00000007, 0x00000001, NDR_EAX, 18) +#define ND_CFF_WRMSRNS ND_CFF(0x00000007, 0x00000001, NDR_EAX, 19) +#define ND_CFF_AMXFP16 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 21) #define ND_CFF_HRESET ND_CFF(0x00000007, 0x00000001, NDR_EAX, 22) +#define ND_CFF_AVXIFMA ND_CFF(0x00000007, 0x00000001, NDR_EAX, 23) +#define ND_CFF_MSRLIST ND_CFF(0x00000007, 0x00000001, NDR_EAX, 27) +#define ND_CFF_AVXVNNIINT8 ND_CFF(0x00000007, 0x00000001, NDR_EDX, 4) +#define ND_CFF_AVXNECONVERT ND_CFF(0x00000007, 0x00000001, NDR_EDX, 5) +#define ND_CFF_PREFETCHITI ND_CFF(0x00000007, 0x00000001, NDR_EDX, 14) #define ND_CFF_XSAVEOPT ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 0) #define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1) #define ND_CFF_XSAVES ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 3) diff --git a/inc/version.h b/inc/version.h index a66790d..3506e46 100644 --- a/inc/version.h +++ b/inc/version.h @@ -6,8 +6,8 @@ #define DISASM_VER_H #define DISASM_VERSION_MAJOR 1 -#define DISASM_VERSION_MINOR 34 -#define DISASM_VERSION_REVISION 18 +#define DISASM_VERSION_MINOR 35 +#define DISASM_VERSION_REVISION 0 // bdshemu depends on bddisasm. It cannot be used without it. #define SHEMU_VERSION_MAJOR 1 diff --git a/isagenerator/disasmlib.py b/isagenerator/disasmlib.py index 8ffe4d5..6dc4439 100644 --- a/isagenerator/disasmlib.py +++ b/isagenerator/disasmlib.py @@ -209,6 +209,7 @@ valid_opsize = [ '384', # 384 bits representing a Key Locker handle. '512', # 512 bits representing a Key Locker handle. + '4096', # 4096 bits representing an MSR address/value table. ] # Implicit/fixed operands. Self explanatory. @@ -292,6 +293,8 @@ valid_impops = {# register size 'MXCSR' : ('MXCSR', 'd'), # MXCSR register. 'PKRU' : ('PKRU', 'd'), # PKRU register. 'SSP' : ('SSP', 'yf'), # Shadow stack pointer. 32 bit in protected/compat mode, 64 in long mode. + 'SMT' : ('SMT', '4096'),# Source MSR table, encododed in [RSI], up to 4096 bits long (64 entries x 64 bits per entry). + 'DMT' : ('DMT', '4096'),# Value MSR table, encododed in [RDI], up to 4096 bits long (64 entries x 64 bits per entry). # Implicit memory operands. 'pAXb' : ('pAX', 'b'), # Implicit byte [rAX], used by MONITOR and MONITORX. Can be overriden. @@ -670,8 +673,8 @@ class Instruction(): self.RedDs16 = self.RedDs32 = self.RedDs64 = self.RedDDs64 = self.RedFDs64 = False # Sixth redirection class: default address size self.RedAs16 = self.RedAs32 = self.RedAs64 = False - # Seventh redirecton class: rex, rex.w, rep, repz - self.RedRexB = self.RedRexW = self.RedRep = self.Red64 = self.RedF3 = False + # Seventh redirecton class: rex, rex.w, rep, repz, rip rel + self.RedRexB = self.RedRexW = self.RedRep = self.Red64 = self.RedF3 = self.RedRipRel = False # Misc - vendor self.Vendor = None # Misc - feature. @@ -705,6 +708,8 @@ class Instruction(): self.RedRexB = True elif 'rep' == t: self.RedRep = True + elif 'riprel' == t: + self.RedRipRel = True elif 'ds16' == t: self.RedDs16 = True elif 'ds32' == t: @@ -811,7 +816,7 @@ class Instruction(): self.Opcodes.append(int(t, 16)) elif t in ['intel', 'amd', 'via', 'cyrix']: self.Vendor = t - elif t in ['mpx', 'cet', 'cldm']: + elif t in ['mpx', 'cet', 'cldm', 'piti']: self.Feature = t elif 'vsib' == t: self.HasVsib = True @@ -1037,6 +1042,8 @@ class Instruction(): oprefixes.append('aF3') if self.RedRep: oprefixes.append('rep') + if self.RedRipRel: + oprefixes.append('riprel') # Vendor redirection, if any. return (opcodes, modrm, mprefixes, mode, dsize, asize, oprefixes, self.Vendor, self.Feature) @@ -1404,7 +1411,7 @@ if __name__ == "__main__": # Parse the instruction file and extract the instructions instructions = [] for fn in glob.glob('%s/table*.dat' % sys.argv[1]): - instructions += parse_ins_file(fn, flags, features) + instructions += parse_ins_file(fn, flags, features, modes) # Sort the instructions. instructions = sorted(instructions, key = lambda x: x.Mnemonic) diff --git a/isagenerator/generate_tables.py b/isagenerator/generate_tables.py index ce4ad5f..b6ec3b0 100644 --- a/isagenerator/generate_tables.py +++ b/isagenerator/generate_tables.py @@ -163,6 +163,8 @@ optype = { 'SHS' : 'ND_OPT_MEM_SHS', 'SHS0' : 'ND_OPT_MEM_SHS0', 'SHSP' : 'ND_OPT_MEM_SHSP', + 'SMT' : 'ND_OPT_MEM_SMSRT', + 'DMT' : 'ND_OPT_MEM_DMSRT', # Special immediates. 'm2zI' : 'ND_OPT_Im2z', @@ -259,6 +261,7 @@ opsize = { 't' : 'ND_OPS_t', '384' : 'ND_OPS_384', '512' : 'ND_OPS_512', + '4096' : 'ND_OPS_4096', } opdecorators = { @@ -322,6 +325,7 @@ extype = { '11' : 'ND_EXT_11', '12' : 'ND_EXT_12', '13' : 'ND_EXT_13', + '14' : 'ND_EXT_14', # EVEX 'E1' : 'ND_EXT_E1', @@ -399,13 +403,13 @@ indexes = { "F3" : 2, "F2" : 3, - # other prefixes + # other prefixes/redirection conditions "rexb" : 1, "rexw" : 2, "64" : 3, "aF3" : 4, "rep" : 5, - "sib" : 6, + "riprel": 6, # Mode "m16" : 1, @@ -435,6 +439,7 @@ indexes = { "mpx" : 1, "cet" : 2, "cldm" : 3, + "piti" : 4, } ilut = { @@ -449,9 +454,9 @@ ilut = { "mode" : ("ND_ILUT_MODE", 4, "ND_TABLE_MODE"), "dsize" : ("ND_ILUT_DSIZE", 6, "ND_TABLE_DSIZE"), "asize" : ("ND_ILUT_ASIZE", 4, "ND_TABLE_ASIZE"), - "auxiliary" : ("ND_ILUT_AUXILIARY", 6, "ND_TABLE_AUXILIARY"), + "auxiliary" : ("ND_ILUT_AUXILIARY", 8, "ND_TABLE_AUXILIARY"), "vendor" : ("ND_ILUT_VENDOR", 6, "ND_TABLE_VENDOR"), - "feature" : ("ND_ILUT_FEATURE", 4, "ND_TABLE_FEATURE"), + "feature" : ("ND_ILUT_FEATURE", 8, "ND_TABLE_FEATURE"), "mmmmm" : ("ND_ILUT_VEX_MMMMM", 32, "ND_TABLE_VEX_MMMMM"), "pp" : ("ND_ILUT_VEX_PP", 4, "ND_TABLE_VEX_PP"), "l" : ("ND_ILUT_VEX_L", 4, "ND_TABLE_VEX_L"), diff --git a/isagenerator/instructions/cpuid.dat b/isagenerator/instructions/cpuid.dat index b15ade6..7c6a456 100644 --- a/isagenerator/instructions/cpuid.dat +++ b/isagenerator/instructions/cpuid.dat @@ -33,6 +33,7 @@ AVX : 0x00000001, 0xFFFFFFFF, ECX, 28 F16C : 0x00000001, 0xFFFFFFFF, ECX, 29 RDRAND : 0x00000001, 0xFFFFFFFF, ECX, 30 + RDWRFSGS : 0x00000007, 0x00000000, EBX, 0 SGX : 0x00000007, 0x00000000, EBX, 2 BMI1 : 0x00000007, 0x00000000, EBX, 3 @@ -88,18 +89,32 @@ AVX512FP16 : 0x00000007, 0x00000000, EDX, 23 AMXTILE : 0x00000007, 0x00000000, EDX, 24 AMXINT8 : 0x00000007, 0x00000000, EDX, 25 + +RAOINT : 0x00000007, 0x00000001, EAX, 3 AVXVNNI : 0x00000007, 0x00000001, EAX, 4 AVX512BF16 : 0x00000007, 0x00000001, EAX, 5 +CMPCCXADD : 0x00000007, 0x00000001, EAX, 7 FRED : 0x00000007, 0x00000001, EAX, 17 LKGS : 0x00000007, 0x00000001, EAX, 18 +WRMSRNS : 0x00000007, 0x00000001, EAX, 19 +AMXFP16 : 0x00000007, 0x00000001, EAX, 21 HRESET : 0x00000007, 0x00000001, EAX, 22 +AVXIFMA : 0x00000007, 0x00000001, EAX, 23 +MSRLIST : 0x00000007, 0x00000001, EAX, 27 + +AVXVNNIINT8 : 0x00000007, 0x00000001, EDX, 4 +AVXNECONVERT : 0x00000007, 0x00000001, EDX, 5 +PREFETCHITI : 0x00000007, 0x00000001, EDX, 14 + XSAVEOPT : 0x0000000D, 0x00000001, EAX, 0 XSAVEC : 0x0000000D, 0x00000001, EAX, 1 XSAVES : 0x0000000D, 0x00000001, EAX, 3 + PTWRITE : 0x00000014, 0x00000000, EBX, 4 + SVM : 0x80000001, 0xFFFFFFFF, ECX, 2 LZCNT : 0x80000001, 0xFFFFFFFF, ECX, 5 SSE4A : 0x80000001, 0xFFFFFFFF, ECX, 6 @@ -113,8 +128,10 @@ INVLPGB : 0x80000001, 0xFFFFFFFF, EDX, 24 RDTSCP : 0x80000001, 0xFFFFFFFF, ECX, 27 3DNOW : 0x80000001, 0xFFFFFFFF, EDX, 31 + WBNOINVD : 0x80000008, 0xFFFFFFFF, EBX, 9 RDPRU : 0x80000008, 0xFFFFFFFF, EBX, 4 MCOMMIT : 0x80000008, 0xFFFFFFFF, EBX, 8 + SNP : 0x8000001F, 0xFFFFFFFF, EAX, 4 diff --git a/isagenerator/instructions/table_0F.dat b/isagenerator/instructions/table_0F.dat index ae0b214..7b798ea 100644 --- a/isagenerator/instructions/table_0F.dat +++ b/isagenerator/instructions/table_0F.dat @@ -27,6 +27,9 @@ VMLAUNCH nil Fv [ NP 0x0F 0x01 /0 VMRESUME nil Fv [ NP 0x0F 0x01 /0xC3] s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT VMXOFF nil Fv [ NP 0x0F 0x01 /0xC4] s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT PCONFIG nil EAX,RBX,RCX,RDX [ NP 0x0F 0x01 /0xC5] s:PCONFIG, t:PCONFIG, w:R|RW|RW|RW, m:NOV86 +WRMSRNS nil EAX,EDX,ECX,MSR [ NP 0x0F 0x01 /0xC6] s:WRMSRNS, t:SYSTEM, w:R|R|R|W, m:KERNEL +WRMSRLIST nil SMT,DMT,ECX [ 0xF3 0x0F 0x01 /0xC6] s:MSRLIST, t:SYSTEM, w:R|R|RW, m:KERNEL|O64 +RDMSRLIST nil SMT,DMT,ECX [ 0xF2 0x0F 0x01 /0xC6] s:MSRLIST, t:SYSTEM, w:R|W|RW, m:KERNEL|O64 MONITOR nil pAXb,ECX,EDX [ NP 0x0F 0x01 /0xC8] s:SSE3, t:MISC, w:R|R|R, i:MONITOR, m:KERNEL|NOV86 MWAIT nil EAX,ECX [ NP 0x0F 0x01 /0xC9] s:SSE3, t:MISC, w:RW|R, i:MONITOR, m:KERNEL|NOV86 CLAC nil Fv [ NP 0x0F 0x01 /0xCA] s:SMAP, t:SMAP, w:W, f:AC=0, m:KERNEL|NOV86 @@ -138,6 +141,8 @@ MOVHPD Vq,Mq nil [ 0x66 0x0F 0x16 /r MOVSHDUP Vx,Wx nil [ 0xF3 0x0F 0x16 /r] s:SSE3, t:DATAXFER, w:W|R, e:4 MOVHPS Mq,Vq nil [ NP 0x0F 0x17 /r:mem] s:SSE, t:DATAXFER, w:W|R, e:5 MOVHPD Mq,Vq nil [ 0x66 0x0F 0x17 /r:mem] s:SSE2, t:DATAXFER, w:W|R, e:5 + +# Default wide-nops/PREFETCH instructions. PREFETCHNTA Mb nil [ 0x0F 0x18 /0:mem] s:SSE, t:PREFETCH, w:P NOP Ev nil [ 0x0F 0x18 /0:reg] s:PPRO, t:WIDENOP, w:N PREFETCHT0 Mb nil [ 0x0F 0x18 /1:mem] s:SSE, t:PREFETCH, w:P @@ -152,6 +157,26 @@ NOP Ev nil [ 0x0F 0x18 /6 NOP Ev nil [ 0x0F 0x18 /7] s:PPRO, t:WIDENOP, w:N NOP Ev nil [ 0x0F 0x19 /r] s:PPRO, t:WIDENOP, w:N +# PREFETCHITI instructions. Most of them duplicates of the above, since they are also present when the PREFETCHIT feature +# is enabled (which applies to the entire opcode). +PREFETCHNTA Mb nil [ piti 0x0F 0x18 /0:mem] s:SSE, t:PREFETCH, w:P +NOP Ev nil [ piti 0x0F 0x18 /0:reg] s:PPRO, t:WIDENOP, w:N +PREFETCHT0 Mb nil [ piti 0x0F 0x18 /1:mem] s:SSE, t:PREFETCH, w:P +NOP Ev nil [ piti 0x0F 0x18 /1:reg] s:PPRO, t:WIDENOP, w:N +PREFETCHT1 Mb nil [ piti 0x0F 0x18 /2:mem] s:SSE, t:PREFETCH, w:P +NOP Ev nil [ piti 0x0F 0x18 /2:reg] s:PPRO, t:WIDENOP, w:N +PREFETCHT2 Mb nil [ piti 0x0F 0x18 /3:mem] s:SSE, t:PREFETCH, w:P +NOP Ev nil [ piti 0x0F 0x18 /3:reg] s:PPRO, t:WIDENOP, w:N +NOP Ev nil [ piti 0x0F 0x18 /4] s:PPRO, t:WIDENOP, w:N +NOP Ev nil [ piti 0x0F 0x18 /5] s:PPRO, t:WIDENOP, w:N +PREFETCHIT1 Mb nil [piti riprel 0x0F 0x18 /6:mem] s:PREFETCHITI, t:PREFETCH, w:N, m:O64 +NOP Ev nil [ piti 0x0F 0x18 /6:mem] s:PPRO, t:WIDENOP, w:N +NOP Ev nil [ piti 0x0F 0x18 /6:reg] s:PPRO, t:WIDENOP, w:N +PREFETCHIT0 Mb nil [piti riprel 0x0F 0x18 /7:mem] s:PREFETCHITI, t:PREFETCH, w:N, m:O64 +NOP Ev nil [ piti 0x0F 0x18 /7:mem] s:PPRO, t:WIDENOP, w:N +NOP Ev nil [ piti 0x0F 0x18 /7:reg] s:PPRO, t:WIDENOP, w:N + + # MPX instructions. According to the SDM, MPX instructions have 64 bit op & address size in 64 bit mode, no matter # if 0x66 or 0x67 prefixes are used. 16 bit addressing cause #UD. However, these checks are not handled here (note # that Xed doesn't do those checks either). @@ -284,8 +309,8 @@ CMOVNLE Gv,Ev Fv [ 0x0F 0x4F /r # 0x50 - 0x5F # Note: for MOVMSKPS & MOVMSKPD, the Intel doc says the destination reg is y (32 or 64 bit) but XED says it must be d (only 32 bits). -MOVMSKPS Gd,Ups nil [ NP 0x0F 0x50 /r:reg] s:SSE, t:DATAXFER, w:W|R, e:7 -MOVMSKPD Gd,Upd nil [ 0x66 0x0F 0x50 /r:reg] s:SSE2, t:DATAXFER, w:W|R, e:7 +MOVMSKPS Gy,Ups nil [ NP 0x0F 0x50 /r:reg] s:SSE, t:DATAXFER, w:W|R, e:7, a:D64 +MOVMSKPD Gy,Upd nil [ 0x66 0x0F 0x50 /r:reg] s:SSE2, t:DATAXFER, w:W|R, e:7, a:D64 SQRTPS Vps,Wps nil [ NP 0x0F 0x51 /r] s:SSE, t:SSE, w:W|R, e:2 SQRTPD Vpd,Wpd nil [ 0x66 0x0F 0x51 /r] s:SSE2, t:SSE, w:W|R, e:2 SQRTSS Vss,Wss nil [ 0xF3 0x0F 0x51 /r] s:SSE, t:SSE, w:W|R, e:3 @@ -562,8 +587,8 @@ PINSRW Pq,Rd,Ib nil [ NP 0x0F 0xC4 /r PINSRW Pq,Mw,Ib nil [ NP 0x0F 0xC4 /r:mem ib] s:MMX, t:MMX, w:RW|R|R PINSRW Vdq,Rd,Ib nil [ 0x66 0x0F 0xC4 /r:reg ib] s:SSE2, t:SSE, w:RW|R|R, e:5 PINSRW Vdq,Mw,Ib nil [ 0x66 0x0F 0xC4 /r:mem ib] s:SSE2, t:SSE, w:RW|R|R, e:5 -PEXTRW Gy,Nq,Ib nil [ NP 0x0F 0xC5 /r:reg ib] s:MMX, t:MMX, w:W|R|R -PEXTRW Gy,Udq,Ib nil [ 0x66 0x0F 0xC5 /r:reg ib] s:SSE2, t:SSE, w:W|R|R, e:5 +PEXTRW Gy,Nq,Ib nil [ NP 0x0F 0xC5 /r:reg ib] s:MMX, t:MMX, w:W|R|R, a:D64 +PEXTRW Gy,Udq,Ib nil [ 0x66 0x0F 0xC5 /r:reg ib] s:SSE2, t:SSE, w:W|R|R, e:5, a:D64 SHUFPS Vps,Wps,Ib nil [ NP 0x0F 0xC6 /r ib] s:SSE, t:SSE, w:RW|R|R, e:4 SHUFPD Vpd,Wpd,Ib nil [ 0x66 0x0F 0xC6 /r ib] s:SSE2, t:SSE, w:RW|R|R, e:4 CMPXCHG8B Mq EDX,EAX,ECX,EBX,Fv [ 0x0F 0xC7 /1:mem] s:PENTIUMREAL, t:SEMAPHORE, w:RCW|RCW|RCW|R|R|W, i:CX8, f:ZF=m, p:LOCK|HLE @@ -610,8 +635,8 @@ PMULLW Vx,Wx nil [ 0x66 0x0F 0xD5 /r MOVQ Wq,Vq nil [ 0x66 0x0F 0xD6 /r] s:SSE2, t:DATAXFER, w:W|R, e:5 MOVQ2DQ Vdq,Nq nil [ 0xF3 0x0F 0xD6 /r:reg] s:SSE2, t:DATAXFER, w:W|R MOVDQ2Q Pq,Uq nil [ 0xF2 0x0F 0xD6 /r:reg] s:SSE2, t:DATAXFER, w:W|R -PMOVMSKB Gd,Nq nil [ NP 0x0F 0xD7 /r:reg] s:SSE, t:MMX, w:W|R, e:7 -PMOVMSKB Gd,Ux nil [ 0x66 0x0F 0xD7 /r:reg] s:SSE2, t:SSE, w:W|R, e:7 +PMOVMSKB Gy,Nq nil [ NP 0x0F 0xD7 /r:reg] s:SSE, t:MMX, w:W|R, e:7, a:D64 +PMOVMSKB Gy,Ux nil [ 0x66 0x0F 0xD7 /r:reg] s:SSE2, t:SSE, w:W|R, e:7, a:D64 PSUBUSB Pq,Qq nil [ NP 0x0F 0xD8 /r] s:MMX, t:MMX, w:RW|R PSUBUSB Vx,Wx nil [ 0x66 0x0F 0xD8 /r] s:SSE2, t:SSE, w:RW|R, e:4 PSUBUSW Pq,Qq nil [ NP 0x0F 0xD9 /r] s:MMX, t:MMX, w:RW|R diff --git a/isagenerator/instructions/table_0F_38.dat b/isagenerator/instructions/table_0F_38.dat index fb160a5..b4bb37f 100644 --- a/isagenerator/instructions/table_0F_38.dat +++ b/isagenerator/instructions/table_0F_38.dat @@ -138,3 +138,8 @@ MOVDIRI My,Gy nil [ NP 0x0F 0x ENCODEKEY128 Gd,Rd XMM0,XMM0-2,XMM4-6,Fv [ 0xF3 0x0F 0x38 0xFA /r:reg] s:KL, t:AESKL, w:W|R|R|W|W|W, f:ZERO ENCODEKEY256 Gd,Rd XMM0-1,XMM2-6,Fv [ 0xF3 0x0F 0x38 0xFB /r:reg] s:KL, t:AESKL, w:W|R|RW|W|W, f:ZERO + +AADD My,Gy nil [ NP 0x0F 0x38 0xFC /r:mem] s:RAOINT, t:RAOINT, w:RW|R +AAND My,Gy nil [ 0x66 0x0F 0x38 0xFC /r:mem] s:RAOINT, t:RAOINT, w:RW|R +AOR My,Gy nil [ 0xF2 0x0F 0x38 0xFC /r:mem] s:RAOINT, t:RAOINT, w:RW|R +AXOR My,Gy nil [ 0xF3 0x0F 0x38 0xFC /r:mem] s:RAOINT, t:RAOINT, w:RW|R diff --git a/isagenerator/instructions/table_0F_3A.dat b/isagenerator/instructions/table_0F_3A.dat index b9adc29..f7a5c4b 100644 --- a/isagenerator/instructions/table_0F_3A.dat +++ b/isagenerator/instructions/table_0F_3A.dat @@ -14,11 +14,13 @@ PALIGNR Vx,Wx,Ib nil [ 0x66 0x0F 0x # 0x10 - 0x1F # TODO: for PEXTRx, a smaller size is accessed, in fact. PEXTRB Mb,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x14 /r:mem ib] s:SSE4, t:SSE, w:W|R|R, e:5 -PEXTRB Rd,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x14 /r:reg ib] s:SSE4, t:SSE, w:W|R|R, e:5 +PEXTRB Ry,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x14 /r:reg ib] s:SSE4, t:SSE, w:W|R|R, e:5, a:D64 PEXTRW Mw,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x15 /r:mem ib] s:SSE4, t:SSE, w:W|R|R, e:5 -PEXTRW Rd,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x15 /r:reg ib] s:SSE4, t:SSE, w:W|R|R, e:5 -PEXTRD Ey,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x16 /r ib] s:SSE4, t:SSE, w:W|R|R, e:5 -PEXTRQ Ey,Vdq,Ib nil [ rexw 0x66 0x0F 0x3A 0x16 /r ib] s:SSE4, t:SSE, w:W|R|R, e:5 +PEXTRW Ry,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x15 /r:reg ib] s:SSE4, t:SSE, w:W|R|R, e:5, a:D64 +PEXTRD Md,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x16 /r:mem ib] s:SSE4, t:SSE, w:W|R|R, e:5 +PEXTRD Ry,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x16 /r:reg ib] s:SSE4, t:SSE, w:W|R|R, e:5, a:D64 +PEXTRQ Mq,Vdq,Ib nil [ rexw 0x66 0x0F 0x3A 0x16 /r:mem ib] s:SSE4, t:SSE, w:W|R|R, e:5 +PEXTRQ Ry,Vdq,Ib nil [ rexw 0x66 0x0F 0x3A 0x16 /r:reg ib] s:SSE4, t:SSE, w:W|R|R, e:5 EXTRACTPS Ed,Vdq,Ib nil [ 0x66 0x0F 0x3A 0x17 /r ib] s:SSE4, t:SSE, w:W|R|R, e:5 # 0x20 - 0x2F diff --git a/isagenerator/instructions/table_base.dat b/isagenerator/instructions/table_base.dat index 9bb00a9..34e2a67 100644 --- a/isagenerator/instructions/table_base.dat +++ b/isagenerator/instructions/table_base.dat @@ -15,7 +15,7 @@ OR Gb,Eb Fv [ 0x0A /r] s:I86 OR Gv,Ev Fv [ 0x0B /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC OR AL,Ib Fv [ 0x0C ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC OR rAX,Iz Fv [ 0x0D iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1 -PUSH CS Kv [ 0x0E] s:I86, t:PUSH, w:R|R, m:NO64|NOSGX +PUSH CS Kv [ 0x0E] s:I86, t:PUSH, w:R|W, m:NO64|NOSGX # 0x10 - 0x1F ADC Eb,Gb Fv [ 0x10 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK diff --git a/isagenerator/instructions/table_evex3.dat b/isagenerator/instructions/table_evex3.dat index 1cc4987..4971412 100644 --- a/isagenerator/instructions/table_evex3.dat +++ b/isagenerator/instructions/table_evex3.dat @@ -17,11 +17,13 @@ VPALIGNR Vn{K}{z},Hn,Wn,Ib nil [evex m:3 p:1 l:x w: # 0x10 - 0x1F VPEXTRB Mb,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x14 /r:mem ib] s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R -VPEXTRB Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x14 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R +VPEXTRB Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x14 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R, a:D64 VPEXTRW Mw,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x15 /r:mem ib] s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R -VPEXTRW Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x15 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R -VPEXTRD Ed,Vdq,Ib nil [evex m:3 p:1 l:0 w:0 0x16 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64 -VPEXTRQ Eq,Vdq,Ib nil [evex m:3 p:1 l:0 w:1 0x16 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64 +VPEXTRW Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x15 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R, a:D64 +VPEXTRD Md,Vdq,Ib nil [evex m:3 p:1 l:0 w:0 0x16 /r:mem ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64 +VPEXTRD Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:0 0x16 /r:reg ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64|D64 +VPEXTRQ Mq,Vdq,Ib nil [evex m:3 p:1 l:0 w:1 0x16 /r:mem ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64 +VPEXTRQ Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:1 0x16 /r:reg ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64 VEXTRACTPS Md,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x17 /r:mem ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R VEXTRACTPS Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x17 /r:reg ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R VINSERTF32X4 Vu{K}{z},Hu,Wdq,Ib nil [evex m:3 p:1 l:x w:0 0x18 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R diff --git a/isagenerator/instructions/table_vex1.dat b/isagenerator/instructions/table_vex1.dat index b1440ab..490f6d8 100644 --- a/isagenerator/instructions/table_vex1.dat +++ b/isagenerator/instructions/table_vex1.dat @@ -119,8 +119,8 @@ KTESTQ rKq,mKq nil [vex m:1 p:0 l:0 w:1 KTESTD rKd,mKd nil [vex m:1 p:1 l:0 w:1 0x99 /r:reg] s:AVX512BW, t:KMASK, c:KTEST, w:W|R, e:K20 # 0x50 - 0x5F -VMOVMSKPS Gy,Ux nil [vex m:1 p:0 l:x w:i 0x50 /r:reg] s:AVX, t:DATAXFER, w:W|R, e:7 -VMOVMSKPD Gy,Ux nil [vex m:1 p:1 l:x w:i 0x50 /r:reg] s:AVX, t:DATAXFER, w:W|R, e:7 +VMOVMSKPS Gy,Ux nil [vex m:1 p:0 l:x w:i 0x50 /r:reg] s:AVX, t:DATAXFER, w:W|R, e:7, a:D64 +VMOVMSKPD Gy,Ux nil [vex m:1 p:1 l:x w:i 0x50 /r:reg] s:AVX, t:DATAXFER, w:W|R, e:7, a:D64 VSQRTPS Vx,Wx nil [vex m:1 p:0 l:x w:i 0x51 /r] s:AVX, t:AVX, w:W|R, e:2 VSQRTPD Vx,Wx nil [vex m:1 p:1 l:x w:i 0x51 /r] s:AVX, t:AVX, w:W|R, e:2 VSQRTSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x51 /r] s:AVX, t:AVX, w:W|R|R, e:3 @@ -244,7 +244,7 @@ VCMPSS Vss,Hss,Wss,Ib nil [vex m:1 p:2 l:i w:i VCMPSD Vsd,Hsd,Wsd,Ib nil [vex m:1 p:3 l:i w:i 0xC2 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:3 VPINSRW Vdq,Hdq,Mw,Ib nil [vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib] s:AVX, t:AVX, w:W|R|R|R, e:5 VPINSRW Vdq,Hdq,Rd,Ib nil [vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib] s:AVX, t:AVX, w:W|R|R|R, e:5 -VPEXTRW Gy,Udq,Ib nil [vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5 +VPEXTRW Gy,Udq,Ib nil [vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5, a:D64 VSHUFPS Vps,Hps,Wps,Ib nil [vex m:1 p:0 l:x w:i 0xC6 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:4 VSHUFPD Vpd,Hpd,Wpd,Ib nil [vex m:1 p:1 l:x w:i 0xC6 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:4 @@ -257,7 +257,7 @@ VPSRLQ Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i VPADDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xD4 /r] s:AVX, t:AVX, w:W|R|R, e:4 VPMULLW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xD5 /r] s:AVX, t:AVX, w:W|R|R, e:4 VMOVQ Wq,Vdq nil [vex m:1 p:1 l:0 w:i 0xD6 /r] s:AVX, t:DATAXFER, w:W|R, e:5 -VPMOVMSKB Gy,Ux nil [vex m:1 p:1 l:x w:i 0xD7 /r:reg] s:AVX, t:DATAXFER, w:W|R, e:7 +VPMOVMSKB Gy,Ux nil [vex m:1 p:1 l:x w:i 0xD7 /r:reg] s:AVX, t:DATAXFER, w:W|R, e:7, a:D64 VPSUBUSB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xD8 /r] s:AVX, t:AVX, w:W|R|R, e:4 VPSUBUSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xD9 /r] s:AVX, t:AVX, w:W|R|R, e:4 VPMINUB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDA /r] s:AVX, t:AVX, w:W|R|R, e:4 diff --git a/isagenerator/instructions/table_vex2.dat b/isagenerator/instructions/table_vex2.dat index dd45ed5..5ea3d9f 100644 --- a/isagenerator/instructions/table_vex2.dat +++ b/isagenerator/instructions/table_vex2.dat @@ -94,8 +94,14 @@ TILERELEASE nil nil [vex m:2 p:0 l:0 w:0 TILEZERO rTt nil [vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0] s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E5 # 0x50 - 0x5F +VPDPBUUD Vx,Hx,Wx nil [vex m:2 p:0 l:x w:0 0x50 /r] s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 VPDPBUSD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x50 /r] s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 +VPDPBSUD Vx,Hx,Wx nil [vex m:2 p:2 l:x w:0 0x50 /r] s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 +VPDPBSSD Vx,Hx,Wx nil [vex m:2 p:3 l:x w:0 0x50 /r] s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 +VPDPBUUDS Vx,Hx,Wx nil [vex m:2 p:0 l:x w:0 0x51 /r] s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 VPDPBUSDS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x51 /r] s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 +VPDPBSUDS Vx,Hx,Wx nil [vex m:2 p:2 l:x w:0 0x51 /r] s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 +VPDPBSSDS Vx,Hx,Wx nil [vex m:2 p:3 l:x w:0 0x51 /r] s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 VPDPWSSD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x52 /r] s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 VPDPWSSDS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x53 /r] s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 @@ -104,6 +110,7 @@ VPBROADCASTQ Vx,Wq nil [vex m:2 p:1 l:x w:0 VBROADCASTI128 Vqq,Mdq nil [vex m:2 p:1 l:1 w:0 0x5A /r:mem] s:AVX2, t:BROADCAST, w:W|R, e:6 TDPBF16PS rTt,mTt,vTt nil [vex m:2 p:2 l:0 w:0 0x5C /r:reg] s:AMXBF16, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPFP16PS rTt,mTt,vTt nil [vex m:2 p:3 l:0 w:0 0x5C /r:reg] s:AMXFP16, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 TDPBUUD rTt,mTt,vTt nil [vex m:2 p:0 l:0 w:0 0x5E /r:reg] s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 TDPBUSD rTt,mTt,vTt nil [vex m:2 p:1 l:0 w:0 0x5E /r:reg] s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 TDPBSUD rTt,mTt,vTt nil [vex m:2 p:2 l:0 w:0 0x5E /r:reg] s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 @@ -112,6 +119,7 @@ TDPBSSD rTt,mTt,vTt nil [vex m:2 p:3 l:0 w:0 # 0x60 - 0x6F # 0x70 - 0x7F +VCVTNEPS2BF16 Vx,Wx nil [vex m:2 p:2 l:x w:0 0x72 /r] s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 VPBROADCASTB Vx,Wb nil [vex m:2 p:1 l:x w:0 0x78 /r] s:AVX2, t:BROADCAST, w:W|R, e:6 VPBROADCASTW Vx,Ww nil [vex m:2 p:1 l:x w:0 0x79 /r] s:AVX2, t:BROADCAST, w:W|R, e:6 @@ -175,6 +183,16 @@ VFNMSUB213SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 VFNMSUB213SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0xAF /r] s:FMA, t:VFMA, w:RW|R|R, e:3 # 0xB0 - 0xBF +VCVTNEOPH2PS Vx,Mx nil [vex m:2 p:0 l:x w:0 0xB0 /r:mem] s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 +VCVTNEEPH2PS Vx,Mx nil [vex m:2 p:1 l:x w:0 0xB0 /r:mem] s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 +VCVTNEEBF162PS Vx,Mx nil [vex m:2 p:2 l:x w:0 0xB0 /r:mem] s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 +VCVTNEOBF162PS Vx,Mx nil [vex m:2 p:3 l:x w:0 0xB0 /r:mem] s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 +VBCSTNESH2PS Vx,Mw nil [vex m:2 p:1 l:x w:0 0xB1 /r:mem] s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:5 +VBCSTNEBF162PS Vx,Mw nil [vex m:2 p:2 l:x w:0 0xB1 /r:mem] s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:5 + +VPMADD52LUQ Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xB4 /r] s:AVXIFMA, t:AVXIFMA, w:RW|R|R, e:4 +VPMADD52HUQ Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xB5 /r] s:AVXIFMA, t:AVXIFMA, w:RW|R|R, e:4 + VFMADDSUB231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xB6 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 VFMADDSUB231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xB6 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 VFMSUBADD231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xB7 /r] s:FMA, t:VFMA, w:RW|R|R, e:2 @@ -202,6 +220,24 @@ VAESENCLAST Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i VAESDEC Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0xDE /r] s:AES, t:AES, w:W|R|R, e:4 VAESDECLAST Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0xDF /r] s:AES, t:AES, w:W|R|R, e:4 +# 0xE0 - 0xEF +CMPOXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xE0 /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPNOXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xE1 /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPCXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xE2 /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPNCXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xE3 /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPZXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xE4 /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPNZXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xE5 /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPBEXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xE6 /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPNBEXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xE7 /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPSXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xE8 /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPNSXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xE9 /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPPXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xEA /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPNPXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xEB /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPLXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xEC /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPNLXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xED /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPLEXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xEE /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 +CMPNLEXADD My,Gy,By Fv [vex m:2 p:1 l:0 w:x 0xEF /r:mem] s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 + # 0xF0 - 0xFF ANDN Gy,By,Ey Fv [vex m:2 p:0 l:0 w:x 0xF2 /r] s:BMI1, t:BMI1, w:W|R|R|W, f:CF=0|PF=u|AF=u|ZF=m|SF=m|OF=0, e:13 BLSR By,Ey Fv [vex m:2 p:0 l:0 w:x 0xF3 /1] s:BMI1, t:BMI1, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=m|OF=0, e:13 diff --git a/isagenerator/instructions/table_vex3.dat b/isagenerator/instructions/table_vex3.dat index baac9fa..745d5df 100644 --- a/isagenerator/instructions/table_vex3.dat +++ b/isagenerator/instructions/table_vex3.dat @@ -18,11 +18,13 @@ VPALIGNR Vx,Hx,Wx,Ib nil [vex m:3 p:1 l:x w:i # 0x10 - 0x1F VPEXTRB Mb,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x14 /r:mem ib] s:AVX, t:AVX, w:W|R|R, e:5 -VPEXTRB Rd,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x14 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5 +VPEXTRB Ry,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x14 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5, a:D64 VPEXTRW Mw,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x15 /r:mem ib] s:AVX, t:AVX, w:W|R|R, e:5 -VPEXTRW Rd,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x15 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5 -VPEXTRD Ey,Vdq,Ib nil [vex m:3 p:1 l:0 w:0 0x16 /r ib] s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64 -VPEXTRQ Ey,Vdq,Ib nil [vex m:3 p:1 l:0 w:1 0x16 /r ib] s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64 +VPEXTRW Ry,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x15 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5, a:D64 +VPEXTRD Md,Vdq,Ib nil [vex m:3 p:1 l:0 w:0 0x16 /r:mem ib] s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64 +VPEXTRD Ry,Vdq,Ib nil [vex m:3 p:1 l:0 w:0 0x16 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64|D64 +VPEXTRQ Mq,Vdq,Ib nil [vex m:3 p:1 l:0 w:1 0x16 /r:mem ib] s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64 +VPEXTRQ Ry,Vdq,Ib nil [vex m:3 p:1 l:0 w:1 0x16 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64 VEXTRACTPS Md,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x17 /r:mem ib] s:AVX, t:AVX, w:W|R|R, e:5 VEXTRACTPS Ry,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x17 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5 VINSERTF128 Vqq,Hqq,Wdq,Ib nil [vex m:3 p:1 l:1 w:0 0x18 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:6