diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h index fad2297..9279744 100644 --- a/bddisasm/include/instructions.h +++ b/bddisasm/include/instructions.h @@ -5951,8 +5951,8 @@ const ND_INSTRUCTION gInstructions[2584] = { ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 245, 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0, 0, @@ -14905,8 +14905,8 @@ const ND_INSTRUCTION gInstructions[2584] = { ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 543, 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, 0, 0, 0, @@ -14953,8 +14953,8 @@ const ND_INSTRUCTION gInstructions[2584] = { ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 546, 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, 0, 0, 0, @@ -42790,7 +42790,7 @@ const ND_INSTRUCTION gInstructions[2584] = }, }, - // Pos:2537 Instruction:"XCHG rAX,Zv" Encoding:"rexb 0x90"/"O" + // Pos:2537 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 0, @@ -42801,12 +42801,12 @@ const ND_INSTRUCTION gInstructions[2584] = 0, 0, { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, - // Pos:2538 Instruction:"XCHG rAX,Zv" Encoding:"0x91"/"O" + // Pos:2538 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 0, @@ -42817,12 +42817,12 @@ const ND_INSTRUCTION gInstructions[2584] = 0, 0, { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, - // Pos:2539 Instruction:"XCHG rAX,Zv" Encoding:"0x92"/"O" + // Pos:2539 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 0, @@ -42833,12 +42833,12 @@ const ND_INSTRUCTION gInstructions[2584] = 0, 0, { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, - // Pos:2540 Instruction:"XCHG rAX,Zv" Encoding:"0x93"/"O" + // Pos:2540 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 0, @@ -42849,12 +42849,12 @@ const ND_INSTRUCTION gInstructions[2584] = 0, 0, { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, - // Pos:2541 Instruction:"XCHG rAX,Zv" Encoding:"0x94"/"O" + // Pos:2541 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 0, @@ -42865,12 +42865,12 @@ const ND_INSTRUCTION gInstructions[2584] = 0, 0, { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, - // Pos:2542 Instruction:"XCHG rAX,Zv" Encoding:"0x95"/"O" + // Pos:2542 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 0, @@ -42881,12 +42881,12 @@ const ND_INSTRUCTION gInstructions[2584] = 0, 0, { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, - // Pos:2543 Instruction:"XCHG rAX,Zv" Encoding:"0x96"/"O" + // Pos:2543 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 0, @@ -42897,12 +42897,12 @@ const ND_INSTRUCTION gInstructions[2584] = 0, 0, { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, - // Pos:2544 Instruction:"XCHG rAX,Zv" Encoding:"0x97"/"O" + // Pos:2544 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1555, 0, @@ -42913,8 +42913,8 @@ const ND_INSTRUCTION gInstructions[2584] = 0, 0, { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, diff --git a/inc/version.h b/inc/version.h index 65d24ee..ed5af09 100644 --- a/inc/version.h +++ b/inc/version.h @@ -7,6 +7,6 @@ #define DISASM_VERSION_MAJOR 1 #define DISASM_VERSION_MINOR 31 -#define DISASM_VERSION_REVISION 5 +#define DISASM_VERSION_REVISION 6 #endif // DISASM_VER_H diff --git a/isagenerator/instructions/table_3dnow.dat b/isagenerator/instructions/table_3dnow.dat index ae6efea..f387122 100644 --- a/isagenerator/instructions/table_3dnow.dat +++ b/isagenerator/instructions/table_3dnow.dat @@ -4,8 +4,8 @@ PI2FW Pq,Qq nil [0x0F 0x0F /r 0x0C] s:3DNOW, PI2FD Pq,Qq nil [0x0F 0x0F /r 0x0D] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW PF2IW Pq,Qq nil [0x0F 0x0F /r 0x1C] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW PF2ID Pq,Qq nil [0x0F 0x0F /r 0x1D] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFRCPV Pq,Qq nil [0x0F 0x0F /r 0x86] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFRSQRTV Pq,Qq nil [0x0F 0x0F /r 0x87] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRCPV Pq,Qq nil [0x0F 0x0F /r 0x86] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW, m:NO64 +PFRSQRTV Pq,Qq nil [0x0F 0x0F /r 0x87] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW, m:NO64 PFNACC Pq,Qq nil [0x0F 0x0F /r 0x8A] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW PFPNACC Pq,Qq nil [0x0F 0x0F /r 0x8E] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW PFCMPGE Pq,Qq nil [0x0F 0x0F /r 0x90] s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW diff --git a/isagenerator/instructions/table_base.dat b/isagenerator/instructions/table_base.dat index 6a39e0a..46fc42a 100644 --- a/isagenerator/instructions/table_base.dat +++ b/isagenerator/instructions/table_base.dat @@ -212,14 +212,14 @@ POP Ev Kv [ 0x8F /0] s:I86 # 0x90 - 0x9F NOP nil nil [ 0x90] s:I86, t:NOP, PAUSE nil nil [ a0xF3 0x90] s:PAUSE, t:MISC, m:NOTSX -XCHG rAX,Zv nil [ rexb 0x90] s:I86, t:DATAXFER, w:RW|RW -XCHG rAX,Zv nil [ 0x91] s:I86, t:DATAXFER, w:RW|RW -XCHG rAX,Zv nil [ 0x92] s:I86, t:DATAXFER, w:RW|RW -XCHG rAX,Zv nil [ 0x93] s:I86, t:DATAXFER, w:RW|RW -XCHG rAX,Zv nil [ 0x94] s:I86, t:DATAXFER, w:RW|RW -XCHG rAX,Zv nil [ 0x95] s:I86, t:DATAXFER, w:RW|RW -XCHG rAX,Zv nil [ 0x96] s:I86, t:DATAXFER, w:RW|RW -XCHG rAX,Zv nil [ 0x97] s:I86, t:DATAXFER, w:RW|RW +XCHG Zv,rAX nil [ rexb 0x90] s:I86, t:DATAXFER, w:RW|RW +XCHG Zv,rAX nil [ 0x91] s:I86, t:DATAXFER, w:RW|RW +XCHG Zv,rAX nil [ 0x92] s:I86, t:DATAXFER, w:RW|RW +XCHG Zv,rAX nil [ 0x93] s:I86, t:DATAXFER, w:RW|RW +XCHG Zv,rAX nil [ 0x94] s:I86, t:DATAXFER, w:RW|RW +XCHG Zv,rAX nil [ 0x95] s:I86, t:DATAXFER, w:RW|RW +XCHG Zv,rAX nil [ 0x96] s:I86, t:DATAXFER, w:RW|RW +XCHG Zv,rAX nil [ 0x97] s:I86, t:DATAXFER, w:RW|RW CBW nil AX,AL [ ds16 0x98] s:I386, t:CONVERT, w:W|R CWDE nil EAX,AX [ ds32 0x98] s:I386, t:CONVERT, w:W|R CDQE nil RAX,EAX [ ds64 0x98] s:I386, t:CONVERT, w:W|R diff --git a/isagenerator/instructions/table_fpu.dat b/isagenerator/instructions/table_fpu.dat index 590e538..be55522 100644 --- a/isagenerator/instructions/table_fpu.dat +++ b/isagenerator/instructions/table_fpu.dat @@ -168,7 +168,7 @@ FXCH ST(0),ST(i) X87TAG [0xDF /1:reg] s FSTP ST(i),ST(0) X87STATUS [0xDF /2:reg] s:X87, t:X87_ALU, w:R|W|W, u:C1=m FSTP ST(i),ST(0) X87STATUS [0xDF /3:reg] s:X87, t:X87_ALU, w:R|W|W, u:C1=m FNSTSW AX X87STATUS [0xDF /0xE0] s:X87, t:X87_ALU, w:W|W, u:C0=u|C1=u|C2=u|C3=u -FSTDW AX nil [0xDF /0xE1] s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u +FSTDW AX nil [0xDF /0xE1] s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u, m:NO64 FSTSG AX nil [0xDF /0xE2] s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u FUCOMIP ST(0),ST(i) X87STATUS,Fv [0xDF /5:reg] s:X87, t:X87_ALU, w:R|R|W|W, f:CF=m|PF=m|ZF=m|OF=0, u:C0=m|C1=0|C2=m|C3=m FCOMIP ST(0),ST(i) X87STATUS,Fv [0xDF /6:reg] s:X87, t:X87_ALU, w:R|R|W|W, f:CF=m|PF=m|ZF=m|OF=0, u:C0=m|C1=0|C2=m|C3=m