From 9652450125688e642b29ea741c2af09bf421e88d Mon Sep 17 00:00:00 2001 From: Andrei Vlad LUTAS Date: Mon, 5 Oct 2020 13:19:03 +0300 Subject: [PATCH] =?UTF-8?q?Added=20support=20for=20UINTR,=20HRESET=20and?= =?UTF-8?q?=20AVX-VNNI=20instructions,=20as=20per=20Intel=C2=AE=20Architec?= =?UTF-8?q?ture=20Instruction=20Set=20Extensions=20Programming=20Reference?= =?UTF-8?q?=2041=20(October=202020).?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bddisasm/bddisasm.c | 13 +- bddisasm/include/instructions.h | 9963 +++++++++++---------- bddisasm/include/mnemonics.h | 290 +- bddisasm/include/table_evex.h | 1234 +-- bddisasm/include/table_root.h | 2952 +++--- bddisasm/include/table_vex.h | 1202 +-- bddisasm/include/table_xop.h | 154 +- bddisasm/include/tabledefs.h | 1 + bddisasm_test/avx/avxvnni_64 | 1 + bddisasm_test/avx/avxvnni_64.asm | 10 + bddisasm_test/avx/avxvnni_64.result | 152 + bddisasm_test/basic/system_64 | Bin 135 -> 141 bytes bddisasm_test/basic/system_64.asm | 4 +- bddisasm_test/basic/system_64.result | 16 + bddisasm_test/uintr/uintr_64 | 1 + bddisasm_test/uintr/uintr_64.asm | 7 + bddisasm_test/uintr/uintr_64.result | 87 + disasmtool/disasmtool.c | 7 + disasmtool_lix/dumpers.cpp | 18 + inc/bddisasm.h | 7 +- inc/constants.h | 12 + inc/cpuidflags.h | 4 + inc/version.h | 2 +- isagenerator/disasmlib.py | 2 + isagenerator/generate_tables.py | 1 + isagenerator/instructions/cpuid.dat | 5 +- isagenerator/instructions/flags.dat | 3 + isagenerator/instructions/table_0F.dat | 5 + isagenerator/instructions/table_0F_3A.dat | 1 + isagenerator/instructions/table_vex2.dat | 5 + pybddisasm/_pybddisasm/_pybddisasm.c | 1 + pybddisasm/setup.py | 2 +- 32 files changed, 8445 insertions(+), 7717 deletions(-) create mode 100644 bddisasm_test/avx/avxvnni_64 create mode 100644 bddisasm_test/avx/avxvnni_64.asm create mode 100644 bddisasm_test/avx/avxvnni_64.result create mode 100644 bddisasm_test/uintr/uintr_64 create mode 100644 bddisasm_test/uintr/uintr_64.asm create mode 100644 bddisasm_test/uintr/uintr_64.result diff --git a/bddisasm/bddisasm.c b/bddisasm/bddisasm.c index e1f73df..ef99545 100644 --- a/bddisasm/bddisasm.c +++ b/bddisasm/bddisasm.c @@ -173,6 +173,7 @@ static const uint16_t gOperandMap[] = ND_OPE_S, // ND_OPT_MXCSR ND_OPE_S, // ND_OPT_PKRU ND_OPE_S, // ND_OPT_SSP + ND_OPE_S, // ND_OPT_UIF ND_OPE_S, // ND_OPT_GPR_AH ND_OPE_S, // ND_OPT_GPR_rAX @@ -1993,6 +1994,14 @@ NdParseOperand( operand->Info.Register.Reg = 0; break; + case ND_OPT_UIF: + // The operand is the User Interrupt Flag. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_UIF; + operand->Info.Register.Size = ND_SIZE_8BIT; // 1 bit, in fact, but there is no size defined for one bit. + operand->Info.Register.Reg = 0; + break; + case ND_OPT_MSR: // The operand is implicit and is a MSR (usually selected by the ECX register). operand->Type = ND_OP_REG; @@ -5083,7 +5092,7 @@ NdGetFullAccessMap( { case ND_REG_GPR: { - uint8_t k; + uint32_t k; for (k = 0; k < pOp->Info.Register.Count; k++) { @@ -5102,7 +5111,7 @@ NdGetFullAccessMap( break; case ND_REG_SSE: { - uint8_t k; + uint32_t k; for (k = 0; k < pOp->Info.Register.Count; k++) { diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h index de33720..b145b7a 100644 --- a/bddisasm/include/instructions.h +++ b/bddisasm/include/instructions.h @@ -5,7 +5,7 @@ #ifndef INSTRUCTIONS_H #define INSTRUCTIONS_H -const ND_INSTRUCTION gInstructions[2576] = +const ND_INSTRUCTION gInstructions[2586] = { // Pos:0 Instruction:"AAA" Encoding:"0x37"/"" { @@ -2100,9 +2100,24 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:127 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M" + // Pos:127 Instruction:"CLUI" Encoding:"0xF3 0x0F 0x01 /0xEE"/"" { - ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 85, + ND_INS_CLUI, ND_CAT_UINTR, ND_SET_UINTR, 85, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:128 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M" + { + ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 86, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLWB, @@ -2115,9 +2130,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:128 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/"" + // Pos:129 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/"" { - ND_INS_CLZERO, ND_CAT_MISC, ND_SET_CLZERO, 86, + ND_INS_CLZERO, ND_CAT_MISC, ND_SET_CLZERO, 87, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2130,9 +2145,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:129 Instruction:"CMC" Encoding:"0xF5"/"" + // Pos:130 Instruction:"CMC" Encoding:"0xF5"/"" { - ND_INS_CMC, ND_CAT_FLAGOP, ND_SET_I86, 87, + ND_INS_CMC, ND_CAT_FLAGOP, ND_SET_I86, 88, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2145,9 +2160,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:130 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM" + // Pos:131 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 88, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 89, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2162,9 +2177,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:131 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM" + // Pos:132 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 89, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 90, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2179,9 +2194,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:132 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM" + // Pos:133 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 90, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 91, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2196,9 +2211,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:133 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM" + // Pos:134 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 91, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 92, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2213,9 +2228,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:134 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM" + // Pos:135 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 92, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 93, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2230,9 +2245,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:135 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM" + // Pos:136 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 93, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 94, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2247,9 +2262,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:136 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM" + // Pos:137 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 94, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 95, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2264,9 +2279,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:137 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM" + // Pos:138 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 95, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 96, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2281,9 +2296,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:138 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM" + // Pos:139 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 96, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 97, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2298,9 +2313,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:139 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM" + // Pos:140 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 97, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 98, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2315,9 +2330,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:140 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM" + // Pos:141 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 98, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 99, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2332,9 +2347,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:141 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM" + // Pos:142 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 99, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 100, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2349,9 +2364,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:142 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM" + // Pos:143 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 100, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 101, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2366,9 +2381,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:143 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM" + // Pos:144 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 101, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 102, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2383,9 +2398,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:144 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM" + // Pos:145 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 102, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 103, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2400,9 +2415,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:145 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM" + // Pos:146 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM" { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 103, + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 104, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, @@ -2417,9 +2432,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:146 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR" + // Pos:147 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 105, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2434,9 +2449,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:147 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR" + // Pos:148 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 105, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2451,9 +2466,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:148 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM" + // Pos:149 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 105, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2468,9 +2483,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:149 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM" + // Pos:150 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 105, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2485,9 +2500,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:150 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I" + // Pos:151 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 105, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2502,9 +2517,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:151 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I" + // Pos:152 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 105, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2519,9 +2534,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:152 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI" + // Pos:153 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 105, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2536,9 +2551,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:153 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI" + // Pos:154 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 105, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2553,9 +2568,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:154 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI" + // Pos:155 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 105, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -2570,9 +2585,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:155 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI" + // Pos:156 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI" { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 105, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2587,9 +2602,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:156 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI" + // Pos:157 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI" { - ND_INS_CMPPD, ND_CAT_SSE, ND_SET_SSE2, 105, + ND_INS_CMPPD, ND_CAT_SSE, ND_SET_SSE2, 106, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -2604,9 +2619,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:157 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI" + // Pos:158 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI" { - ND_INS_CMPPS, ND_CAT_SSE, ND_SET_SSE, 106, + ND_INS_CMPPS, ND_CAT_SSE, ND_SET_SSE, 107, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -2621,9 +2636,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:158 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/"" + // Pos:159 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 107, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 108, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2640,9 +2655,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:159 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/"" + // Pos:160 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 107, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 108, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2660,9 +2675,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:160 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI" + // Pos:161 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI" { - ND_INS_CMPSD, ND_CAT_SSE, ND_SET_SSE2, 108, + ND_INS_CMPSD, ND_CAT_SSE, ND_SET_SSE2, 109, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -2677,9 +2692,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:161 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/"" + // Pos:162 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 108, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 109, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2696,9 +2711,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:162 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/"" + // Pos:163 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 108, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 109, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2716,9 +2731,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:163 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/"" + // Pos:164 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 109, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 110, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2735,9 +2750,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:164 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/"" + // Pos:165 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 109, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 110, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2755,9 +2770,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:165 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI" + // Pos:166 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI" { - ND_INS_CMPSS, ND_CAT_SSE, ND_SET_SSE, 110, + ND_INS_CMPSS, ND_CAT_SSE, ND_SET_SSE, 111, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -2772,9 +2787,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:166 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/"" + // Pos:167 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 111, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 112, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2791,9 +2806,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:167 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/"" + // Pos:168 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/"" { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 111, + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 112, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2811,9 +2826,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:168 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR" + // Pos:169 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR" { - ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 112, + ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 113, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2829,9 +2844,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:169 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR" + // Pos:170 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR" { - ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 112, + ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 113, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -2847,9 +2862,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:170 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M" + // Pos:171 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M" { - ND_INS_CMPXCHG16B, ND_CAT_SEMAPHORE, ND_SET_CMPXCHG16B, 113, + ND_INS_CMPXCHG16B, ND_CAT_SEMAPHORE, ND_SET_CMPXCHG16B, 114, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, @@ -2867,9 +2882,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:171 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M" + // Pos:172 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M" { - ND_INS_CMPXCHG8B, ND_CAT_SEMAPHORE, ND_SET_PENTIUMREAL, 114, + ND_INS_CMPXCHG8B, ND_CAT_SEMAPHORE, ND_SET_PENTIUMREAL, 115, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, @@ -2887,9 +2902,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:172 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM" + // Pos:173 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM" { - ND_INS_COMISD, ND_CAT_SSE2, ND_SET_SSE2, 115, + ND_INS_COMISD, ND_CAT_SSE2, ND_SET_SSE2, 116, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -2904,9 +2919,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:173 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM" + // Pos:174 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM" { - ND_INS_COMISS, ND_CAT_SSE, ND_SET_SSE, 116, + ND_INS_COMISS, ND_CAT_SSE, ND_SET_SSE, 117, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -2921,9 +2936,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:174 Instruction:"CPUID" Encoding:"0x0F 0xA2"/"" + // Pos:175 Instruction:"CPUID" Encoding:"0x0F 0xA2"/"" { - ND_INS_CPUID, ND_CAT_MISC, ND_SET_I486REAL, 117, + ND_INS_CPUID, ND_CAT_MISC, ND_SET_I486REAL, 118, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -2939,9 +2954,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:175 Instruction:"CPU_READ" Encoding:"0x0F 0x3D"/"" + // Pos:176 Instruction:"CPU_READ" Encoding:"0x0F 0x3D"/"" { - ND_INS_CPU_READ, ND_CAT_SYSTEM, ND_SET_CYRIX, 118, + ND_INS_CPU_READ, ND_CAT_SYSTEM, ND_SET_CYRIX, 119, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2954,9 +2969,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:176 Instruction:"CPU_WRITE" Encoding:"0x0F 0x3C"/"" + // Pos:177 Instruction:"CPU_WRITE" Encoding:"0x0F 0x3C"/"" { - ND_INS_CPU_WRITE, ND_CAT_SYSTEM, ND_SET_CYRIX, 119, + ND_INS_CPU_WRITE, ND_CAT_SYSTEM, ND_SET_CYRIX, 120, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2969,9 +2984,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:177 Instruction:"CQO" Encoding:"ds64 0x99"/"" + // Pos:178 Instruction:"CQO" Encoding:"ds64 0x99"/"" { - ND_INS_CQO, ND_CAT_CONVERT, ND_SET_I386, 120, + ND_INS_CQO, ND_CAT_CONVERT, ND_SET_I386, 121, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -2985,9 +3000,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:178 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM" + // Pos:179 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM" { - ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 121, + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 122, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, @@ -3001,9 +3016,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:179 Instruction:"CRC32 Gy,Eb" Encoding:"0x66 0xF2 0x0F 0x38 0xF0 /r"/"RM" + // Pos:180 Instruction:"CRC32 Gy,Eb" Encoding:"0x66 0xF2 0x0F 0x38 0xF0 /r"/"RM" { - ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 121, + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 122, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, @@ -3017,9 +3032,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:180 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM" + // Pos:181 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM" { - ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 121, + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 122, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, @@ -3033,9 +3048,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:181 Instruction:"CRC32 Gy,Ev" Encoding:"0x66 0xF2 0x0F 0x38 0xF1 /r"/"RM" + // Pos:182 Instruction:"CRC32 Gy,Ev" Encoding:"0x66 0xF2 0x0F 0x38 0xF1 /r"/"RM" { - ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 121, + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 122, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, @@ -3049,9 +3064,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:182 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM" + // Pos:183 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM" { - ND_INS_CVTDQ2PD, ND_CAT_CONVERT, ND_SET_SSE2, 122, + ND_INS_CVTDQ2PD, ND_CAT_CONVERT, ND_SET_SSE2, 123, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3065,9 +3080,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:183 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM" + // Pos:184 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM" { - ND_INS_CVTDQ2PS, ND_CAT_CONVERT, ND_SET_SSE2, 123, + ND_INS_CVTDQ2PS, ND_CAT_CONVERT, ND_SET_SSE2, 124, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3081,9 +3096,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:184 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM" + // Pos:185 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM" { - ND_INS_CVTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 124, + ND_INS_CVTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 125, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3097,9 +3112,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:185 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM" + // Pos:186 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM" { - ND_INS_CVTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 125, + ND_INS_CVTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 126, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3113,9 +3128,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:186 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM" + // Pos:187 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM" { - ND_INS_CVTPD2PS, ND_CAT_CONVERT, ND_SET_SSE2, 126, + ND_INS_CVTPD2PS, ND_CAT_CONVERT, ND_SET_SSE2, 127, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3129,9 +3144,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:187 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM" + // Pos:188 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM" { - ND_INS_CVTPI2PD, ND_CAT_CONVERT, ND_SET_SSE2, 127, + ND_INS_CVTPI2PD, ND_CAT_CONVERT, ND_SET_SSE2, 128, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3145,9 +3160,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:188 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM" + // Pos:189 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM" { - ND_INS_CVTPI2PS, ND_CAT_CONVERT, ND_SET_SSE, 128, + ND_INS_CVTPI2PS, ND_CAT_CONVERT, ND_SET_SSE, 129, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3161,9 +3176,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:189 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM" + // Pos:190 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM" { - ND_INS_CVTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 129, + ND_INS_CVTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 130, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3177,9 +3192,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:190 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM" + // Pos:191 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM" { - ND_INS_CVTPS2PD, ND_CAT_CONVERT, ND_SET_SSE2, 130, + ND_INS_CVTPS2PD, ND_CAT_CONVERT, ND_SET_SSE2, 131, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3193,9 +3208,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:191 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM" + // Pos:192 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM" { - ND_INS_CVTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 131, + ND_INS_CVTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 132, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3209,9 +3224,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:192 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM" + // Pos:193 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM" { - ND_INS_CVTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 132, + ND_INS_CVTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 133, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3225,9 +3240,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:193 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM" + // Pos:194 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM" { - ND_INS_CVTSD2SS, ND_CAT_CONVERT, ND_SET_SSE2, 133, + ND_INS_CVTSD2SS, ND_CAT_CONVERT, ND_SET_SSE2, 134, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3241,9 +3256,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:194 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM" + // Pos:195 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM" { - ND_INS_CVTSI2SD, ND_CAT_CONVERT, ND_SET_SSE2, 134, + ND_INS_CVTSI2SD, ND_CAT_CONVERT, ND_SET_SSE2, 135, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3257,9 +3272,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:195 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM" + // Pos:196 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM" { - ND_INS_CVTSI2SS, ND_CAT_CONVERT, ND_SET_SSE, 135, + ND_INS_CVTSI2SS, ND_CAT_CONVERT, ND_SET_SSE, 136, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3273,9 +3288,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:196 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM" + // Pos:197 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM" { - ND_INS_CVTSS2SD, ND_CAT_CONVERT, ND_SET_SSE2, 136, + ND_INS_CVTSS2SD, ND_CAT_CONVERT, ND_SET_SSE2, 137, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3289,9 +3304,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:197 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM" + // Pos:198 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM" { - ND_INS_CVTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 137, + ND_INS_CVTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 138, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3305,9 +3320,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:198 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM" + // Pos:199 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM" { - ND_INS_CVTTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 138, + ND_INS_CVTTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 139, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3321,9 +3336,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:199 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM" + // Pos:200 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM" { - ND_INS_CVTTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 139, + ND_INS_CVTTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 140, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3337,9 +3352,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:200 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM" + // Pos:201 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM" { - ND_INS_CVTTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 140, + ND_INS_CVTTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 141, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3353,9 +3368,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:201 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM" + // Pos:202 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM" { - ND_INS_CVTTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 141, + ND_INS_CVTTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 142, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3369,9 +3384,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:202 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM" + // Pos:203 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM" { - ND_INS_CVTTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 142, + ND_INS_CVTTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 143, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3385,9 +3400,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:203 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM" + // Pos:204 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM" { - ND_INS_CVTTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 143, + ND_INS_CVTTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 144, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3401,9 +3416,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:204 Instruction:"CWD" Encoding:"ds16 0x99"/"" + // Pos:205 Instruction:"CWD" Encoding:"ds16 0x99"/"" { - ND_INS_CWD, ND_CAT_CONVERT, ND_SET_I386, 144, + ND_INS_CWD, ND_CAT_CONVERT, ND_SET_I386, 145, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -3417,9 +3432,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:205 Instruction:"CWDE" Encoding:"ds32 0x98"/"" + // Pos:206 Instruction:"CWDE" Encoding:"ds32 0x98"/"" { - ND_INS_CWDE, ND_CAT_CONVERT, ND_SET_I386, 145, + ND_INS_CWDE, ND_CAT_CONVERT, ND_SET_I386, 146, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -3433,9 +3448,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:206 Instruction:"DAA" Encoding:"0x27"/"" + // Pos:207 Instruction:"DAA" Encoding:"0x27"/"" { - ND_INS_DAA, ND_CAT_DECIMAL, ND_SET_I86, 146, + ND_INS_DAA, ND_CAT_DECIMAL, ND_SET_I86, 147, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3449,9 +3464,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:207 Instruction:"DAS" Encoding:"0x2F"/"" + // Pos:208 Instruction:"DAS" Encoding:"0x2F"/"" { - ND_INS_DAS, ND_CAT_DECIMAL, ND_SET_I86, 147, + ND_INS_DAS, ND_CAT_DECIMAL, ND_SET_I86, 148, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3465,9 +3480,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:208 Instruction:"DEC Zv" Encoding:"0x48"/"O" + // Pos:209 Instruction:"DEC Zv" Encoding:"0x48"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3481,9 +3496,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:209 Instruction:"DEC Zv" Encoding:"0x49"/"O" + // Pos:210 Instruction:"DEC Zv" Encoding:"0x49"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3497,9 +3512,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:210 Instruction:"DEC Zv" Encoding:"0x4A"/"O" + // Pos:211 Instruction:"DEC Zv" Encoding:"0x4A"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3513,9 +3528,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:211 Instruction:"DEC Zv" Encoding:"0x4B"/"O" + // Pos:212 Instruction:"DEC Zv" Encoding:"0x4B"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3529,9 +3544,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:212 Instruction:"DEC Zv" Encoding:"0x4C"/"O" + // Pos:213 Instruction:"DEC Zv" Encoding:"0x4C"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3545,9 +3560,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:213 Instruction:"DEC Zv" Encoding:"0x4D"/"O" + // Pos:214 Instruction:"DEC Zv" Encoding:"0x4D"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3561,9 +3576,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:214 Instruction:"DEC Zv" Encoding:"0x4E"/"O" + // Pos:215 Instruction:"DEC Zv" Encoding:"0x4E"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3577,9 +3592,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:215 Instruction:"DEC Zv" Encoding:"0x4F"/"O" + // Pos:216 Instruction:"DEC Zv" Encoding:"0x4F"/"O" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -3593,9 +3608,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:216 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M" + // Pos:217 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 149, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -3609,9 +3624,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:217 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M" + // Pos:218 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M" { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 149, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -3625,9 +3640,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:218 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M" + // Pos:219 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M" { - ND_INS_DELAY, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 149, + ND_INS_DELAY, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 150, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -3640,9 +3655,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:219 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M" + // Pos:220 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M" { - ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 150, + ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 151, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -3659,9 +3674,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:220 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M" + // Pos:221 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M" { - ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 150, + ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 151, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -3677,9 +3692,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:221 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM" + // Pos:222 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM" { - ND_INS_DIVPD, ND_CAT_SSE, ND_SET_SSE2, 151, + ND_INS_DIVPD, ND_CAT_SSE, ND_SET_SSE2, 152, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3693,9 +3708,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:222 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM" + // Pos:223 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM" { - ND_INS_DIVPS, ND_CAT_SSE, ND_SET_SSE, 152, + ND_INS_DIVPS, ND_CAT_SSE, ND_SET_SSE, 153, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3709,9 +3724,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:223 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM" + // Pos:224 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM" { - ND_INS_DIVSD, ND_CAT_SSE, ND_SET_SSE2, 153, + ND_INS_DIVSD, ND_CAT_SSE, ND_SET_SSE2, 154, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -3725,9 +3740,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:224 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM" + // Pos:225 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM" { - ND_INS_DIVSS, ND_CAT_SSE, ND_SET_SSE, 154, + ND_INS_DIVSS, ND_CAT_SSE, ND_SET_SSE, 155, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -3741,9 +3756,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:225 Instruction:"DMINT" Encoding:"0x0F 0x39"/"" + // Pos:226 Instruction:"DMINT" Encoding:"0x0F 0x39"/"" { - ND_INS_DMINT, ND_CAT_SYSTEM, ND_SET_CYRIX, 155, + ND_INS_DMINT, ND_CAT_SYSTEM, ND_SET_CYRIX, 156, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -3756,9 +3771,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:226 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI" + // Pos:227 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI" { - ND_INS_DPPD, ND_CAT_SSE, ND_SET_SSE4, 156, + ND_INS_DPPD, ND_CAT_SSE, ND_SET_SSE4, 157, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -3773,9 +3788,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:227 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI" + // Pos:228 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI" { - ND_INS_DPPS, ND_CAT_SSE, ND_SET_SSE4, 157, + ND_INS_DPPS, ND_CAT_SSE, ND_SET_SSE4, 158, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -3790,9 +3805,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:228 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/"" + // Pos:229 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/"" { - ND_INS_EMMS, ND_CAT_MMX, ND_SET_MMX, 158, + ND_INS_EMMS, ND_CAT_MMX, ND_SET_MMX, 159, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MMX, @@ -3805,9 +3820,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:229 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/"" + // Pos:230 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/"" { - ND_INS_ENCLS, ND_CAT_SGX, ND_SET_SGX, 159, + ND_INS_ENCLS, ND_CAT_SGX, ND_SET_SGX, 160, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, @@ -3823,9 +3838,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:230 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/"" + // Pos:231 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/"" { - ND_INS_ENCLU, ND_CAT_SGX, ND_SET_SGX, 160, + ND_INS_ENCLU, ND_CAT_SGX, ND_SET_SGX, 161, 0, ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, @@ -3841,9 +3856,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:231 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/"" + // Pos:232 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/"" { - ND_INS_ENCLV, ND_CAT_SGX, ND_SET_SGX, 161, + ND_INS_ENCLV, ND_CAT_SGX, ND_SET_SGX, 162, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, @@ -3859,9 +3874,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:232 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFA /r:reg"/"RM" + // Pos:233 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFA /r:reg"/"RM" { - ND_INS_ENCODEKEY128, ND_CAT_AESKL, ND_SET_KL, 162, + ND_INS_ENCODEKEY128, ND_CAT_AESKL, ND_SET_KL, 163, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, @@ -3879,9 +3894,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:233 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFB /r:reg"/"RM" + // Pos:234 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFB /r:reg"/"RM" { - ND_INS_ENCODEKEY256, ND_CAT_AESKL, ND_SET_KL, 163, + ND_INS_ENCODEKEY256, ND_CAT_AESKL, ND_SET_KL, 164, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, @@ -3898,9 +3913,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:234 Instruction:"ENDBR32" Encoding:"cet a0xF3 0x0F 0x1E /0xFB"/"" + // Pos:235 Instruction:"ENDBR32" Encoding:"cet a0xF3 0x0F 0x1E /0xFB"/"" { - ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 164, + ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 165, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, @@ -3913,9 +3928,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:235 Instruction:"ENDBR64" Encoding:"cet a0xF3 0x0F 0x1E /0xFA"/"" + // Pos:236 Instruction:"ENDBR64" Encoding:"cet a0xF3 0x0F 0x1E /0xFA"/"" { - ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 165, + ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 166, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, @@ -3928,9 +3943,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:236 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M" + // Pos:237 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M" { - ND_INS_ENQCMD, ND_CAT_ENQCMD, ND_SET_ENQCMD, 166, + ND_INS_ENQCMD, ND_CAT_ENQCMD, ND_SET_ENQCMD, 167, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, @@ -3945,9 +3960,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:237 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M" + // Pos:238 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M" { - ND_INS_ENQCMDS, ND_CAT_ENQCMD, ND_SET_ENQCMD, 167, + ND_INS_ENQCMDS, ND_CAT_ENQCMD, ND_SET_ENQCMD, 168, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, @@ -3962,9 +3977,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:238 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II" + // Pos:239 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II" { - ND_INS_ENTER, ND_CAT_MISC, ND_SET_I186, 168, + ND_INS_ENTER, ND_CAT_MISC, ND_SET_I186, 169, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -3981,9 +3996,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:239 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI" + // Pos:240 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI" { - ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 169, + ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 170, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -3998,9 +4013,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:240 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII" + // Pos:241 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII" { - ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 170, + ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 171, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, @@ -4015,9 +4030,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:241 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM" + // Pos:242 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM" { - ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 170, + ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 171, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, @@ -4031,9 +4046,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:242 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/"" + // Pos:243 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/"" { - ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 171, + ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 172, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4046,9 +4061,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:243 Instruction:"FABS" Encoding:"0xD9 /0xE1"/"" + // Pos:244 Instruction:"FABS" Encoding:"0xD9 /0xE1"/"" { - ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 172, + ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 173, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -4061,9 +4076,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:244 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M" + // Pos:245 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M" { - ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 173, + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 174, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4078,9 +4093,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:245 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M" + // Pos:246 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M" { - ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 173, + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 174, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4095,9 +4110,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:246 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M" + // Pos:247 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M" { - ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 173, + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 174, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4112,9 +4127,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:247 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M" + // Pos:248 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M" { - ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 173, + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 174, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4129,9 +4144,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:248 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M" + // Pos:249 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M" { - ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 174, + ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 175, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4146,9 +4161,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:249 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M" + // Pos:250 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M" { - ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 175, + ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 176, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4163,9 +4178,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:250 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M" + // Pos:251 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M" { - ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 176, + ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 177, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4180,9 +4195,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:251 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/"" + // Pos:252 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/"" { - ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 177, + ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 178, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -4195,9 +4210,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:252 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M" + // Pos:253 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M" { - ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 178, + ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 179, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4213,9 +4228,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:253 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M" + // Pos:254 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M" { - ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 179, + ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 180, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4231,9 +4246,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:254 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M" + // Pos:255 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M" { - ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 180, + ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 181, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4249,9 +4264,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:255 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M" + // Pos:256 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M" { - ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 181, + ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 182, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4267,9 +4282,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:256 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M" + // Pos:257 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M" { - ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 182, + ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 183, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4285,9 +4300,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:257 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M" + // Pos:258 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M" { - ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 183, + ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 184, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4303,9 +4318,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:258 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M" + // Pos:259 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M" { - ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 184, + ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 185, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4321,9 +4336,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:259 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M" + // Pos:260 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M" { - ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 185, + ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 186, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4339,9 +4354,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:260 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M" + // Pos:261 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M" { - ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 186, + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 187, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4356,9 +4371,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:261 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M" + // Pos:262 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M" { - ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 186, + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 187, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4373,9 +4388,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:262 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M" + // Pos:263 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M" { - ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 186, + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 187, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4390,9 +4405,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:263 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M" + // Pos:264 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M" { - ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 186, + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 187, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4407,9 +4422,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:264 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M" + // Pos:265 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M" { - ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 187, + ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 188, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4425,9 +4440,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:265 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M" + // Pos:266 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M" { - ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 188, + ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 189, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4443,9 +4458,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:266 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M" + // Pos:267 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M" { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 190, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4460,9 +4475,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:267 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M" + // Pos:268 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M" { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 190, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4477,9 +4492,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:268 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M" + // Pos:269 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M" { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 190, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4494,9 +4509,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:269 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M" + // Pos:270 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M" { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 190, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4511,9 +4526,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:270 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M" + // Pos:271 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M" { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 190, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4528,9 +4543,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:271 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/"" + // Pos:272 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/"" { - ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 190, + ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 191, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -4543,9 +4558,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:272 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/"" + // Pos:273 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/"" { - ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 191, + ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 192, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, @@ -4558,9 +4573,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:273 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/"" + // Pos:274 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/"" { - ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 192, + ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 193, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -4573,9 +4588,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:274 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M" + // Pos:275 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M" { - ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 194, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4590,9 +4605,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:275 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M" + // Pos:276 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M" { - ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 194, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4607,9 +4622,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:276 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M" + // Pos:277 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M" { - ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 194, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4624,9 +4639,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:277 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M" + // Pos:278 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M" { - ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 194, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4641,9 +4656,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:278 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M" + // Pos:279 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M" { - ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 194, + ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 195, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4658,9 +4673,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:279 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M" + // Pos:280 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M" { - ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 196, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4675,9 +4690,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:280 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M" + // Pos:281 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M" { - ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 196, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4692,9 +4707,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:281 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M" + // Pos:282 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M" { - ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 196, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4709,9 +4724,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:282 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M" + // Pos:283 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M" { - ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 196, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4726,9 +4741,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:283 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M" + // Pos:284 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M" { - ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 196, + ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 197, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4743,9 +4758,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:284 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/"" + // Pos:285 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/"" { - ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 197, + ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 198, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_3DNOW, @@ -4758,9 +4773,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:285 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M" + // Pos:286 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M" { - ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 198, + ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 199, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -4774,9 +4789,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:286 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M" + // Pos:287 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M" { - ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 199, + ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 200, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -4790,9 +4805,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:287 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M" + // Pos:288 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M" { - ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 200, + ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 201, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4807,9 +4822,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:288 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M" + // Pos:289 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M" { - ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 200, + ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 201, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4824,9 +4839,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:289 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M" + // Pos:290 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M" { - ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 201, + ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 202, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -4841,9 +4856,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:290 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M" + // Pos:291 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M" { - ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 201, + ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 202, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -4858,9 +4873,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:291 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M" + // Pos:292 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M" { - ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 202, + ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 203, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -4875,9 +4890,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:292 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M" + // Pos:293 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M" { - ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 202, + ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 203, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -4892,9 +4907,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:293 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M" + // Pos:294 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M" { - ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 203, + ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 204, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4909,9 +4924,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:294 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M" + // Pos:295 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M" { - ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 203, + ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 204, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4926,9 +4941,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:295 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M" + // Pos:296 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M" { - ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 204, + ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 205, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4943,9 +4958,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:296 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M" + // Pos:297 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M" { - ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 204, + ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 205, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4960,9 +4975,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:297 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M" + // Pos:298 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M" { - ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 205, + ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 206, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4977,9 +4992,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:298 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M" + // Pos:299 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M" { - ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 205, + ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 206, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -4994,9 +5009,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:299 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M" + // Pos:300 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M" { - ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 205, + ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 206, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5011,9 +5026,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:300 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M" + // Pos:301 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M" { - ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 206, + ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 207, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5028,9 +5043,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:301 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M" + // Pos:302 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M" { - ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 206, + ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 207, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5045,9 +5060,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:302 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/"" + // Pos:303 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/"" { - ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 207, + ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 208, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -5060,9 +5075,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:303 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M" + // Pos:304 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M" { - ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 208, + ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 209, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5077,9 +5092,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:304 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M" + // Pos:305 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M" { - ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 208, + ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 209, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5094,9 +5109,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:305 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M" + // Pos:306 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M" { - ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 209, + ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 210, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5111,9 +5126,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:306 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M" + // Pos:307 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M" { - ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 209, + ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 210, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5128,9 +5143,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:307 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M" + // Pos:308 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M" { - ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 209, + ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 210, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5145,9 +5160,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:308 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M" + // Pos:309 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M" { - ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 210, + ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -5162,9 +5177,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:309 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M" + // Pos:310 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M" { - ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 210, + ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -5179,9 +5194,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:310 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M" + // Pos:311 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M" { - ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 210, + ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -5196,9 +5211,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:311 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M" + // Pos:312 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M" { - ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 211, + ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 212, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5213,9 +5228,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:312 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M" + // Pos:313 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M" { - ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 211, + ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 212, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5230,9 +5245,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:313 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M" + // Pos:314 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M" { - ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 212, + ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 213, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5247,9 +5262,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:314 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M" + // Pos:315 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M" { - ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 212, + ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 213, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5264,9 +5279,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:315 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M" + // Pos:316 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M" { - ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 214, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5281,9 +5296,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:316 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M" + // Pos:317 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M" { - ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 214, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5298,9 +5313,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:317 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M" + // Pos:318 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M" { - ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 214, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5315,9 +5330,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:318 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M" + // Pos:319 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M" { - ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 214, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5332,9 +5347,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:319 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/"" + // Pos:320 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/"" { - ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 214, + ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 215, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5347,9 +5362,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:320 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M" + // Pos:321 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M" { - ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 215, + ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 216, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5364,9 +5379,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:321 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M" + // Pos:322 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M" { - ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 216, + ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 217, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -5380,9 +5395,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:322 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/"" + // Pos:323 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/"" { - ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 217, + ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 218, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5395,9 +5410,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:323 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/"" + // Pos:324 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/"" { - ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 218, + ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 219, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5410,9 +5425,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:324 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/"" + // Pos:325 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/"" { - ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 219, + ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 220, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5425,9 +5440,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:325 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/"" + // Pos:326 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/"" { - ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 220, + ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 221, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5440,9 +5455,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:326 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/"" + // Pos:327 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/"" { - ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 221, + ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 222, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5455,9 +5470,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:327 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/"" + // Pos:328 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/"" { - ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 222, + ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 223, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5470,9 +5485,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:328 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M" + // Pos:329 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M" { - ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 223, + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 224, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5487,9 +5502,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:329 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M" + // Pos:330 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M" { - ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 223, + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 224, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5504,9 +5519,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:330 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M" + // Pos:331 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M" { - ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 223, + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 224, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5521,9 +5536,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:331 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M" + // Pos:332 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M" { - ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 223, + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 224, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5538,9 +5553,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:332 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M" + // Pos:333 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M" { - ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 224, + ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 225, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5555,9 +5570,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:333 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/"" + // Pos:334 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/"" { - ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 225, + ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 226, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5570,9 +5585,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:334 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/"" + // Pos:335 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/"" { - ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 226, + ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 227, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5585,9 +5600,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:335 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/"" + // Pos:336 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/"" { - ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 227, + ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 228, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, @@ -5602,9 +5617,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:336 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/"" + // Pos:337 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/"" { - ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 228, + ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 229, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5617,9 +5632,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:337 Instruction:"FNOP" Encoding:"0xDB /0xE0"/"" + // Pos:338 Instruction:"FNOP" Encoding:"0xDB /0xE0"/"" { - ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 228, + ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 229, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5632,9 +5647,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:338 Instruction:"FNOP" Encoding:"0xDB /0xE4"/"" + // Pos:339 Instruction:"FNOP" Encoding:"0xDB /0xE4"/"" { - ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 228, + ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 229, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5647,9 +5662,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:339 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M" + // Pos:340 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M" { - ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 229, + ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 230, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, @@ -5665,9 +5680,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:340 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M" + // Pos:341 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M" { - ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 230, + ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 231, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5682,9 +5697,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:341 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M" + // Pos:342 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M" { - ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 231, + ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 232, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5698,9 +5713,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:342 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M" + // Pos:343 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M" { - ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 232, + ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 233, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5714,9 +5729,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:343 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/"" + // Pos:344 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/"" { - ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 232, + ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 233, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5730,9 +5745,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:344 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/"" + // Pos:345 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/"" { - ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 233, + ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 234, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5745,9 +5760,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:345 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/"" + // Pos:346 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/"" { - ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 234, + ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 235, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -5760,9 +5775,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:346 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/"" + // Pos:347 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/"" { - ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 235, + ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 236, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -5775,9 +5790,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:347 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/"" + // Pos:348 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/"" { - ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 237, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, @@ -5790,9 +5805,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:348 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/"" + // Pos:349 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/"" { - ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 237, + ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 238, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5805,9 +5820,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:349 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/"" + // Pos:350 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/"" { - ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 238, + ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 239, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5820,9 +5835,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:350 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M" + // Pos:351 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M" { - ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 239, + ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 240, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -5836,9 +5851,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:351 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/"" + // Pos:352 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/"" { - ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 240, + ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 241, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5851,9 +5866,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:352 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/"" + // Pos:353 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/"" { - ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 241, + ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 242, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, @@ -5866,9 +5881,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:353 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/"" + // Pos:354 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/"" { - ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 242, + ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 243, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, @@ -5881,9 +5896,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:354 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/"" + // Pos:355 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/"" { - ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 243, + ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 244, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5896,9 +5911,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:355 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M" + // Pos:356 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M" { - ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 244, + ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 245, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5913,9 +5928,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:356 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M" + // Pos:357 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M" { - ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 244, + ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 245, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5930,9 +5945,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:357 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M" + // Pos:358 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M" { - ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 244, + ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 245, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5947,9 +5962,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:358 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/"" + // Pos:359 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/"" { - ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 245, + ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 246, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -5962,9 +5977,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:359 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M" + // Pos:360 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M" { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 247, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5979,9 +5994,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:360 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M" + // Pos:361 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M" { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 247, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -5996,9 +6011,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:361 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M" + // Pos:362 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M" { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 247, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6013,9 +6028,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:362 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M" + // Pos:363 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M" { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 247, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6030,9 +6045,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:363 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M" + // Pos:364 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M" { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 247, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6047,9 +6062,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:364 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M" + // Pos:365 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M" { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 247, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6064,9 +6079,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:365 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M" + // Pos:366 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M" { - ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 247, + ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 248, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -6081,9 +6096,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:366 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/"" + // Pos:367 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/"" { - ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 248, + ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 249, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, @@ -6096,9 +6111,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:367 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M" + // Pos:368 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M" { - ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 249, + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 250, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6113,9 +6128,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:368 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M" + // Pos:369 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M" { - ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 249, + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 250, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6130,9 +6145,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:369 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M" + // Pos:370 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M" { - ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 249, + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 250, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6147,9 +6162,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:370 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M" + // Pos:371 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M" { - ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 249, + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 250, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6164,9 +6179,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:371 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M" + // Pos:372 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M" { - ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 250, + ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 251, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6181,9 +6196,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:372 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M" + // Pos:373 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M" { - ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 251, + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 252, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6198,9 +6213,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:373 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M" + // Pos:374 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M" { - ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 251, + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 252, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6215,9 +6230,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:374 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M" + // Pos:375 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M" { - ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 251, + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 252, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6232,9 +6247,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:375 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M" + // Pos:376 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M" { - ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 251, + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 252, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6249,9 +6264,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:376 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M" + // Pos:377 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M" { - ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 252, + ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 253, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6266,9 +6281,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:377 Instruction:"FTST" Encoding:"0xD9 /0xE4"/"" + // Pos:378 Instruction:"FTST" Encoding:"0xD9 /0xE4"/"" { - ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 253, + ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 254, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -6281,9 +6296,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:378 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M" + // Pos:379 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M" { - ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 254, + ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 255, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -6298,9 +6313,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:379 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M" + // Pos:380 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M" { - ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 255, + ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 256, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -6316,9 +6331,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:380 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M" + // Pos:381 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M" { - ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 256, + ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 257, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, @@ -6334,9 +6349,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:381 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M" + // Pos:382 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M" { - ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 257, + ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 258, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -6351,9 +6366,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:382 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/"" + // Pos:383 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/"" { - ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 258, + ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 259, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -6366,9 +6381,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:383 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/"" + // Pos:384 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/"" { - ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 259, + ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 260, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, @@ -6381,9 +6396,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:384 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M" + // Pos:385 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M" { - ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 260, + ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 261, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -6398,9 +6413,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:385 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M" + // Pos:386 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M" { - ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 260, + ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 261, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -6415,9 +6430,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:386 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M" + // Pos:387 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M" { - ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 260, + ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 261, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, @@ -6432,9 +6447,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:387 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M" + // Pos:388 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M" { - ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 261, + ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 262, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, @@ -6448,9 +6463,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:388 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M" + // Pos:389 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M" { - ND_INS_FXRSTOR64, ND_CAT_SSE, ND_SET_FXSAVE, 262, + ND_INS_FXRSTOR64, ND_CAT_SSE, ND_SET_FXSAVE, 263, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, @@ -6464,9 +6479,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:389 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M" + // Pos:390 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M" { - ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 263, + ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 264, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, @@ -6480,9 +6495,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:390 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M" + // Pos:391 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M" { - ND_INS_FXSAVE64, ND_CAT_SSE, ND_SET_FXSAVE, 264, + ND_INS_FXSAVE64, ND_CAT_SSE, ND_SET_FXSAVE, 265, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, @@ -6496,9 +6511,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:391 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/"" + // Pos:392 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/"" { - ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 265, + ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 266, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6511,9 +6526,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:392 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/"" + // Pos:393 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/"" { - ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 266, + ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 267, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6526,9 +6541,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:393 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/"" + // Pos:394 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/"" { - ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 267, + ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, @@ -6541,9 +6556,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:394 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/"" + // Pos:395 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/"" { - ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 268, + ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 269, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SMX, @@ -6557,9 +6572,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:395 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI" + // Pos:396 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI" { - ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 269, + ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 270, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -6574,9 +6589,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:396 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI" + // Pos:397 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI" { - ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 270, + ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 271, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -6591,9 +6606,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:397 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM" + // Pos:398 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM" { - ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 271, + ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 272, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -6607,9 +6622,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:398 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM" + // Pos:399 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM" { - ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 272, + ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 273, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -6623,9 +6638,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:399 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM" + // Pos:400 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM" { - ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 273, + ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 274, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -6639,9 +6654,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:400 Instruction:"HLT" Encoding:"0xF4"/"" + // Pos:401 Instruction:"HLT" Encoding:"0xF4"/"" { - ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 274, + ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 275, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -6654,9 +6669,25 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:401 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM" + // Pos:402 Instruction:"HRESET Ib" Encoding:"0xF3 0x0F 0x3A 0xF0 /0xC0 ib"/"I" + { + ND_INS_HRESET, ND_CAT_HRESET, ND_SET_HRESET, 276, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_HRESET, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + }, + }, + + // Pos:403 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM" { - ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 275, + ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 277, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -6670,9 +6701,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:402 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM" + // Pos:404 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM" { - ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 276, + ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 278, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -6686,9 +6717,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:403 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M" + // Pos:405 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M" { - ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 277, + ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 279, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6705,9 +6736,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:404 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M" + // Pos:406 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M" { - ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 277, + ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 279, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6723,9 +6754,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:405 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM" + // Pos:407 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM" { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 278, + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 280, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6740,9 +6771,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:406 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI" + // Pos:408 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI" { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 278, + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 280, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6758,9 +6789,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:407 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI" + // Pos:409 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI" { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 278, + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 280, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6776,9 +6807,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:408 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M" + // Pos:410 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M" { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 278, + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 280, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6794,9 +6825,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:409 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M" + // Pos:411 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M" { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 278, + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 280, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -6812,9 +6843,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:410 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I" + // Pos:412 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I" { - ND_INS_IN, ND_CAT_IO, ND_SET_I86, 279, + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 281, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -6829,9 +6860,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:411 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I" + // Pos:413 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I" { - ND_INS_IN, ND_CAT_IO, ND_SET_I86, 279, + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 281, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -6846,9 +6877,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:412 Instruction:"IN AL,DX" Encoding:"0xEC"/"" + // Pos:414 Instruction:"IN AL,DX" Encoding:"0xEC"/"" { - ND_INS_IN, ND_CAT_IO, ND_SET_I86, 279, + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 281, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -6863,9 +6894,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:413 Instruction:"IN eAX,DX" Encoding:"0xED"/"" + // Pos:415 Instruction:"IN eAX,DX" Encoding:"0xED"/"" { - ND_INS_IN, ND_CAT_IO, ND_SET_I86, 279, + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 281, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -6880,9 +6911,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:414 Instruction:"INC Zv" Encoding:"0x40"/"O" + // Pos:416 Instruction:"INC Zv" Encoding:"0x40"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -6896,9 +6927,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:415 Instruction:"INC Zv" Encoding:"0x41"/"O" + // Pos:417 Instruction:"INC Zv" Encoding:"0x41"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -6912,9 +6943,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:416 Instruction:"INC Zv" Encoding:"0x42"/"O" + // Pos:418 Instruction:"INC Zv" Encoding:"0x42"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -6928,9 +6959,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:417 Instruction:"INC Zv" Encoding:"0x43"/"O" + // Pos:419 Instruction:"INC Zv" Encoding:"0x43"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -6944,9 +6975,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:418 Instruction:"INC Zv" Encoding:"0x44"/"O" + // Pos:420 Instruction:"INC Zv" Encoding:"0x44"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -6960,9 +6991,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:419 Instruction:"INC Zv" Encoding:"0x45"/"O" + // Pos:421 Instruction:"INC Zv" Encoding:"0x45"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -6976,9 +7007,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:420 Instruction:"INC Zv" Encoding:"0x46"/"O" + // Pos:422 Instruction:"INC Zv" Encoding:"0x46"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -6992,9 +7023,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:421 Instruction:"INC Zv" Encoding:"0x47"/"O" + // Pos:423 Instruction:"INC Zv" Encoding:"0x47"/"O" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -7008,9 +7039,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:422 Instruction:"INC Eb" Encoding:"0xFE /0"/"M" + // Pos:424 Instruction:"INC Eb" Encoding:"0xFE /0"/"M" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 282, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -7024,9 +7055,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:423 Instruction:"INC Ev" Encoding:"0xFF /0"/"M" + // Pos:425 Instruction:"INC Ev" Encoding:"0xFF /0"/"M" { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 282, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -7040,9 +7071,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:424 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M" + // Pos:426 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M" { - ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 281, + ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 283, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -7057,9 +7088,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:425 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M" + // Pos:427 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M" { - ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 282, + ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 284, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -7074,9 +7105,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:426 Instruction:"INSB Yb,DX" Encoding:"0x6C"/"" + // Pos:428 Instruction:"INSB Yb,DX" Encoding:"0x6C"/"" { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 283, + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 285, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7092,9 +7123,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:427 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/"" + // Pos:429 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/"" { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 283, + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 285, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7111,9 +7142,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:428 Instruction:"INSD Yz,DX" Encoding:"0x6D"/"" + // Pos:430 Instruction:"INSD Yz,DX" Encoding:"0x6D"/"" { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 284, + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 286, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7129,9 +7160,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:429 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/"" + // Pos:431 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/"" { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 284, + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 286, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7148,9 +7179,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:430 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI" + // Pos:432 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI" { - ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 285, + ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 287, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -7165,9 +7196,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:431 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI" + // Pos:433 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI" { - ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 285, + ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 287, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -7182,9 +7213,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:432 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII" + // Pos:434 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII" { - ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 286, + ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 288, 0, ND_MOD_ANY, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, @@ -7200,9 +7231,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:433 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM" + // Pos:435 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM" { - ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 286, + ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 288, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, @@ -7216,9 +7247,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:434 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/"" + // Pos:436 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/"" { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 287, + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 289, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7234,9 +7265,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:435 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/"" + // Pos:437 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/"" { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 287, + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 289, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7253,9 +7284,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:436 Instruction:"INT Ib" Encoding:"0xCD ib"/"I" + // Pos:438 Instruction:"INT Ib" Encoding:"0xCD ib"/"I" { - ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 288, + ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 290, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7273,9 +7304,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:437 Instruction:"INT1" Encoding:"0xF1"/"" + // Pos:439 Instruction:"INT1" Encoding:"0xF1"/"" { - ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 289, + ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 291, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7291,9 +7322,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:438 Instruction:"INT3" Encoding:"0xCC"/"" + // Pos:440 Instruction:"INT3" Encoding:"0xCC"/"" { - ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 290, + ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 292, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7310,9 +7341,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:439 Instruction:"INTO" Encoding:"0xCE"/"" + // Pos:441 Instruction:"INTO" Encoding:"0xCE"/"" { - ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 291, + ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 293, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, @@ -7329,9 +7360,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:440 Instruction:"INVD" Encoding:"0x0F 0x08"/"" + // Pos:442 Instruction:"INVD" Encoding:"0x0F 0x08"/"" { - ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 292, + ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 294, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -7344,9 +7375,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:441 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM" + // Pos:443 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM" { - ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 293, + ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 295, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, @@ -7361,9 +7392,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:442 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M" + // Pos:444 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M" { - ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 294, + ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 296, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, @@ -7376,9 +7407,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:443 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/"" + // Pos:445 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/"" { - ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 295, + ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 297, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -7392,9 +7423,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:444 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/"" + // Pos:446 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/"" { - ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 296, + ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 298, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, @@ -7409,9 +7440,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:445 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM" + // Pos:447 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM" { - ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 297, + ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 299, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_INVPCID, @@ -7425,9 +7456,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:446 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM" + // Pos:448 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM" { - ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 298, + ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 300, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, @@ -7442,9 +7473,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:447 Instruction:"IRETD" Encoding:"ds32 0xCF"/"" + // Pos:449 Instruction:"IRETD" Encoding:"ds32 0xCF"/"" { - ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 299, + ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 301, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -7461,9 +7492,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:448 Instruction:"IRETQ" Encoding:"ds64 0xCF"/"" + // Pos:450 Instruction:"IRETQ" Encoding:"ds64 0xCF"/"" { - ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 300, + ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 302, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -7480,9 +7511,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:449 Instruction:"IRETW" Encoding:"ds16 0xCF"/"" + // Pos:451 Instruction:"IRETW" Encoding:"ds16 0xCF"/"" { - ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 301, + ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 303, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -7499,9 +7530,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:450 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D" + // Pos:452 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7516,9 +7547,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:451 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D" + // Pos:453 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7533,9 +7564,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:452 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D" + // Pos:454 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7550,9 +7581,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:453 Instruction:"JC Jb" Encoding:"0x72 cb"/"D" + // Pos:455 Instruction:"JC Jb" Encoding:"0x72 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7567,9 +7598,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:454 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D" + // Pos:456 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D" { - ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 304, + ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 306, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -7584,9 +7615,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:455 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D" + // Pos:457 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D" { - ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 305, + ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 307, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -7601,9 +7632,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:456 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D" + // Pos:458 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7618,9 +7649,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:457 Instruction:"JL Jb" Encoding:"0x7C cb"/"D" + // Pos:459 Instruction:"JL Jb" Encoding:"0x7C cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7635,9 +7666,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:458 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D" + // Pos:460 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7652,9 +7683,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:459 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D" + // Pos:461 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7669,9 +7700,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:460 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D" + // Pos:462 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D" { - ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 308, + ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 310, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -7685,9 +7716,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:461 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D" + // Pos:463 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D" { - ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 308, + ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 310, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -7701,9 +7732,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:462 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M" + // Pos:464 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M" { - ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 308, + ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 310, ND_PREF_BND|ND_PREF_DNT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, @@ -7717,9 +7748,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:463 Instruction:"JMPE Ev" Encoding:"0x0F 0x00 /6"/"M" + // Pos:465 Instruction:"JMPE Ev" Encoding:"0x0F 0x00 /6"/"M" { - ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 309, + ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 311, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -7733,9 +7764,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:464 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D" + // Pos:466 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D" { - ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 309, + ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 311, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -7749,9 +7780,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:465 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D" + // Pos:467 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D" { - ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 310, + ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 312, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -7766,9 +7797,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:466 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M" + // Pos:468 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M" { - ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 310, + ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 312, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, @@ -7783,9 +7814,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:467 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D" + // Pos:469 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 311, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7800,9 +7831,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:468 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D" + // Pos:470 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 311, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7817,9 +7848,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:469 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D" + // Pos:471 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 314, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7834,9 +7865,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:470 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D" + // Pos:472 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 314, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7851,9 +7882,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:471 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D" + // Pos:473 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 315, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7868,9 +7899,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:472 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D" + // Pos:474 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 315, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7885,9 +7916,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:473 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D" + // Pos:475 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 314, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 316, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7902,9 +7933,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:474 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D" + // Pos:476 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 314, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 316, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7919,9 +7950,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:475 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D" + // Pos:477 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 315, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 317, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7936,9 +7967,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:476 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D" + // Pos:478 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 315, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 317, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7953,9 +7984,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:477 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D" + // Pos:479 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 316, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 318, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7970,9 +8001,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:478 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D" + // Pos:480 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 316, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 318, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -7987,9 +8018,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:479 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D" + // Pos:481 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 317, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 319, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8004,9 +8035,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:480 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D" + // Pos:482 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 317, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 319, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8021,9 +8052,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:481 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D" + // Pos:483 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 318, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 320, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8038,9 +8069,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:482 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D" + // Pos:484 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 318, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 320, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8055,9 +8086,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:483 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D" + // Pos:485 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 319, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 321, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8072,9 +8103,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:484 Instruction:"JO Jb" Encoding:"0x70 cb"/"D" + // Pos:486 Instruction:"JO Jb" Encoding:"0x70 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 319, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 321, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8089,9 +8120,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:485 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D" + // Pos:487 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 320, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 322, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8106,9 +8137,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:486 Instruction:"JP Jb" Encoding:"0x7A cb"/"D" + // Pos:488 Instruction:"JP Jb" Encoding:"0x7A cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 320, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 322, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8123,9 +8154,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:487 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D" + // Pos:489 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D" { - ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 321, + ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 323, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -8140,9 +8171,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:488 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D" + // Pos:490 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 322, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 324, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8157,9 +8188,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:489 Instruction:"JS Jb" Encoding:"0x78 cb"/"D" + // Pos:491 Instruction:"JS Jb" Encoding:"0x78 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 322, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 324, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8174,9 +8205,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:490 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D" + // Pos:492 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 323, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 325, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8191,9 +8222,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:491 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D" + // Pos:493 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D" { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 323, + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 325, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, @@ -8208,9 +8239,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:492 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM" + // Pos:494 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM" { - ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 324, + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8225,9 +8256,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:493 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM" + // Pos:495 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM" { - ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 325, + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 327, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8242,9 +8273,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:494 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM" + // Pos:496 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM" { - ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 326, + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 328, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8259,9 +8290,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:495 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM" + // Pos:497 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM" { - ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 327, + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 329, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8276,9 +8307,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:496 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM" + // Pos:498 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM" { - ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 330, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8293,9 +8324,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:497 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM" + // Pos:499 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM" { - ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 329, + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 331, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8310,9 +8341,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:498 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM" + // Pos:500 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM" { - ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 330, + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 332, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8327,9 +8358,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:499 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM" + // Pos:501 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM" { - ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 331, + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 333, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8344,9 +8375,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:500 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM" + // Pos:502 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM" { - ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 332, + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 334, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8361,9 +8392,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:501 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM" + // Pos:503 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM" { - ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 333, + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 335, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8378,9 +8409,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:502 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM" + // Pos:504 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM" { - ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 334, + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 336, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8395,9 +8426,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:503 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM" + // Pos:505 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM" { - ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 335, + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 337, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8412,9 +8443,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:504 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM" + // Pos:506 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM" { - ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 336, + ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 338, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -8428,9 +8459,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:505 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM" + // Pos:507 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM" { - ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 337, + ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 339, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -8444,9 +8475,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:506 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM" + // Pos:508 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 338, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 340, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8460,9 +8491,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:507 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM" + // Pos:509 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 338, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 340, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8476,9 +8507,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:508 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR" + // Pos:510 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 338, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 340, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8492,9 +8523,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:509 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM" + // Pos:511 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 338, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 340, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8508,9 +8539,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:510 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM" + // Pos:512 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 338, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 340, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8524,9 +8555,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:511 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM" + // Pos:513 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 339, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 341, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8540,9 +8571,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:512 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM" + // Pos:514 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 339, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 341, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8556,9 +8587,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:513 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR" + // Pos:515 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 339, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 341, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8572,9 +8603,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:514 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM" + // Pos:516 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 339, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 341, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8588,9 +8619,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:515 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM" + // Pos:517 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 339, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 341, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8604,9 +8635,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:516 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM" + // Pos:518 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8620,9 +8651,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:517 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM" + // Pos:519 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8636,9 +8667,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:518 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR" + // Pos:520 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8652,9 +8683,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:519 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM" + // Pos:521 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8668,9 +8699,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:520 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM" + // Pos:522 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 342, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8684,9 +8715,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:521 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM" + // Pos:523 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 341, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 343, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8700,9 +8731,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:522 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM" + // Pos:524 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 341, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 343, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8716,9 +8747,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:523 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR" + // Pos:525 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 341, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 343, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8732,9 +8763,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:524 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM" + // Pos:526 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 341, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 343, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8748,9 +8779,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:525 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM" + // Pos:527 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM" { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 341, + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 343, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8764,9 +8795,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:526 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM" + // Pos:528 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM" { - ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 342, + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 344, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8780,9 +8811,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:527 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM" + // Pos:529 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM" { - ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 343, + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 345, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8796,9 +8827,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:528 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM" + // Pos:530 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM" { - ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 344, + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 346, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8812,9 +8843,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:529 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM" + // Pos:531 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM" { - ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 345, + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 347, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8828,9 +8859,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:530 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM" + // Pos:532 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM" { - ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 346, + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 348, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8845,9 +8876,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:531 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM" + // Pos:533 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM" { - ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 347, + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 349, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8862,9 +8893,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:532 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM" + // Pos:534 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM" { - ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 348, + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 350, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8879,9 +8910,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:533 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM" + // Pos:535 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM" { - ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 349, + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 351, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8896,9 +8927,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:534 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM" + // Pos:536 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM" { - ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 350, + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 352, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8913,9 +8944,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:535 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM" + // Pos:537 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM" { - ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 351, + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 353, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8930,9 +8961,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:536 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM" + // Pos:538 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM" { - ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 352, + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 354, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8947,9 +8978,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:537 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM" + // Pos:539 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM" { - ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 353, + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -8964,9 +8995,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:538 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI" + // Pos:540 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI" { - ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 354, + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -8981,9 +9012,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:539 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI" + // Pos:541 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI" { - ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 355, + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -8998,9 +9029,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:540 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI" + // Pos:542 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI" { - ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 356, + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 358, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9015,9 +9046,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:541 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI" + // Pos:543 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI" { - ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 357, + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 359, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -9032,9 +9063,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:542 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI" + // Pos:544 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI" { - ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 358, + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 360, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -9049,9 +9080,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:543 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI" + // Pos:545 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI" { - ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 359, + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9066,9 +9097,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:544 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI" + // Pos:546 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI" { - ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 360, + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9083,9 +9114,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:545 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI" + // Pos:547 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI" { - ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 361, + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -9100,9 +9131,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:546 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM" + // Pos:548 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM" { - ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 362, + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -9116,9 +9147,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:547 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM" + // Pos:549 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM" { - ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 363, + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 365, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9132,9 +9163,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:548 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM" + // Pos:550 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM" { - ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 364, + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 366, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9148,9 +9179,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:549 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM" + // Pos:551 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM" { - ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 365, + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 367, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -9164,9 +9195,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:550 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM" + // Pos:552 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM" { - ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 366, + ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 368, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -9181,9 +9212,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:551 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM" + // Pos:553 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM" { - ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 367, + ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 369, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9198,9 +9229,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:552 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM" + // Pos:554 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM" { - ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 368, + ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 370, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9215,9 +9246,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:553 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM" + // Pos:555 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM" { - ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 369, + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 371, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -9232,9 +9263,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:554 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM" + // Pos:556 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM" { - ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 370, + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 372, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9249,9 +9280,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:555 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM" + // Pos:557 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM" { - ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 371, + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9266,9 +9297,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:556 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM" + // Pos:558 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM" { - ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 372, + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -9283,9 +9314,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:557 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM" + // Pos:559 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM" { - ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 373, + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 375, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, @@ -9300,9 +9331,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:558 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM" + // Pos:560 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM" { - ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 374, + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 376, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9317,9 +9348,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:559 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM" + // Pos:561 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM" { - ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 375, + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 377, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, @@ -9334,9 +9365,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:560 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM" + // Pos:562 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM" { - ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 376, + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 378, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, @@ -9351,9 +9382,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:561 Instruction:"LAHF" Encoding:"0x9F"/"" + // Pos:563 Instruction:"LAHF" Encoding:"0x9F"/"" { - ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 377, + ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 379, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9367,9 +9398,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:562 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM" + // Pos:564 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM" { - ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 378, + ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 380, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9384,9 +9415,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:563 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM" + // Pos:565 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM" { - ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 378, + ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 380, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9401,9 +9432,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:564 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM" + // Pos:566 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM" { - ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 379, + ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 381, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -9417,9 +9448,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:565 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M" + // Pos:567 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M" { - ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 380, + ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 382, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -9433,9 +9464,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:566 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM" + // Pos:568 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM" { - ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 381, + ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 383, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -9450,9 +9481,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:567 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M" + // Pos:569 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M" { - ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 382, + ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 384, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E1, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -9465,9 +9496,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:568 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM" + // Pos:570 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM" { - ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 383, + ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 385, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, @@ -9481,9 +9512,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:569 Instruction:"LEAVE" Encoding:"0xC9"/"" + // Pos:571 Instruction:"LEAVE" Encoding:"0xC9"/"" { - ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 384, + ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 386, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -9499,9 +9530,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:570 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM" + // Pos:572 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM" { - ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 385, + ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 387, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -9516,9 +9547,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:571 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/"" + // Pos:573 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/"" { - ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 386, + ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 388, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -9531,9 +9562,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:572 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM" + // Pos:574 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM" { - ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 387, + ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 389, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9548,9 +9579,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:573 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M" + // Pos:575 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M" { - ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 388, + ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 390, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -9564,9 +9595,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:574 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM" + // Pos:576 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM" { - ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 389, + ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 391, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9581,9 +9612,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:575 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M" + // Pos:577 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M" { - ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 390, + ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 392, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -9597,9 +9628,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:576 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M" + // Pos:578 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M" { - ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 391, + ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 393, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -9613,9 +9644,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:577 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M" + // Pos:579 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M" { - ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 392, + ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 394, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, @@ -9628,9 +9659,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:578 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M" + // Pos:580 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M" { - ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 393, + ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 395, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -9644,9 +9675,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:579 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM" + // Pos:581 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM" { - ND_INS_LOADIWKEY, ND_CAT_KL, ND_SET_KL, 394, + ND_INS_LOADIWKEY, ND_CAT_KL, ND_SET_KL, 396, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, @@ -9663,9 +9694,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:580 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/"" + // Pos:582 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 395, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 397, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9681,9 +9712,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:581 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/"" + // Pos:583 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 395, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 397, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9700,9 +9731,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:582 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/"" + // Pos:584 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 396, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 398, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9718,9 +9749,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:583 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/"" + // Pos:585 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 396, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 398, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9737,9 +9768,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:584 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/"" + // Pos:586 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 397, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 399, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9755,9 +9786,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:585 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/"" + // Pos:587 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 397, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 399, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9774,9 +9805,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:586 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/"" + // Pos:588 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 398, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 400, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9792,9 +9823,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:587 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/"" + // Pos:589 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/"" { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 398, + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 400, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -9811,9 +9842,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:588 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D" + // Pos:590 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D" { - ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 399, + ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 401, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -9829,9 +9860,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:589 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D" + // Pos:591 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D" { - ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 400, + ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 402, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -9847,9 +9878,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:590 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D" + // Pos:592 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D" { - ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 401, + ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 403, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -9865,9 +9896,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:591 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM" + // Pos:593 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM" { - ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 402, + ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 404, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9882,9 +9913,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:592 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM" + // Pos:594 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM" { - ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 402, + ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 404, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9899,9 +9930,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:593 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM" + // Pos:595 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM" { - ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 403, + ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 405, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -9916,9 +9947,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:594 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M" + // Pos:596 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M" { - ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 404, + ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 406, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -9932,9 +9963,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:595 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI" + // Pos:597 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI" { - ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 405, + ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 407, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, @@ -9949,9 +9980,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:596 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI" + // Pos:598 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI" { - ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 406, + ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 408, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, @@ -9966,9 +9997,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:597 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM" + // Pos:599 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM" { - ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 407, + ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 409, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LZCNT, @@ -9983,9 +10014,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:598 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM" + // Pos:600 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM" { - ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 408, + ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 410, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10000,9 +10031,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:599 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM" + // Pos:601 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM" { - ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 409, + ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 411, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -10017,9 +10048,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:600 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM" + // Pos:602 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM" { - ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 410, + ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 412, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10033,9 +10064,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:601 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM" + // Pos:603 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM" { - ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 411, + ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 413, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -10049,9 +10080,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:602 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM" + // Pos:604 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM" { - ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 412, + ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 414, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10065,9 +10096,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:603 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM" + // Pos:605 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM" { - ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 413, + ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 415, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -10081,9 +10112,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:604 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/"" + // Pos:606 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/"" { - ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 414, + ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 416, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MCOMMIT, @@ -10096,9 +10127,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:605 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/"" + // Pos:607 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/"" { - ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 415, + ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 417, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -10111,9 +10142,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:606 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM" + // Pos:608 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM" { - ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 416, + ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 418, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10127,9 +10158,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:607 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM" + // Pos:609 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM" { - ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 417, + ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 419, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -10143,9 +10174,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:608 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM" + // Pos:610 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM" { - ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 418, + ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 420, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10159,9 +10190,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:609 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM" + // Pos:611 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM" { - ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 419, + ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 421, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -10175,9 +10206,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:610 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/"" + // Pos:612 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/"" { - ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 420, + ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 422, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, @@ -10192,9 +10223,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:611 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/"" + // Pos:613 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/"" { - ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 421, + ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 423, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10209,9 +10240,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:612 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/"" + // Pos:614 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/"" { - ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 422, + ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 424, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10224,9 +10255,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:613 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR" + // Pos:615 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR" { - ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, @@ -10240,9 +10271,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:614 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR" + // Pos:616 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR" { - ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, @@ -10256,9 +10287,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:615 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM" + // Pos:617 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM" { - ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -10272,9 +10303,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:616 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM" + // Pos:618 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM" { - ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, @@ -10288,9 +10319,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:617 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR" + // Pos:619 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR" { - ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, @@ -10304,9 +10335,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:618 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM" + // Pos:620 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM" { - ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, @@ -10320,9 +10351,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:619 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR" + // Pos:621 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10336,9 +10367,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:620 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR" + // Pos:622 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10352,9 +10383,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:621 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM" + // Pos:623 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10368,9 +10399,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:622 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM" + // Pos:624 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10384,9 +10415,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:623 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR" + // Pos:625 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10400,9 +10431,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:624 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR" + // Pos:626 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10416,9 +10447,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:625 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM" + // Pos:627 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10432,9 +10463,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:626 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM" + // Pos:628 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10448,9 +10479,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:627 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D" + // Pos:629 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10464,9 +10495,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:628 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D" + // Pos:630 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10480,9 +10511,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:629 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D" + // Pos:631 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10496,9 +10527,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:630 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D" + // Pos:632 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10512,9 +10543,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:631 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI" + // Pos:633 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10528,9 +10559,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:632 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI" + // Pos:634 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10544,9 +10575,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:633 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI" + // Pos:635 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10560,9 +10591,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:634 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI" + // Pos:636 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10576,9 +10607,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:635 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI" + // Pos:637 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10592,9 +10623,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:636 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI" + // Pos:638 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10608,9 +10639,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:637 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI" + // Pos:639 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10624,9 +10655,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:638 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI" + // Pos:640 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10640,9 +10671,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:639 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI" + // Pos:641 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10656,9 +10687,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:640 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI" + // Pos:642 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10672,9 +10703,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:641 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI" + // Pos:643 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10688,9 +10719,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:642 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI" + // Pos:644 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10704,9 +10735,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:643 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI" + // Pos:645 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10720,9 +10751,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:644 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI" + // Pos:646 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10736,9 +10767,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:645 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI" + // Pos:647 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10752,9 +10783,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:646 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI" + // Pos:648 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -10768,9 +10799,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:647 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI" + // Pos:649 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10784,9 +10815,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:648 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI" + // Pos:650 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI" { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 425, ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -10800,9 +10831,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:649 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM" + // Pos:651 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM" { - ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 424, + ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 426, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10816,9 +10847,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:650 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR" + // Pos:652 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR" { - ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 424, + ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 426, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10832,9 +10863,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:651 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM" + // Pos:653 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM" { - ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, + ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 427, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -10848,9 +10879,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:652 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR" + // Pos:654 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR" { - ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, + ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 427, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -10864,9 +10895,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:653 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM" + // Pos:655 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM" { - ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 426, + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 428, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, @@ -10880,9 +10911,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:654 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM" + // Pos:656 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM" { - ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 426, + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 428, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, @@ -10896,9 +10927,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:655 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR" + // Pos:657 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR" { - ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 426, + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 428, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, @@ -10912,9 +10943,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:656 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR" + // Pos:658 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR" { - ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 426, + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 428, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, @@ -10928,9 +10959,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:657 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM" + // Pos:659 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM" { - ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 427, + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 429, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -10944,9 +10975,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:658 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM" + // Pos:660 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM" { - ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 427, + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 429, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10960,9 +10991,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:659 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR" + // Pos:661 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR" { - ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 427, + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 429, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -10976,9 +11007,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:660 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR" + // Pos:662 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR" { - ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 427, + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 429, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -10992,9 +11023,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:661 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM" + // Pos:663 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM" { - ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 428, + ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 430, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -11008,9 +11039,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:662 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M" + // Pos:664 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M" { - ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 429, + ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 431, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIR64B, @@ -11024,9 +11055,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:663 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR" + // Pos:665 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR" { - ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 430, + ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 432, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIRI, @@ -11040,9 +11071,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:664 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM" + // Pos:666 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM" { - ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 431, + ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 433, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11056,9 +11087,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:665 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM" + // Pos:667 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM" { - ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 432, + ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 434, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11072,9 +11103,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:666 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR" + // Pos:668 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR" { - ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 432, + ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 434, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11088,9 +11119,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:667 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM" + // Pos:669 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM" { - ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 433, + ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 435, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11104,9 +11135,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:668 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR" + // Pos:670 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR" { - ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 433, + ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 435, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11120,9 +11151,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:669 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM" + // Pos:671 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM" { - ND_INS_MOVHLPS, ND_CAT_DATAXFER, ND_SET_SSE, 434, + ND_INS_MOVHLPS, ND_CAT_DATAXFER, ND_SET_SSE, 436, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11136,9 +11167,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:670 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM" + // Pos:672 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM" { - ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 435, + ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 437, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11152,9 +11183,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:671 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR" + // Pos:673 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR" { - ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 435, + ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 437, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11168,9 +11199,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:672 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM" + // Pos:674 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM" { - ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 436, + ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 438, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11184,9 +11215,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:673 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR" + // Pos:675 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR" { - ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 436, + ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 438, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11200,9 +11231,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:674 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM" + // Pos:676 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM" { - ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 437, + ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 439, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11216,9 +11247,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:675 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM" + // Pos:677 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM" { - ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 438, + ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 440, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11232,9 +11263,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:676 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR" + // Pos:678 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR" { - ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 438, + ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 440, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11248,9 +11279,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:677 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR" + // Pos:679 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR" { - ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 439, + ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 441, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11264,9 +11295,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:678 Instruction:"MOVMSKPD Gd,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM" + // Pos:680 Instruction:"MOVMSKPD Gd,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM" { - ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 440, + ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 442, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11280,9 +11311,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:679 Instruction:"MOVMSKPS Gd,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM" + // Pos:681 Instruction:"MOVMSKPS Gd,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM" { - ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 441, + ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 443, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11296,9 +11327,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:680 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR" + // Pos:682 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR" { - ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 442, + ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 444, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11312,9 +11343,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:681 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM" + // Pos:683 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM" { - ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 443, + ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 445, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -11328,9 +11359,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:682 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR" + // Pos:684 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR" { - ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 444, + ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 446, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -11344,9 +11375,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:683 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR" + // Pos:685 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR" { - ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 445, + ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11360,9 +11391,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:684 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR" + // Pos:686 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR" { - ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 446, + ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 448, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11376,9 +11407,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:685 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR" + // Pos:687 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR" { - ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 447, + ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 449, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -11392,9 +11423,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:686 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR" + // Pos:688 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR" { - ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 448, + ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 450, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, @@ -11408,9 +11439,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:687 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR" + // Pos:689 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR" { - ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 449, + ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 451, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, @@ -11424,9 +11455,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:688 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM" + // Pos:690 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 450, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 452, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -11440,9 +11471,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:689 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM" + // Pos:691 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 450, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 452, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11456,9 +11487,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:690 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM" + // Pos:692 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 450, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 452, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -11472,9 +11503,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:691 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR" + // Pos:693 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 450, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 452, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -11488,9 +11519,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:692 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR" + // Pos:694 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 450, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 452, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11504,9 +11535,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:693 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM" + // Pos:695 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 450, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 452, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11520,9 +11551,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:694 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR" + // Pos:696 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 450, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 452, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -11536,9 +11567,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:695 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR" + // Pos:697 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR" { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 450, + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 452, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11552,9 +11583,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:696 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM" + // Pos:698 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM" { - ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 451, + ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 453, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11568,9 +11599,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:697 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" + // Pos:699 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 452, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 454, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11587,9 +11618,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:698 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" + // Pos:700 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 452, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 454, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11607,9 +11638,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:699 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" + // Pos:701 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" { - ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 453, + ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 455, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11623,9 +11654,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:700 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" + // Pos:702 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" { - ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 453, + ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 455, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11639,9 +11670,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:701 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" + // Pos:703 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 453, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 455, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11658,9 +11689,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:702 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" + // Pos:704 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 453, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 455, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11678,9 +11709,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:703 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" + // Pos:705 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" { - ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 454, + ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 456, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -11694,9 +11725,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:704 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" + // Pos:706 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" { - ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 455, + ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 457, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, @@ -11710,9 +11741,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:705 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" + // Pos:707 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 456, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 458, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11729,9 +11760,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:706 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" + // Pos:708 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 456, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 458, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11749,9 +11780,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:707 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" + // Pos:709 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" { - ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 457, + ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 459, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11765,9 +11796,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:708 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" + // Pos:710 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" { - ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 457, + ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 459, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11781,9 +11812,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:709 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" + // Pos:711 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 458, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 460, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11800,9 +11831,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:710 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" + // Pos:712 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 458, + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 460, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -11820,9 +11851,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:711 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" + // Pos:713 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" { - ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 459, + ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 461, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -11836,9 +11867,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:712 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" + // Pos:714 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" { - ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 459, + ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 461, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -11852,9 +11883,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:713 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM" + // Pos:715 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM" { - ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 460, + ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 462, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -11868,9 +11899,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:714 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" + // Pos:716 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" { - ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 461, + ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 463, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11884,9 +11915,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:715 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" + // Pos:717 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" { - ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 461, + ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 463, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -11900,9 +11931,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:716 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" + // Pos:718 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" { - ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 462, + ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 464, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11916,9 +11947,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:717 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" + // Pos:719 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" { - ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 462, + ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 464, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -11932,9 +11963,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:718 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" + // Pos:720 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" { - ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 463, + ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 465, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -11948,9 +11979,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:719 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" + // Pos:721 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" { - ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 463, + ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 465, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -11964,9 +11995,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:720 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" + // Pos:722 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" { - ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 464, + ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 466, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -11981,9 +12012,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:721 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" + // Pos:723 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" { - ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 465, + ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 467, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -11999,9 +12030,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:722 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" + // Pos:724 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" { - ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 465, + ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 467, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12017,9 +12048,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:723 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" + // Pos:725 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" { - ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 466, + ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 468, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -12033,9 +12064,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:724 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" + // Pos:726 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" { - ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 467, + ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 469, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -12049,9 +12080,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:725 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" + // Pos:727 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" { - ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 468, + ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 470, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -12065,9 +12096,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:726 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" + // Pos:728 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" { - ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 469, + ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 471, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -12081,9 +12112,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:727 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" + // Pos:729 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" { - ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 470, + ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 472, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -12099,9 +12130,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:728 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" + // Pos:730 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" { - ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 471, + ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 473, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, @@ -12115,9 +12146,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:729 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" + // Pos:731 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" { - ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 472, + ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 474, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12132,9 +12163,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:730 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" + // Pos:732 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" { - ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 473, + ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 475, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12148,9 +12179,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:731 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" + // Pos:733 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" { - ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 473, + ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 475, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12164,9 +12195,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:732 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" + // Pos:734 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12180,9 +12211,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:733 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" + // Pos:735 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12196,9 +12227,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:734 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" + // Pos:736 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12212,9 +12243,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:735 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" + // Pos:737 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12228,9 +12259,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:736 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" + // Pos:738 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12244,9 +12275,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:737 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" + // Pos:739 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12260,9 +12291,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:738 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" + // Pos:740 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12276,9 +12307,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:739 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" + // Pos:741 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12292,9 +12323,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:740 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" + // Pos:742 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12307,9 +12338,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:741 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" + // Pos:743 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12322,9 +12353,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:742 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" + // Pos:744 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12337,9 +12368,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:743 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" + // Pos:745 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12352,9 +12383,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:744 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" + // Pos:746 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12367,9 +12398,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:745 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" + // Pos:747 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12382,9 +12413,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:746 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" + // Pos:748 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12397,9 +12428,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:747 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" + // Pos:749 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12412,9 +12443,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:748 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" + // Pos:750 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12427,9 +12458,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:749 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1A /r"/"RM" + // Pos:751 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1A /r"/"RM" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12443,9 +12474,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:750 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM" + // Pos:752 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12459,9 +12490,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:751 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR" + // Pos:753 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12475,9 +12506,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:752 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" + // Pos:754 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12491,9 +12522,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:753 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR" + // Pos:755 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12507,9 +12538,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:754 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" + // Pos:756 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12523,9 +12554,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:755 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1A /r:reg"/"RM" + // Pos:757 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1A /r:reg"/"RM" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12539,9 +12570,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:756 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1B /r:reg"/"RM" + // Pos:758 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1B /r:reg"/"RM" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12555,9 +12586,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:757 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM" + // Pos:759 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12571,9 +12602,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:758 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR" + // Pos:760 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12587,9 +12618,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:759 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR" + // Pos:761 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12603,9 +12634,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:760 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR" + // Pos:762 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12619,9 +12650,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:761 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR" + // Pos:763 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12635,9 +12666,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:762 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR" + // Pos:764 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12651,9 +12682,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:763 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR" + // Pos:765 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12667,9 +12698,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:764 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR" + // Pos:766 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12683,9 +12714,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:765 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR" + // Pos:767 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12699,9 +12730,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:766 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR" + // Pos:768 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12715,9 +12746,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:767 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR" + // Pos:769 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12731,9 +12762,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:768 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR" + // Pos:770 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12747,9 +12778,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:769 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /r:mem"/"MR" + // Pos:771 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /r:mem"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12763,9 +12794,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:770 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR" + // Pos:772 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12779,9 +12810,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:771 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR" + // Pos:773 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12795,9 +12826,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:772 Instruction:"NOP Rv,Gv" Encoding:"cet rexw 0x0F 0x1E /1:reg"/"MR" + // Pos:774 Instruction:"NOP Rv,Gv" Encoding:"cet rexw 0x0F 0x1E /1:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12811,9 +12842,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:773 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR" + // Pos:775 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12827,9 +12858,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:774 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR" + // Pos:776 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12843,9 +12874,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:775 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR" + // Pos:777 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12859,9 +12890,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:776 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR" + // Pos:778 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12875,9 +12906,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:777 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR" + // Pos:779 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12891,9 +12922,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:778 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR" + // Pos:780 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12907,9 +12938,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:779 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR" + // Pos:781 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12923,9 +12954,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:780 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR" + // Pos:782 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12939,9 +12970,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:781 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR" + // Pos:783 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12955,9 +12986,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:782 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR" + // Pos:784 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12971,9 +13002,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:783 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR" + // Pos:785 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -12987,9 +13018,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:784 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR" + // Pos:786 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13003,9 +13034,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:785 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR" + // Pos:787 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR" { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13019,9 +13050,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:786 Instruction:"NOP" Encoding:"0x90"/"" + // Pos:788 Instruction:"NOP" Encoding:"0x90"/"" { - ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 474, + ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 476, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -13034,9 +13065,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:787 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" + // Pos:789 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" { - ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 475, + ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 477, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13049,9 +13080,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:788 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" + // Pos:790 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" { - ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 475, + ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 477, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13064,9 +13095,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:789 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" + // Pos:791 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 478, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13081,9 +13112,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:790 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" + // Pos:792 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 478, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13098,9 +13129,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:791 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" + // Pos:793 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 478, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13115,9 +13146,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:792 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" + // Pos:794 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 478, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13132,9 +13163,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:793 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" + // Pos:795 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 478, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -13149,9 +13180,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:794 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" + // Pos:796 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 478, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -13166,9 +13197,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:795 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" + // Pos:797 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 478, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13183,9 +13214,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:796 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" + // Pos:798 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 478, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13200,9 +13231,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:797 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI" + // Pos:799 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 478, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -13217,9 +13248,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:798 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" + // Pos:800 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 478, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -13234,9 +13265,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:799 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" + // Pos:801 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" { - ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 477, + ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 479, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13250,9 +13281,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:800 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" + // Pos:802 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" { - ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 478, + ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 480, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -13266,9 +13297,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:801 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" + // Pos:803 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" { - ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 479, + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 481, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13283,9 +13314,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:802 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" + // Pos:804 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" { - ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 479, + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 481, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13300,9 +13331,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:803 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" + // Pos:805 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" { - ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 479, + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 481, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13317,9 +13348,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:804 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" + // Pos:806 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" { - ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 479, + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 481, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13334,9 +13365,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:805 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" + // Pos:807 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 480, + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 482, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13352,9 +13383,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:806 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" + // Pos:808 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 480, + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 482, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13371,9 +13402,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:807 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" + // Pos:809 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 481, + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 483, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13389,9 +13420,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:808 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" + // Pos:810 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 481, + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 483, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13408,9 +13439,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:809 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" + // Pos:811 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 482, + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 484, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13426,9 +13457,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:810 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" + // Pos:812 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 482, + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 484, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -13445,9 +13476,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:811 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" + // Pos:813 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" { - ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 483, + ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 485, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -13461,9 +13492,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:812 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" + // Pos:814 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" { - ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 483, + ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 485, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -13477,9 +13508,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:813 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" + // Pos:815 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" { - ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 484, + ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 486, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -13493,9 +13524,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:814 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" + // Pos:816 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" { - ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 484, + ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 486, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -13509,9 +13540,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:815 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" + // Pos:817 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" { - ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 485, + ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 487, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -13525,9 +13556,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:816 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" + // Pos:818 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" { - ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 485, + ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 487, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -13541,9 +13572,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:817 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" + // Pos:819 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" { - ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 486, + ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 488, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13557,9 +13588,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:818 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" + // Pos:820 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" { - ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 486, + ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 488, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13573,9 +13604,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:819 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" + // Pos:821 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" { - ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 487, + ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 489, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13589,9 +13620,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:820 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" + // Pos:822 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" { - ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 487, + ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 489, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13605,9 +13636,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:821 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" + // Pos:823 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" { - ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 488, + ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 490, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -13621,9 +13652,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:822 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" + // Pos:824 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" { - ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 489, + ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 491, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13637,9 +13668,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:823 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" + // Pos:825 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" { - ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 489, + ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 491, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13653,9 +13684,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:824 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" + // Pos:826 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" { - ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 490, + ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 492, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13669,9 +13700,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:825 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" + // Pos:827 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" { - ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 490, + ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 492, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13685,9 +13716,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:826 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" + // Pos:828 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" { - ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 491, + ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 493, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13701,9 +13732,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:827 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" + // Pos:829 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" { - ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 491, + ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 493, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13717,9 +13748,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:828 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" + // Pos:830 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" { - ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 492, + ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 494, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -13733,9 +13764,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:829 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" + // Pos:831 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" { - ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 492, + ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 494, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13749,9 +13780,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:830 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" + // Pos:832 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" { - ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 493, + ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 495, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13765,9 +13796,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:831 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" + // Pos:833 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" { - ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 493, + ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 495, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13781,9 +13812,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:832 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" + // Pos:834 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" { - ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 494, + ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 496, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13797,9 +13828,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:833 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" + // Pos:835 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" { - ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 494, + ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 496, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13813,9 +13844,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:834 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" + // Pos:836 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" { - ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 495, + ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 497, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13829,9 +13860,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:835 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" + // Pos:837 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" { - ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 495, + ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 497, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13845,9 +13876,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:836 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" + // Pos:838 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" { - ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 496, + ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13861,9 +13892,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:837 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" + // Pos:839 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" { - ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 496, + ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13877,9 +13908,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:838 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" + // Pos:840 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" { - ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 497, + ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 499, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13893,9 +13924,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:839 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" + // Pos:841 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" { - ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 497, + ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 499, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13909,9 +13940,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:840 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" + // Pos:842 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" { - ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 498, + ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 500, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -13926,9 +13957,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:841 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" + // Pos:843 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" { - ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 498, + ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 500, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -13943,9 +13974,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:842 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" + // Pos:844 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" { - ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 499, + ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 501, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13959,9 +13990,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:843 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" + // Pos:845 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" { - ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 499, + ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 501, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -13975,9 +14006,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:844 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" + // Pos:846 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" { - ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 500, + ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 502, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -13991,9 +14022,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:845 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" + // Pos:847 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" { - ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 500, + ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 502, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14007,9 +14038,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:846 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/"" + // Pos:848 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/"" { - ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 501, + ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -14022,9 +14053,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:847 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" + // Pos:849 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" { - ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 502, + ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 504, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14038,9 +14069,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:848 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" + // Pos:850 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" { - ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 502, + ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 504, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14054,9 +14085,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:849 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" + // Pos:851 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" { - ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 503, + ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 505, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14070,9 +14101,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:850 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" + // Pos:852 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" { - ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 504, + ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 506, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14086,9 +14117,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:851 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" + // Pos:853 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" { - ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 504, + ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 506, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14102,9 +14133,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:852 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" + // Pos:854 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" { - ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 505, + ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 507, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14119,9 +14150,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:853 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" + // Pos:855 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" { - ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 506, + ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 508, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14136,9 +14167,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:854 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" + // Pos:856 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" { - ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 507, + ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 509, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_PCLMULQDQ, @@ -14153,9 +14184,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:855 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" + // Pos:857 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" { - ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 508, + ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 510, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14169,9 +14200,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:856 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" + // Pos:858 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" { - ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 508, + ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 510, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14185,9 +14216,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:857 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" + // Pos:859 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" { - ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 509, + ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 511, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14201,9 +14232,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:858 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" + // Pos:860 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" { - ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 509, + ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 511, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14217,9 +14248,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:859 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" + // Pos:861 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" { - ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 510, + ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 512, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14233,9 +14264,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:860 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" + // Pos:862 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" { - ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 511, + ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 513, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14249,9 +14280,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:861 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" + // Pos:863 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" { - ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 511, + ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 513, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14265,9 +14296,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:862 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" + // Pos:864 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" { - ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 512, + ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 514, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, @@ -14286,9 +14317,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:863 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" + // Pos:865 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" { - ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 513, + ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 515, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, @@ -14307,9 +14338,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:864 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" + // Pos:866 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" { - ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 514, + ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 516, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14323,9 +14354,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:865 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" + // Pos:867 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" { - ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 514, + ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 516, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14339,9 +14370,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:866 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" + // Pos:868 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" { - ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 515, + ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 517, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14355,9 +14386,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:867 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" + // Pos:869 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" { - ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 515, + ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 517, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14371,9 +14402,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:868 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" + // Pos:870 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" { - ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 516, + ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 518, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, @@ -14387,9 +14418,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:869 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" + // Pos:871 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" { - ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 517, + ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 519, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14403,9 +14434,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:870 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" + // Pos:872 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" { - ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 517, + ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 519, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14419,9 +14450,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:871 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" + // Pos:873 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" { - ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 518, + ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 520, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, @@ -14438,9 +14469,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:872 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" + // Pos:874 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" { - ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 519, + ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 521, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, @@ -14457,9 +14488,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:873 Instruction:"PCOMMIT" Encoding:"0x66 0x0F 0xAE /7:reg"/"" + // Pos:875 Instruction:"PCOMMIT" Encoding:"0x66 0x0F 0xAE /7:reg"/"" { - ND_INS_PCOMMIT, ND_CAT_MISC, ND_SET_PCOMMIT, 520, + ND_INS_PCOMMIT, ND_CAT_MISC, ND_SET_PCOMMIT, 522, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCOMMIT, @@ -14472,9 +14503,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:874 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" + // Pos:876 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" { - ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 521, + ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 523, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, @@ -14490,9 +14521,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:875 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" + // Pos:877 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" { - ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 522, + ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 524, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -14507,9 +14538,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:876 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" + // Pos:878 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" { - ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 523, + ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 525, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -14524,9 +14555,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:877 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" + // Pos:879 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" { - ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 524, + ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 526, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14541,9 +14572,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:878 Instruction:"PEXTRB Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" + // Pos:880 Instruction:"PEXTRB Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" { - ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 524, + ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 526, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14558,9 +14589,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:879 Instruction:"PEXTRD Ey,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r ib"/"MRI" + // Pos:881 Instruction:"PEXTRD Ey,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r ib"/"MRI" { - ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 525, + ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 527, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14575,9 +14606,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:880 Instruction:"PEXTRQ Ey,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r ib"/"MRI" + // Pos:882 Instruction:"PEXTRQ Ey,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r ib"/"MRI" { - ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 526, + ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 528, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14592,9 +14623,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:881 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" + // Pos:883 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" { - ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 527, + ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 529, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -14609,9 +14640,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:882 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" + // Pos:884 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" { - ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 527, + ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 529, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -14626,9 +14657,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:883 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" + // Pos:885 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" { - ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 527, + ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 529, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14643,9 +14674,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:884 Instruction:"PEXTRW Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" + // Pos:886 Instruction:"PEXTRW Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" { - ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 527, + ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 529, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -14660,9 +14691,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:885 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" + // Pos:887 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" { - ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 528, + ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 530, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14676,9 +14707,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:886 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" + // Pos:888 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" { - ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 529, + ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 531, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14692,9 +14723,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:887 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" + // Pos:889 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" { - ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 530, + ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 532, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14708,9 +14739,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:888 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" + // Pos:890 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" { - ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 531, + ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 533, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14724,9 +14755,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:889 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" + // Pos:891 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" { - ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 532, + ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 534, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14740,9 +14771,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:890 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" + // Pos:892 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" { - ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 533, + ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 535, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14756,9 +14787,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:891 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" + // Pos:893 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" { - ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 534, + ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 536, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14772,9 +14803,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:892 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" + // Pos:894 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" { - ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 535, + ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 537, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14788,9 +14819,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:893 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" + // Pos:895 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" { - ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 536, + ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 538, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14804,9 +14835,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:894 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" + // Pos:896 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" { - ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 537, + ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 539, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14820,9 +14851,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:895 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" + // Pos:897 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" { - ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 538, + ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 540, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14836,9 +14867,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:896 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" + // Pos:898 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" { - ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 539, + ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 541, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14852,9 +14883,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:897 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" + // Pos:899 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" { - ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 540, + ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 542, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14868,9 +14899,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:898 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" + // Pos:900 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" { - ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 541, + ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 543, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14884,9 +14915,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:899 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" + // Pos:901 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" { - ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 542, + ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 544, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14900,9 +14931,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:900 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" + // Pos:902 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" { - ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 543, + ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 545, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14916,9 +14947,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:901 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" + // Pos:903 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" { - ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 544, + ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 546, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14932,9 +14963,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:902 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" + // Pos:904 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" { - ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 545, + ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 547, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14948,9 +14979,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:903 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" + // Pos:905 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" { - ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 546, + ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 548, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14964,9 +14995,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:904 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" + // Pos:906 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" { - ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 547, + ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 549, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14980,9 +15011,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:905 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" + // Pos:907 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" { - ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 548, + ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 550, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -14996,9 +15027,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:906 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" + // Pos:908 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" { - ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 549, + ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 551, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15012,9 +15043,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:907 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" + // Pos:909 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" { - ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 549, + ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 551, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15028,9 +15059,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:908 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" + // Pos:910 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" { - ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 550, + ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 552, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15044,9 +15075,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:909 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" + // Pos:911 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" { - ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 550, + ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 552, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15060,9 +15091,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:910 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" + // Pos:912 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" { - ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 551, + ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 553, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15076,9 +15107,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:911 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" + // Pos:913 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" { - ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 551, + ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 553, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15092,9 +15123,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:912 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" + // Pos:914 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" { - ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 552, + ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 554, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15108,9 +15139,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:913 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" + // Pos:915 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" { - ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 553, + ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 555, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15124,9 +15155,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:914 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" + // Pos:916 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" { - ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 553, + ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 555, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15140,9 +15171,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:915 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" + // Pos:917 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" { - ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 554, + ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 556, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15156,9 +15187,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:916 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" + // Pos:918 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" { - ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 554, + ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 556, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15172,9 +15203,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:917 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" + // Pos:919 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" { - ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 555, + ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 557, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15188,9 +15219,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:918 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" + // Pos:920 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" { - ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 555, + ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 557, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15204,9 +15235,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:919 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" + // Pos:921 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" { - ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 556, + ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 558, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -15220,9 +15251,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:920 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" + // Pos:922 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" { - ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 557, + ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 559, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -15236,9 +15267,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:921 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" + // Pos:923 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" { - ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 558, + ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 560, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15253,9 +15284,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:922 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" + // Pos:924 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" { - ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 558, + ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 560, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15270,9 +15301,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:923 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + // Pos:925 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" { - ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 559, + ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 561, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15287,9 +15318,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:924 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + // Pos:926 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" { - ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 560, + ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 562, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15304,9 +15335,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:925 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" + // Pos:927 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" { - ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 561, + ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 563, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15321,9 +15352,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:926 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" + // Pos:928 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" { - ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 561, + ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 563, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15338,9 +15369,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:927 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" + // Pos:929 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" { - ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 561, + ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 563, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15355,9 +15386,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:928 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" + // Pos:930 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" { - ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 561, + ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 563, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15372,9 +15403,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:929 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" + // Pos:931 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" { - ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 562, + ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 564, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15388,9 +15419,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:930 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" + // Pos:932 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" { - ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 562, + ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 564, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15404,9 +15435,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:931 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" + // Pos:933 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" { - ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 563, + ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 565, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15420,9 +15451,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:932 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" + // Pos:934 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" { - ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 563, + ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 565, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15436,9 +15467,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:933 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" + // Pos:935 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" { - ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 564, + ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 566, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15452,9 +15483,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:934 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" + // Pos:936 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" { - ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 565, + ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 567, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15468,9 +15499,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:935 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" + // Pos:937 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" { - ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 566, + ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 568, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15484,9 +15515,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:936 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" + // Pos:938 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" { - ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 566, + ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 568, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15500,9 +15531,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:937 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" + // Pos:939 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" { - ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 567, + ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 569, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15516,9 +15547,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:938 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" + // Pos:940 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" { - ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 567, + ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 569, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15532,9 +15563,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:939 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" + // Pos:941 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" { - ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 568, + ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 570, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15548,9 +15579,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:940 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" + // Pos:942 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" { - ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 569, + ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 571, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15564,9 +15595,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:941 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" + // Pos:943 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" { - ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 570, + ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 572, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15580,9 +15611,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:942 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" + // Pos:944 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" { - ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 571, + ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 573, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15596,9 +15627,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:943 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" + // Pos:945 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" { - ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 572, + ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 574, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15612,9 +15643,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:944 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" + // Pos:946 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" { - ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 572, + ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 574, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15628,9 +15659,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:945 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" + // Pos:947 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" { - ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 573, + ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 575, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15644,9 +15675,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:946 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" + // Pos:948 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" { - ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 573, + ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 575, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15660,9 +15691,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:947 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" + // Pos:949 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" { - ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 574, + ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 576, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15676,9 +15707,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:948 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" + // Pos:950 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" { - ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 575, + ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 577, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15692,9 +15723,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:949 Instruction:"PMOVMSKB Gd,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" + // Pos:951 Instruction:"PMOVMSKB Gd,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" { - ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 576, + ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 578, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -15708,9 +15739,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:950 Instruction:"PMOVMSKB Gd,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" + // Pos:952 Instruction:"PMOVMSKB Gd,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" { - ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 576, + ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 578, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -15724,9 +15755,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:951 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" + // Pos:953 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" { - ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 577, + ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 579, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15740,9 +15771,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:952 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" + // Pos:954 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" { - ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 578, + ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 580, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15756,9 +15787,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:953 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" + // Pos:955 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" { - ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 579, + ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 581, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15772,9 +15803,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:954 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" + // Pos:956 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" { - ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 580, + ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 582, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15788,9 +15819,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:955 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" + // Pos:957 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" { - ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 581, + ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 583, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15804,9 +15835,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:956 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" + // Pos:958 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" { - ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 582, + ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 584, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15820,9 +15851,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:957 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" + // Pos:959 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" { - ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 583, + ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 585, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15836,9 +15867,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:958 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" + // Pos:960 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" { - ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 584, + ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 586, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15852,9 +15883,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:959 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" + // Pos:961 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" { - ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 585, + ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 587, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15868,9 +15899,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:960 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" + // Pos:962 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" { - ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 586, + ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 588, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15884,9 +15915,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:961 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" + // Pos:963 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" { - ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 587, + ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 589, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15900,9 +15931,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:962 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" + // Pos:964 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" { - ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 588, + ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 590, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15916,9 +15947,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:963 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" + // Pos:965 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" { - ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 589, + ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 591, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -15932,9 +15963,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:964 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" + // Pos:966 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" { - ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 590, + ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 592, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -15948,9 +15979,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:965 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" + // Pos:967 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" { - ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 590, + ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 592, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -15964,9 +15995,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:966 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" + // Pos:968 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" { - ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 591, + ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 593, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -15980,9 +16011,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:967 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" + // Pos:969 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" { - ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 592, + ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 594, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -15996,9 +16027,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:968 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" + // Pos:970 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" { - ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 592, + ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 594, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16012,9 +16043,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:969 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" + // Pos:971 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" { - ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 593, + ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 595, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16028,9 +16059,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:970 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" + // Pos:972 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" { - ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 593, + ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 595, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16044,9 +16075,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:971 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" + // Pos:973 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" { - ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 594, + ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 596, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -16060,9 +16091,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:972 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" + // Pos:974 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" { - ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 595, + ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 597, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16076,9 +16107,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:973 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" + // Pos:975 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" { - ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 595, + ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 597, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16092,9 +16123,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:974 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" + // Pos:976 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" { - ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 596, + ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 598, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -16108,9 +16139,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:975 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" + // Pos:977 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" { - ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 596, + ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 598, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16124,9 +16155,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:976 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" + // Pos:978 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16140,9 +16171,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:977 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" + // Pos:979 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16156,9 +16187,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:978 Instruction:"POP ES" Encoding:"0x07"/"" + // Pos:980 Instruction:"POP ES" Encoding:"0x07"/"" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -16172,9 +16203,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:979 Instruction:"POP SS" Encoding:"0x17"/"" + // Pos:981 Instruction:"POP SS" Encoding:"0x17"/"" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -16188,9 +16219,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:980 Instruction:"POP DS" Encoding:"0x1F"/"" + // Pos:982 Instruction:"POP DS" Encoding:"0x1F"/"" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -16204,9 +16235,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:981 Instruction:"POP Zv" Encoding:"0x58"/"O" + // Pos:983 Instruction:"POP Zv" Encoding:"0x58"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16220,9 +16251,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:982 Instruction:"POP Zv" Encoding:"0x59"/"O" + // Pos:984 Instruction:"POP Zv" Encoding:"0x59"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16236,9 +16267,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:983 Instruction:"POP Zv" Encoding:"0x5A"/"O" + // Pos:985 Instruction:"POP Zv" Encoding:"0x5A"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16252,9 +16283,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:984 Instruction:"POP Zv" Encoding:"0x5B"/"O" + // Pos:986 Instruction:"POP Zv" Encoding:"0x5B"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16268,9 +16299,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:985 Instruction:"POP Zv" Encoding:"0x5C"/"O" + // Pos:987 Instruction:"POP Zv" Encoding:"0x5C"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16284,9 +16315,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:986 Instruction:"POP Zv" Encoding:"0x5D"/"O" + // Pos:988 Instruction:"POP Zv" Encoding:"0x5D"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16300,9 +16331,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:987 Instruction:"POP Zv" Encoding:"0x5E"/"O" + // Pos:989 Instruction:"POP Zv" Encoding:"0x5E"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16316,9 +16347,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:988 Instruction:"POP Zv" Encoding:"0x5F"/"O" + // Pos:990 Instruction:"POP Zv" Encoding:"0x5F"/"O" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16332,9 +16363,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:989 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" + // Pos:991 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 599, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, @@ -16348,9 +16379,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:990 Instruction:"POPA" Encoding:"ds16 0x61"/"" + // Pos:992 Instruction:"POPA" Encoding:"ds16 0x61"/"" { - ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 598, + ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 600, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -16364,9 +16395,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:991 Instruction:"POPAD" Encoding:"ds32 0x61"/"" + // Pos:993 Instruction:"POPAD" Encoding:"ds32 0x61"/"" { - ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 599, + ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 601, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -16380,9 +16411,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:992 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM" + // Pos:994 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM" { - ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 600, + ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 602, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, @@ -16397,9 +16428,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:993 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" + // Pos:995 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" { - ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 601, + ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 603, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16413,9 +16444,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:994 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" + // Pos:996 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" { - ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 602, + ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 604, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16429,9 +16460,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:995 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" + // Pos:997 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" { - ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 603, + ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 605, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -16445,9 +16476,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:996 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" + // Pos:998 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" { - ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 604, + ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 606, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16461,9 +16492,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:997 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" + // Pos:999 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" { - ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 604, + ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 606, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16477,9 +16508,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:998 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M" + // Pos:1000 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M" { - ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 605, + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 607, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16492,9 +16523,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:999 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M" + // Pos:1001 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M" { - ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 605, + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 607, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16507,9 +16538,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1000 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M" + // Pos:1002 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M" { - ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 605, + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 607, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16522,9 +16553,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1001 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M" + // Pos:1003 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M" { - ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 605, + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 607, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16537,9 +16568,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1002 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M" + // Pos:1004 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M" { - ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 606, + ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 608, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16552,9 +16583,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1003 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M" + // Pos:1005 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M" { - ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 607, + ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 609, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16567,9 +16598,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1004 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M" + // Pos:1006 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M" { - ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 608, + ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 610, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -16582,9 +16613,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1005 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M" + // Pos:1007 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M" { - ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 609, + ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 611, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -16597,9 +16628,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1006 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M" + // Pos:1008 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M" { - ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 610, + ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 612, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -16612,9 +16643,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1007 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M" + // Pos:1009 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M" { - ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 611, + ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 613, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -16627,9 +16658,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1008 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M" + // Pos:1010 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M" { - ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 612, + ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 614, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16642,9 +16673,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1009 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M" + // Pos:1011 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M" { - ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 613, + ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 615, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -16657,9 +16688,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1010 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" + // Pos:1012 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" { - ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 614, + ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 616, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16673,9 +16704,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1011 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" + // Pos:1013 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" { - ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 614, + ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 616, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16689,9 +16720,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1012 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" + // Pos:1014 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" { - ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 615, + ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 617, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -16705,9 +16736,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1013 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" + // Pos:1015 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" { - ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 615, + ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 617, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -16721,9 +16752,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1014 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" + // Pos:1016 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" { - ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 616, + ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 618, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16738,9 +16769,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1015 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" + // Pos:1017 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" { - ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 617, + ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 619, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16755,9 +16786,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1016 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" + // Pos:1018 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" { - ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 618, + ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 620, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16772,9 +16803,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1017 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" + // Pos:1019 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" { - ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 619, + ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 621, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16789,9 +16820,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1018 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" + // Pos:1020 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" { - ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 620, + ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 622, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -16805,9 +16836,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1019 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" + // Pos:1021 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" { - ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 620, + ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 622, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -16821,9 +16852,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1020 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" + // Pos:1022 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" { - ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 621, + ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 623, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -16837,9 +16868,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1021 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" + // Pos:1023 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" { - ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 621, + ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 623, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -16853,9 +16884,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1022 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" + // Pos:1024 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" { - ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 622, + ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 624, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, @@ -16869,9 +16900,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1023 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" + // Pos:1025 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" { - ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 622, + ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 624, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, @@ -16885,9 +16916,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1024 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" + // Pos:1026 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" { - ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 623, + ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 625, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16901,9 +16932,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1025 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" + // Pos:1027 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" { - ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 623, + ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 625, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16917,9 +16948,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1026 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" + // Pos:1028 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" { - ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 623, + ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 625, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16933,9 +16964,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1027 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" + // Pos:1029 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" { - ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 623, + ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 625, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16949,9 +16980,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1028 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" + // Pos:1030 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" { - ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 624, + ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 626, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16965,9 +16996,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1029 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" + // Pos:1031 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" { - ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 625, + ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 627, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -16981,9 +17012,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1030 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" + // Pos:1032 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" { - ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 625, + ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 627, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -16997,9 +17028,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1031 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" + // Pos:1033 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" { - ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 625, + ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 627, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17013,9 +17044,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1032 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" + // Pos:1034 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" { - ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 625, + ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 627, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17029,9 +17060,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1033 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" + // Pos:1035 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" { - ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 626, + ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 628, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17045,9 +17076,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1034 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" + // Pos:1036 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" { - ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 626, + ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 628, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17061,9 +17092,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1035 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" + // Pos:1037 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" { - ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 626, + ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 628, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17077,9 +17108,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1036 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" + // Pos:1038 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" { - ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 626, + ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 628, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17093,9 +17124,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1037 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" + // Pos:1039 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" { - ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 627, + ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 629, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, @@ -17109,9 +17140,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1038 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" + // Pos:1040 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" { - ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 628, + ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 630, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17125,9 +17156,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1039 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" + // Pos:1041 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" { - ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 628, + ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 630, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17141,9 +17172,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1040 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" + // Pos:1042 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" { - ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 628, + ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 630, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17157,9 +17188,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1041 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" + // Pos:1043 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" { - ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 628, + ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 630, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17173,9 +17204,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1042 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" + // Pos:1044 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" { - ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 629, + ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 631, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17189,9 +17220,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1043 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" + // Pos:1045 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" { - ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 629, + ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 631, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17205,9 +17236,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1044 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" + // Pos:1046 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" { - ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 629, + ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 631, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17221,9 +17252,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1045 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" + // Pos:1047 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" { - ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 629, + ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 631, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17237,9 +17268,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1046 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" + // Pos:1048 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" { - ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 630, + ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 632, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17253,9 +17284,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1047 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" + // Pos:1049 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" { - ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 630, + ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 632, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17269,9 +17300,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1048 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" + // Pos:1050 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" { - ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 630, + ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 632, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17285,9 +17316,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1049 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" + // Pos:1051 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" { - ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 630, + ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 632, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17301,9 +17332,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1050 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" + // Pos:1052 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" { - ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 631, + ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 633, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17317,9 +17348,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1051 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" + // Pos:1053 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" { - ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 632, + ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 634, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17333,9 +17364,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1052 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" + // Pos:1054 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" { - ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 632, + ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 634, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17349,9 +17380,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1053 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" + // Pos:1055 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" { - ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 632, + ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 634, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17365,9 +17396,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1054 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" + // Pos:1056 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" { - ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 632, + ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 634, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17381,9 +17412,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1055 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" + // Pos:1057 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" { - ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 633, + ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 635, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17397,9 +17428,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1056 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" + // Pos:1058 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" { - ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 633, + ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 635, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17413,9 +17444,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1057 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" + // Pos:1059 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" { - ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 633, + ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 635, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17429,9 +17460,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1058 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" + // Pos:1060 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" { - ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 633, + ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 635, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17445,9 +17476,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1059 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" + // Pos:1061 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" { - ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 634, + ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 636, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17461,9 +17492,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1060 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" + // Pos:1062 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" { - ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 634, + ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 636, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17477,9 +17508,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1061 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" + // Pos:1063 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" { - ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 635, + ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 637, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17493,9 +17524,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1062 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" + // Pos:1064 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" { - ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 635, + ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 637, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17509,9 +17540,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1063 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" + // Pos:1065 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" { - ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 636, + ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 638, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17525,9 +17556,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1064 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" + // Pos:1066 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" { - ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 636, + ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 638, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17541,9 +17572,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1065 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" + // Pos:1067 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" { - ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 637, + ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 639, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17557,9 +17588,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1066 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" + // Pos:1068 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" { - ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 637, + ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 639, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17573,9 +17604,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1067 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" + // Pos:1069 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" { - ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 638, + ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 640, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17589,9 +17620,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1068 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" + // Pos:1070 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" { - ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 638, + ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 640, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17605,9 +17636,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1069 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" + // Pos:1071 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" { - ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 639, + ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 641, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17621,9 +17652,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1070 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" + // Pos:1072 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" { - ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 639, + ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 641, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17637,9 +17668,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1071 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" + // Pos:1073 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" { - ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 640, + ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 642, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17653,9 +17684,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1072 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" + // Pos:1074 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" { - ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 640, + ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 642, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17669,9 +17700,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1073 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" + // Pos:1075 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" { - ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 641, + ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 643, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17685,9 +17716,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1074 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" + // Pos:1076 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" { - ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 641, + ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 643, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17701,9 +17732,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1075 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" + // Pos:1077 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" { - ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 642, + ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 644, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, @@ -17717,9 +17748,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1076 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" + // Pos:1078 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" { - ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 643, + ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 645, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -17734,9 +17765,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1077 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" + // Pos:1079 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" { - ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 644, + ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 646, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NO66|ND_FLAG_MODRM, ND_CFF_PTWRITE, @@ -17749,9 +17780,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1078 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" + // Pos:1080 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" { - ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 645, + ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 647, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17765,9 +17796,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1079 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" + // Pos:1081 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" { - ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 645, + ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 647, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17781,9 +17812,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1080 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" + // Pos:1082 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" { - ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 646, + ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 648, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17797,9 +17828,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1081 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" + // Pos:1083 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" { - ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 646, + ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 648, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17813,9 +17844,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1082 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" + // Pos:1084 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" { - ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 647, + ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 649, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17829,9 +17860,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1083 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" + // Pos:1085 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" { - ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 648, + ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 650, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17845,9 +17876,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1084 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" + // Pos:1086 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" { - ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 648, + ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 650, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17861,9 +17892,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1085 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" + // Pos:1087 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" { - ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 649, + ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 651, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17877,9 +17908,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1086 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" + // Pos:1088 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" { - ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 649, + ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 651, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17893,9 +17924,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1087 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" + // Pos:1089 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" { - ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 650, + ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 652, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17909,9 +17940,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1088 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" + // Pos:1090 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" { - ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 650, + ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 652, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17925,9 +17956,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1089 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" + // Pos:1091 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" { - ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 651, + ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 653, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17941,9 +17972,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1090 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" + // Pos:1092 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" { - ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 652, + ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 654, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -17957,9 +17988,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1091 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" + // Pos:1093 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" { - ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 652, + ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 654, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -17973,9 +18004,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1092 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" + // Pos:1094 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -17989,9 +18020,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1093 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" + // Pos:1095 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18005,9 +18036,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1094 Instruction:"PUSH ES" Encoding:"0x06"/"" + // Pos:1096 Instruction:"PUSH ES" Encoding:"0x06"/"" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -18021,9 +18052,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1095 Instruction:"PUSH CS" Encoding:"0x0E"/"" + // Pos:1097 Instruction:"PUSH CS" Encoding:"0x0E"/"" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -18037,9 +18068,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1096 Instruction:"PUSH SS" Encoding:"0x16"/"" + // Pos:1098 Instruction:"PUSH SS" Encoding:"0x16"/"" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -18053,9 +18084,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1097 Instruction:"PUSH DS" Encoding:"0x1E"/"" + // Pos:1099 Instruction:"PUSH DS" Encoding:"0x1E"/"" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -18069,9 +18100,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1098 Instruction:"PUSH Zv" Encoding:"0x50"/"O" + // Pos:1100 Instruction:"PUSH Zv" Encoding:"0x50"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18085,9 +18116,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1099 Instruction:"PUSH Zv" Encoding:"0x51"/"O" + // Pos:1101 Instruction:"PUSH Zv" Encoding:"0x51"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18101,9 +18132,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1100 Instruction:"PUSH Zv" Encoding:"0x52"/"O" + // Pos:1102 Instruction:"PUSH Zv" Encoding:"0x52"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18117,9 +18148,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1101 Instruction:"PUSH Zv" Encoding:"0x53"/"O" + // Pos:1103 Instruction:"PUSH Zv" Encoding:"0x53"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18133,9 +18164,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1102 Instruction:"PUSH Zv" Encoding:"0x54"/"O" + // Pos:1104 Instruction:"PUSH Zv" Encoding:"0x54"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18149,9 +18180,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1103 Instruction:"PUSH Zv" Encoding:"0x55"/"O" + // Pos:1105 Instruction:"PUSH Zv" Encoding:"0x55"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18165,9 +18196,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1104 Instruction:"PUSH Zv" Encoding:"0x56"/"O" + // Pos:1106 Instruction:"PUSH Zv" Encoding:"0x56"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18181,9 +18212,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1105 Instruction:"PUSH Zv" Encoding:"0x57"/"O" + // Pos:1107 Instruction:"PUSH Zv" Encoding:"0x57"/"O" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18197,9 +18228,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1106 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" + // Pos:1108 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18213,9 +18244,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1107 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" + // Pos:1109 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18229,9 +18260,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1108 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" + // Pos:1110 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, @@ -18245,9 +18276,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1109 Instruction:"PUSHA" Encoding:"ds16 0x60"/"" + // Pos:1111 Instruction:"PUSHA" Encoding:"ds16 0x60"/"" { - ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 654, + ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 656, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -18261,9 +18292,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1110 Instruction:"PUSHAD" Encoding:"ds32 0x60"/"" + // Pos:1112 Instruction:"PUSHAD" Encoding:"ds32 0x60"/"" { - ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 655, + ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 657, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, @@ -18277,9 +18308,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1111 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" + // Pos:1113 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" { - ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 656, + ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 658, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18293,9 +18324,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1112 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" + // Pos:1114 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" { - ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 657, + ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 659, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18309,9 +18340,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1113 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" + // Pos:1115 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" { - ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 658, + ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 660, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, @@ -18325,9 +18356,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1114 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" + // Pos:1116 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" { - ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 659, + ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 661, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, @@ -18343,9 +18374,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1115 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" + // Pos:1117 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" { - ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 660, + ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 662, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, @@ -18359,9 +18390,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1116 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" + // Pos:1118 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" { - ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 660, + ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 662, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -18375,9 +18406,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1117 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" + // Pos:1119 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 663, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18392,9 +18423,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1118 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" + // Pos:1120 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 663, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18409,9 +18440,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1119 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" + // Pos:1121 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 663, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18426,9 +18457,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1120 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" + // Pos:1122 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 663, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18443,9 +18474,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1121 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" + // Pos:1123 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 663, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18460,9 +18491,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1122 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" + // Pos:1124 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 663, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18477,9 +18508,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1123 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" + // Pos:1125 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" { - ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 662, + ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 664, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -18493,9 +18524,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1124 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" + // Pos:1126 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" { - ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 663, + ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 665, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -18509,9 +18540,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1125 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" + // Pos:1127 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 666, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18526,9 +18557,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1126 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" + // Pos:1128 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 666, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18543,9 +18574,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1127 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" + // Pos:1129 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 666, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18560,9 +18591,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1128 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" + // Pos:1130 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 666, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18577,9 +18608,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1129 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" + // Pos:1131 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 666, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18594,9 +18625,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1130 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" + // Pos:1132 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 666, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18611,9 +18642,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1131 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M" + // Pos:1133 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M" { - ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 665, + ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 667, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, @@ -18627,9 +18658,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1132 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M" + // Pos:1134 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M" { - ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 666, + ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 668, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, @@ -18643,9 +18674,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1133 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" + // Pos:1135 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" { - ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 667, + ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 669, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MSR, @@ -18661,9 +18692,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1134 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" + // Pos:1136 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" { - ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 668, + ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 670, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPID, @@ -18677,9 +18708,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1135 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" + // Pos:1137 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" { - ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 669, + ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 671, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, @@ -18695,9 +18726,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1136 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" + // Pos:1138 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" { - ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 670, + ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 672, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -18713,9 +18744,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1137 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/"" + // Pos:1139 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/"" { - ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 671, + ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 673, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, @@ -18731,9 +18762,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1138 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M" + // Pos:1140 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M" { - ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 672, + ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 674, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, @@ -18747,9 +18778,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1139 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" + // Pos:1141 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" { - ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 672, + ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 674, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, @@ -18763,9 +18794,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1140 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M" + // Pos:1142 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M" { - ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 673, + ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 675, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, @@ -18779,9 +18810,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1141 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" + // Pos:1143 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" { - ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 673, + ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 675, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, @@ -18795,9 +18826,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1142 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M" + // Pos:1144 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M" { - ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 674, + ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 676, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -18810,9 +18841,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1143 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M" + // Pos:1145 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M" { - ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 675, + ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 677, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -18826,9 +18857,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1144 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M" + // Pos:1146 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M" { - ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 676, + ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -18842,9 +18873,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1145 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" + // Pos:1147 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" { - ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 677, + ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 679, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -18859,9 +18890,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1146 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" + // Pos:1148 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" { - ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 678, + ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 680, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDTSCP, @@ -18878,9 +18909,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1147 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" + // Pos:1149 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" { - ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 679, + ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 681, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -18897,9 +18928,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1148 Instruction:"RETF" Encoding:"0xCB"/"" + // Pos:1150 Instruction:"RETF" Encoding:"0xCB"/"" { - ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 679, + ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 681, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, @@ -18915,9 +18946,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1149 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" + // Pos:1151 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" { - ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 680, + ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 682, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -18934,9 +18965,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1150 Instruction:"RETN" Encoding:"0xC3"/"" + // Pos:1152 Instruction:"RETN" Encoding:"0xC3"/"" { - ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 680, + ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 682, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, @@ -18951,9 +18982,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1151 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" + // Pos:1153 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" { - ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 681, + ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 683, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, @@ -18969,9 +19000,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1152 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" + // Pos:1154 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" { - ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 682, + ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 684, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, @@ -18986,9 +19017,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1153 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" + // Pos:1155 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 685, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19003,9 +19034,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1154 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" + // Pos:1156 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 685, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19020,9 +19051,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1155 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" + // Pos:1157 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 685, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19037,9 +19068,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1156 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" + // Pos:1158 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 685, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19054,9 +19085,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1157 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" + // Pos:1159 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 685, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19071,9 +19102,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1158 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" + // Pos:1160 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 685, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19088,9 +19119,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1159 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" + // Pos:1161 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19105,9 +19136,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1160 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" + // Pos:1162 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19122,9 +19153,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1161 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" + // Pos:1163 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19139,9 +19170,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1162 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" + // Pos:1164 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19156,9 +19187,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1163 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" + // Pos:1165 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19173,9 +19204,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1164 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" + // Pos:1166 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19190,9 +19221,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1165 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" + // Pos:1167 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" { - ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 685, + ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 687, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -19207,9 +19238,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1166 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" + // Pos:1168 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" { - ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 686, + ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 688, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -19224,9 +19255,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1167 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" + // Pos:1169 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" { - ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 687, + ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 689, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -19241,9 +19272,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1168 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" + // Pos:1170 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" { - ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 688, + ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 690, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -19258,9 +19289,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1169 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" + // Pos:1171 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" { - ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 689, + ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 691, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -19275,9 +19306,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1170 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM" + // Pos:1172 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM" { - ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 690, + ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 692, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19291,9 +19322,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1171 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M" + // Pos:1173 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M" { - ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 691, + ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 693, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19306,9 +19337,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1172 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" + // Pos:1174 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" { - ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 692, + ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 694, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -19323,9 +19354,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1173 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" + // Pos:1175 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" { - ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 693, + ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 695, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -19339,9 +19370,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1174 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" + // Pos:1176 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" { - ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 694, + ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 696, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -19355,9 +19386,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1175 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" + // Pos:1177 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" { - ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 695, + ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 697, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -19371,9 +19402,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1176 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M" + // Pos:1178 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M" { - ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 696, + ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 698, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19386,9 +19417,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1177 Instruction:"SAHF" Encoding:"0x9E"/"" + // Pos:1179 Instruction:"SAHF" Encoding:"0x9E"/"" { - ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 697, + ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 699, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19402,9 +19433,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1178 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" + // Pos:1180 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 700, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19419,9 +19450,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1179 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" + // Pos:1181 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 700, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19436,9 +19467,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1180 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" + // Pos:1182 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 700, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19453,9 +19484,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1181 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" + // Pos:1183 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 700, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19470,9 +19501,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1182 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" + // Pos:1184 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 700, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19487,9 +19518,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1183 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" + // Pos:1185 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 700, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19504,9 +19535,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1184 Instruction:"SALC" Encoding:"0xD6"/"" + // Pos:1186 Instruction:"SALC" Encoding:"0xD6"/"" { - ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 699, + ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 701, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19520,9 +19551,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1185 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" + // Pos:1187 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19537,9 +19568,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1186 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" + // Pos:1188 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19554,9 +19585,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1187 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" + // Pos:1189 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19571,9 +19602,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1188 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" + // Pos:1190 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19588,9 +19619,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1189 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" + // Pos:1191 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19605,9 +19636,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1190 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" + // Pos:1192 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19622,9 +19653,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1191 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" + // Pos:1193 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" { - ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 701, + ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 703, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -19639,9 +19670,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1192 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" + // Pos:1194 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" { - ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 702, + ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 704, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -19655,9 +19686,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1193 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" + // Pos:1195 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 705, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19672,9 +19703,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1194 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" + // Pos:1196 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 705, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19689,9 +19720,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1195 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" + // Pos:1197 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 705, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19706,9 +19737,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1196 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" + // Pos:1198 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 705, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19723,9 +19754,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1197 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" + // Pos:1199 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 705, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19740,9 +19771,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1198 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" + // Pos:1200 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 705, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19757,9 +19788,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1199 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" + // Pos:1201 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 705, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19774,9 +19805,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1200 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" + // Pos:1202 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 705, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19791,9 +19822,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1201 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" + // Pos:1203 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 705, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -19808,9 +19839,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1202 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" + // Pos:1204 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 705, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19825,9 +19856,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1203 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" + // Pos:1205 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 704, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 706, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19843,9 +19874,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1204 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" + // Pos:1206 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 704, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 706, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19862,9 +19893,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1205 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" + // Pos:1207 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 705, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 707, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19880,9 +19911,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1206 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" + // Pos:1208 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 705, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 707, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19899,9 +19930,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1207 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" + // Pos:1209 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 706, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 708, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19917,9 +19948,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1208 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" + // Pos:1210 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 706, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 708, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19936,9 +19967,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1209 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" + // Pos:1211 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 707, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 709, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19954,9 +19985,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1210 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" + // Pos:1212 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 707, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 709, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -19973,9 +20004,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1211 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" + // Pos:1213 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" { - ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 708, + ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 710, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -19988,9 +20019,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1212 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" + // Pos:1214 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" { - ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 709, + ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 711, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -20007,9 +20038,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1213 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" + // Pos:1215 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" { - ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 710, + ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 712, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -20022,9 +20053,24 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1214 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" + // Pos:1216 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M" { - ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 711, + ND_INS_SENDUIPI, ND_CAT_UINTR, ND_SET_UINTR, 713, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1217 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" + { + ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 714, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_SERIALIZE, @@ -20037,9 +20083,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1215 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" + // Pos:1218 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 712, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 715, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20053,9 +20099,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1216 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" + // Pos:1219 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 713, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 716, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20069,9 +20115,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1217 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" + // Pos:1220 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 714, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 717, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20085,9 +20131,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1218 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" + // Pos:1221 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 715, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 718, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20101,9 +20147,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1219 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" + // Pos:1222 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 716, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 719, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20117,9 +20163,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1220 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" + // Pos:1223 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 717, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 720, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20133,9 +20179,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1221 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" + // Pos:1224 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 718, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 721, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20149,9 +20195,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1222 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" + // Pos:1225 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 719, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 722, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20165,9 +20211,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1223 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" + // Pos:1226 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 720, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 723, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20181,9 +20227,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1224 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" + // Pos:1227 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 721, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 724, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20197,9 +20243,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1225 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" + // Pos:1228 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 722, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 725, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20213,9 +20259,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1226 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" + // Pos:1229 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 723, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20229,9 +20275,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1227 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" + // Pos:1230 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 724, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 727, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20245,9 +20291,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1228 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" + // Pos:1231 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 725, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 728, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20261,9 +20307,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1229 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" + // Pos:1232 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 726, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 729, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20277,9 +20323,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1230 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" + // Pos:1233 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" { - ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 727, + ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 730, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -20293,9 +20339,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1231 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" + // Pos:1234 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 728, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 731, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20309,9 +20355,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1232 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" + // Pos:1235 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" { - ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 729, + ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 732, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -20324,9 +20370,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1233 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" + // Pos:1236 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" { - ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 730, + ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 733, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20340,9 +20386,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1234 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" + // Pos:1237 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" { - ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 731, + ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 734, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20356,9 +20402,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1235 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" + // Pos:1238 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" { - ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 732, + ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 735, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20372,9 +20418,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1236 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" + // Pos:1239 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" { - ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 733, + ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 736, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20388,9 +20434,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1237 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" + // Pos:1240 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" { - ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 734, + ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 737, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20405,9 +20451,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1238 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" + // Pos:1241 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" { - ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 735, + ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 738, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20421,9 +20467,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1239 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" + // Pos:1242 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" { - ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 736, + ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 739, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20437,9 +20483,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1240 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" + // Pos:1243 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" { - ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 737, + ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 740, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -20454,9 +20500,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1241 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" + // Pos:1244 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 738, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 741, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20471,9 +20517,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1242 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" + // Pos:1245 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 738, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 741, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20488,9 +20534,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1243 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" + // Pos:1246 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 738, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 741, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20505,9 +20551,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1244 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" + // Pos:1247 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 738, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 741, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20522,9 +20568,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1245 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" + // Pos:1248 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 738, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 741, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20539,9 +20585,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1246 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" + // Pos:1249 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 738, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 741, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20556,9 +20602,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1247 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" + // Pos:1250 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" { - ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 739, + ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 742, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20574,9 +20620,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1248 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" + // Pos:1251 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" { - ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 739, + ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 742, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20592,9 +20638,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1249 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" + // Pos:1252 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" { - ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 740, + ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 743, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -20609,9 +20655,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1250 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" + // Pos:1253 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 741, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 744, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20626,9 +20672,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1251 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" + // Pos:1254 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 741, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 744, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20643,9 +20689,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1252 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" + // Pos:1255 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 741, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 744, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20660,9 +20706,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1253 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" + // Pos:1256 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 741, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 744, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20677,9 +20723,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1254 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" + // Pos:1257 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 741, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 744, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20694,9 +20740,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1255 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" + // Pos:1258 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 741, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 744, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20711,9 +20757,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1256 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" + // Pos:1259 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" { - ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 742, + ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 745, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20729,9 +20775,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1257 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" + // Pos:1260 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" { - ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 742, + ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 745, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20747,9 +20793,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1258 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" + // Pos:1261 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" { - ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 743, + ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 746, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -20764,9 +20810,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1259 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" + // Pos:1262 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" { - ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 744, + ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 747, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -20781,9 +20827,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1260 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" + // Pos:1263 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" { - ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 745, + ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 748, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -20798,9 +20844,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1261 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" + // Pos:1264 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" { - ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 746, + ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 749, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20814,9 +20860,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1262 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" + // Pos:1265 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" { - ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 747, + ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 750, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -20829,9 +20875,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1263 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" + // Pos:1266 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" { - ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 748, + ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 751, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20845,9 +20891,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1264 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" + // Pos:1267 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" { - ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 748, + ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 751, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20861,9 +20907,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1265 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" + // Pos:1268 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" { - ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 749, + ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 752, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, @@ -20876,9 +20922,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1266 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/"" + // Pos:1269 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/"" { - ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 750, + ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 753, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20891,9 +20937,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1267 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" + // Pos:1270 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" { - ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 751, + ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 754, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20907,9 +20953,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1268 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" + // Pos:1271 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" { - ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 751, + ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 754, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20923,9 +20969,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1269 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" + // Pos:1272 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" { - ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 752, + ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 755, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20938,9 +20984,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1270 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" + // Pos:1273 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 753, + ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 756, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -20954,9 +21000,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1271 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" + // Pos:1274 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 754, + ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 757, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -20970,9 +21016,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1272 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" + // Pos:1275 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 755, + ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 758, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -20986,9 +21032,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1273 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" + // Pos:1276 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 756, + ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 759, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -21002,9 +21048,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1274 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" + // Pos:1277 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" { - ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 757, + ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 760, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, @@ -21017,9 +21063,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1275 Instruction:"STC" Encoding:"0xF9"/"" + // Pos:1278 Instruction:"STC" Encoding:"0xF9"/"" { - ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 758, + ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 761, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21032,9 +21078,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1276 Instruction:"STD" Encoding:"0xFD"/"" + // Pos:1279 Instruction:"STD" Encoding:"0xFD"/"" { - ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 759, + ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 762, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21047,9 +21093,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1277 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" + // Pos:1280 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" { - ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 760, + ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 763, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -21062,9 +21108,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1278 Instruction:"STI" Encoding:"0xFB"/"" + // Pos:1281 Instruction:"STI" Encoding:"0xFB"/"" { - ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 761, + ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 764, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21077,9 +21123,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1279 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" + // Pos:1282 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" { - ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 762, + ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 765, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -21093,9 +21139,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1280 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" + // Pos:1283 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 763, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 766, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21111,9 +21157,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1281 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" + // Pos:1284 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 763, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 766, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21130,9 +21176,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1282 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" + // Pos:1285 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 764, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 767, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21148,9 +21194,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1283 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" + // Pos:1286 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 764, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 767, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21167,9 +21213,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1284 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" + // Pos:1287 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 765, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 768, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21185,9 +21231,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1285 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" + // Pos:1288 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 765, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 768, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21204,9 +21250,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1286 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" + // Pos:1289 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 766, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 769, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21222,9 +21268,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1287 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" + // Pos:1290 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 766, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 769, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21241,9 +21287,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1288 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" + // Pos:1291 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" { - ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 767, + ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 770, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21257,9 +21303,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1289 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" + // Pos:1292 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" { - ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 767, + ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 770, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21273,9 +21319,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1290 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" + // Pos:1293 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" { - ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 768, + ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 771, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -21288,9 +21334,24 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1291 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" + // Pos:1294 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/"" + { + ND_INS_STUI, ND_CAT_UINTR, ND_SET_UINTR, 772, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1295 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 773, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21305,9 +21366,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1292 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" + // Pos:1296 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 773, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21322,9 +21383,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1293 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" + // Pos:1297 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 773, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21339,9 +21400,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1294 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" + // Pos:1298 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 773, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21356,9 +21417,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1295 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" + // Pos:1299 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 773, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21373,9 +21434,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1296 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" + // Pos:1300 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 773, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21390,9 +21451,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1297 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" + // Pos:1301 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 773, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21407,9 +21468,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1298 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" + // Pos:1302 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 773, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21424,9 +21485,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1299 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" + // Pos:1303 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 773, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -21441,9 +21502,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1300 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" + // Pos:1304 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 773, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21458,9 +21519,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1301 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" + // Pos:1305 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" { - ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 770, + ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 774, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -21474,9 +21535,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1302 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" + // Pos:1306 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" { - ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 771, + ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 775, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -21490,9 +21551,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1303 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" + // Pos:1307 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" { - ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 772, + ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 776, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -21506,9 +21567,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1304 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" + // Pos:1308 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" { - ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 773, + ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 777, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -21522,9 +21583,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1305 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR" + // Pos:1309 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR" { - ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 774, + ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 778, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21538,9 +21599,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1306 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M" + // Pos:1310 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M" { - ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 775, + ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 779, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21553,9 +21614,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1307 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M" + // Pos:1311 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M" { - ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 776, + ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 780, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21568,9 +21629,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1308 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" + // Pos:1312 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" { - ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 777, + ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 781, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -21584,9 +21645,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1309 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" + // Pos:1313 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" { - ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 778, + ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 782, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 10), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_FSC, @@ -21608,9 +21669,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1310 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" + // Pos:1314 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" { - ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 779, + ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 783, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SEP, @@ -21631,9 +21692,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1311 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" + // Pos:1315 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" { - ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 780, + ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 784, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_SEP, @@ -21650,9 +21711,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1312 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" + // Pos:1316 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" { - ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 781, + ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 785, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_FSC, @@ -21672,9 +21733,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1313 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" + // Pos:1317 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" { - ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 782, + ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 786, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -21688,9 +21749,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1314 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" + // Pos:1318 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" { - ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 783, + ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 787, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21703,9 +21764,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1315 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" + // Pos:1319 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" { - ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 784, + ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 788, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, @@ -21720,9 +21781,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1316 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" + // Pos:1320 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 785, + ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 789, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, @@ -21737,9 +21798,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1317 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" + // Pos:1321 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 786, + ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 790, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, @@ -21754,9 +21815,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1318 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" + // Pos:1322 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 787, + ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 791, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, @@ -21771,9 +21832,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1319 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" + // Pos:1323 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 788, + ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 792, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, @@ -21788,9 +21849,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1320 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" + // Pos:1324 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 793, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21805,9 +21866,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1321 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" + // Pos:1325 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 793, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21822,9 +21883,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1322 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" + // Pos:1326 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 793, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21839,9 +21900,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1323 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" + // Pos:1327 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 793, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21856,9 +21917,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1324 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" + // Pos:1328 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 793, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21873,9 +21934,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1325 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" + // Pos:1329 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 793, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21890,9 +21951,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1326 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" + // Pos:1330 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 793, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21907,9 +21968,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1327 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" + // Pos:1331 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 793, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21924,9 +21985,25 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1328 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:1332 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/"" + { + ND_INS_TESTUI, ND_CAT_UINTR, ND_SET_UINTR, 794, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, + 0, + 0|NDR_RFLAG_CF, + 0, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + { + OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1333 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" { - ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 790, + ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 795, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -21940,9 +22017,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1329 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:1334 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" { - ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 791, + ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 796, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -21956,9 +22033,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1330 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" + // Pos:1335 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" { - ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 792, + ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 797, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -21971,9 +22048,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1331 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:1336 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" { - ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 793, + ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 798, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -21987,9 +22064,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1332 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" + // Pos:1337 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" { - ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 794, + ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 799, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -22002,9 +22079,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1333 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/"" + // Pos:1338 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/"" { - ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 795, + ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 800, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, @@ -22017,9 +22094,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1334 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" + // Pos:1339 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" { - ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 796, + ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 801, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, @@ -22035,9 +22112,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1335 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM" + // Pos:1340 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM" { - ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 797, + ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 802, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, @@ -22052,9 +22129,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1336 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" + // Pos:1341 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" { - ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 798, + ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 803, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -22068,9 +22145,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1337 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" + // Pos:1342 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" { - ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 799, + ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 804, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -22085,9 +22162,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1338 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" + // Pos:1343 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" { - ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 800, + ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 805, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -22102,9 +22179,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1339 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" + // Pos:1344 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" { - ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 801, + ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 806, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22118,9 +22195,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1340 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" + // Pos:1345 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" { - ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 802, + ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 807, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22134,9 +22211,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1341 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" + // Pos:1346 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" { - ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 803, + ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 808, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -22149,9 +22226,29 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1342 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" + // Pos:1347 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/"" { - ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 804, + ND_INS_UIRET, ND_CAT_UINTR, ND_SET_UINTR, 809, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 6), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1348 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" + { + ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 810, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, @@ -22165,9 +22262,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1343 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" + // Pos:1349 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" { - ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 805, + ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 811, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, @@ -22182,9 +22279,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1344 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" + // Pos:1350 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" { - ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 806, + ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 812, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -22198,9 +22295,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1345 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" + // Pos:1351 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" { - ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 807, + ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 813, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -22214,9 +22311,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1346 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" + // Pos:1352 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" { - ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 808, + ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 814, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -22230,9 +22327,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1347 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" + // Pos:1353 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" { - ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 809, + ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 815, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -22246,9 +22343,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1348 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" + // Pos:1354 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" { - ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 810, + ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 816, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, @@ -22264,9 +22361,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1349 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" + // Pos:1355 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" { - ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 811, + ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 817, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, @@ -22282,9 +22379,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1350 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" + // Pos:1356 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" { - ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 812, + ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 818, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, @@ -22300,9 +22397,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1351 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" + // Pos:1357 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" { - ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 813, + ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 819, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, @@ -22318,9 +22415,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1352 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" + // Pos:1358 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" { - ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 814, + ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 820, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22336,9 +22433,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1353 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" + // Pos:1359 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" { - ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 814, + ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 820, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22353,9 +22450,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1354 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" + // Pos:1360 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" { - ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 815, + ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 821, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22371,9 +22468,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1355 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" + // Pos:1361 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" { - ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 815, + ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 821, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22388,9 +22485,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1356 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" + // Pos:1362 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" { - ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 816, + ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 822, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22406,9 +22503,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1357 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" + // Pos:1363 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" { - ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 816, + ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 822, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22423,9 +22520,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1358 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" + // Pos:1364 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" { - ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 817, + ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 823, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22441,9 +22538,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1359 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" + // Pos:1365 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" { - ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 817, + ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 823, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22458,9 +22555,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1360 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" + // Pos:1366 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" { - ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 818, + ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 824, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22475,9 +22572,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1361 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" + // Pos:1367 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" { - ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 819, + ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 825, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22492,9 +22589,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1362 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:1368 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { - ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 820, + ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 826, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, @@ -22509,9 +22606,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1363 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:1369 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { - ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 820, + ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 826, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -22526,9 +22623,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1364 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:1370 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { - ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 821, + ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 827, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, @@ -22543,9 +22640,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1365 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:1371 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { - ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 821, + ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 827, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -22560,9 +22657,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1366 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:1372 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { - ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 822, + ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 828, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, @@ -22577,9 +22674,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1367 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:1373 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { - ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 822, + ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 828, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -22594,9 +22691,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1368 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:1374 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { - ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 823, + ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 829, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, @@ -22611,9 +22708,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1369 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:1375 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { - ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 823, + ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 829, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -22628,9 +22725,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1370 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" + // Pos:1376 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" { - ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 824, + ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 830, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -22644,9 +22741,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1371 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" + // Pos:1377 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" { - ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 825, + ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 831, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -22661,9 +22758,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1372 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" + // Pos:1378 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" { - ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 826, + ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 832, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22680,9 +22777,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1373 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" + // Pos:1379 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" { - ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 827, + ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 833, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22699,9 +22796,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1374 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" + // Pos:1380 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" { - ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 828, + ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 834, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -22717,9 +22814,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1375 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" + // Pos:1381 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" { - ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 828, + ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 834, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22734,9 +22831,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1376 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" + // Pos:1382 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" { - ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 829, + ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 835, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -22752,9 +22849,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1377 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" + // Pos:1383 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" { - ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 829, + ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 835, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22769,9 +22866,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1378 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" + // Pos:1384 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" { - ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 830, + ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 836, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -22787,9 +22884,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1379 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" + // Pos:1385 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" { - ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 830, + ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 836, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22804,9 +22901,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1380 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" + // Pos:1386 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" { - ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 831, + ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 837, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -22822,9 +22919,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1381 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" + // Pos:1387 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" { - ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 831, + ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 837, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22839,9 +22936,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1382 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" + // Pos:1388 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" { - ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 832, + ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 838, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22857,9 +22954,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1383 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" + // Pos:1389 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" { - ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 833, + ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 839, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22875,9 +22972,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1384 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" + // Pos:1390 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" { - ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 834, + ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 840, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22893,9 +22990,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1385 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" + // Pos:1391 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" { - ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 835, + ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 841, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22911,9 +23008,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1386 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" + // Pos:1392 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" { - ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 836, + ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 842, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22929,9 +23026,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1387 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" + // Pos:1393 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" { - ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 837, + ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 843, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22947,9 +23044,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1388 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" + // Pos:1394 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" { - ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 838, + ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 844, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -22963,9 +23060,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1389 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" + // Pos:1395 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" { - ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 839, + ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 845, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -22980,9 +23077,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1390 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" + // Pos:1396 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" { - ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 840, + ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 846, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -22997,9 +23094,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1391 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" + // Pos:1397 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" { - ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 841, + ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 847, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23014,9 +23111,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1392 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" + // Pos:1398 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" { - ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 842, + ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 848, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23031,9 +23128,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1393 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" + // Pos:1399 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" { - ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 843, + ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 849, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23048,9 +23145,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1394 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" + // Pos:1400 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" { - ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 844, + ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 850, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -23064,9 +23161,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1395 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" + // Pos:1401 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" { - ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 845, + ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 851, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23081,9 +23178,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1396 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" + // Pos:1402 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" { - ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 846, + ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 852, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23098,9 +23195,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1397 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" + // Pos:1403 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" { - ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 847, + ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 853, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23115,9 +23212,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1398 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" + // Pos:1404 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" { - ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 848, + ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 854, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23132,9 +23229,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1399 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" + // Pos:1405 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" { - ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 849, + ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 855, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23149,9 +23246,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1400 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" + // Pos:1406 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" { - ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 850, + ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 856, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23166,9 +23263,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1401 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" + // Pos:1407 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" { - ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 850, + ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 856, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23182,9 +23279,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1402 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" + // Pos:1408 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" { - ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 851, + ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 857, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23199,9 +23296,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1403 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" + // Pos:1409 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" { - ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 851, + ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 857, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23215,9 +23312,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1404 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" + // Pos:1410 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 852, + ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 858, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23234,9 +23331,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1405 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" + // Pos:1411 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 852, + ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 858, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23252,9 +23349,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1406 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:1412 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 853, + ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 859, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23271,9 +23368,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1407 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:1413 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 853, + ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 859, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23289,9 +23386,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1408 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" + // Pos:1414 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 854, + ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 860, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23308,9 +23405,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1409 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:1415 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 854, + ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 860, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23326,9 +23423,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1410 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:1416 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 855, + ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 861, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23345,9 +23442,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1411 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:1417 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 855, + ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 861, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23363,9 +23460,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1412 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" + // Pos:1418 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" { - ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 856, + ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 862, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23380,9 +23477,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1413 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" + // Pos:1419 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" { - ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 856, + ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 862, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23397,9 +23494,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1414 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" + // Pos:1420 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" { - ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 857, + ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 863, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23414,9 +23511,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1415 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" + // Pos:1421 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" { - ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 857, + ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 863, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23431,9 +23528,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1416 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" + // Pos:1422 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" { - ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 858, + ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 864, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23448,9 +23545,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1417 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" + // Pos:1423 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" { - ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 859, + ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 865, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23465,9 +23562,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1418 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" + // Pos:1424 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 860, + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 866, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23482,9 +23579,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1419 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" + // Pos:1425 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 860, + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 866, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23498,9 +23595,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1420 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" + // Pos:1426 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 860, + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 866, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23514,9 +23611,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1421 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" + // Pos:1427 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 861, + ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 867, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23531,9 +23628,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1422 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" + // Pos:1428 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" { - ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 861, + ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 867, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23547,9 +23644,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1423 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" + // Pos:1429 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" { - ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 862, + ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 868, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, @@ -23565,9 +23662,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1424 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" + // Pos:1430 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" { - ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 863, + ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 869, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, @@ -23582,9 +23679,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1425 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" + // Pos:1431 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" { - ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 864, + ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 870, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23599,9 +23696,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1426 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" + // Pos:1432 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" { - ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 864, + ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 870, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23615,9 +23712,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1427 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" + // Pos:1433 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 865, + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 871, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23632,9 +23729,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1428 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" + // Pos:1434 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 865, + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 871, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23648,9 +23745,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1429 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" + // Pos:1435 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 865, + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 871, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23664,9 +23761,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1430 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" + // Pos:1436 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" { - ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 866, + ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 872, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23681,9 +23778,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1431 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" + // Pos:1437 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" { - ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 867, + ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 873, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23698,9 +23795,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1432 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" + // Pos:1438 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" { - ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 868, + ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 874, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23715,9 +23812,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1433 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" + // Pos:1439 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 869, + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 875, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23732,9 +23829,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1434 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" + // Pos:1440 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 869, + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 875, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, @@ -23748,9 +23845,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1435 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" + // Pos:1441 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 869, + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 875, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, @@ -23764,9 +23861,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1436 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" + // Pos:1442 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 870, + ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 876, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23781,9 +23878,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1437 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" + // Pos:1443 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" { - ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 870, + ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 876, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23797,9 +23894,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1438 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" + // Pos:1444 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 871, + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 877, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23814,9 +23911,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1439 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" + // Pos:1445 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 871, + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 877, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23830,9 +23927,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1440 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" + // Pos:1446 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 871, + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 877, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23846,9 +23943,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1441 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" + // Pos:1447 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 872, + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 878, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23864,9 +23961,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1442 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" + // Pos:1448 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 872, + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 878, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, @@ -23881,9 +23978,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1443 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" + // Pos:1449 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 872, + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 878, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, @@ -23898,9 +23995,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1444 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" + // Pos:1450 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" { - ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 873, + ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 879, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23915,9 +24012,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1445 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" + // Pos:1451 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 874, + ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 880, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23932,9 +24029,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1446 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:1452 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 875, + ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 881, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23949,9 +24046,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1447 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" + // Pos:1453 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" { - ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 876, + ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 882, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23966,9 +24063,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1448 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" + // Pos:1454 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" { - ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 877, + ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 883, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23983,9 +24080,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1449 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" + // Pos:1455 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 878, + ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 884, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23999,9 +24096,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1450 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" + // Pos:1456 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 878, + ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 884, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24015,9 +24112,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1451 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" + // Pos:1457 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" { - ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 879, + ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 885, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24033,9 +24130,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1452 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" + // Pos:1458 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" { - ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 879, + ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 885, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24050,9 +24147,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1453 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" + // Pos:1459 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" { - ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 880, + ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 886, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24066,9 +24163,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1454 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" + // Pos:1460 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 881, + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 887, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24083,9 +24180,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1455 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" + // Pos:1461 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 881, + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 887, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24100,9 +24197,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1456 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" + // Pos:1462 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 881, + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 887, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24117,9 +24214,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1457 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:1463 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 882, + ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 888, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24134,9 +24231,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1458 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:1464 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 882, + ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 888, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24151,9 +24248,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1459 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" + // Pos:1465 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" { - ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 883, + ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 889, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24169,9 +24266,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1460 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" + // Pos:1466 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" { - ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 883, + ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 889, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24186,9 +24283,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1461 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:1467 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 884, + ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 890, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24202,9 +24299,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1462 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:1468 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 884, + ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 890, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24218,9 +24315,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1463 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" + // Pos:1469 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" { - ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 885, + ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 891, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24234,9 +24331,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1464 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" + // Pos:1470 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" { - ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 886, + ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 892, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24251,9 +24348,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1465 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" + // Pos:1471 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" { - ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 886, + ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 892, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24267,9 +24364,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1466 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" + // Pos:1472 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 887, + ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 893, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24284,9 +24381,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1467 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" + // Pos:1473 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" { - ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 888, + ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 894, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24301,9 +24398,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1468 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" + // Pos:1474 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" { - ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 889, + ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 895, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24318,9 +24415,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1469 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" + // Pos:1475 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 890, + ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 896, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24335,9 +24432,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1470 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" + // Pos:1476 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" { - ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 890, + ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 896, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24351,9 +24448,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1471 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" + // Pos:1477 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 891, + ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 897, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24368,9 +24465,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1472 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" + // Pos:1478 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 892, + ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 898, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24385,9 +24482,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1473 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:1479 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 893, + ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 899, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24402,9 +24499,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1474 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" + // Pos:1480 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 894, + ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 900, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24418,9 +24515,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1475 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" + // Pos:1481 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 894, + ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 900, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24434,9 +24531,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1476 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" + // Pos:1482 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" { - ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 895, + ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 901, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24450,9 +24547,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1477 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:1483 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 896, + ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 902, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24466,9 +24563,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1478 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:1484 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 896, + ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 902, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24482,9 +24579,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1479 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" + // Pos:1485 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" { - ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 897, + ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 903, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24498,9 +24595,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1480 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" + // Pos:1486 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 898, + ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 904, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24515,9 +24612,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1481 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" + // Pos:1487 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 899, + ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 905, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24532,9 +24629,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1482 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" + // Pos:1488 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 900, + ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 906, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24549,9 +24646,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1483 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" + // Pos:1489 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 901, + ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 907, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24566,9 +24663,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1484 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" + // Pos:1490 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 902, + ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 908, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24583,9 +24680,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1485 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" + // Pos:1491 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 902, + ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 908, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24600,9 +24697,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1486 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" + // Pos:1492 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 903, + ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 909, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24617,9 +24714,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1487 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" + // Pos:1493 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" { - ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 904, + ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 910, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -24636,9 +24733,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1488 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" + // Pos:1494 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" { - ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 905, + ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 911, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24654,9 +24751,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1489 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" + // Pos:1495 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" { - ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 905, + ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 911, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24671,9 +24768,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1490 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" + // Pos:1496 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" { - ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 906, + ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 912, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24689,9 +24786,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1491 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" + // Pos:1497 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" { - ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 906, + ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 912, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24706,9 +24803,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1492 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" + // Pos:1498 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" { - ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 907, + ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 913, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24724,9 +24821,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1493 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" + // Pos:1499 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" { - ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 907, + ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 913, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24741,9 +24838,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1494 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" + // Pos:1500 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" { - ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 908, + ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 914, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24759,9 +24856,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1495 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" + // Pos:1501 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" { - ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 908, + ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 914, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24776,9 +24873,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1496 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" + // Pos:1502 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" { - ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 909, + ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 915, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, @@ -24794,9 +24891,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1497 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" + // Pos:1503 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" { - ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 910, + ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 916, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24812,9 +24909,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1498 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" + // Pos:1504 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" { - ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 911, + ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 917, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24830,9 +24927,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1499 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" + // Pos:1505 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" { - ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 912, + ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 918, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -24846,9 +24943,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1500 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" + // Pos:1506 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" { - ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 913, + ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 919, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -24862,9 +24959,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1501 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" + // Pos:1507 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" { - ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 914, + ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 920, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -24879,9 +24976,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1502 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" + // Pos:1508 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" { - ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 915, + ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 921, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -24896,9 +24993,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1503 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" + // Pos:1509 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" { - ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 916, + ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 922, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24913,9 +25010,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1504 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" + // Pos:1510 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" { - ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 917, + ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 923, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24930,9 +25027,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1505 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" + // Pos:1511 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" { - ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 918, + ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 924, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24947,9 +25044,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1506 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" + // Pos:1512 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" { - ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 919, + ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 925, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24965,9 +25062,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1507 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" + // Pos:1513 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" { - ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 920, + ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 926, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24983,9 +25080,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1508 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" + // Pos:1514 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" { - ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 921, + ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 927, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25001,9 +25098,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1509 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" + // Pos:1515 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" { - ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 922, + ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 928, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25019,9 +25116,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1510 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" + // Pos:1516 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" { - ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 923, + ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 929, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -25036,9 +25133,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1511 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" + // Pos:1517 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" { - ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 924, + ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 930, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25054,9 +25151,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1512 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" + // Pos:1518 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" { - ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 925, + ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 931, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25072,9 +25169,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1513 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" + // Pos:1519 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" { - ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 926, + ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 932, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25090,9 +25187,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1514 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" + // Pos:1520 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" { - ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 927, + ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 933, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25108,9 +25205,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1515 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + // Pos:1521 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 928, + ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 934, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25125,9 +25222,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1516 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + // Pos:1522 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 928, + ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 934, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25142,9 +25239,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1517 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + // Pos:1523 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 928, + ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 934, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25159,9 +25256,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1518 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + // Pos:1524 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 928, + ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 934, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25176,9 +25273,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1519 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" + // Pos:1525 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 929, + ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 935, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25195,9 +25292,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1520 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" + // Pos:1526 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 930, + ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 936, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25214,9 +25311,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1521 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" + // Pos:1527 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 931, + ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 937, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25233,9 +25330,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1522 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" + // Pos:1528 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 932, + ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 938, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25252,9 +25349,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1523 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" + // Pos:1529 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" { - ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 933, + ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 939, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25270,9 +25367,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1524 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" + // Pos:1530 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" { - ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 933, + ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 939, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25287,9 +25384,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1525 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" + // Pos:1531 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" { - ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 934, + ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 940, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25305,9 +25402,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1526 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" + // Pos:1532 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" { - ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 934, + ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 940, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25322,9 +25419,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1527 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" + // Pos:1533 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" { - ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 935, + ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 941, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25340,9 +25437,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1528 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" + // Pos:1534 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" { - ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 935, + ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 941, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25357,9 +25454,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1529 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" + // Pos:1535 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" { - ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 936, + ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 942, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25375,9 +25472,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1530 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" + // Pos:1536 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" { - ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 936, + ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 942, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25392,9 +25489,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1531 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" + // Pos:1537 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" { - ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 937, + ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 943, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25410,9 +25507,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1532 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" + // Pos:1538 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" { - ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 937, + ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 943, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25427,9 +25524,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1533 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" + // Pos:1539 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" { - ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 938, + ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 944, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25445,9 +25542,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1534 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" + // Pos:1540 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" { - ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 938, + ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 944, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25462,9 +25559,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1535 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" + // Pos:1541 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" { - ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 939, + ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 945, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25480,9 +25577,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1536 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" + // Pos:1542 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" { - ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 939, + ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 945, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25497,9 +25594,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1537 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" + // Pos:1543 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" { - ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 940, + ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 946, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25515,9 +25612,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1538 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" + // Pos:1544 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" { - ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 940, + ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 946, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25532,9 +25629,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1539 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" + // Pos:1545 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" { - ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 941, + ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 947, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25550,9 +25647,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1540 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" + // Pos:1546 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" { - ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 941, + ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 947, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25567,9 +25664,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1541 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" + // Pos:1547 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" { - ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 942, + ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 948, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25585,9 +25682,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1542 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" + // Pos:1548 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" { - ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 942, + ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 948, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25602,9 +25699,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1543 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" + // Pos:1549 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" { - ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 943, + ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 949, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25620,9 +25717,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1544 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" + // Pos:1550 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" { - ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 943, + ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 949, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25637,9 +25734,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1545 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" + // Pos:1551 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" { - ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 944, + ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 950, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25655,9 +25752,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1546 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" + // Pos:1552 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" { - ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 944, + ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 950, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25672,9 +25769,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1547 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" + // Pos:1553 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" { - ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 945, + ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 951, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -25690,9 +25787,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1548 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" + // Pos:1554 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" { - ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 945, + ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 951, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -25708,9 +25805,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1549 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" + // Pos:1555 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" { - ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 946, + ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 952, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -25726,9 +25823,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1550 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" + // Pos:1556 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" { - ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 946, + ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 952, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -25744,9 +25841,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1551 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" + // Pos:1557 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" { - ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 947, + ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 953, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -25762,9 +25859,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1552 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" + // Pos:1558 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" { - ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 947, + ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 953, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -25780,9 +25877,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1553 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" + // Pos:1559 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" { - ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 948, + ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 954, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -25798,9 +25895,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1554 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" + // Pos:1560 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" { - ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 948, + ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 954, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -25816,9 +25913,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1555 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" + // Pos:1561 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" { - ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 949, + ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 955, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25834,9 +25931,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1556 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" + // Pos:1562 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" { - ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 949, + ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 955, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25851,9 +25948,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1557 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" + // Pos:1563 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" { - ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 950, + ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 956, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25869,9 +25966,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1558 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" + // Pos:1564 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" { - ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 950, + ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 956, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25886,9 +25983,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1559 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" + // Pos:1565 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" { - ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 951, + ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 957, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25904,9 +26001,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1560 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" + // Pos:1566 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" { - ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 951, + ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 957, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25921,9 +26018,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1561 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" + // Pos:1567 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" { - ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 952, + ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 958, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25939,9 +26036,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1562 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" + // Pos:1568 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" { - ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 952, + ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 958, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25956,9 +26053,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1563 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" + // Pos:1569 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" { - ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 953, + ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 959, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25974,9 +26071,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1564 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" + // Pos:1570 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" { - ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 953, + ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 959, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -25991,9 +26088,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1565 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" + // Pos:1571 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" { - ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 954, + ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 960, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26009,9 +26106,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1566 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" + // Pos:1572 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" { - ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 954, + ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 960, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26026,9 +26123,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1567 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" + // Pos:1573 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" { - ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 955, + ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 961, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26044,9 +26141,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1568 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" + // Pos:1574 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" { - ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 955, + ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 961, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26062,9 +26159,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1569 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" + // Pos:1575 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" { - ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 956, + ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 962, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26080,9 +26177,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1570 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" + // Pos:1576 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" { - ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 956, + ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 962, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26098,9 +26195,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1571 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" + // Pos:1577 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" { - ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 957, + ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 963, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26116,9 +26213,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1572 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" + // Pos:1578 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" { - ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 957, + ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 963, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26133,9 +26230,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1573 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" + // Pos:1579 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" { - ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 958, + ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 964, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26151,9 +26248,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1574 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" + // Pos:1580 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" { - ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 958, + ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 964, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26168,9 +26265,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1575 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" + // Pos:1581 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" { - ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 959, + ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 965, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26186,9 +26283,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1576 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" + // Pos:1582 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" { - ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 959, + ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 965, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26203,9 +26300,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1577 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" + // Pos:1583 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" { - ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 960, + ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 966, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26221,9 +26318,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1578 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" + // Pos:1584 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" { - ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 960, + ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 966, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26238,9 +26335,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1579 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" + // Pos:1585 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" { - ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 961, + ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 967, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26256,9 +26353,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1580 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" + // Pos:1586 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" { - ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 961, + ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 967, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26273,9 +26370,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1581 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" + // Pos:1587 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" { - ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 962, + ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 968, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26291,9 +26388,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1582 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" + // Pos:1588 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" { - ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 962, + ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 968, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26308,9 +26405,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1583 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" + // Pos:1589 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" { - ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 963, + ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 969, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26326,9 +26423,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1584 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" + // Pos:1590 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" { - ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 963, + ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 969, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26343,9 +26440,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1585 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" + // Pos:1591 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" { - ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 964, + ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 970, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26361,9 +26458,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1586 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" + // Pos:1592 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" { - ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 964, + ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 970, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26378,9 +26475,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1587 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" + // Pos:1593 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" { - ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 965, + ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 971, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26396,9 +26493,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1588 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" + // Pos:1594 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" { - ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 965, + ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 971, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26413,9 +26510,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1589 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" + // Pos:1595 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" { - ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 966, + ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 972, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26431,9 +26528,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1590 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" + // Pos:1596 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" { - ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 966, + ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 972, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26448,9 +26545,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1591 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" + // Pos:1597 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" { - ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 967, + ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 973, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26466,9 +26563,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1592 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" + // Pos:1598 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" { - ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 967, + ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 973, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26483,9 +26580,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1593 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" + // Pos:1599 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" { - ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 968, + ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 974, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26501,9 +26598,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1594 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" + // Pos:1600 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" { - ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 968, + ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 974, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26518,9 +26615,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1595 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" + // Pos:1601 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" { - ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 969, + ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 975, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26536,9 +26633,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1596 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" + // Pos:1602 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" { - ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 969, + ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 975, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26553,9 +26650,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1597 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" + // Pos:1603 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" { - ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 970, + ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 976, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26571,9 +26668,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1598 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" + // Pos:1604 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" { - ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 970, + ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 976, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26588,9 +26685,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1599 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" + // Pos:1605 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" { - ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 971, + ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 977, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26606,9 +26703,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1600 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" + // Pos:1606 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" { - ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 971, + ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 977, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26623,9 +26720,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1601 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" + // Pos:1607 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" { - ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 972, + ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 978, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26641,9 +26738,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1602 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" + // Pos:1608 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" { - ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 972, + ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 978, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26658,9 +26755,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1603 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" + // Pos:1609 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" { - ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 973, + ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 979, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26676,9 +26773,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1604 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" + // Pos:1610 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" { - ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 973, + ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 979, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26693,9 +26790,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1605 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" + // Pos:1611 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" { - ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 974, + ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 980, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26711,9 +26808,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1606 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" + // Pos:1612 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" { - ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 974, + ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 980, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26728,9 +26825,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1607 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" + // Pos:1613 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" { - ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 975, + ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 981, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26746,9 +26843,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1608 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" + // Pos:1614 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" { - ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 975, + ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 981, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26764,9 +26861,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1609 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" + // Pos:1615 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" { - ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 976, + ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 982, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26782,9 +26879,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1610 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" + // Pos:1616 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" { - ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 976, + ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 982, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26800,9 +26897,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1611 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" + // Pos:1617 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" { - ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 977, + ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 983, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26818,9 +26915,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1612 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" + // Pos:1618 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" { - ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 977, + ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 983, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26836,9 +26933,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1613 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" + // Pos:1619 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" { - ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 978, + ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 984, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26854,9 +26951,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1614 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" + // Pos:1620 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" { - ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 978, + ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 984, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26872,9 +26969,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1615 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" + // Pos:1621 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" { - ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 979, + ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 985, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26890,9 +26987,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1616 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" + // Pos:1622 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" { - ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 979, + ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 985, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26908,9 +27005,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1617 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" + // Pos:1623 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" { - ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 980, + ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 986, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26926,9 +27023,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1618 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" + // Pos:1624 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" { - ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 980, + ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 986, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -26944,9 +27041,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1619 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" + // Pos:1625 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" { - ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 981, + ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 987, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26962,9 +27059,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1620 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" + // Pos:1626 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" { - ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 981, + ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 987, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26979,9 +27076,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1621 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" + // Pos:1627 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" { - ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 982, + ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 988, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26997,9 +27094,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1622 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" + // Pos:1628 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" { - ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 982, + ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 988, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27014,9 +27111,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1623 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" + // Pos:1629 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" { - ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 983, + ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 989, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27032,9 +27129,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1624 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" + // Pos:1630 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" { - ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 983, + ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 989, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27049,9 +27146,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1625 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" + // Pos:1631 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" { - ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 984, + ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 990, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27067,9 +27164,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1626 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" + // Pos:1632 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" { - ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 984, + ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 990, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27084,9 +27181,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1627 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" + // Pos:1633 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" { - ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 985, + ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 991, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27102,9 +27199,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1628 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" + // Pos:1634 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" { - ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 985, + ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 991, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27119,9 +27216,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1629 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" + // Pos:1635 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" { - ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 986, + ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 992, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27137,9 +27234,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1630 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" + // Pos:1636 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" { - ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 986, + ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 992, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27154,9 +27251,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1631 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" + // Pos:1637 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" { - ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 987, + ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 993, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27172,9 +27269,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1632 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" + // Pos:1638 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" { - ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 987, + ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 993, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27189,9 +27286,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1633 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" + // Pos:1639 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" { - ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 988, + ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 994, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27207,9 +27304,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1634 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" + // Pos:1640 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" { - ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 988, + ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 994, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27224,9 +27321,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1635 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" + // Pos:1641 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" { - ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 989, + ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 995, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27242,9 +27339,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1636 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" + // Pos:1642 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" { - ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 989, + ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 995, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27259,9 +27356,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1637 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" + // Pos:1643 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" { - ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 990, + ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 996, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27277,9 +27374,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1638 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" + // Pos:1644 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" { - ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 990, + ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 996, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27294,9 +27391,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1639 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" + // Pos:1645 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" { - ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 991, + ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 997, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27312,9 +27409,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1640 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" + // Pos:1646 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" { - ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 991, + ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 997, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27329,9 +27426,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1641 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" + // Pos:1647 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" { - ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 992, + ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 998, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27347,9 +27444,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1642 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" + // Pos:1648 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" { - ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 992, + ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 998, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27364,9 +27461,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1643 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" + // Pos:1649 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" { - ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 993, + ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 999, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27382,9 +27479,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1644 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" + // Pos:1650 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" { - ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 993, + ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 999, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27400,9 +27497,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1645 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" + // Pos:1651 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" { - ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 994, + ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1000, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27418,9 +27515,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1646 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" + // Pos:1652 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" { - ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 994, + ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1000, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27436,9 +27533,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1647 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" + // Pos:1653 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" { - ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 995, + ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1001, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27454,9 +27551,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1648 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" + // Pos:1654 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" { - ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 995, + ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1001, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27472,9 +27569,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1649 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" + // Pos:1655 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" { - ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 996, + ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1002, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27490,9 +27587,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1650 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" + // Pos:1656 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" { - ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 996, + ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1002, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27508,9 +27605,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1651 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" + // Pos:1657 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" { - ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 997, + ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1003, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27526,9 +27623,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1652 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" + // Pos:1658 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" { - ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 997, + ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1003, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27543,9 +27640,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1653 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" + // Pos:1659 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" { - ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 998, + ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1004, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27561,9 +27658,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1654 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" + // Pos:1660 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" { - ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 998, + ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1004, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27578,9 +27675,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1655 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" + // Pos:1661 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" { - ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 999, + ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1005, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27596,9 +27693,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1656 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" + // Pos:1662 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" { - ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 999, + ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1005, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27613,9 +27710,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1657 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" + // Pos:1663 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" { - ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1000, + ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1006, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27631,9 +27728,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1658 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" + // Pos:1664 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" { - ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1000, + ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1006, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27648,9 +27745,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1659 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" + // Pos:1665 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" { - ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1001, + ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1007, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27666,9 +27763,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1660 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" + // Pos:1666 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" { - ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1001, + ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1007, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27683,9 +27780,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1661 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" + // Pos:1667 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" { - ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1002, + ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1008, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27701,9 +27798,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1662 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" + // Pos:1668 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" { - ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1002, + ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1008, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27718,9 +27815,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1663 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" + // Pos:1669 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" { - ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1003, + ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1009, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27736,9 +27833,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1664 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" + // Pos:1670 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" { - ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1003, + ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1009, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27753,9 +27850,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1665 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" + // Pos:1671 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" { - ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1004, + ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1010, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27771,9 +27868,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1666 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" + // Pos:1672 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" { - ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1004, + ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1010, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27788,9 +27885,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1667 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" + // Pos:1673 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" { - ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1005, + ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1011, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27806,9 +27903,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1668 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" + // Pos:1674 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" { - ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1005, + ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1011, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27823,9 +27920,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1669 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" + // Pos:1675 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" { - ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1006, + ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1012, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27841,9 +27938,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1670 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" + // Pos:1676 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" { - ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1006, + ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1012, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27858,9 +27955,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1671 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" + // Pos:1677 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" { - ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1007, + ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1013, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27876,9 +27973,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1672 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" + // Pos:1678 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" { - ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1007, + ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1013, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27893,9 +27990,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1673 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" + // Pos:1679 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" { - ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1008, + ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1014, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27911,9 +28008,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1674 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" + // Pos:1680 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" { - ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1008, + ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1014, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27928,9 +28025,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1675 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" + // Pos:1681 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" { - ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1009, + ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1015, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27946,9 +28043,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1676 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" + // Pos:1682 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" { - ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1009, + ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1015, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27964,9 +28061,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1677 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" + // Pos:1683 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" { - ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1010, + ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1016, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27982,9 +28079,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1678 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" + // Pos:1684 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" { - ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1010, + ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1016, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28000,9 +28097,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1679 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" + // Pos:1685 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" { - ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1011, + ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1017, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28018,9 +28115,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1680 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" + // Pos:1686 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" { - ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1011, + ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1017, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28036,9 +28133,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1681 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" + // Pos:1687 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" { - ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1012, + ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1018, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28054,9 +28151,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1682 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" + // Pos:1688 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" { - ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1012, + ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1018, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28072,9 +28169,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1683 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" + // Pos:1689 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" { - ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1013, + ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1019, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -28090,9 +28187,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1684 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" + // Pos:1690 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" { - ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1014, + ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1020, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -28108,9 +28205,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1685 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" + // Pos:1691 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" { - ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1015, + ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1021, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -28126,9 +28223,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1686 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" + // Pos:1692 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" { - ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1016, + ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1022, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -28144,9 +28241,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1687 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" + // Pos:1693 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" { - ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1017, + ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1023, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -28160,9 +28257,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1688 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" + // Pos:1694 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" { - ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1018, + ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1024, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -28176,9 +28273,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1689 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" + // Pos:1695 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" { - ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1019, + ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1025, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -28192,9 +28289,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1690 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" + // Pos:1696 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" { - ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1020, + ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1026, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -28208,9 +28305,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1691 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" + // Pos:1697 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" { - ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1021, + ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1027, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28225,9 +28322,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1692 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" + // Pos:1698 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" { - ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1021, + ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1027, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -28242,9 +28339,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1693 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" + // Pos:1699 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" { - ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1022, + ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1028, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28259,9 +28356,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1694 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" + // Pos:1700 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" { - ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1022, + ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1028, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -28276,9 +28373,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1695 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" + // Pos:1701 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" { - ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1023, + ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1029, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -28292,9 +28389,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1696 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" + // Pos:1702 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" { - ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1024, + ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1030, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -28308,9 +28405,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1697 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" + // Pos:1703 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" { - ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1025, + ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1031, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -28324,9 +28421,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1698 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" + // Pos:1704 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" { - ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1026, + ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1032, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -28340,9 +28437,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1699 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" + // Pos:1705 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" { - ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1027, + ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1033, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -28356,9 +28453,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1700 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" + // Pos:1706 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" { - ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1028, + ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1034, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -28372,9 +28469,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1701 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" + // Pos:1707 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" { - ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1029, + ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1035, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -28388,9 +28485,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1702 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" + // Pos:1708 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" { - ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1030, + ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1036, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -28404,9 +28501,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1703 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" + // Pos:1709 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" { - ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1031, + ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1037, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28421,9 +28518,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1704 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" + // Pos:1710 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" { - ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1031, + ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1037, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -28438,9 +28535,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1705 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" + // Pos:1711 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" { - ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1032, + ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1038, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28455,9 +28552,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1706 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" + // Pos:1712 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" { - ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1032, + ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1038, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -28472,9 +28569,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1707 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" + // Pos:1713 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" { - ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1033, + ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1039, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28489,9 +28586,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1708 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" + // Pos:1714 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" { - ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1034, + ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1040, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28506,9 +28603,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1709 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" + // Pos:1715 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" { - ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1035, + ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1041, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28524,9 +28621,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1710 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" + // Pos:1716 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" { - ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1036, + ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1042, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28542,9 +28639,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1711 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" + // Pos:1717 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" { - ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1037, + ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1043, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28560,9 +28657,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1712 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" + // Pos:1718 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" { - ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1038, + ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1044, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28578,9 +28675,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1713 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" + // Pos:1719 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" { - ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1039, + ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1045, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28597,9 +28694,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1714 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" + // Pos:1720 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" { - ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1040, + ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1046, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28616,9 +28713,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1715 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" + // Pos:1721 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" { - ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1041, + ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1047, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -28635,9 +28732,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1716 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" + // Pos:1722 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" { - ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1041, + ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1047, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -28653,9 +28750,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1717 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" + // Pos:1723 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" { - ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1042, + ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1048, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -28672,9 +28769,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1718 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" + // Pos:1724 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" { - ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1042, + ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1048, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -28690,9 +28787,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1719 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" + // Pos:1725 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" { - ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1043, + ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1049, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -28708,9 +28805,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1720 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" + // Pos:1726 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" { - ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1043, + ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1049, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -28725,9 +28822,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1721 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" + // Pos:1727 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" { - ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1044, + ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1050, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -28742,9 +28839,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1722 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" + // Pos:1728 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" { - ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1045, + ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1051, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -28759,9 +28856,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1723 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" + // Pos:1729 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" { - ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1046, + ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1052, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -28776,9 +28873,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1724 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" + // Pos:1730 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" { - ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1047, + ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1053, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -28793,9 +28890,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1725 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" + // Pos:1731 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" { - ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1048, + ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1054, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -28811,9 +28908,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1726 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" + // Pos:1732 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" { - ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1049, + ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1055, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28830,9 +28927,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1727 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" + // Pos:1733 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" { - ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1050, + ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1056, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -28849,9 +28946,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1728 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" + // Pos:1734 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" { - ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1051, + ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1057, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -28868,9 +28965,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1729 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" + // Pos:1735 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" { - ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1052, + ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1058, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28887,9 +28984,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1730 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" + // Pos:1736 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" { - ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1053, + ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1059, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -28905,9 +29002,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1731 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" + // Pos:1737 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" { - ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1054, + ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1060, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28924,9 +29021,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1732 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" + // Pos:1738 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" { - ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1055, + ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1061, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -28943,9 +29040,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1733 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" + // Pos:1739 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" { - ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1056, + ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1062, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -28962,9 +29059,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1734 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" + // Pos:1740 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" { - ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1057, + ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1063, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28981,9 +29078,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1735 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + // Pos:1741 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" { - ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1058, + ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1064, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28999,9 +29096,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1736 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + // Pos:1742 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" { - ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1058, + ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1064, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29017,9 +29114,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1737 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + // Pos:1743 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" { - ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1058, + ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1064, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29035,9 +29132,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1738 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + // Pos:1744 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" { - ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1058, + ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1064, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29053,9 +29150,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1739 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" + // Pos:1745 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" { - ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1059, + ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1065, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29069,9 +29166,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1740 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" + // Pos:1746 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" { - ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1060, + ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1066, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, @@ -29085,9 +29182,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1741 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" + // Pos:1747 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" { - ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1061, + ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1067, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29102,9 +29199,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1742 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" + // Pos:1748 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" { - ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1062, + ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1068, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29119,9 +29216,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1743 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" + // Pos:1749 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" { - ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1062, + ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1068, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29136,9 +29233,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1744 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" + // Pos:1750 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" { - ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1063, + ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1069, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29153,9 +29250,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1745 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" + // Pos:1751 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" { - ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1063, + ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1069, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29170,9 +29267,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1746 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" + // Pos:1752 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" { - ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1064, + ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1070, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29188,9 +29285,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1747 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" + // Pos:1753 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" { - ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1064, + ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1070, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29205,9 +29302,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1748 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" + // Pos:1754 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" { - ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1065, + ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1071, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29223,9 +29320,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1749 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" + // Pos:1755 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" { - ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1065, + ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1071, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29240,9 +29337,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1750 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" + // Pos:1756 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" { - ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1066, + ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1072, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29258,9 +29355,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1751 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" + // Pos:1757 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" { - ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1066, + ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1072, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29275,9 +29372,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1752 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" + // Pos:1758 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" { - ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1067, + ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1073, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29293,9 +29390,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1753 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" + // Pos:1759 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" { - ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1067, + ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1073, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29310,9 +29407,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1754 Instruction:"VMCALL" Encoding:"0x0F 0x01 /0xC1"/"" + // Pos:1760 Instruction:"VMCALL" Encoding:"0x0F 0x01 /0xC1"/"" { - ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1068, + ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1074, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -29325,9 +29422,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1755 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" + // Pos:1761 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" { - ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1069, + ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1075, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -29341,9 +29438,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1756 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" + // Pos:1762 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" { - ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1070, + ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1076, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -29356,9 +29453,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1757 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" + // Pos:1763 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" { - ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1071, + ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1077, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -29371,9 +29468,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1758 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" + // Pos:1764 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" { - ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1071, + ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1077, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -29386,9 +29483,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1759 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" + // Pos:1765 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" { - ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1072, + ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1078, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29404,9 +29501,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1760 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" + // Pos:1766 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" { - ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1072, + ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1078, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29421,9 +29518,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1761 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" + // Pos:1767 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" { - ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1073, + ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1079, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29439,9 +29536,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1762 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" + // Pos:1768 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" { - ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1073, + ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1079, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29456,9 +29553,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1763 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" + // Pos:1769 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" { - ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1074, + ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1080, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29474,9 +29571,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1764 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" + // Pos:1770 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" { - ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1074, + ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1080, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29491,9 +29588,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1765 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" + // Pos:1771 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" { - ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1075, + ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1081, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29509,9 +29606,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1766 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" + // Pos:1772 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" { - ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1075, + ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1081, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29526,9 +29623,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1767 Instruction:"VMLAUNCH" Encoding:"0x0F 0x01 /0xC2"/"" + // Pos:1773 Instruction:"VMLAUNCH" Encoding:"0x0F 0x01 /0xC2"/"" { - ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1076, + ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1082, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -29541,9 +29638,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1768 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" + // Pos:1774 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" { - ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1077, + ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1083, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -29556,9 +29653,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1769 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/"" + // Pos:1775 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/"" { - ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1078, + ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1084, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -29571,9 +29668,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1770 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" + // Pos:1776 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" { - ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1078, + ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1084, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -29586,9 +29683,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1771 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" + // Pos:1777 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1079, + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29603,9 +29700,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1772 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" + // Pos:1778 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1079, + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29620,9 +29717,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1773 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" + // Pos:1779 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1079, + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1085, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29636,9 +29733,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1774 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" + // Pos:1780 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1079, + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1085, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29652,9 +29749,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1775 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" + // Pos:1781 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1080, + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1086, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29669,9 +29766,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1776 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" + // Pos:1782 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1080, + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1086, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29686,9 +29783,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1777 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" + // Pos:1783 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1080, + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1086, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29702,9 +29799,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1778 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" + // Pos:1784 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1080, + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1086, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29718,9 +29815,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1779 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + // Pos:1785 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1081, + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1087, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29734,9 +29831,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1780 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + // Pos:1786 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1081, + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1087, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29750,9 +29847,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1781 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + // Pos:1787 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1081, + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1087, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29766,9 +29863,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1782 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + // Pos:1788 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1081, + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1087, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29782,9 +29879,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1783 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" + // Pos:1789 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1082, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29799,9 +29896,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1784 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" + // Pos:1790 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1082, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29816,9 +29913,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1785 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" + // Pos:1791 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1082, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29833,9 +29930,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1786 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" + // Pos:1792 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1082, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1088, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29849,9 +29946,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1787 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" + // Pos:1793 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1082, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1088, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29865,9 +29962,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1788 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" + // Pos:1794 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" { - ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1083, + ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1089, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29881,9 +29978,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1789 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" + // Pos:1795 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" { - ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1083, + ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1089, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29897,9 +29994,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1790 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" + // Pos:1796 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" { - ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, + ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1090, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29914,9 +30011,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1791 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" + // Pos:1797 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" { - ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, + ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1090, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29931,9 +30028,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1792 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" + // Pos:1798 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" { - ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, + ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1091, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29948,9 +30045,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1793 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" + // Pos:1799 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" { - ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, + ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1091, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29965,9 +30062,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1794 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" + // Pos:1800 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" { - ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1086, + ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1092, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29981,9 +30078,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1795 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" + // Pos:1801 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" { - ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1086, + ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1092, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -29997,9 +30094,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1796 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" + // Pos:1802 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" { - ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1087, + ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1093, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -30014,9 +30111,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1797 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" + // Pos:1803 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" { - ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1087, + ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1093, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -30031,9 +30128,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1798 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" + // Pos:1804 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" { - ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, + ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1094, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30048,9 +30145,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1799 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" + // Pos:1805 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" { - ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, + ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1094, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30065,9 +30162,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1800 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" + // Pos:1806 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" { - ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, + ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1095, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30082,9 +30179,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1801 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" + // Pos:1807 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" { - ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, + ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1095, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30099,9 +30196,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1802 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" + // Pos:1808 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" { - ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1090, + ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1096, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -30116,9 +30213,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1803 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" + // Pos:1809 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" { - ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1090, + ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1096, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -30133,9 +30230,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1804 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" + // Pos:1810 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" { - ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1091, + ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1097, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30150,9 +30247,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1805 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" + // Pos:1811 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" { - ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1091, + ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1097, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30167,9 +30264,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1806 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" + // Pos:1812 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1098, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30184,9 +30281,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1807 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" + // Pos:1813 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1098, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30200,9 +30297,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1808 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" + // Pos:1814 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1092, + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1098, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30217,9 +30314,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1809 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" + // Pos:1815 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1092, + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1098, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30233,9 +30330,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1810 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" + // Pos:1816 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1093, + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1099, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30250,9 +30347,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1811 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" + // Pos:1817 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1093, + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1099, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30266,9 +30363,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1812 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" + // Pos:1818 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1093, + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1099, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30283,9 +30380,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1813 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" + // Pos:1819 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1093, + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1099, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30299,9 +30396,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1814 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" + // Pos:1820 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" { - ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1094, + ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1100, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30316,9 +30413,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1815 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" + // Pos:1821 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" { - ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1094, + ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1100, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30333,9 +30430,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1816 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" + // Pos:1822 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1095, + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1101, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30350,9 +30447,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1817 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" + // Pos:1823 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1095, + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1101, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30366,9 +30463,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1818 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" + // Pos:1824 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1095, + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1101, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30383,9 +30480,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1819 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" + // Pos:1825 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1095, + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1101, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30399,9 +30496,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1820 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" + // Pos:1826 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1096, + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1102, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30416,9 +30513,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1821 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" + // Pos:1827 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1096, + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1102, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30432,9 +30529,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1822 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" + // Pos:1828 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1096, + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1102, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30449,9 +30546,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1823 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" + // Pos:1829 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1096, + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1102, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30465,9 +30562,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1824 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" + // Pos:1830 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" { - ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1097, + ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1103, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30481,9 +30578,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1825 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" + // Pos:1831 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" { - ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1098, + ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1104, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30497,9 +30594,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1826 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" + // Pos:1832 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" { - ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1099, + ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1105, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30513,9 +30610,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1827 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" + // Pos:1833 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" { - ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1099, + ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1105, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30529,9 +30626,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1828 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" + // Pos:1834 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" { - ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1100, + ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1106, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30545,9 +30642,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1829 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" + // Pos:1835 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" { - ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1100, + ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1106, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30561,9 +30658,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1830 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" + // Pos:1836 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" { - ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1101, + ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30577,9 +30674,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1831 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" + // Pos:1837 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" { - ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1101, + ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1107, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30593,9 +30690,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1832 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" + // Pos:1838 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" { - ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1102, + ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1108, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30609,9 +30706,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1833 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" + // Pos:1839 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" { - ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1102, + ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1108, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30625,9 +30722,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1834 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + // Pos:1840 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1103, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30641,9 +30738,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1835 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + // Pos:1841 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1103, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30657,9 +30754,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1836 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" + // Pos:1842 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1103, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30673,9 +30770,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1837 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" + // Pos:1843 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1103, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30689,9 +30786,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1838 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + // Pos:1844 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1103, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30705,9 +30802,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1839 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + // Pos:1845 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1103, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30721,9 +30818,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1840 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" + // Pos:1846 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1103, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30737,9 +30834,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1841 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" + // Pos:1847 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1103, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30753,9 +30850,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1842 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" + // Pos:1848 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1104, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30770,9 +30867,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1843 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" + // Pos:1849 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1104, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30788,9 +30885,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1844 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" + // Pos:1850 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1104, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30805,9 +30902,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1845 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" + // Pos:1851 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1104, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30823,9 +30920,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1846 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" + // Pos:1852 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1104, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30840,9 +30937,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1847 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" + // Pos:1853 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1104, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30856,9 +30953,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1848 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" + // Pos:1854 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1104, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30873,9 +30970,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1849 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" + // Pos:1855 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1104, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30889,9 +30986,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1850 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" + // Pos:1856 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" { - ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1105, + ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1111, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30906,9 +31003,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1851 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" + // Pos:1857 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" { - ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1105, + ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1111, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30922,9 +31019,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1852 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" + // Pos:1858 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" { - ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1106, + ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1112, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30939,9 +31036,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1853 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" + // Pos:1859 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" { - ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1106, + ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1112, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -30955,9 +31052,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1854 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" + // Pos:1860 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30972,9 +31069,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1855 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" + // Pos:1861 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30990,9 +31087,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1856 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" + // Pos:1862 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31007,9 +31104,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1857 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" + // Pos:1863 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31025,9 +31122,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1858 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" + // Pos:1864 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1107, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31042,9 +31139,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1859 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" + // Pos:1865 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1107, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31058,9 +31155,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1860 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" + // Pos:1866 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1107, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31075,9 +31172,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1861 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" + // Pos:1867 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1107, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31091,9 +31188,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1862 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" + // Pos:1868 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1108, + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1114, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31108,9 +31205,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1863 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" + // Pos:1869 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1108, + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1114, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31125,9 +31222,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1864 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" + // Pos:1870 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1108, + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1114, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31141,9 +31238,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1865 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" + // Pos:1871 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1108, + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1114, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31157,9 +31254,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1866 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" + // Pos:1872 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1109, + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1115, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31174,9 +31271,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1867 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" + // Pos:1873 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1109, + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1115, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31191,9 +31288,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1868 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" + // Pos:1874 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1109, + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1115, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31207,9 +31304,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1869 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" + // Pos:1875 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1109, + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1115, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31223,9 +31320,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1870 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" + // Pos:1876 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" { - ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1110, + ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1116, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31241,9 +31338,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1871 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" + // Pos:1877 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" { - ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1111, + ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1117, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -31257,9 +31354,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1872 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" + // Pos:1878 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" { - ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1112, + ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1118, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -31273,9 +31370,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1873 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" + // Pos:1879 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" { - ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1113, + ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1119, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, @@ -31290,9 +31387,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1874 Instruction:"VMRESUME" Encoding:"0x0F 0x01 /0xC3"/"" + // Pos:1880 Instruction:"VMRESUME" Encoding:"0x0F 0x01 /0xC3"/"" { - ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1114, + ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1120, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -31305,9 +31402,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1875 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" + // Pos:1881 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" { - ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1115, + ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1121, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -31320,9 +31417,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1876 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" + // Pos:1882 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" { - ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1116, + ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1122, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -31335,9 +31432,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1877 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" + // Pos:1883 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" { - ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1117, + ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1123, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31353,9 +31450,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1878 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" + // Pos:1884 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" { - ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1117, + ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1123, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31370,9 +31467,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1879 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" + // Pos:1885 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" { - ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1118, + ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1124, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31388,9 +31485,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1880 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" + // Pos:1886 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" { - ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1118, + ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1124, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31405,9 +31502,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1881 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" + // Pos:1887 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" { - ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1119, + ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1125, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31423,9 +31520,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1882 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" + // Pos:1888 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" { - ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1119, + ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1125, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31440,9 +31537,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1883 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" + // Pos:1889 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" { - ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1120, + ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1126, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31458,9 +31555,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1884 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" + // Pos:1890 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" { - ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1120, + ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1126, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31475,9 +31572,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1885 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" + // Pos:1891 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" { - ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1121, + ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1127, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, @@ -31492,9 +31589,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1886 Instruction:"VMXOFF" Encoding:"0x0F 0x01 /0xC4"/"" + // Pos:1892 Instruction:"VMXOFF" Encoding:"0x0F 0x01 /0xC4"/"" { - ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1122, + ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1128, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -31507,9 +31604,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1887 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" + // Pos:1893 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" { - ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1123, + ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1129, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -31523,9 +31620,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1888 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" + // Pos:1894 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" { - ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1124, + ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1130, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -31541,9 +31638,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1889 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" + // Pos:1895 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" { - ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1124, + ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1130, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31558,9 +31655,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1890 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" + // Pos:1896 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" { - ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1125, + ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1131, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -31576,9 +31673,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1891 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" + // Pos:1897 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" { - ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1125, + ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1131, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31593,9 +31690,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1892 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" + // Pos:1898 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" { - ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1126, + ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1132, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, @@ -31610,9 +31707,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1893 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" + // Pos:1899 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" { - ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1127, + ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1133, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, @@ -31627,9 +31724,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1894 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" + // Pos:1900 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" { - ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1128, + ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1134, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, @@ -31645,9 +31742,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1895 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" + // Pos:1901 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" { - ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1129, + ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1135, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, @@ -31663,9 +31760,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1896 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" + // Pos:1902 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" { - ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1130, + ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1136, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -31680,9 +31777,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1897 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" + // Pos:1903 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" { - ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1130, + ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1136, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31696,9 +31793,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1898 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" + // Pos:1904 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" { - ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1131, + ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1137, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31713,9 +31810,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1899 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" + // Pos:1905 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" { - ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1131, + ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1137, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31729,9 +31826,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1900 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" + // Pos:1906 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" { - ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1132, + ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1138, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31746,9 +31843,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1901 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" + // Pos:1907 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" { - ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1133, + ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1139, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -31763,9 +31860,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1902 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" + // Pos:1908 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" { - ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1133, + ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1139, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31779,9 +31876,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1903 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" + // Pos:1909 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" { - ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1134, + ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1140, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -31797,9 +31894,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1904 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" + // Pos:1910 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" { - ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1134, + ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1140, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31814,9 +31911,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1905 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" + // Pos:1911 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" { - ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1135, + ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1141, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -31832,9 +31929,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1906 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" + // Pos:1912 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" { - ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1135, + ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1141, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31849,9 +31946,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1907 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" + // Pos:1913 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" { - ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1136, + ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1142, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -31867,9 +31964,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1908 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" + // Pos:1914 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" { - ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1136, + ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1142, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31884,9 +31981,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1909 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" + // Pos:1915 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" { - ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1137, + ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1143, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -31902,9 +31999,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1910 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" + // Pos:1916 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" { - ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1137, + ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1143, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31919,9 +32016,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1911 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" + // Pos:1917 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" { - ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1138, + ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1144, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -31937,9 +32034,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1912 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" + // Pos:1918 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" { - ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1138, + ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1144, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31954,9 +32051,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1913 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" + // Pos:1919 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" { - ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1139, + ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1145, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31972,9 +32069,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1914 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" + // Pos:1920 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" { - ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1139, + ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1145, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31989,9 +32086,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1915 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" + // Pos:1921 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" { - ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1140, + ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1146, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32007,9 +32104,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1916 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" + // Pos:1922 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" { - ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1140, + ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1146, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32024,9 +32121,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1917 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" + // Pos:1923 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" { - ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1141, + ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1147, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32042,9 +32139,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1918 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" + // Pos:1924 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" { - ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1141, + ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1147, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32059,9 +32156,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1919 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" + // Pos:1925 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" { - ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1142, + ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1148, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32077,9 +32174,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1920 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" + // Pos:1926 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" { - ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1142, + ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1148, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32094,9 +32191,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1921 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" + // Pos:1927 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" { - ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1143, + ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32112,9 +32209,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1922 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:1928 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" { - ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1143, + ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32129,9 +32226,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1923 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" + // Pos:1929 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" { - ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1144, + ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1150, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32147,9 +32244,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1924 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:1930 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" { - ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1144, + ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1150, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32164,9 +32261,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1925 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" + // Pos:1931 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" { - ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1145, + ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1151, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32182,9 +32279,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1926 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" + // Pos:1932 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" { - ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1145, + ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1151, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32199,9 +32296,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1927 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" + // Pos:1933 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" { - ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1146, + ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1152, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32218,9 +32315,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1928 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" + // Pos:1934 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" { - ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1146, + ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1152, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32236,9 +32333,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1929 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" + // Pos:1935 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" { - ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1147, + ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1153, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32253,9 +32350,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1930 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" + // Pos:1936 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" { - ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1148, + ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1154, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32271,9 +32368,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1931 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:1937 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" { - ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1149, + ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1155, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32288,9 +32385,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1932 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" + // Pos:1938 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" { - ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1150, + ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1156, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32306,9 +32403,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1933 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" + // Pos:1939 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" { - ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1151, + ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1157, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32324,9 +32421,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1934 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" + // Pos:1940 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" { - ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1152, + ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1158, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32342,9 +32439,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1935 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" + // Pos:1941 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" { - ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1153, + ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1159, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32360,9 +32457,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1936 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" + // Pos:1942 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" { - ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1153, + ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1159, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32377,9 +32474,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1937 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" + // Pos:1943 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" { - ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1154, + ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1160, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32395,9 +32492,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1938 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" + // Pos:1944 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" { - ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1154, + ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1160, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32412,9 +32509,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1939 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" + // Pos:1945 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" { - ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1155, + ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1161, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -32430,9 +32527,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1940 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" + // Pos:1946 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" { - ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1156, + ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1162, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32448,9 +32545,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1941 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" + // Pos:1947 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" { - ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1157, + ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1163, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32466,9 +32563,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1942 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" + // Pos:1948 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" { - ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1158, + ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1164, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32484,9 +32581,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1943 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" + // Pos:1949 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" { - ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1159, + ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1165, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32502,9 +32599,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1944 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" + // Pos:1950 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" { - ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1160, + ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1166, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32520,9 +32617,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1945 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" + // Pos:1951 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" { - ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1161, + ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1167, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32538,9 +32635,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1946 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:1952 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1162, + ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32555,9 +32652,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1947 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" + // Pos:1953 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" { - ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1162, + ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32572,9 +32669,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1948 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" + // Pos:1954 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" { - ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1162, + ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -32588,9 +32685,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1949 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" + // Pos:1955 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" { - ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1163, + ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1169, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32605,9 +32702,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1950 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" + // Pos:1956 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" { - ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1163, + ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1169, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32622,9 +32719,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1951 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" + // Pos:1957 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" { - ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1163, + ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1169, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -32638,9 +32735,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1952 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" + // Pos:1958 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" { - ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1164, + ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1170, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -32654,9 +32751,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1953 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" + // Pos:1959 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" { - ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1165, + ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1171, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -32670,9 +32767,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1954 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" + // Pos:1960 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" { - ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1166, + ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1172, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32687,9 +32784,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1955 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" + // Pos:1961 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" { - ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1166, + ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1172, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32704,9 +32801,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1956 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" + // Pos:1962 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" { - ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1166, + ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1172, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -32720,9 +32817,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1957 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:1963 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1167, + ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1173, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32737,9 +32834,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1958 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" + // Pos:1964 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" { - ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1167, + ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1173, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32754,9 +32851,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1959 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" + // Pos:1965 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" { - ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1167, + ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1173, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -32770,9 +32867,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1960 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + // Pos:1966 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" { - ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1168, + ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1174, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, @@ -32788,9 +32885,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1961 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + // Pos:1967 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" { - ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1168, + ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1174, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, @@ -32806,9 +32903,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1962 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" + // Pos:1968 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" { - ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1169, + ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1175, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -32824,9 +32921,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1963 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" + // Pos:1969 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" { - ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1169, + ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1175, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -32842,9 +32939,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1964 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" + // Pos:1970 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" { - ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1170, + ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1176, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32861,9 +32958,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1965 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" + // Pos:1971 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" { - ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1171, + ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1177, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32880,9 +32977,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1966 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" + // Pos:1972 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" { - ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1172, + ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1178, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32898,9 +32995,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1967 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" + // Pos:1973 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" { - ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1172, + ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1178, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32915,9 +33012,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1968 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" + // Pos:1974 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" { - ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1173, + ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1179, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32933,9 +33030,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1969 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" + // Pos:1975 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" { - ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1173, + ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1179, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32950,9 +33047,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1970 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" + // Pos:1976 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" { - ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1174, + ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1180, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32968,9 +33065,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1971 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" + // Pos:1977 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" { - ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1174, + ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1180, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32985,9 +33082,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1972 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" + // Pos:1978 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" { - ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1175, + ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1181, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33003,9 +33100,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1973 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" + // Pos:1979 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" { - ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1175, + ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1181, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33020,9 +33117,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1974 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" + // Pos:1980 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" { - ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1176, + ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1182, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33041,9 +33138,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1975 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" + // Pos:1981 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" { - ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1177, + ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1183, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33062,9 +33159,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1976 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" + // Pos:1982 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" { - ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1178, + ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1184, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33080,9 +33177,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1977 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" + // Pos:1983 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" { - ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1178, + ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1184, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33097,9 +33194,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1978 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" + // Pos:1984 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" { - ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1179, + ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1185, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33115,9 +33212,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1979 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" + // Pos:1985 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" { - ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1179, + ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1185, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33132,9 +33229,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1980 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" + // Pos:1986 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" { - ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1180, + ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1186, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33150,9 +33247,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1981 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" + // Pos:1987 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" { - ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1180, + ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1186, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33167,9 +33264,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1982 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" + // Pos:1988 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" { - ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1181, + ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1187, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33185,9 +33282,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1983 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" + // Pos:1989 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" { - ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1181, + ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1187, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33202,9 +33299,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1984 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" + // Pos:1990 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" { - ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1182, + ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1188, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33221,9 +33318,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1985 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" + // Pos:1991 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" { - ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1183, + ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1189, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33240,9 +33337,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1986 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" + // Pos:1992 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" { - ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1184, + ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1190, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33259,9 +33356,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1987 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" + // Pos:1993 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" { - ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1185, + ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1191, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33278,9 +33375,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1988 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" + // Pos:1994 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" { - ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1186, + ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1192, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33297,9 +33394,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1989 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" + // Pos:1995 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" { - ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1187, + ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1193, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33316,9 +33413,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1990 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" + // Pos:1996 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" { - ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1188, + ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1194, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33335,9 +33432,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1991 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" + // Pos:1997 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" { - ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1189, + ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1195, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33354,9 +33451,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1992 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" + // Pos:1998 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" { - ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1190, + ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1196, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -33372,9 +33469,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1993 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" + // Pos:1999 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" { - ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1191, + ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1197, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -33390,9 +33487,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1994 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" + // Pos:2000 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" { - ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1192, + ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1198, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -33407,9 +33504,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1995 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" + // Pos:2001 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" { - ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1193, + ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1199, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33424,9 +33521,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1996 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" + // Pos:2002 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" { - ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1194, + ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1200, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33441,9 +33538,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1997 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" + // Pos:2003 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" { - ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1195, + ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1201, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -33458,9 +33555,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1998 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" + // Pos:2004 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" { - ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1196, + ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1202, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -33476,9 +33573,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:1999 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" + // Pos:2005 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" { - ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1197, + ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1203, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -33494,9 +33591,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2000 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" + // Pos:2006 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" { - ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1198, + ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1204, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -33512,9 +33609,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2001 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" + // Pos:2007 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" { - ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1199, + ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1205, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -33530,9 +33627,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2002 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" + // Pos:2008 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" { - ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1200, + ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1206, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -33548,9 +33645,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2003 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" + // Pos:2009 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" { - ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1201, + ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1207, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -33566,9 +33663,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2004 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" + // Pos:2010 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" { - ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1202, + ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1208, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -33583,9 +33680,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2005 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" + // Pos:2011 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" { - ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1203, + ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1209, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -33600,9 +33697,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2006 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" + // Pos:2012 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" { - ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1204, + ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1210, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, @@ -33618,9 +33715,26 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2007 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" + // Pos:2013 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM" + { + ND_INS_VPDPBUSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1210, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2014 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" { - ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1205, + ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1211, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, @@ -33636,9 +33750,26 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2008 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" + // Pos:2015 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM" + { + ND_INS_VPDPBUSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1211, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2016 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" { - ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1206, + ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1212, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, @@ -33654,9 +33785,26 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2009 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" + // Pos:2017 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM" + { + ND_INS_VPDPWSSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1212, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2018 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" { - ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1207, + ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1213, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, @@ -33672,9 +33820,26 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2010 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" + // Pos:2019 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM" + { + ND_INS_VPDPWSSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1213, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2020 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" { - ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1208, + ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1214, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33690,9 +33855,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2011 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" + // Pos:2021 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" { - ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1209, + ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1215, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -33708,9 +33873,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2012 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" + // Pos:2022 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" { - ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1210, + ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1216, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, @@ -33726,9 +33891,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2013 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" + // Pos:2023 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" { - ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1211, + ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1217, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33744,9 +33909,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2014 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" + // Pos:2024 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" { - ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1211, + ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1217, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -33761,9 +33926,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2015 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" + // Pos:2025 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" { - ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1212, + ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1218, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, @@ -33779,9 +33944,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2016 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" + // Pos:2026 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" { - ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1213, + ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1219, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33797,9 +33962,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2017 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" + // Pos:2027 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" { - ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1214, + ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33815,9 +33980,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2018 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" + // Pos:2028 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" { - ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1215, + ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1221, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33833,9 +33998,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2019 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" + // Pos:2029 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" { - ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1216, + ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1222, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33851,9 +34016,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2020 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" + // Pos:2030 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" { - ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1217, + ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1223, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -33869,9 +34034,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2021 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML" + // Pos:2031 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML" { - ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1218, + ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1224, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -33888,9 +34053,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2022 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM" + // Pos:2032 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM" { - ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1218, + ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1224, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -33907,9 +34072,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2023 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML" + // Pos:2033 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML" { - ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1219, + ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1225, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -33926,9 +34091,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2024 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM" + // Pos:2034 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM" { - ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1219, + ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1225, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -33945,9 +34110,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2025 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" + // Pos:2035 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" { - ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1220, + ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1226, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33963,9 +34128,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2026 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" + // Pos:2036 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" { - ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1220, + ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1226, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33981,9 +34146,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2027 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" + // Pos:2037 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" { - ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1220, + ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1226, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33998,9 +34163,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2028 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" + // Pos:2038 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" { - ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1220, + ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1226, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34015,9 +34180,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2029 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" + // Pos:2039 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" { - ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1221, + ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34033,9 +34198,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2030 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" + // Pos:2040 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" { - ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1221, + ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34051,9 +34216,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2031 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" + // Pos:2041 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" { - ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1221, + ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34068,9 +34233,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2032 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" + // Pos:2042 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" { - ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1221, + ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34085,9 +34250,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2033 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" + // Pos:2043 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" { - ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1222, + ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34103,9 +34268,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2034 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" + // Pos:2044 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" { - ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1222, + ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34121,9 +34286,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2035 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" + // Pos:2045 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" { - ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1222, + ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34139,9 +34304,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2036 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" + // Pos:2046 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" { - ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1222, + ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -34156,9 +34321,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2037 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" + // Pos:2047 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" { - ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1223, + ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34174,9 +34339,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2038 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" + // Pos:2048 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" { - ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1223, + ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34192,9 +34357,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2039 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" + // Pos:2049 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" { - ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1223, + ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -34209,9 +34374,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2040 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" + // Pos:2050 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" { - ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1224, + ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1230, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34227,9 +34392,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2041 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" + // Pos:2051 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" { - ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1224, + ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1230, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34245,9 +34410,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2042 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" + // Pos:2052 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" { - ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1224, + ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1230, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -34262,9 +34427,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2043 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" + // Pos:2053 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" { - ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1225, + ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, @@ -34280,9 +34445,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2044 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" + // Pos:2054 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" { - ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1226, + ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34298,9 +34463,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2045 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" + // Pos:2055 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" { - ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1227, + ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34316,9 +34481,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2046 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" + // Pos:2056 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" { - ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1228, + ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1234, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34334,9 +34499,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2047 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" + // Pos:2057 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" { - ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1229, + ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1235, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34352,9 +34517,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2048 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" + // Pos:2058 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" { - ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1230, + ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34370,9 +34535,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2049 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" + // Pos:2059 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" { - ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1231, + ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1237, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34388,9 +34553,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2050 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" + // Pos:2060 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" { - ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1232, + ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1238, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -34405,9 +34570,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2051 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" + // Pos:2061 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" { - ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1233, + ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1239, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34422,9 +34587,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2052 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" + // Pos:2062 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" { - ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1234, + ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1240, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34439,9 +34604,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2053 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" + // Pos:2063 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" { - ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1235, + ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1241, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -34456,9 +34621,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2054 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + // Pos:2064 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" { - ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1236, + ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1242, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34473,9 +34638,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2055 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + // Pos:2065 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" { - ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1236, + ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1242, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34490,9 +34655,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2056 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + // Pos:2066 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" { - ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1236, + ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1242, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34507,9 +34672,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2057 Instruction:"VPEXTRB Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + // Pos:2067 Instruction:"VPEXTRB Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" { - ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1236, + ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1242, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34524,9 +34689,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2058 Instruction:"VPEXTRD Ed,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI" + // Pos:2068 Instruction:"VPEXTRD Ed,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI" { - ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1237, + ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1243, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -34541,9 +34706,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2059 Instruction:"VPEXTRD Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI" + // Pos:2069 Instruction:"VPEXTRD Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI" { - ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1237, + ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1243, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34558,9 +34723,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2060 Instruction:"VPEXTRQ Eq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI" + // Pos:2070 Instruction:"VPEXTRQ Eq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI" { - ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1238, + ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1244, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -34575,9 +34740,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2061 Instruction:"VPEXTRQ Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI" + // Pos:2071 Instruction:"VPEXTRQ Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI" { - ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1238, + ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1244, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34592,9 +34757,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2062 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + // Pos:2072 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" { - ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1239, + ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1245, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34609,9 +34774,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2063 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + // Pos:2073 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1239, + ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1245, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34626,9 +34791,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2064 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + // Pos:2074 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1239, + ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1245, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34643,9 +34808,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2065 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + // Pos:2075 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" { - ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1239, + ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1245, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34660,9 +34825,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2066 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + // Pos:2076 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1239, + ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1245, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34677,9 +34842,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2067 Instruction:"VPEXTRW Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + // Pos:2077 Instruction:"VPEXTRW Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1239, + ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1245, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34694,9 +34859,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2068 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" + // Pos:2078 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" { - ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1240, + ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1246, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34711,9 +34876,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2069 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" + // Pos:2079 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" { - ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1240, + ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1246, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -34728,9 +34893,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2070 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" + // Pos:2080 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" { - ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1241, + ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1247, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34745,9 +34910,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2071 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" + // Pos:2081 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" { - ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1241, + ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1247, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -34762,9 +34927,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2072 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" + // Pos:2082 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" { - ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1242, + ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1248, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34779,9 +34944,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2073 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" + // Pos:2083 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" { - ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1242, + ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1248, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -34796,9 +34961,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2074 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" + // Pos:2084 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" { - ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1243, + ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1249, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34813,9 +34978,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2075 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" + // Pos:2085 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" { - ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1243, + ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1249, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -34830,9 +34995,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2076 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" + // Pos:2086 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" { - ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1244, + ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1250, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -34846,9 +35011,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2077 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" + // Pos:2087 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" { - ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1245, + ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1251, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -34862,9 +35027,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2078 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" + // Pos:2088 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" { - ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1246, + ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1252, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -34878,9 +35043,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2079 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" + // Pos:2089 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" { - ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1247, + ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1253, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34895,9 +35060,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2080 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" + // Pos:2090 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" { - ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1248, + ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1254, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -34911,9 +35076,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2081 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" + // Pos:2091 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" { - ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1249, + ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1255, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34928,9 +35093,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2082 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" + // Pos:2092 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" { - ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1250, + ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1256, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -34944,9 +35109,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2083 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" + // Pos:2093 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" { - ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1251, + ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1257, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -34960,9 +35125,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2084 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" + // Pos:2094 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" { - ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1252, + ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1258, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -34976,9 +35141,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2085 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" + // Pos:2095 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" { - ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1253, + ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1259, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -34992,9 +35157,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2086 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" + // Pos:2096 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" { - ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1254, + ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1260, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35008,9 +35173,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2087 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" + // Pos:2097 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" { - ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1255, + ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1261, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35024,9 +35189,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2088 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" + // Pos:2098 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" { - ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1256, + ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1262, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35041,9 +35206,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2089 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" + // Pos:2099 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" { - ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1257, + ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1263, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35057,9 +35222,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2090 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" + // Pos:2100 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" { - ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1258, + ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1264, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35073,9 +35238,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2091 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" + // Pos:2101 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" { - ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1259, + ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1265, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35089,9 +35254,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2092 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" + // Pos:2102 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" { - ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1260, + ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1266, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35105,9 +35270,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2093 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" + // Pos:2103 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" { - ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1261, + ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1267, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35122,9 +35287,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2094 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" + // Pos:2104 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" { - ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1262, + ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1268, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35138,9 +35303,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2095 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" + // Pos:2105 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" { - ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1263, + ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1269, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35155,9 +35320,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2096 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" + // Pos:2106 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" { - ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1264, + ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1270, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35172,9 +35337,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2097 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" + // Pos:2107 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" { - ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1265, + ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1271, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35188,9 +35353,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2098 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + // Pos:2108 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" { - ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1266, + ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1272, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35206,9 +35371,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2099 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + // Pos:2109 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" { - ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1266, + ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1272, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35224,9 +35389,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2100 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + // Pos:2110 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" { - ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1266, + ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1272, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35242,9 +35407,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2101 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + // Pos:2111 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" { - ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1266, + ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1272, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35260,9 +35425,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2102 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + // Pos:2112 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" { - ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1267, + ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1273, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -35278,9 +35443,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2103 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + // Pos:2113 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" { - ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1267, + ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1273, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35296,9 +35461,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2104 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + // Pos:2114 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" { - ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1268, + ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1274, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -35314,9 +35479,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2105 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + // Pos:2115 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" { - ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1268, + ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1274, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35332,9 +35497,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2106 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + // Pos:2116 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" { - ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1269, + ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1275, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35350,9 +35515,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2107 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + // Pos:2117 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" { - ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1269, + ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1275, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35368,9 +35533,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2108 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + // Pos:2118 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" { - ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1269, + ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1275, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35386,9 +35551,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2109 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + // Pos:2119 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" { - ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1269, + ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1275, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35404,9 +35569,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2110 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" + // Pos:2120 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" { - ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1270, + ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1276, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -35421,9 +35586,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2111 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" + // Pos:2121 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" { - ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1271, + ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1277, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -35438,9 +35603,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2112 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" + // Pos:2122 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" { - ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1272, + ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1278, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35456,9 +35621,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2113 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" + // Pos:2123 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" { - ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1273, + ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1279, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35474,9 +35639,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2114 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" + // Pos:2124 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" { - ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1274, + ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1280, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35492,9 +35657,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2115 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" + // Pos:2125 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" { - ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1275, + ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1281, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35510,9 +35675,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2116 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" + // Pos:2126 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" { - ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1276, + ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35528,9 +35693,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2117 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" + // Pos:2127 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" { - ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1277, + ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1283, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35546,9 +35711,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2118 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" + // Pos:2128 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" { - ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1278, + ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1284, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35564,9 +35729,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2119 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" + // Pos:2129 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" { - ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1279, + ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1285, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35582,9 +35747,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2120 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" + // Pos:2130 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" { - ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1280, + ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1286, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35600,9 +35765,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2121 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" + // Pos:2131 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" { - ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1281, + ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1287, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35618,9 +35783,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2122 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" + // Pos:2132 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" { - ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1282, + ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1288, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35636,9 +35801,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2123 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" + // Pos:2133 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" { - ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1283, + ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1289, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35654,9 +35819,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2124 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" + // Pos:2134 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" { - ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1284, + ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1290, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, @@ -35672,9 +35837,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2125 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" + // Pos:2135 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" { - ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1285, + ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1291, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, @@ -35690,9 +35855,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2126 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" + // Pos:2136 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" { - ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1286, + ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1292, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35708,9 +35873,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2127 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" + // Pos:2137 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" { - ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1286, + ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1292, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35725,9 +35890,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2128 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" + // Pos:2138 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" { - ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1287, + ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1293, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35743,9 +35908,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2129 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" + // Pos:2139 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" { - ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1287, + ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1293, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35760,9 +35925,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2130 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" + // Pos:2140 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" { - ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1288, + ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1294, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -35777,9 +35942,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2131 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" + // Pos:2141 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" { - ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1288, + ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1294, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -35794,9 +35959,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2132 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" + // Pos:2142 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" { - ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1289, + ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1295, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -35811,9 +35976,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2133 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" + // Pos:2143 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" { - ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1289, + ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1295, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -35828,9 +35993,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2134 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" + // Pos:2144 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" { - ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1290, + ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1296, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35846,9 +36011,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2135 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" + // Pos:2145 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" { - ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1290, + ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1296, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35863,9 +36028,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2136 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" + // Pos:2146 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" { - ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1291, + ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1297, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35881,9 +36046,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2137 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" + // Pos:2147 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" { - ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1291, + ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1297, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35898,9 +36063,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2138 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" + // Pos:2148 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" { - ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1292, + ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1298, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35916,9 +36081,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2139 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" + // Pos:2149 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" { - ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1293, + ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1299, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35934,9 +36099,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2140 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" + // Pos:2150 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" { - ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1293, + ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1299, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35951,9 +36116,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2141 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" + // Pos:2151 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" { - ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1294, + ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1300, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35969,9 +36134,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2142 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:2152 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" { - ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1294, + ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1300, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35986,9 +36151,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2143 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" + // Pos:2153 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" { - ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1295, + ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1301, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36004,9 +36169,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2144 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" + // Pos:2154 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" { - ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1295, + ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1301, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36021,9 +36186,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2145 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" + // Pos:2155 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" { - ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1296, + ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36039,9 +36204,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2146 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" + // Pos:2156 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" { - ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1297, + ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36057,9 +36222,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2147 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" + // Pos:2157 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" { - ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1297, + ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36074,9 +36239,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2148 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" + // Pos:2158 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" { - ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1298, + ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1304, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36092,9 +36257,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2149 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" + // Pos:2159 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" { - ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1298, + ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1304, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36109,9 +36274,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2150 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" + // Pos:2160 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" { - ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1299, + ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1305, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36127,9 +36292,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2151 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" + // Pos:2161 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" { - ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1299, + ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1305, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36144,9 +36309,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2152 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" + // Pos:2162 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" { - ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1300, + ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1306, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36162,9 +36327,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2153 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" + // Pos:2163 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" { - ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1301, + ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1307, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36180,9 +36345,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2154 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" + // Pos:2164 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" { - ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1301, + ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1307, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36197,9 +36362,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2155 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" + // Pos:2165 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" { - ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1302, + ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1308, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36215,9 +36380,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2156 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" + // Pos:2166 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" { - ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1302, + ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1308, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36232,9 +36397,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2157 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" + // Pos:2167 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" { - ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1303, + ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1309, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36250,9 +36415,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2158 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" + // Pos:2168 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" { - ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1303, + ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1309, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36267,9 +36432,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2159 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" + // Pos:2169 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" { - ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1304, + ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1310, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36285,9 +36450,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2160 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" + // Pos:2170 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" { - ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1305, + ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1311, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36303,9 +36468,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2161 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" + // Pos:2171 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" { - ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1305, + ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1311, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36320,9 +36485,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2162 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" + // Pos:2172 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" { - ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1306, + ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1312, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36336,9 +36501,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2163 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" + // Pos:2173 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" { - ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1307, + ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1313, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -36352,9 +36517,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2164 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" + // Pos:2174 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" { - ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1308, + ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1314, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36369,9 +36534,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2165 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" + // Pos:2175 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" { - ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1309, + ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1315, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36386,9 +36551,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2166 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" + // Pos:2176 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" { - ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1310, + ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1316, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36402,9 +36567,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2167 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" + // Pos:2177 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" { - ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1311, + ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1317, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -36418,9 +36583,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2168 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" + // Pos:2178 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" { - ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1312, + ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1318, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -36434,9 +36599,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2169 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" + // Pos:2179 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" { - ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1313, + ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1319, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36450,9 +36615,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2170 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" + // Pos:2180 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" { - ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1314, + ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1320, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36466,9 +36631,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2171 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" + // Pos:2181 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" { - ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1315, + ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1321, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -36482,9 +36647,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2172 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" + // Pos:2182 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" { - ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1316, + ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1322, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36499,9 +36664,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2173 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" + // Pos:2183 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" { - ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1317, + ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1323, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36516,9 +36681,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2174 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" + // Pos:2184 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" { - ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1318, + ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1324, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36533,9 +36698,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2175 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" + // Pos:2185 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" { - ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1319, + ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1325, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36550,9 +36715,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2176 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" + // Pos:2186 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" { - ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1320, + ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1326, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36567,9 +36732,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2177 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" + // Pos:2187 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" { - ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1321, + ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1327, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36584,9 +36749,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2178 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" + // Pos:2188 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" { - ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1322, + ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1328, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36601,9 +36766,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2179 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" + // Pos:2189 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" { - ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1323, + ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1329, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36618,9 +36783,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2180 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" + // Pos:2190 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" { - ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1324, + ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1330, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36635,9 +36800,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2181 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" + // Pos:2191 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" { - ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1325, + ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1331, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36652,9 +36817,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2182 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" + // Pos:2192 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" { - ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1325, + ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1331, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36668,9 +36833,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2183 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" + // Pos:2193 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" { - ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1325, + ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1331, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -36684,9 +36849,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2184 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" + // Pos:2194 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" { - ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1326, + ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1332, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36701,9 +36866,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2185 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" + // Pos:2195 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" { - ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1326, + ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1332, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36717,9 +36882,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2186 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" + // Pos:2196 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" { - ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1326, + ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1332, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -36733,9 +36898,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2187 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" + // Pos:2197 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" { - ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1327, + ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1333, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36750,9 +36915,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2188 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" + // Pos:2198 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" { - ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1327, + ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1333, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36766,9 +36931,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2189 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" + // Pos:2199 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" { - ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1327, + ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1333, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -36782,9 +36947,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2190 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" + // Pos:2200 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" { - ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1328, + ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1334, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36799,9 +36964,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2191 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" + // Pos:2201 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" { - ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1328, + ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1334, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36815,9 +36980,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2192 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" + // Pos:2202 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" { - ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1328, + ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1334, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -36831,9 +36996,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2193 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" + // Pos:2203 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" { - ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1329, + ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1335, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36848,9 +37013,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2194 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" + // Pos:2204 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" { - ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1329, + ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1335, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36864,9 +37029,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2195 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" + // Pos:2205 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" { - ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1329, + ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1335, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -36880,9 +37045,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2196 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" + // Pos:2206 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" { - ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1330, + ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1336, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36897,9 +37062,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2197 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" + // Pos:2207 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" { - ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1330, + ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1336, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36913,9 +37078,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2198 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" + // Pos:2208 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" { - ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1330, + ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1336, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -36929,9 +37094,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2199 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" + // Pos:2209 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" { - ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1331, + ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1337, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36946,9 +37111,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2200 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" + // Pos:2210 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" { - ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1332, + ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1338, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36963,9 +37128,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2201 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" + // Pos:2211 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" { - ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1333, + ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1339, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36980,9 +37145,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2202 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" + // Pos:2212 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" { - ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1334, + ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1340, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36997,9 +37162,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2203 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" + // Pos:2213 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" { - ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1335, + ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1341, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37014,9 +37179,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2204 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" + // Pos:2214 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" { - ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1336, + ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1342, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37031,9 +37196,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2205 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" + // Pos:2215 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" { - ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1337, + ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1343, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37047,9 +37212,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2206 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" + // Pos:2216 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" { - ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1338, + ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1344, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37064,9 +37229,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2207 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" + // Pos:2217 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" { - ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1339, + ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1345, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37081,9 +37246,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2208 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" + // Pos:2218 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" { - ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1339, + ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1345, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37097,9 +37262,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2209 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" + // Pos:2219 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" { - ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1339, + ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1345, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -37113,9 +37278,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2210 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" + // Pos:2220 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" { - ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1340, + ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1346, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37130,9 +37295,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2211 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" + // Pos:2221 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" { - ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1340, + ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1346, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37146,9 +37311,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2212 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" + // Pos:2222 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" { - ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1340, + ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1346, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -37162,9 +37327,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2213 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" + // Pos:2223 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" { - ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1341, + ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1347, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37179,9 +37344,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2214 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" + // Pos:2224 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" { - ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1341, + ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1347, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37195,9 +37360,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2215 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" + // Pos:2225 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" { - ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1341, + ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1347, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -37211,9 +37376,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2216 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" + // Pos:2226 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" { - ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1342, + ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1348, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37228,9 +37393,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2217 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" + // Pos:2227 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" { - ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1342, + ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1348, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37244,9 +37409,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2218 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" + // Pos:2228 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" { - ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1342, + ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1348, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -37260,9 +37425,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2219 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" + // Pos:2229 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" { - ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1343, + ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1349, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37277,9 +37442,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2220 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" + // Pos:2230 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" { - ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1343, + ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1349, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37293,9 +37458,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2221 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" + // Pos:2231 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" { - ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1343, + ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1349, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -37309,9 +37474,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2222 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" + // Pos:2232 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" { - ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1344, + ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1350, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37326,9 +37491,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2223 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" + // Pos:2233 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" { - ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1344, + ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1350, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37342,9 +37507,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2224 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" + // Pos:2234 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" { - ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1344, + ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1350, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -37358,9 +37523,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2225 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" + // Pos:2235 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" { - ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1345, + ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1351, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37376,9 +37541,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2226 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" + // Pos:2236 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" { - ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1345, + ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1351, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37393,9 +37558,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2227 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" + // Pos:2237 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" { - ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1346, + ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1352, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37411,9 +37576,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2228 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" + // Pos:2238 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" { - ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1346, + ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1352, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37428,9 +37593,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2229 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" + // Pos:2239 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" { - ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1347, + ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1353, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37446,9 +37611,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2230 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" + // Pos:2240 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" { - ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1347, + ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1353, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37463,9 +37628,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2231 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" + // Pos:2241 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" { - ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1348, + ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1354, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37481,9 +37646,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2232 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" + // Pos:2242 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" { - ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1348, + ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1354, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37498,9 +37663,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2233 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" + // Pos:2243 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" { - ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1349, + ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37516,9 +37681,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2234 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" + // Pos:2244 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" { - ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1349, + ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37533,9 +37698,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2235 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" + // Pos:2245 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" { - ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1350, + ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -37551,9 +37716,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2236 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" + // Pos:2246 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" { - ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1351, + ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37569,9 +37734,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2237 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" + // Pos:2247 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" { - ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1351, + ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37586,9 +37751,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2238 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" + // Pos:2248 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" { - ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1352, + ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1358, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, @@ -37604,9 +37769,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2239 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" + // Pos:2249 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" { - ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1353, + ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1359, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37622,9 +37787,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2240 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" + // Pos:2250 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" { - ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1353, + ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1359, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37639,9 +37804,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2241 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" + // Pos:2251 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" { - ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1354, + ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1360, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, @@ -37656,9 +37821,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2242 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" + // Pos:2252 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" { - ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1355, + ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, @@ -37673,9 +37838,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2243 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" + // Pos:2253 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" { - ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1356, + ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, @@ -37690,9 +37855,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2244 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" + // Pos:2254 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" { - ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1357, + ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, @@ -37707,9 +37872,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2245 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" + // Pos:2255 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" { - ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1358, + ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37724,9 +37889,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2246 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" + // Pos:2256 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" { - ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1359, + ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1365, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37742,9 +37907,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2247 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" + // Pos:2257 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" { - ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1360, + ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1366, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37760,9 +37925,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2248 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" + // Pos:2258 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" { - ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1361, + ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1367, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37778,9 +37943,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2249 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" + // Pos:2259 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" { - ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1361, + ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1367, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37796,9 +37961,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2250 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" + // Pos:2260 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" { - ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1362, + ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1368, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37814,9 +37979,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2251 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" + // Pos:2261 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" { - ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1363, + ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1369, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37832,9 +37997,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2252 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" + // Pos:2262 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" { - ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1364, + ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1370, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37850,9 +38015,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2253 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" + // Pos:2263 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" { - ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1365, + ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1371, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37868,9 +38033,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2254 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" + // Pos:2264 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" { - ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1366, + ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1372, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37886,9 +38051,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2255 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" + // Pos:2265 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" { - ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1367, + ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37904,9 +38069,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2256 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" + // Pos:2266 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" { - ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1368, + ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37922,9 +38087,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2257 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" + // Pos:2267 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" { - ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1369, + ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1375, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37940,9 +38105,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2258 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" + // Pos:2268 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" { - ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1370, + ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1376, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37957,9 +38122,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2259 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" + // Pos:2269 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" { - ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1370, + ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1376, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37974,9 +38139,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2260 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" + // Pos:2270 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" { - ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1370, + ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1376, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37991,9 +38156,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2261 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" + // Pos:2271 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" { - ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1371, + ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1377, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38008,9 +38173,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2262 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" + // Pos:2272 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" { - ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1371, + ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1377, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38025,9 +38190,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2263 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" + // Pos:2273 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" { - ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1371, + ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1377, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38042,9 +38207,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2264 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" + // Pos:2274 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" { - ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1372, + ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1378, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38059,9 +38224,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2265 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" + // Pos:2275 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" { - ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1372, + ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1378, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38076,9 +38241,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2266 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" + // Pos:2276 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" { - ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1372, + ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1378, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38093,9 +38258,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2267 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" + // Pos:2277 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" { - ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1373, + ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1379, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38110,9 +38275,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2268 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" + // Pos:2278 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" { - ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1373, + ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1379, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38127,9 +38292,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2269 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" + // Pos:2279 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" { - ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1373, + ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1379, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38144,9 +38309,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2270 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + // Pos:2280 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" { - ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1374, + ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1380, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38161,9 +38326,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2271 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + // Pos:2281 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" { - ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1374, + ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1380, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38178,9 +38343,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2272 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" + // Pos:2282 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" { - ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1375, + ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1381, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38195,9 +38360,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2273 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" + // Pos:2283 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" { - ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1376, + ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1382, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38212,9 +38377,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2274 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" + // Pos:2284 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" { - ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1377, + ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1383, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38229,9 +38394,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2275 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" + // Pos:2285 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" { - ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1378, + ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1384, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38246,9 +38411,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2276 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" + // Pos:2286 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" { - ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1379, + ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1385, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38263,9 +38428,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2277 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" + // Pos:2287 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" { - ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1379, + ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1385, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38280,9 +38445,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2278 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" + // Pos:2288 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" { - ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1380, + ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1386, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38297,9 +38462,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2279 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" + // Pos:2289 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" { - ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1380, + ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1386, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38314,9 +38479,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2280 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" + // Pos:2290 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" { - ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1381, + ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1387, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38331,9 +38496,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2281 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" + // Pos:2291 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" { - ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1381, + ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1387, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38348,9 +38513,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2282 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" + // Pos:2292 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" { - ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1382, + ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1388, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38365,9 +38530,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2283 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" + // Pos:2293 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" { - ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1382, + ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1388, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38382,9 +38547,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2284 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" + // Pos:2294 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1383, + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1389, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38399,9 +38564,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2285 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" + // Pos:2295 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1383, + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1389, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38416,9 +38581,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2286 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" + // Pos:2296 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1383, + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1389, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38433,9 +38598,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2287 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" + // Pos:2297 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1383, + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1389, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38450,9 +38615,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2288 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" + // Pos:2298 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" { - ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1384, + ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1390, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38467,9 +38632,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2289 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" + // Pos:2299 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" { - ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1385, + ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1391, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -38486,9 +38651,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2290 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" + // Pos:2300 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" { - ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1386, + ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1392, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -38505,9 +38670,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2291 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" + // Pos:2301 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" { - ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1387, + ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1393, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -38523,9 +38688,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2292 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" + // Pos:2302 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" { - ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1388, + ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1394, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -38541,9 +38706,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2293 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" + // Pos:2303 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" { - ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1389, + ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1395, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -38559,9 +38724,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2294 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" + // Pos:2304 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" { - ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1390, + ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1396, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -38578,9 +38743,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2295 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" + // Pos:2305 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" { - ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1391, + ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1397, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38595,9 +38760,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2296 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" + // Pos:2306 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" { - ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1391, + ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1397, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38612,9 +38777,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2297 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" + // Pos:2307 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" { - ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1392, + ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1398, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38629,9 +38794,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2298 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" + // Pos:2308 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" { - ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1393, + ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1399, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -38648,9 +38813,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2299 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" + // Pos:2309 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" { - ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1394, + ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1400, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -38667,9 +38832,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2300 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" + // Pos:2310 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" { - ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1395, + ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1401, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -38685,9 +38850,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2301 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" + // Pos:2311 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" { - ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1396, + ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1402, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -38703,9 +38868,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2302 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" + // Pos:2312 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" { - ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1397, + ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1403, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -38721,9 +38886,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2303 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" + // Pos:2313 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" { - ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1398, + ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1404, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -38740,9 +38905,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2304 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" + // Pos:2314 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" { - ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1399, + ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1405, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38758,9 +38923,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2305 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" + // Pos:2315 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" { - ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1399, + ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1405, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38775,9 +38940,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2306 Instruction:"VPSHUFBITQMB rK{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" + // Pos:2316 Instruction:"VPSHUFBITQMB rK{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" { - ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1400, + ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1406, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, @@ -38793,9 +38958,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2307 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" + // Pos:2317 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" { - ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1401, + ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1407, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38811,9 +38976,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2308 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" + // Pos:2318 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" { - ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1401, + ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1407, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38828,9 +38993,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2309 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" + // Pos:2319 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" { - ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1402, + ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1408, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38846,9 +39011,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2310 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" + // Pos:2320 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" { - ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1402, + ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1408, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38863,9 +39028,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2311 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" + // Pos:2321 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" { - ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1403, + ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1409, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38881,9 +39046,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2312 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" + // Pos:2322 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" { - ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1403, + ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1409, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38898,9 +39063,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2313 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" + // Pos:2323 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" { - ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1404, + ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1410, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38915,9 +39080,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2314 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" + // Pos:2324 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" { - ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1405, + ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1411, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38932,9 +39097,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2315 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" + // Pos:2325 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" { - ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1406, + ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1412, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38949,9 +39114,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2316 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" + // Pos:2326 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" { - ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1407, + ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1413, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38967,9 +39132,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2317 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" + // Pos:2327 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" { - ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1407, + ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1413, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38985,9 +39150,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2318 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" + // Pos:2328 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" { - ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1407, + ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1413, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39002,9 +39167,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2319 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" + // Pos:2329 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" { - ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1407, + ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1413, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39019,9 +39184,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2320 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" + // Pos:2330 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" { - ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1408, + ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1414, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39036,9 +39201,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2321 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" + // Pos:2331 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" { - ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1408, + ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1414, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39053,9 +39218,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2322 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" + // Pos:2332 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" { - ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1409, + ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1415, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39071,9 +39236,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2323 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" + // Pos:2333 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" { - ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1409, + ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1415, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39089,9 +39254,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2324 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" + // Pos:2334 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" { - ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1409, + ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1415, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39106,9 +39271,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2325 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" + // Pos:2335 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" { - ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1409, + ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1415, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39123,9 +39288,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2326 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" + // Pos:2336 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" { - ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1410, + ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1416, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39141,9 +39306,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2327 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" + // Pos:2337 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" { - ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1410, + ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1416, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39158,9 +39323,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2328 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" + // Pos:2338 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" { - ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1411, + ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1417, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39176,9 +39341,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2329 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" + // Pos:2339 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" { - ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1411, + ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1417, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39193,9 +39358,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2330 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" + // Pos:2340 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" { - ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1412, + ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1418, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39211,9 +39376,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2331 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" + // Pos:2341 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" { - ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1413, + ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1419, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39229,9 +39394,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2332 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" + // Pos:2342 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" { - ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1413, + ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1419, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39247,9 +39412,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2333 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" + // Pos:2343 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" { - ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1413, + ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1419, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39264,9 +39429,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2334 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" + // Pos:2344 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" { - ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1413, + ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1419, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39281,9 +39446,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2335 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" + // Pos:2345 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" { - ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1414, + ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1420, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39299,9 +39464,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2336 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" + // Pos:2346 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" { - ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1414, + ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1420, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39317,9 +39482,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2337 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" + // Pos:2347 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" { - ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1414, + ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1420, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39334,9 +39499,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2338 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" + // Pos:2348 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" { - ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1414, + ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1420, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39351,9 +39516,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2339 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" + // Pos:2349 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" { - ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1415, + ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1421, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39369,9 +39534,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2340 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" + // Pos:2350 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" { - ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1415, + ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1421, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39387,9 +39552,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2341 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" + // Pos:2351 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" { - ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1416, + ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1422, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39405,9 +39570,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2342 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" + // Pos:2352 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" { - ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1416, + ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1422, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39422,9 +39587,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2343 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" + // Pos:2353 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" { - ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1417, + ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1423, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39440,9 +39605,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2344 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" + // Pos:2354 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" { - ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1418, + ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1424, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39458,9 +39623,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2345 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" + // Pos:2355 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" { - ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1419, + ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1425, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39476,9 +39641,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2346 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" + // Pos:2356 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" { - ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1419, + ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1425, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39494,9 +39659,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2347 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" + // Pos:2357 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" { - ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1419, + ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1425, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39511,9 +39676,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2348 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" + // Pos:2358 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" { - ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1419, + ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1425, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39528,9 +39693,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2349 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" + // Pos:2359 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" { - ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1420, + ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1426, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39546,9 +39711,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2350 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" + // Pos:2360 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" { - ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1420, + ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1426, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39564,9 +39729,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2351 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" + // Pos:2361 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" { - ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1420, + ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1426, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39581,9 +39746,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2352 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" + // Pos:2362 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" { - ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1420, + ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1426, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39598,9 +39763,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2353 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" + // Pos:2363 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" { - ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1421, + ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1427, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39615,9 +39780,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2354 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" + // Pos:2364 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" { - ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1421, + ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1427, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39632,9 +39797,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2355 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" + // Pos:2365 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" { - ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1422, + ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1428, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39650,9 +39815,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2356 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" + // Pos:2366 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" { - ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1422, + ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1428, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39668,9 +39833,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2357 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" + // Pos:2367 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" { - ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1422, + ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1428, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39685,9 +39850,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2358 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" + // Pos:2368 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" { - ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1422, + ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1428, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39702,9 +39867,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2359 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" + // Pos:2369 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" { - ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1423, + ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1429, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39720,9 +39885,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2360 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" + // Pos:2370 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" { - ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1423, + ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1429, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39737,9 +39902,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2361 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" + // Pos:2371 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" { - ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1424, + ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1430, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39755,9 +39920,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2362 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" + // Pos:2372 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" { - ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1424, + ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1430, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39772,9 +39937,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2363 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" + // Pos:2373 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" { - ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1425, + ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1431, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39790,9 +39955,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2364 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" + // Pos:2374 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" { - ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1426, + ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1432, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39808,9 +39973,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2365 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" + // Pos:2375 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" { - ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1426, + ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1432, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39826,9 +39991,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2366 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" + // Pos:2376 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" { - ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1426, + ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1432, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39843,9 +40008,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2367 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" + // Pos:2377 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" { - ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1426, + ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1432, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39860,9 +40025,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2368 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" + // Pos:2378 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" { - ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1427, + ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1433, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39878,9 +40043,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2369 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" + // Pos:2379 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" { - ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1427, + ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1433, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39895,9 +40060,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2370 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" + // Pos:2380 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" { - ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1428, + ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1434, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39913,9 +40078,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2371 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" + // Pos:2381 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" { - ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1428, + ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1434, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39930,9 +40095,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2372 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" + // Pos:2382 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" { - ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1429, + ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1435, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39948,9 +40113,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2373 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" + // Pos:2383 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" { - ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1429, + ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1435, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39965,9 +40130,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2374 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" + // Pos:2384 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" { - ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1430, + ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1436, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39983,9 +40148,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2375 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" + // Pos:2385 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" { - ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1430, + ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1436, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40000,9 +40165,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2376 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" + // Pos:2386 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" { - ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1431, + ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1437, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40018,9 +40183,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2377 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" + // Pos:2387 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" { - ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1431, + ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1437, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40035,9 +40200,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2378 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" + // Pos:2388 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" { - ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1432, + ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1438, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40053,9 +40218,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2379 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" + // Pos:2389 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" { - ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1432, + ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1438, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40070,9 +40235,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2380 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" + // Pos:2390 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" { - ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1433, + ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1439, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40088,9 +40253,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2381 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" + // Pos:2391 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" { - ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1433, + ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1439, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40105,9 +40270,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2382 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" + // Pos:2392 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" { - ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1434, + ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1440, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40123,9 +40288,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2383 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" + // Pos:2393 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" { - ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1434, + ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1440, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40140,9 +40305,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2384 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" + // Pos:2394 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" { - ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1435, + ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1441, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40159,9 +40324,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2385 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" + // Pos:2395 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" { - ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1436, + ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1442, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40178,9 +40343,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2386 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" + // Pos:2396 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" { - ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1437, + ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1443, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40195,9 +40360,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2387 Instruction:"VPTESTMB rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" + // Pos:2397 Instruction:"VPTESTMB rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" { - ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1438, + ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1444, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40213,9 +40378,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2388 Instruction:"VPTESTMD rKq{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" + // Pos:2398 Instruction:"VPTESTMD rKq{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" { - ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1439, + ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1445, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40231,9 +40396,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2389 Instruction:"VPTESTMQ rKq{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" + // Pos:2399 Instruction:"VPTESTMQ rKq{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" { - ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1440, + ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1446, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40249,9 +40414,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2390 Instruction:"VPTESTMW rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" + // Pos:2400 Instruction:"VPTESTMW rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" { - ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1441, + ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1447, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40267,9 +40432,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2391 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" + // Pos:2401 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" { - ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1442, + ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1448, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40285,9 +40450,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2392 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" + // Pos:2402 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" { - ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1443, + ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1449, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40303,9 +40468,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2393 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" + // Pos:2403 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" { - ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1444, + ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1450, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40321,9 +40486,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2394 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" + // Pos:2404 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" { - ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1445, + ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1451, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40339,9 +40504,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2395 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" + // Pos:2405 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" { - ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1446, + ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1452, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40357,9 +40522,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2396 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" + // Pos:2406 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" { - ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1446, + ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1452, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40374,9 +40539,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2397 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" + // Pos:2407 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" { - ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1447, + ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1453, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40392,9 +40557,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2398 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" + // Pos:2408 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" { - ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1447, + ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1453, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40409,9 +40574,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2399 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" + // Pos:2409 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" { - ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1448, + ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1454, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40427,9 +40592,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2400 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" + // Pos:2410 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" { - ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1448, + ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1454, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40444,9 +40609,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2401 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" + // Pos:2411 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" { - ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1449, + ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1455, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40462,9 +40627,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2402 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" + // Pos:2412 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" { - ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1449, + ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1455, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40479,9 +40644,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2403 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" + // Pos:2413 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" { - ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1450, + ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1456, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40497,9 +40662,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2404 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" + // Pos:2414 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" { - ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1450, + ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1456, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40514,9 +40679,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2405 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" + // Pos:2415 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" { - ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1451, + ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1457, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40532,9 +40697,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2406 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" + // Pos:2416 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" { - ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1451, + ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1457, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40549,9 +40714,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2407 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" + // Pos:2417 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" { - ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1452, + ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1458, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40567,9 +40732,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2408 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" + // Pos:2418 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" { - ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1452, + ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1458, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40584,9 +40749,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2409 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" + // Pos:2419 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" { - ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1453, + ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1459, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40602,9 +40767,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2410 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" + // Pos:2420 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" { - ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1453, + ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1459, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40619,9 +40784,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2411 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" + // Pos:2421 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" { - ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1454, + ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1460, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40636,9 +40801,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2412 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" + // Pos:2422 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" { - ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1455, + ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1461, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40654,9 +40819,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2413 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" + // Pos:2423 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" { - ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1456, + ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1462, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40672,9 +40837,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2414 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" + // Pos:2424 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" { - ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1457, + ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1463, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -40691,9 +40856,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2415 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" + // Pos:2425 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" { - ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1458, + ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1464, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -40710,9 +40875,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2416 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" + // Pos:2426 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" { - ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1459, + ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1465, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -40729,9 +40894,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2417 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" + // Pos:2427 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" { - ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1460, + ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1466, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -40748,9 +40913,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2418 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" + // Pos:2428 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" { - ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1461, + ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1467, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40765,9 +40930,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2419 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" + // Pos:2429 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" { - ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1462, + ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1468, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40782,9 +40947,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2420 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" + // Pos:2430 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" { - ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1463, + ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1469, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40800,9 +40965,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2421 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" + // Pos:2431 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" { - ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1464, + ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1470, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40818,9 +40983,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2422 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" + // Pos:2432 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" { - ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1465, + ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1471, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -40835,9 +41000,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2423 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" + // Pos:2433 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" { - ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1466, + ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1472, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -40852,9 +41017,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2424 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" + // Pos:2434 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" { - ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1467, + ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1473, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -40870,9 +41035,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2425 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" + // Pos:2435 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" { - ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1468, + ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1474, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -40888,9 +41053,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2426 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" + // Pos:2436 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" { - ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1469, + ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1475, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40904,9 +41069,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2427 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" + // Pos:2437 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" { - ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1470, + ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1476, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40921,9 +41086,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2428 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" + // Pos:2438 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" { - ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1471, + ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1477, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -40939,9 +41104,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2429 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" + // Pos:2439 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" { - ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1472, + ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1478, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -40957,9 +41122,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2430 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" + // Pos:2440 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" { - ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1473, + ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1479, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -40976,9 +41141,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2431 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" + // Pos:2441 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" { - ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1474, + ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1480, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -40995,9 +41160,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2432 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" + // Pos:2442 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" { - ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1475, + ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1481, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41013,9 +41178,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2433 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" + // Pos:2443 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" { - ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1476, + ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1482, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41031,9 +41196,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2434 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" + // Pos:2444 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" { - ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1477, + ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1483, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41050,9 +41215,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2435 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" + // Pos:2445 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" { - ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1478, + ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1484, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41069,9 +41234,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2436 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" + // Pos:2446 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" { - ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1479, + ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1485, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41086,9 +41251,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2437 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" + // Pos:2447 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" { - ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1480, + ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1486, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41103,9 +41268,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2438 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" + // Pos:2448 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" { - ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1481, + ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1487, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41121,9 +41286,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2439 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" + // Pos:2449 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" { - ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1482, + ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1488, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41139,9 +41304,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2440 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" + // Pos:2450 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" { - ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1483, + ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1489, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41156,9 +41321,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2441 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" + // Pos:2451 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" { - ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1484, + ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1490, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41173,9 +41338,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2442 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" + // Pos:2452 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" { - ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1485, + ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1491, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41191,9 +41356,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2443 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" + // Pos:2453 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" { - ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1486, + ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1492, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41209,9 +41374,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2444 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" + // Pos:2454 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" { - ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1487, + ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1493, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -41226,9 +41391,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2445 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" + // Pos:2455 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" { - ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1488, + ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1494, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -41243,9 +41408,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2446 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" + // Pos:2456 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" { - ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1489, + ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1495, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -41261,9 +41426,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2447 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" + // Pos:2457 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" { - ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1490, + ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1496, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -41279,9 +41444,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2448 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" + // Pos:2458 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" { - ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1491, + ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1497, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41295,9 +41460,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2449 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" + // Pos:2459 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" { - ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1492, + ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1498, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41312,9 +41477,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2450 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" + // Pos:2460 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" { - ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1493, + ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1499, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41330,9 +41495,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2451 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" + // Pos:2461 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" { - ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1494, + ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1500, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41348,9 +41513,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2452 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" + // Pos:2462 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" { - ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1495, + ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1501, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41366,9 +41531,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2453 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" + // Pos:2463 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" { - ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1496, + ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1502, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41384,9 +41549,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2454 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" + // Pos:2464 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" { - ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1497, + ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41401,9 +41566,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2455 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" + // Pos:2465 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" { - ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1498, + ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1504, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41418,9 +41583,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2456 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" + // Pos:2466 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" { - ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1499, + ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1505, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -41434,9 +41599,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2457 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" + // Pos:2467 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" { - ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1500, + ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1506, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -41450,9 +41615,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2458 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" + // Pos:2468 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" { - ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1501, + ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1507, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -41466,9 +41631,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2459 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" + // Pos:2469 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" { - ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1502, + ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1508, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -41482,9 +41647,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2460 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" + // Pos:2470 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" { - ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1503, + ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1509, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -41498,9 +41663,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2461 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" + // Pos:2471 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" { - ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1504, + ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1510, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -41514,9 +41679,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2462 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" + // Pos:2472 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" { - ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1505, + ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1511, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -41530,9 +41695,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2463 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" + // Pos:2473 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" { - ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1506, + ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1512, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -41546,9 +41711,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2464 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" + // Pos:2474 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" { - ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1507, + ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1513, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41563,9 +41728,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2465 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" + // Pos:2475 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" { - ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1508, + ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1514, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41580,9 +41745,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2466 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" + // Pos:2476 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" { - ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1509, + ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1515, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41599,9 +41764,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2467 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" + // Pos:2477 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" { - ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1510, + ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1516, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41618,9 +41783,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2468 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" + // Pos:2478 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" { - ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1511, + ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1517, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41637,9 +41802,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2469 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" + // Pos:2479 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" { - ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1512, + ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1518, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41656,9 +41821,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2470 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" + // Pos:2480 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" { - ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1513, + ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1519, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41675,9 +41840,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2471 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" + // Pos:2481 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" { - ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1513, + ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1519, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41693,9 +41858,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2472 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" + // Pos:2482 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" { - ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1514, + ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1520, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41712,9 +41877,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2473 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" + // Pos:2483 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" { - ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1514, + ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1520, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41730,9 +41895,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2474 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" + // Pos:2484 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" { - ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1515, + ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1521, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41747,9 +41912,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2475 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" + // Pos:2485 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" { - ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1515, + ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1521, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41763,9 +41928,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2476 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" + // Pos:2486 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" { - ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1516, + ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1522, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41780,9 +41945,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2477 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" + // Pos:2487 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" { - ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1516, + ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1522, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41796,9 +41961,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2478 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" + // Pos:2488 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" { - ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1517, + ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1523, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41814,9 +41979,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2479 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" + // Pos:2489 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" { - ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1517, + ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1523, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41831,9 +41996,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2480 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" + // Pos:2490 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" { - ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1518, + ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1524, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41849,9 +42014,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2481 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" + // Pos:2491 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" { - ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1518, + ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1524, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41866,9 +42031,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2482 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" + // Pos:2492 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" { - ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1519, + ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1525, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, @@ -41882,9 +42047,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2483 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" + // Pos:2493 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" { - ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1520, + ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1526, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41900,9 +42065,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2484 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" + // Pos:2494 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" { - ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1520, + ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1526, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41917,9 +42082,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2485 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" + // Pos:2495 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" { - ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1521, + ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1527, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41935,9 +42100,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2486 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" + // Pos:2496 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" { - ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1521, + ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1527, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41952,9 +42117,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2487 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" + // Pos:2497 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" { - ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1522, + ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1528, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41970,9 +42135,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2488 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" + // Pos:2498 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" { - ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1522, + ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1528, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41987,9 +42152,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2489 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" + // Pos:2499 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" { - ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1523, + ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1529, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42005,9 +42170,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2490 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" + // Pos:2500 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" { - ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1523, + ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1529, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42022,9 +42187,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2491 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" + // Pos:2501 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" { - ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1524, + ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1530, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42039,9 +42204,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2492 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" + // Pos:2502 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" { - ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1525, + ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1531, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42056,9 +42221,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2493 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" + // Pos:2503 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" { - ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1526, + ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1532, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42073,9 +42238,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2494 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" + // Pos:2504 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" { - ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1526, + ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1532, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42090,9 +42255,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2495 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" + // Pos:2505 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" { - ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1527, + ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1533, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42107,9 +42272,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2496 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" + // Pos:2506 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" { - ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1527, + ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1533, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42124,9 +42289,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2497 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" + // Pos:2507 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" { - ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1528, + ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1534, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42142,9 +42307,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2498 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" + // Pos:2508 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" { - ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1528, + ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1534, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42159,9 +42324,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2499 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" + // Pos:2509 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" { - ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1529, + ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1535, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42177,9 +42342,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2500 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" + // Pos:2510 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" { - ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1529, + ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1535, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42194,9 +42359,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2501 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" + // Pos:2511 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" { - ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1530, + ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1536, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42212,9 +42377,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2502 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" + // Pos:2512 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" { - ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1530, + ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1536, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42229,9 +42394,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2503 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" + // Pos:2513 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" { - ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1531, + ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1537, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42247,9 +42412,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2504 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" + // Pos:2514 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" { - ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1531, + ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1537, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42264,9 +42429,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2505 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" + // Pos:2515 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" { - ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1532, + ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1538, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -42282,9 +42447,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2506 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" + // Pos:2516 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" { - ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1532, + ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1538, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42299,9 +42464,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2507 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" + // Pos:2517 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" { - ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1533, + ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1539, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -42317,9 +42482,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2508 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" + // Pos:2518 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" { - ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1533, + ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1539, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42334,9 +42499,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2509 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" + // Pos:2519 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" { - ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1534, + ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1540, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, @@ -42349,9 +42514,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2510 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" + // Pos:2520 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" { - ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1535, + ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1541, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, @@ -42364,9 +42529,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2511 Instruction:"WAIT" Encoding:"0x9B"/"" + // Pos:2521 Instruction:"WAIT" Encoding:"0x9B"/"" { - ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1536, + ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1542, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, 0, 0, @@ -42379,9 +42544,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2512 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" + // Pos:2522 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" { - ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1537, + ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1543, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -42394,9 +42559,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2513 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/"" + // Pos:2523 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/"" { - ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1538, + ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1544, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_WBNOINVD, @@ -42409,9 +42574,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2514 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M" + // Pos:2524 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M" { - ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1539, + ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1545, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, @@ -42425,9 +42590,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2515 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M" + // Pos:2525 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M" { - ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1540, + ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1546, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, @@ -42441,9 +42606,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2516 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" + // Pos:2526 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" { - ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1541, + ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1547, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, ND_CFF_MSR, @@ -42459,9 +42624,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2517 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" + // Pos:2527 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" { - ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1542, + ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1548, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, @@ -42477,9 +42642,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2518 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M" + // Pos:2528 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M" { - ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1543, + ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1549, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42492,9 +42657,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2519 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" + // Pos:2529 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" { - ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1544, + ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1550, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -42508,9 +42673,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2520 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" + // Pos:2530 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" { - ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1545, + ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1551, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -42524,9 +42689,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2521 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + // Pos:2531 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" { - ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1546, + ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1552, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -42540,9 +42705,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2522 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + // Pos:2532 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" { - ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1547, + ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1553, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -42556,9 +42721,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2523 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" + // Pos:2533 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" { - ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1548, + ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1554, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, @@ -42572,9 +42737,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2524 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" + // Pos:2534 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" { - ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1549, + ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1555, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42589,9 +42754,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2525 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" + // Pos:2535 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" { - ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1549, + ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1555, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42606,9 +42771,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2526 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" + // Pos:2536 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" { - ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1550, + ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1556, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, @@ -42623,9 +42788,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2527 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" + // Pos:2537 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1557, ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42639,9 +42804,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2528 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" + // Pos:2538 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1557, ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42655,9 +42820,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2529 Instruction:"XCHG rAX,Zv" Encoding:"rex 0x90"/"O" + // Pos:2539 Instruction:"XCHG rAX,Zv" Encoding:"rex 0x90"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1557, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -42671,9 +42836,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2530 Instruction:"XCHG rAX,Zv" Encoding:"0x91"/"O" + // Pos:2540 Instruction:"XCHG rAX,Zv" Encoding:"0x91"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1557, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -42687,9 +42852,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2531 Instruction:"XCHG rAX,Zv" Encoding:"0x92"/"O" + // Pos:2541 Instruction:"XCHG rAX,Zv" Encoding:"0x92"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1557, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -42703,9 +42868,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2532 Instruction:"XCHG rAX,Zv" Encoding:"0x93"/"O" + // Pos:2542 Instruction:"XCHG rAX,Zv" Encoding:"0x93"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1557, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -42719,9 +42884,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2533 Instruction:"XCHG rAX,Zv" Encoding:"0x94"/"O" + // Pos:2543 Instruction:"XCHG rAX,Zv" Encoding:"0x94"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1557, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -42735,9 +42900,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2534 Instruction:"XCHG rAX,Zv" Encoding:"0x95"/"O" + // Pos:2544 Instruction:"XCHG rAX,Zv" Encoding:"0x95"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1557, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -42751,9 +42916,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2535 Instruction:"XCHG rAX,Zv" Encoding:"0x96"/"O" + // Pos:2545 Instruction:"XCHG rAX,Zv" Encoding:"0x96"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1557, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -42767,9 +42932,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2536 Instruction:"XCHG rAX,Zv" Encoding:"0x97"/"O" + // Pos:2546 Instruction:"XCHG rAX,Zv" Encoding:"0x97"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1557, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -42783,9 +42948,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2537 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/"" + // Pos:2547 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/"" { - ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1552, + ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1558, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42798,9 +42963,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2538 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/"" + // Pos:2548 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/"" { - ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1553, + ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1559, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42813,9 +42978,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2539 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/"" + // Pos:2549 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/"" { - ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1554, + ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1560, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42828,9 +42993,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2540 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/"" + // Pos:2550 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/"" { - ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1555, + ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1561, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42843,9 +43008,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2541 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/"" + // Pos:2551 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/"" { - ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1556, + ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1562, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42858,9 +43023,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2542 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" + // Pos:2552 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" { - ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1557, + ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1563, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, @@ -42873,9 +43038,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2543 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" + // Pos:2553 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" { - ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1558, + ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1564, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -42891,9 +43056,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2544 Instruction:"XLATB" Encoding:"0xD7"/"" + // Pos:2554 Instruction:"XLATB" Encoding:"0xD7"/"" { - ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1559, + ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1565, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -42907,9 +43072,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2545 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" + // Pos:2555 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1566, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42924,9 +43089,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2546 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" + // Pos:2556 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1566, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42941,9 +43106,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2547 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" + // Pos:2557 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1566, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42958,9 +43123,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2548 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" + // Pos:2558 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1566, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -42975,9 +43140,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2549 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" + // Pos:2559 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1566, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -42992,9 +43157,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2550 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" + // Pos:2560 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1566, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -43009,9 +43174,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2551 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" + // Pos:2561 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1566, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -43026,9 +43191,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2552 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" + // Pos:2562 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1566, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -43043,9 +43208,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2553 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" + // Pos:2563 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1566, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -43060,9 +43225,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2554 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" + // Pos:2564 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1566, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -43077,9 +43242,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2555 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" + // Pos:2565 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" { - ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1561, + ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1567, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -43093,9 +43258,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2556 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" + // Pos:2566 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" { - ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1562, + ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1568, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -43109,9 +43274,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2557 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" + // Pos:2567 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" { - ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1563, + ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1569, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, @@ -43124,9 +43289,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2558 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" + // Pos:2568 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" { - ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1564, + ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1570, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -43143,9 +43308,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2559 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" + // Pos:2569 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" { - ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1565, + ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1571, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -43162,9 +43327,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2560 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" + // Pos:2570 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" { - ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1566, + ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1572, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, @@ -43181,9 +43346,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2561 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" + // Pos:2571 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" { - ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1567, + ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1573, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, @@ -43200,9 +43365,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2562 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" + // Pos:2572 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" { - ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1568, + ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1574, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -43219,9 +43384,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2563 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" + // Pos:2573 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" { - ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1569, + ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1575, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -43238,9 +43403,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2564 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" + // Pos:2574 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" { - ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1570, + ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1576, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, @@ -43257,9 +43422,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2565 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" + // Pos:2575 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" { - ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1571, + ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1577, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, @@ -43276,9 +43441,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2566 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" + // Pos:2576 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" { - ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1572, + ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1578, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -43295,9 +43460,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2567 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" + // Pos:2577 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" { - ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1573, + ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1579, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -43314,9 +43479,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2568 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" + // Pos:2578 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" { - ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1574, + ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1580, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, @@ -43333,9 +43498,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2569 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" + // Pos:2579 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" { - ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1575, + ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1581, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, @@ -43352,9 +43517,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2570 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" + // Pos:2580 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" { - ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1576, + ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1582, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -43370,9 +43535,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2571 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/"" + // Pos:2581 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/"" { - ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1577, + ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1583, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -43385,9 +43550,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2572 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/"" + // Pos:2582 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/"" { - ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1578, + ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1584, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -43400,9 +43565,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2573 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/"" + // Pos:2583 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/"" { - ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1579, + ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1585, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -43415,9 +43580,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2574 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" + // Pos:2584 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" { - ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1580, + ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1586, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, @@ -43430,9 +43595,9 @@ const ND_INSTRUCTION gInstructions[2576] = }, }, - // Pos:2575 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" + // Pos:2585 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" { - ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1581, + ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1587, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, diff --git a/bddisasm/include/mnemonics.h b/bddisasm/include/mnemonics.h index f2c6911..c17fb23 100644 --- a/bddisasm/include/mnemonics.h +++ b/bddisasm/include/mnemonics.h @@ -1,7 +1,7 @@ #ifndef MNEMONICS_H #define MNEMONICS_H -const char *gMnemonics[1582] = +const char *gMnemonics[1588] = { "AAA", "AAD", "AAM", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", "AESDEC", "AESDEC128KL", @@ -15,151 +15,153 @@ const char *gMnemonics[1582] = "BNDSTX", "BOUND", "BSF", "BSR", "BSWAP", "BT", "BTC", "BTR", "BTS", "BZHI", "CALL", "CALLF", "CBW", "CDQ", "CDQE", "CL1INVMB", "CLAC", "CLC", "CLD", "CLDEMOTE", "CLEVICT0", "CLEVICT1", "CLFLUSH", - "CLFLUSHOPT", "CLGI", "CLI", "CLRSSBSY", "CLTS", "CLWB", "CLZERO", - "CMC", "CMOVBE", "CMOVC", "CMOVL", "CMOVLE", "CMOVNBE", "CMOVNC", - "CMOVNL", "CMOVNLE", "CMOVNO", "CMOVNP", "CMOVNS", "CMOVNZ", - "CMOVO", "CMOVP", "CMOVS", "CMOVZ", "CMP", "CMPPD", "CMPPS", - "CMPSB", "CMPSD", "CMPSQ", "CMPSS", "CMPSW", "CMPXCHG", "CMPXCHG16B", - "CMPXCHG8B", "COMISD", "COMISS", "CPUID", "CPU_READ", "CPU_WRITE", - "CQO", "CRC32", "CVTDQ2PD", "CVTDQ2PS", "CVTPD2DQ", "CVTPD2PI", - "CVTPD2PS", "CVTPI2PD", "CVTPI2PS", "CVTPS2DQ", "CVTPS2PD", "CVTPS2PI", - "CVTSD2SI", "CVTSD2SS", "CVTSI2SD", "CVTSI2SS", "CVTSS2SD", "CVTSS2SI", - "CVTTPD2DQ", "CVTTPD2PI", "CVTTPS2DQ", "CVTTPS2PI", "CVTTSD2SI", - "CVTTSS2SI", "CWD", "CWDE", "DAA", "DAS", "DEC", "DELAY", "DIV", - "DIVPD", "DIVPS", "DIVSD", "DIVSS", "DMINT", "DPPD", "DPPS", - "EMMS", "ENCLS", "ENCLU", "ENCLV", "ENCODEKEY128", "ENCODEKEY256", - "ENDBR32", "ENDBR64", "ENQCMD", "ENQCMDS", "ENTER", "EXTRACTPS", - "EXTRQ", "F2XM1", "FABS", "FADD", "FADDP", "FBLD", "FBSTP", "FCHS", - "FCMOVB", "FCMOVBE", "FCMOVE", "FCMOVNB", "FCMOVNBE", "FCMOVNE", - "FCMOVNU", "FCMOVU", "FCOM", "FCOMI", "FCOMIP", "FCOMP", "FCOMPP", - "FCOS", "FDECSTP", "FDIV", "FDIVP", "FDIVR", "FDIVRP", "FEMMS", - "FFREE", "FFREEP", "FIADD", "FICOM", "FICOMP", "FIDIV", "FIDIVR", - "FILD", "FIMUL", "FINCSTP", "FIST", "FISTP", "FISTTP", "FISUB", - "FISUBR", "FLD", "FLD1", "FLDCW", "FLDENV", "FLDL2E", "FLDL2T", - "FLDLG2", "FLDLN2", "FLDPI", "FLDZ", "FMUL", "FMULP", "FNCLEX", - "FNDISI", "FNINIT", "FNOP", "FNSAVE", "FNSTCW", "FNSTENV", "FNSTSW", - "FPATAN", "FPREM", "FPREM1", "FPTAN", "FRINEAR", "FRNDINT", "FRSTOR", - "FSCALE", "FSIN", "FSINCOS", "FSQRT", "FST", "FSTDW", "FSTP", - "FSTPNCE", "FSTSG", "FSUB", "FSUBP", "FSUBR", "FSUBRP", "FTST", - "FUCOM", "FUCOMI", "FUCOMIP", "FUCOMP", "FUCOMPP", "FXAM", "FXCH", - "FXRSTOR", "FXRSTOR64", "FXSAVE", "FXSAVE64", "FXTRACT", "FYL2X", - "FYL2XP1", "GETSEC", "GF2P8AFFINEINVQB", "GF2P8AFFINEQB", "GF2P8MULB", - "HADDPD", "HADDPS", "HLT", "HSUBPD", "HSUBPS", "IDIV", "IMUL", - "IN", "INC", "INCSSPD", "INCSSPQ", "INSB", "INSD", "INSERTPS", - "INSERTQ", "INSW", "INT", "INT1", "INT3", "INTO", "INVD", "INVEPT", - "INVLPG", "INVLPGA", "INVLPGB", "INVPCID", "INVVPID", "IRETD", - "IRETQ", "IRETW", "JBE", "JC", "JCXZ", "JECXZ", "JL", "JLE", - "JMP", "JMPE", "JMPF", "JNBE", "JNC", "JNL", "JNLE", "JNO", "JNP", - "JNS", "JNZ", "JO", "JP", "JRCXZ", "JS", "JZ", "KADDB", "KADDD", - "KADDQ", "KADDW", "KANDB", "KANDD", "KANDNB", "KANDND", "KANDNQ", - "KANDNW", "KANDQ", "KANDW", "KMERGE2L1H", "KMERGE2L1L", "KMOVB", - "KMOVD", "KMOVQ", "KMOVW", "KNOTB", "KNOTD", "KNOTQ", "KNOTW", - "KORB", "KORD", "KORQ", "KORTESTB", "KORTESTD", "KORTESTQ", "KORTESTW", - "KORW", "KSHIFTLB", "KSHIFTLD", "KSHIFTLQ", "KSHIFTLW", "KSHIFTRB", - "KSHIFTRD", "KSHIFTRQ", "KSHIFTRW", "KTESTB", "KTESTD", "KTESTQ", - "KTESTW", "KUNPCKBW", "KUNPCKDQ", "KUNPCKWD", "KXNORB", "KXNORD", - "KXNORQ", "KXNORW", "KXORB", "KXORD", "KXORQ", "KXORW", "LAHF", - "LAR", "LDDQU", "LDMXCSR", "LDS", "LDTILECFG", "LEA", "LEAVE", - "LES", "LFENCE", "LFS", "LGDT", "LGS", "LIDT", "LLDT", "LLWPCB", - "LMSW", "LOADIWKEY", "LODSB", "LODSD", "LODSQ", "LODSW", "LOOP", - "LOOPNZ", "LOOPZ", "LSL", "LSS", "LTR", "LWPINS", "LWPVAL", "LZCNT", - "MASKMOVDQU", "MASKMOVQ", "MAXPD", "MAXPS", "MAXSD", "MAXSS", - "MCOMMIT", "MFENCE", "MINPD", "MINPS", "MINSD", "MINSS", "MONITOR", - "MONITORX", "MONTMUL", "MOV", "MOVAPD", "MOVAPS", "MOVBE", "MOVD", - "MOVDDUP", "MOVDIR64B", "MOVDIRI", "MOVDQ2Q", "MOVDQA", "MOVDQU", - "MOVHLPS", "MOVHPD", "MOVHPS", "MOVLHPS", "MOVLPD", "MOVLPS", - "MOVMSKPD", "MOVMSKPS", "MOVNTDQ", "MOVNTDQA", "MOVNTI", "MOVNTPD", - "MOVNTPS", "MOVNTQ", "MOVNTSD", "MOVNTSS", "MOVQ", "MOVQ2DQ", - "MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP", "MOVSQ", "MOVSS", "MOVSW", - "MOVSX", "MOVSXD", "MOVUPD", "MOVUPS", "MOVZX", "MPSADBW", "MUL", - "MULPD", "MULPS", "MULSD", "MULSS", "MULX", "MWAIT", "MWAITX", - "NEG", "NOP", "NOT", "OR", "ORPD", "ORPS", "OUT", "OUTSB", "OUTSD", - "OUTSW", "PABSB", "PABSD", "PABSW", "PACKSSDW", "PACKSSWB", "PACKUSDW", - "PACKUSWB", "PADDB", "PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB", - "PADDUSW", "PADDW", "PALIGNR", "PAND", "PANDN", "PAUSE", "PAVGB", - "PAVGUSB", "PAVGW", "PBLENDVB", "PBLENDW", "PCLMULQDQ", "PCMPEQB", - "PCMPEQD", "PCMPEQQ", "PCMPEQW", "PCMPESTRI", "PCMPESTRM", "PCMPGTB", - "PCMPGTD", "PCMPGTQ", "PCMPGTW", "PCMPISTRI", "PCMPISTRM", "PCOMMIT", - "PCONFIG", "PDEP", "PEXT", "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", - "PF2ID", "PF2IW", "PFACC", "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", - "PFMAX", "PFMIN", "PFMUL", "PFNACC", "PFPNACC", "PFRCP", "PFRCPIT1", - "PFRCPIT2", "PFRCPV", "PFRSQIT1", "PFRSQRT", "PFRSQRTV", "PFSUB", - "PFSUBR", "PHADDD", "PHADDSW", "PHADDW", "PHMINPOSUW", "PHSUBD", - "PHSUBSW", "PHSUBW", "PI2FD", "PI2FW", "PINSRB", "PINSRD", "PINSRQ", - "PINSRW", "PMADDUBSW", "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", - "PMAXUB", "PMAXUD", "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", - "PMINUD", "PMINUW", "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", - "PMOVSXDQ", "PMOVSXWD", "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", - "PMOVZXDQ", "PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", - "PMULHUW", "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", - "POPAD", "POPCNT", "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", - "PREFETCHE", "PREFETCHM", "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", - "PREFETCHT2", "PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB", - "PSHUFD", "PSHUFHW", "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", - "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", "PSLLW", "PSMASH", "PSRAD", - "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", "PSRLW", "PSUBB", "PSUBD", - "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD", - "PTEST", "PTWRITE", "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", - "PUNPCKLBW", "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", - "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW", "PVALIDATE", - "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", "RDGSBASE", - "RDMSR", "RDPID", "RDPKRU", "RDPMC", "RDPRU", "RDRAND", "RDSEED", - "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC", "RDTSCP", "RETF", "RETN", - "RMPADJUST", "RMPUPDATE", "ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", - "ROUNDSD", "ROUNDSS", "RSDC", "RSLDT", "RSM", "RSQRTPS", "RSQRTSS", - "RSTORSSP", "RSTS", "SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP", - "SBB", "SCASB", "SCASD", "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", - "SEAMRET", "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", - "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", - "SETO", "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", - "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", - "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", - "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", - "SMINT", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", - "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", - "STOSQ", "STOSW", "STR", "STTILECFG", "SUB", "SUBPD", "SUBPS", + "CLFLUSHOPT", "CLGI", "CLI", "CLRSSBSY", "CLTS", "CLUI", "CLWB", + "CLZERO", "CMC", "CMOVBE", "CMOVC", "CMOVL", "CMOVLE", "CMOVNBE", + "CMOVNC", "CMOVNL", "CMOVNLE", "CMOVNO", "CMOVNP", "CMOVNS", + "CMOVNZ", "CMOVO", "CMOVP", "CMOVS", "CMOVZ", "CMP", "CMPPD", + "CMPPS", "CMPSB", "CMPSD", "CMPSQ", "CMPSS", "CMPSW", "CMPXCHG", + "CMPXCHG16B", "CMPXCHG8B", "COMISD", "COMISS", "CPUID", "CPU_READ", + "CPU_WRITE", "CQO", "CRC32", "CVTDQ2PD", "CVTDQ2PS", "CVTPD2DQ", + "CVTPD2PI", "CVTPD2PS", "CVTPI2PD", "CVTPI2PS", "CVTPS2DQ", "CVTPS2PD", + "CVTPS2PI", "CVTSD2SI", "CVTSD2SS", "CVTSI2SD", "CVTSI2SS", "CVTSS2SD", + "CVTSS2SI", "CVTTPD2DQ", "CVTTPD2PI", "CVTTPS2DQ", "CVTTPS2PI", + "CVTTSD2SI", "CVTTSS2SI", "CWD", "CWDE", "DAA", "DAS", "DEC", + "DELAY", "DIV", "DIVPD", "DIVPS", "DIVSD", "DIVSS", "DMINT", + "DPPD", "DPPS", "EMMS", "ENCLS", "ENCLU", "ENCLV", "ENCODEKEY128", + "ENCODEKEY256", "ENDBR32", "ENDBR64", "ENQCMD", "ENQCMDS", "ENTER", + "EXTRACTPS", "EXTRQ", "F2XM1", "FABS", "FADD", "FADDP", "FBLD", + "FBSTP", "FCHS", "FCMOVB", "FCMOVBE", "FCMOVE", "FCMOVNB", "FCMOVNBE", + "FCMOVNE", "FCMOVNU", "FCMOVU", "FCOM", "FCOMI", "FCOMIP", "FCOMP", + "FCOMPP", "FCOS", "FDECSTP", "FDIV", "FDIVP", "FDIVR", "FDIVRP", + "FEMMS", "FFREE", "FFREEP", "FIADD", "FICOM", "FICOMP", "FIDIV", + "FIDIVR", "FILD", "FIMUL", "FINCSTP", "FIST", "FISTP", "FISTTP", + "FISUB", "FISUBR", "FLD", "FLD1", "FLDCW", "FLDENV", "FLDL2E", + "FLDL2T", "FLDLG2", "FLDLN2", "FLDPI", "FLDZ", "FMUL", "FMULP", + "FNCLEX", "FNDISI", "FNINIT", "FNOP", "FNSAVE", "FNSTCW", "FNSTENV", + "FNSTSW", "FPATAN", "FPREM", "FPREM1", "FPTAN", "FRINEAR", "FRNDINT", + "FRSTOR", "FSCALE", "FSIN", "FSINCOS", "FSQRT", "FST", "FSTDW", + "FSTP", "FSTPNCE", "FSTSG", "FSUB", "FSUBP", "FSUBR", "FSUBRP", + "FTST", "FUCOM", "FUCOMI", "FUCOMIP", "FUCOMP", "FUCOMPP", "FXAM", + "FXCH", "FXRSTOR", "FXRSTOR64", "FXSAVE", "FXSAVE64", "FXTRACT", + "FYL2X", "FYL2XP1", "GETSEC", "GF2P8AFFINEINVQB", "GF2P8AFFINEQB", + "GF2P8MULB", "HADDPD", "HADDPS", "HLT", "HRESET", "HSUBPD", "HSUBPS", + "IDIV", "IMUL", "IN", "INC", "INCSSPD", "INCSSPQ", "INSB", "INSD", + "INSERTPS", "INSERTQ", "INSW", "INT", "INT1", "INT3", "INTO", + "INVD", "INVEPT", "INVLPG", "INVLPGA", "INVLPGB", "INVPCID", + "INVVPID", "IRETD", "IRETQ", "IRETW", "JBE", "JC", "JCXZ", "JECXZ", + "JL", "JLE", "JMP", "JMPE", "JMPF", "JNBE", "JNC", "JNL", "JNLE", + "JNO", "JNP", "JNS", "JNZ", "JO", "JP", "JRCXZ", "JS", "JZ", + "KADDB", "KADDD", "KADDQ", "KADDW", "KANDB", "KANDD", "KANDNB", + "KANDND", "KANDNQ", "KANDNW", "KANDQ", "KANDW", "KMERGE2L1H", + "KMERGE2L1L", "KMOVB", "KMOVD", "KMOVQ", "KMOVW", "KNOTB", "KNOTD", + "KNOTQ", "KNOTW", "KORB", "KORD", "KORQ", "KORTESTB", "KORTESTD", + "KORTESTQ", "KORTESTW", "KORW", "KSHIFTLB", "KSHIFTLD", "KSHIFTLQ", + "KSHIFTLW", "KSHIFTRB", "KSHIFTRD", "KSHIFTRQ", "KSHIFTRW", "KTESTB", + "KTESTD", "KTESTQ", "KTESTW", "KUNPCKBW", "KUNPCKDQ", "KUNPCKWD", + "KXNORB", "KXNORD", "KXNORQ", "KXNORW", "KXORB", "KXORD", "KXORQ", + "KXORW", "LAHF", "LAR", "LDDQU", "LDMXCSR", "LDS", "LDTILECFG", + "LEA", "LEAVE", "LES", "LFENCE", "LFS", "LGDT", "LGS", "LIDT", + "LLDT", "LLWPCB", "LMSW", "LOADIWKEY", "LODSB", "LODSD", "LODSQ", + "LODSW", "LOOP", "LOOPNZ", "LOOPZ", "LSL", "LSS", "LTR", "LWPINS", + "LWPVAL", "LZCNT", "MASKMOVDQU", "MASKMOVQ", "MAXPD", "MAXPS", + "MAXSD", "MAXSS", "MCOMMIT", "MFENCE", "MINPD", "MINPS", "MINSD", + "MINSS", "MONITOR", "MONITORX", "MONTMUL", "MOV", "MOVAPD", "MOVAPS", + "MOVBE", "MOVD", "MOVDDUP", "MOVDIR64B", "MOVDIRI", "MOVDQ2Q", + "MOVDQA", "MOVDQU", "MOVHLPS", "MOVHPD", "MOVHPS", "MOVLHPS", + "MOVLPD", "MOVLPS", "MOVMSKPD", "MOVMSKPS", "MOVNTDQ", "MOVNTDQA", + "MOVNTI", "MOVNTPD", "MOVNTPS", "MOVNTQ", "MOVNTSD", "MOVNTSS", + "MOVQ", "MOVQ2DQ", "MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP", + "MOVSQ", "MOVSS", "MOVSW", "MOVSX", "MOVSXD", "MOVUPD", "MOVUPS", + "MOVZX", "MPSADBW", "MUL", "MULPD", "MULPS", "MULSD", "MULSS", + "MULX", "MWAIT", "MWAITX", "NEG", "NOP", "NOT", "OR", "ORPD", + "ORPS", "OUT", "OUTSB", "OUTSD", "OUTSW", "PABSB", "PABSD", "PABSW", + "PACKSSDW", "PACKSSWB", "PACKUSDW", "PACKUSWB", "PADDB", "PADDD", + "PADDQ", "PADDSB", "PADDSW", "PADDUSB", "PADDUSW", "PADDW", "PALIGNR", + "PAND", "PANDN", "PAUSE", "PAVGB", "PAVGUSB", "PAVGW", "PBLENDVB", + "PBLENDW", "PCLMULQDQ", "PCMPEQB", "PCMPEQD", "PCMPEQQ", "PCMPEQW", + "PCMPESTRI", "PCMPESTRM", "PCMPGTB", "PCMPGTD", "PCMPGTQ", "PCMPGTW", + "PCMPISTRI", "PCMPISTRM", "PCOMMIT", "PCONFIG", "PDEP", "PEXT", + "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", "PF2ID", "PF2IW", "PFACC", + "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", "PFMAX", "PFMIN", "PFMUL", + "PFNACC", "PFPNACC", "PFRCP", "PFRCPIT1", "PFRCPIT2", "PFRCPV", + "PFRSQIT1", "PFRSQRT", "PFRSQRTV", "PFSUB", "PFSUBR", "PHADDD", + "PHADDSW", "PHADDW", "PHMINPOSUW", "PHSUBD", "PHSUBSW", "PHSUBW", + "PI2FD", "PI2FW", "PINSRB", "PINSRD", "PINSRQ", "PINSRW", "PMADDUBSW", + "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", "PMAXUB", "PMAXUD", + "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", "PMINUD", "PMINUW", + "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", "PMOVSXDQ", "PMOVSXWD", + "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", "PMOVZXDQ", "PMOVZXWD", + "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", "PMULHUW", "PMULHW", + "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", "POPAD", "POPCNT", + "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", "PREFETCHE", "PREFETCHM", + "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", "PREFETCHW", + "PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFLW", + "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", + "PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", + "PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", + "PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE", "PUNPCKHBW", + "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", "PUNPCKLDQ", + "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSHA", "PUSHAD", "PUSHFD", + "PUSHFQ", "PUSHFW", "PVALIDATE", "PXOR", "RCL", "RCPPS", "RCPSS", + "RCR", "RDFSBASE", "RDGSBASE", "RDMSR", "RDPID", "RDPKRU", "RDPMC", + "RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC", + "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPUPDATE", "ROL", "ROR", + "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSDC", "RSLDT", + "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", "SAHF", "SAL", + "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD", + "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", "SENDUIPI", + "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", "SETNC", + "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", "SETO", + "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", "SHA1MSG1", + "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", + "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", "SHRX", + "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", "SMINT", + "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", "STAC", + "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", "STOSQ", + "STOSW", "STR", "STTILECFG", "STUI", "SUB", "SUBPD", "SUBPS", "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", "SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TDCALL", "TDPBF16PS", - "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TEST", "TILELOADD", - "TILELOADDT1", "TILERELEASE", "TILESTORED", "TILEZERO", "TLBSYNC", - "TPAUSE", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", "UD0", "UD1", - "UD2", "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", - "UNPCKLPS", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", - "VADDPD", "VADDPS", "VADDSD", "VADDSS", "VADDSUBPD", "VADDSUBPS", - "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC", - "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", "VANDNPS", - "VANDPD", "VANDPS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", - "VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", - "VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", - "VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", - "VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", - "VCMPPD", "VCMPPS", "VCMPSD", "VCMPSS", "VCOMISD", "VCOMISS", - "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PS", "VCVTNE2PS2BF16", - "VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", - "VCVTPD2UQQ", "VCVTPH2PS", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", - "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PS", - "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", "VCVTSI2SD", "VCVTSI2SS", - "VCVTSS2SD", "VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", - "VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", - "VCVTTPS2UQQ", "VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSS2SI", "VCVTTSS2USI", - "VCVTUDQ2PD", "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PS", "VCVTUSI2SD", - "VCVTUSI2SS", "VDBPSADBW", "VDIVPD", "VDIVPS", "VDIVSD", "VDIVSS", - "VDPBF16PS", "VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", - "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", - "VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4", - "VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS", - "VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD", - "VFMADD132PS", "VFMADD132SD", "VFMADD132SS", "VFMADD213PD", "VFMADD213PS", - "VFMADD213SD", "VFMADD213SS", "VFMADD231PD", "VFMADD231PS", "VFMADD231SD", - "VFMADD231SS", "VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS", - "VFMADDSUB132PD", "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PS", - "VFMADDSUB231PD", "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS", - "VFMSUB132PD", "VFMSUB132PS", "VFMSUB132SD", "VFMSUB132SS", "VFMSUB213PD", - "VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SS", "VFMSUB231PD", "VFMSUB231PS", - "VFMSUB231SD", "VFMSUB231SS", "VFMSUBADD132PD", "VFMSUBADD132PS", - "VFMSUBADD213PD", "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PS", - "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD", - "VFMSUBSS", "VFNMADD132PD", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SS", + "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TEST", "TESTUI", + "TILELOADD", "TILELOADDT1", "TILERELEASE", "TILESTORED", "TILEZERO", + "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", + "UD0", "UD1", "UD2", "UIRET", "UMONITOR", "UMWAIT", "UNPCKHPD", + "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "V4FMADDPS", "V4FMADDSS", + "V4FNMADDPS", "V4FNMADDSS", "VADDPD", "VADDPS", "VADDSD", "VADDSS", + "VADDSUBPD", "VADDSUBPS", "VAESDEC", "VAESDECLAST", "VAESENC", + "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", + "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", "VBLENDMPD", "VBLENDMPS", + "VBLENDPD", "VBLENDPS", "VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", + "VBROADCASTF32X2", "VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", + "VBROADCASTF64X4", "VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", + "VBROADCASTI32X8", "VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", + "VBROADCASTSS", "VCMPPD", "VCMPPS", "VCMPSD", "VCMPSS", "VCOMISD", + "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PS", + "VCVTNE2PS2BF16", "VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PS", + "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", "VCVTPH2PS", "VCVTPS2DQ", + "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", + "VCVTQQ2PD", "VCVTQQ2PS", "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", + "VCVTSI2SD", "VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SI", "VCVTSS2USI", + "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPS2DQ", + "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", "VCVTTSD2SI", "VCVTTSD2USI", + "VCVTTSS2SI", "VCVTTSS2USI", "VCVTUDQ2PD", "VCVTUDQ2PS", "VCVTUQQ2PD", + "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SS", "VDBPSADBW", "VDIVPD", + "VDIVPS", "VDIVSD", "VDIVSS", "VDPBF16PS", "VDPPD", "VDPPS", + "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD", "VEXPANDPS", + "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", "VEXTRACTF64X2", + "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4", "VEXTRACTI32X8", + "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS", "VFIXUPIMMPD", + "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD", "VFMADD132PS", + "VFMADD132SD", "VFMADD132SS", "VFMADD213PD", "VFMADD213PS", "VFMADD213SD", + "VFMADD213SS", "VFMADD231PD", "VFMADD231PS", "VFMADD231SD", "VFMADD231SS", + "VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD", + "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PS", "VFMADDSUB231PD", + "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS", "VFMSUB132PD", + "VFMSUB132PS", "VFMSUB132SD", "VFMSUB132SS", "VFMSUB213PD", "VFMSUB213PS", + "VFMSUB213SD", "VFMSUB213SS", "VFMSUB231PD", "VFMSUB231PS", "VFMSUB231SD", + "VFMSUB231SS", "VFMSUBADD132PD", "VFMSUBADD132PS", "VFMSUBADD213PD", + "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PS", "VFMSUBADDPD", + "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD", "VFMSUBSS", + "VFNMADD132PD", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SS", "VFNMADD213PD", "VFNMADD213PS", "VFNMADD213SD", "VFNMADD213SS", "VFNMADD231PD", "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SS", "VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", "VFNMSUB132PD", diff --git a/bddisasm/include/table_evex.h b/bddisasm/include/table_evex.h index 04c2997..b5c1473 100644 --- a/bddisasm/include/table_evex.h +++ b/bddisasm/include/table_evex.h @@ -4,7 +4,7 @@ const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_03_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1348] + (const void *)&gInstructions[1354] }; const ND_TABLE_VEX_W gEvexTable_root_02_9a_03_mem_02_w = @@ -39,13 +39,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9a_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1571] + (const void *)&gInstructions[1577] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1573] + (const void *)&gInstructions[1579] }; const ND_TABLE_VEX_W gEvexTable_root_02_9a_01_w = @@ -71,7 +71,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_03_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1349] + (const void *)&gInstructions[1355] }; const ND_TABLE_VEX_W gEvexTable_root_02_9b_03_mem_w = @@ -95,13 +95,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9b_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1575] + (const void *)&gInstructions[1581] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1577] + (const void *)&gInstructions[1583] }; const ND_TABLE_VEX_W gEvexTable_root_02_9b_01_w = @@ -127,7 +127,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_03_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1350] + (const void *)&gInstructions[1356] }; const ND_TABLE_VEX_W gEvexTable_root_02_aa_03_mem_02_w = @@ -162,13 +162,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_aa_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1579] + (const void *)&gInstructions[1585] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1581] + (const void *)&gInstructions[1587] }; const ND_TABLE_VEX_W gEvexTable_root_02_aa_01_w = @@ -194,7 +194,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_aa_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_03_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1351] + (const void *)&gInstructions[1357] }; const ND_TABLE_VEX_W gEvexTable_root_02_ab_03_mem_w = @@ -218,13 +218,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_ab_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1583] + (const void *)&gInstructions[1589] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1585] + (const void *)&gInstructions[1591] }; const ND_TABLE_VEX_W gEvexTable_root_02_ab_01_w = @@ -250,7 +250,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ab_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_de_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1362] + (const void *)&gInstructions[1368] }; const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp = @@ -267,7 +267,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_df_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1364] + (const void *)&gInstructions[1370] }; const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp = @@ -284,7 +284,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_dc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1366] + (const void *)&gInstructions[1372] }; const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp = @@ -301,7 +301,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_dd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1368] + (const void *)&gInstructions[1374] }; const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp = @@ -318,13 +318,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1382] + (const void *)&gInstructions[1388] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1383] + (const void *)&gInstructions[1389] }; const ND_TABLE_VEX_W gEvexTable_root_02_65_01_w = @@ -350,13 +350,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_65_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1389] + (const void *)&gInstructions[1395] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1400] + (const void *)&gInstructions[1406] }; const ND_TABLE_VEX_W gEvexTable_root_02_19_01_w = @@ -382,13 +382,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_19_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1390] + (const void *)&gInstructions[1396] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1392] + (const void *)&gInstructions[1398] }; const ND_TABLE_VEX_W gEvexTable_root_02_1a_01_mem_w = @@ -423,13 +423,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1391] + (const void *)&gInstructions[1397] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1393] + (const void *)&gInstructions[1399] }; const ND_TABLE_VEX_W gEvexTable_root_02_1b_01_mem_02_w = @@ -475,13 +475,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1395] + (const void *)&gInstructions[1401] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1954] + (const void *)&gInstructions[1960] }; const ND_TABLE_VEX_W gEvexTable_root_02_59_01_w = @@ -507,13 +507,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_59_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1396] + (const void *)&gInstructions[1402] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1398] + (const void *)&gInstructions[1404] }; const ND_TABLE_VEX_W gEvexTable_root_02_5a_01_mem_w = @@ -548,13 +548,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1397] + (const void *)&gInstructions[1403] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1399] + (const void *)&gInstructions[1405] }; const ND_TABLE_VEX_W gEvexTable_root_02_5b_01_mem_02_w = @@ -600,7 +600,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_18_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1402] + (const void *)&gInstructions[1408] }; const ND_TABLE_VEX_W gEvexTable_root_02_18_01_w = @@ -626,13 +626,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_18_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1416] + (const void *)&gInstructions[1422] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1417] + (const void *)&gInstructions[1423] }; const ND_TABLE_VEX_W gEvexTable_root_02_8a_01_w = @@ -658,7 +658,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1423] + (const void *)&gInstructions[1429] }; const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w = @@ -673,7 +673,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1424] + (const void *)&gInstructions[1430] }; const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w = @@ -688,7 +688,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2302] + (const void *)&gInstructions[2312] }; const ND_TABLE_VEX_W gEvexTable_root_02_72_01_w = @@ -714,7 +714,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_72_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1433] + (const void *)&gInstructions[1439] }; const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w = @@ -729,7 +729,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2200] + (const void *)&gInstructions[2210] }; const ND_TABLE_VEX_W gEvexTable_root_02_13_02_w = @@ -755,7 +755,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_13_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1496] + (const void *)&gInstructions[1502] }; const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w = @@ -770,7 +770,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_03_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1894] + (const void *)&gInstructions[1900] }; const ND_TABLE_VEX_W gEvexTable_root_02_52_03_mem_02_w = @@ -805,7 +805,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_52_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2008] + (const void *)&gInstructions[2016] }; const ND_TABLE_VEX_W gEvexTable_root_02_52_01_w = @@ -831,13 +831,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_52_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1501] + (const void *)&gInstructions[1507] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1502] + (const void *)&gInstructions[1508] }; const ND_TABLE_VEX_W gEvexTable_root_02_c8_01_02_w = @@ -874,13 +874,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1503] + (const void *)&gInstructions[1509] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1504] + (const void *)&gInstructions[1510] }; const ND_TABLE_VEX_W gEvexTable_root_02_88_01_w = @@ -906,13 +906,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_88_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1523] + (const void *)&gInstructions[1529] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1525] + (const void *)&gInstructions[1531] }; const ND_TABLE_VEX_W gEvexTable_root_02_98_01_w = @@ -938,13 +938,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_98_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1527] + (const void *)&gInstructions[1533] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1529] + (const void *)&gInstructions[1535] }; const ND_TABLE_VEX_W gEvexTable_root_02_99_01_w = @@ -970,13 +970,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_99_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1531] + (const void *)&gInstructions[1537] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1533] + (const void *)&gInstructions[1539] }; const ND_TABLE_VEX_W gEvexTable_root_02_a8_01_w = @@ -1002,13 +1002,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1535] + (const void *)&gInstructions[1541] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1537] + (const void *)&gInstructions[1543] }; const ND_TABLE_VEX_W gEvexTable_root_02_a9_01_w = @@ -1034,13 +1034,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1539] + (const void *)&gInstructions[1545] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1541] + (const void *)&gInstructions[1547] }; const ND_TABLE_VEX_W gEvexTable_root_02_b8_01_w = @@ -1066,13 +1066,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1543] + (const void *)&gInstructions[1549] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1545] + (const void *)&gInstructions[1551] }; const ND_TABLE_VEX_W gEvexTable_root_02_b9_01_w = @@ -1098,13 +1098,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1555] + (const void *)&gInstructions[1561] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1557] + (const void *)&gInstructions[1563] }; const ND_TABLE_VEX_W gEvexTable_root_02_96_01_w = @@ -1130,13 +1130,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_96_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1559] + (const void *)&gInstructions[1565] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1561] + (const void *)&gInstructions[1567] }; const ND_TABLE_VEX_W gEvexTable_root_02_a6_01_w = @@ -1162,13 +1162,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1563] + (const void *)&gInstructions[1569] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1565] + (const void *)&gInstructions[1571] }; const ND_TABLE_VEX_W gEvexTable_root_02_b6_01_w = @@ -1194,13 +1194,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1587] + (const void *)&gInstructions[1593] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1589] + (const void *)&gInstructions[1595] }; const ND_TABLE_VEX_W gEvexTable_root_02_ba_01_w = @@ -1226,13 +1226,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ba_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1591] + (const void *)&gInstructions[1597] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1593] + (const void *)&gInstructions[1599] }; const ND_TABLE_VEX_W gEvexTable_root_02_bb_01_w = @@ -1258,13 +1258,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1595] + (const void *)&gInstructions[1601] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1597] + (const void *)&gInstructions[1603] }; const ND_TABLE_VEX_W gEvexTable_root_02_97_01_w = @@ -1290,13 +1290,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_97_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1599] + (const void *)&gInstructions[1605] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1601] + (const void *)&gInstructions[1607] }; const ND_TABLE_VEX_W gEvexTable_root_02_a7_01_w = @@ -1322,13 +1322,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1603] + (const void *)&gInstructions[1609] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1605] + (const void *)&gInstructions[1611] }; const ND_TABLE_VEX_W gEvexTable_root_02_b7_01_w = @@ -1354,13 +1354,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1619] + (const void *)&gInstructions[1625] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1621] + (const void *)&gInstructions[1627] }; const ND_TABLE_VEX_W gEvexTable_root_02_9c_01_w = @@ -1386,13 +1386,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1623] + (const void *)&gInstructions[1629] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1625] + (const void *)&gInstructions[1631] }; const ND_TABLE_VEX_W gEvexTable_root_02_9d_01_w = @@ -1418,13 +1418,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1627] + (const void *)&gInstructions[1633] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1629] + (const void *)&gInstructions[1635] }; const ND_TABLE_VEX_W gEvexTable_root_02_ac_01_w = @@ -1450,13 +1450,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ac_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1631] + (const void *)&gInstructions[1637] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1633] + (const void *)&gInstructions[1639] }; const ND_TABLE_VEX_W gEvexTable_root_02_ad_01_w = @@ -1482,13 +1482,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ad_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1635] + (const void *)&gInstructions[1641] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1637] + (const void *)&gInstructions[1643] }; const ND_TABLE_VEX_W gEvexTable_root_02_bc_01_w = @@ -1514,13 +1514,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1639] + (const void *)&gInstructions[1645] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1641] + (const void *)&gInstructions[1647] }; const ND_TABLE_VEX_W gEvexTable_root_02_bd_01_w = @@ -1546,13 +1546,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1651] + (const void *)&gInstructions[1657] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1653] + (const void *)&gInstructions[1659] }; const ND_TABLE_VEX_W gEvexTable_root_02_9e_01_w = @@ -1578,13 +1578,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1655] + (const void *)&gInstructions[1661] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1657] + (const void *)&gInstructions[1663] }; const ND_TABLE_VEX_W gEvexTable_root_02_9f_01_w = @@ -1610,13 +1610,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1659] + (const void *)&gInstructions[1665] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1661] + (const void *)&gInstructions[1667] }; const ND_TABLE_VEX_W gEvexTable_root_02_ae_01_w = @@ -1642,13 +1642,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ae_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1663] + (const void *)&gInstructions[1669] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1665] + (const void *)&gInstructions[1671] }; const ND_TABLE_VEX_W gEvexTable_root_02_af_01_w = @@ -1674,13 +1674,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_af_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1667] + (const void *)&gInstructions[1673] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1669] + (const void *)&gInstructions[1675] }; const ND_TABLE_VEX_W gEvexTable_root_02_be_01_w = @@ -1706,13 +1706,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_be_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1671] + (const void *)&gInstructions[1677] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1673] + (const void *)&gInstructions[1679] }; const ND_TABLE_VEX_W gEvexTable_root_02_bf_01_w = @@ -1738,13 +1738,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bf_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1691] + (const void *)&gInstructions[1697] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1693] + (const void *)&gInstructions[1699] }; const ND_TABLE_VEX_W gEvexTable_root_02_92_01_mem_w = @@ -1779,13 +1779,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_92_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1695] + (const void *)&gInstructions[1701] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1696] + (const void *)&gInstructions[1702] }; const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_01_02_w = @@ -1811,13 +1811,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_01_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1699] + (const void *)&gInstructions[1705] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1700] + (const void *)&gInstructions[1706] }; const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_02_02_w = @@ -1843,13 +1843,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_02_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2456] + (const void *)&gInstructions[2466] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2457] + (const void *)&gInstructions[2467] }; const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_05_02_w = @@ -1875,13 +1875,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_05_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2460] + (const void *)&gInstructions[2470] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2461] + (const void *)&gInstructions[2471] }; const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_06_02_w = @@ -1942,13 +1942,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1697] + (const void *)&gInstructions[1703] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1698] + (const void *)&gInstructions[1704] }; const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_01_02_w = @@ -1974,13 +1974,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_01_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1701] + (const void *)&gInstructions[1707] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1702] + (const void *)&gInstructions[1708] }; const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_02_02_w = @@ -2006,13 +2006,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_02_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2458] + (const void *)&gInstructions[2468] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2459] + (const void *)&gInstructions[2469] }; const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_05_02_w = @@ -2038,13 +2038,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_05_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2462] + (const void *)&gInstructions[2472] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2463] + (const void *)&gInstructions[2473] }; const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_06_02_w = @@ -2105,13 +2105,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1703] + (const void *)&gInstructions[1709] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1705] + (const void *)&gInstructions[1711] }; const ND_TABLE_VEX_W gEvexTable_root_02_93_01_mem_w = @@ -2146,13 +2146,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_93_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1707] + (const void *)&gInstructions[1713] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1708] + (const void *)&gInstructions[1714] }; const ND_TABLE_VEX_W gEvexTable_root_02_42_01_w = @@ -2178,13 +2178,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_42_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1709] + (const void *)&gInstructions[1715] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1710] + (const void *)&gInstructions[1716] }; const ND_TABLE_VEX_W gEvexTable_root_02_43_01_w = @@ -2210,7 +2210,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_43_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_cf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1719] + (const void *)&gInstructions[1725] }; const ND_TABLE_VEX_W gEvexTable_root_02_cf_01_w = @@ -2236,7 +2236,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cf_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1828] + (const void *)&gInstructions[1834] }; const ND_TABLE_VEX_W gEvexTable_root_02_2a_01_mem_w = @@ -2260,7 +2260,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1952] + (const void *)&gInstructions[1958] }; const ND_TABLE_VEX_W gEvexTable_root_02_2a_02_reg_w = @@ -2295,13 +2295,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1892] + (const void *)&gInstructions[1898] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1893] + (const void *)&gInstructions[1899] }; const ND_TABLE_VEX_W gEvexTable_root_02_68_03_w = @@ -2327,7 +2327,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_68_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_03_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1895] + (const void *)&gInstructions[1901] }; const ND_TABLE_VEX_W gEvexTable_root_02_53_03_mem_02_w = @@ -2362,7 +2362,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_53_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2009] + (const void *)&gInstructions[2018] }; const ND_TABLE_VEX_W gEvexTable_root_02_53_01_w = @@ -2388,7 +2388,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_53_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1896] + (const void *)&gInstructions[1902] }; const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp = @@ -2405,7 +2405,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1898] + (const void *)&gInstructions[1904] }; const ND_TABLE_VEX_W gEvexTable_root_02_1e_01_w = @@ -2431,7 +2431,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1900] + (const void *)&gInstructions[1906] }; const ND_TABLE_VEX_W gEvexTable_root_02_1f_01_w = @@ -2457,7 +2457,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1901] + (const void *)&gInstructions[1907] }; const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp = @@ -2474,7 +2474,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1907] + (const void *)&gInstructions[1913] }; const ND_TABLE_VEX_W gEvexTable_root_02_2b_01_w = @@ -2500,13 +2500,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1940] + (const void *)&gInstructions[1946] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1943] + (const void *)&gInstructions[1949] }; const ND_TABLE_VEX_W gEvexTable_root_02_66_01_w = @@ -2532,13 +2532,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_66_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1941] + (const void *)&gInstructions[1947] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1942] + (const void *)&gInstructions[1948] }; const ND_TABLE_VEX_W gEvexTable_root_02_64_01_w = @@ -2564,7 +2564,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_64_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1946] + (const void *)&gInstructions[1952] }; const ND_TABLE_VEX_W gEvexTable_root_02_78_01_w = @@ -2590,7 +2590,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_78_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7a_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1947] + (const void *)&gInstructions[1953] }; const ND_TABLE_VEX_W gEvexTable_root_02_7a_01_reg_w = @@ -2625,7 +2625,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_58_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1949] + (const void *)&gInstructions[1955] }; const ND_TABLE_VEX_W gEvexTable_root_02_58_01_w = @@ -2651,13 +2651,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_58_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1950] + (const void *)&gInstructions[1956] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1955] + (const void *)&gInstructions[1961] }; const ND_TABLE_VEX_W gEvexTable_root_02_7c_01_reg_w = @@ -2692,7 +2692,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1953] + (const void *)&gInstructions[1959] }; const ND_TABLE_VEX_W gEvexTable_root_02_3a_02_reg_w = @@ -2716,7 +2716,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_3a_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2160] + (const void *)&gInstructions[2170] }; const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp = @@ -2733,7 +2733,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1957] + (const void *)&gInstructions[1963] }; const ND_TABLE_VEX_W gEvexTable_root_02_79_01_w = @@ -2759,7 +2759,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_79_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7b_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1958] + (const void *)&gInstructions[1964] }; const ND_TABLE_VEX_W gEvexTable_root_02_7b_01_reg_w = @@ -2794,7 +2794,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1970] + (const void *)&gInstructions[1976] }; const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w = @@ -2809,13 +2809,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2162] + (const void *)&gInstructions[2172] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2205] + (const void *)&gInstructions[2215] }; const ND_TABLE_VEX_W gEvexTable_root_02_29_02_reg_w = @@ -2850,7 +2850,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_29_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_37_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1980] + (const void *)&gInstructions[1986] }; const ND_TABLE_VEX_W gEvexTable_root_02_37_01_w = @@ -2876,13 +2876,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_37_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1994] + (const void *)&gInstructions[2000] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1997] + (const void *)&gInstructions[2003] }; const ND_TABLE_VEX_W gEvexTable_root_02_63_01_w = @@ -2908,13 +2908,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_63_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1995] + (const void *)&gInstructions[2001] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1996] + (const void *)&gInstructions[2002] }; const ND_TABLE_VEX_W gEvexTable_root_02_8b_01_w = @@ -2940,13 +2940,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2004] + (const void *)&gInstructions[2010] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2005] + (const void *)&gInstructions[2011] }; const ND_TABLE_VEX_W gEvexTable_root_02_c4_01_w = @@ -2972,7 +2972,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_50_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2006] + (const void *)&gInstructions[2012] }; const ND_TABLE_VEX_W gEvexTable_root_02_50_01_w = @@ -2998,7 +2998,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_50_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_51_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2007] + (const void *)&gInstructions[2014] }; const ND_TABLE_VEX_W gEvexTable_root_02_51_01_w = @@ -3024,13 +3024,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_51_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2012] + (const void *)&gInstructions[2022] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2049] + (const void *)&gInstructions[2059] }; const ND_TABLE_VEX_W gEvexTable_root_02_8d_01_w = @@ -3056,13 +3056,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2013] + (const void *)&gInstructions[2023] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2040] + (const void *)&gInstructions[2050] }; const ND_TABLE_VEX_W gEvexTable_root_02_36_01_w = @@ -3088,13 +3088,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_36_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2015] + (const void *)&gInstructions[2025] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2020] + (const void *)&gInstructions[2030] }; const ND_TABLE_VEX_W gEvexTable_root_02_75_01_w = @@ -3120,13 +3120,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_75_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2016] + (const void *)&gInstructions[2026] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2019] + (const void *)&gInstructions[2029] }; const ND_TABLE_VEX_W gEvexTable_root_02_76_01_w = @@ -3152,13 +3152,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_76_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2017] + (const void *)&gInstructions[2027] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2018] + (const void *)&gInstructions[2028] }; const ND_TABLE_VEX_W gEvexTable_root_02_77_01_w = @@ -3184,7 +3184,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_77_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_0d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2025] + (const void *)&gInstructions[2035] }; const ND_TABLE_VEX_W gEvexTable_root_02_0d_01_w = @@ -3210,7 +3210,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_0c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2029] + (const void *)&gInstructions[2039] }; const ND_TABLE_VEX_W gEvexTable_root_02_0c_01_w = @@ -3236,13 +3236,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2033] + (const void *)&gInstructions[2043] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2037] + (const void *)&gInstructions[2047] }; const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w = @@ -3257,13 +3257,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2034] + (const void *)&gInstructions[2044] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2038] + (const void *)&gInstructions[2048] }; const ND_TABLE_VEX_W gEvexTable_root_02_16_01_02_w = @@ -3300,13 +3300,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_16_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2043] + (const void *)&gInstructions[2053] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2048] + (const void *)&gInstructions[2058] }; const ND_TABLE_VEX_W gEvexTable_root_02_7d_01_w = @@ -3332,13 +3332,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2044] + (const void *)&gInstructions[2054] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2047] + (const void *)&gInstructions[2057] }; const ND_TABLE_VEX_W gEvexTable_root_02_7e_01_w = @@ -3364,13 +3364,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2045] + (const void *)&gInstructions[2055] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2046] + (const void *)&gInstructions[2056] }; const ND_TABLE_VEX_W gEvexTable_root_02_7f_01_w = @@ -3396,13 +3396,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2050] + (const void *)&gInstructions[2060] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2053] + (const void *)&gInstructions[2063] }; const ND_TABLE_VEX_W gEvexTable_root_02_62_01_w = @@ -3428,13 +3428,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_62_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2051] + (const void *)&gInstructions[2061] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2052] + (const void *)&gInstructions[2062] }; const ND_TABLE_VEX_W gEvexTable_root_02_89_01_w = @@ -3460,13 +3460,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_89_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2068] + (const void *)&gInstructions[2078] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2070] + (const void *)&gInstructions[2080] }; const ND_TABLE_VEX_W gEvexTable_root_02_90_01_mem_w = @@ -3501,13 +3501,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_90_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2072] + (const void *)&gInstructions[2082] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2074] + (const void *)&gInstructions[2084] }; const ND_TABLE_VEX_W gEvexTable_root_02_91_01_mem_w = @@ -3542,13 +3542,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_91_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2110] + (const void *)&gInstructions[2120] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2111] + (const void *)&gInstructions[2121] }; const ND_TABLE_VEX_W gEvexTable_root_02_44_01_w = @@ -3574,7 +3574,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_44_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b5_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2124] + (const void *)&gInstructions[2134] }; const ND_TABLE_VEX_W gEvexTable_root_02_b5_01_w = @@ -3600,7 +3600,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2125] + (const void *)&gInstructions[2135] }; const ND_TABLE_VEX_W gEvexTable_root_02_b4_01_w = @@ -3626,7 +3626,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2126] + (const void *)&gInstructions[2136] }; const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp = @@ -3643,7 +3643,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2134] + (const void *)&gInstructions[2144] }; const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp = @@ -3660,13 +3660,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2136] + (const void *)&gInstructions[2146] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2138] + (const void *)&gInstructions[2148] }; const ND_TABLE_VEX_W gEvexTable_root_02_3d_01_w = @@ -3692,13 +3692,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2143] + (const void *)&gInstructions[2153] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2145] + (const void *)&gInstructions[2155] }; const ND_TABLE_VEX_W gEvexTable_root_02_3f_01_w = @@ -3724,7 +3724,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2146] + (const void *)&gInstructions[2156] }; const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp = @@ -3741,19 +3741,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2148] + (const void *)&gInstructions[2158] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2167] + (const void *)&gInstructions[2177] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2168] + (const void *)&gInstructions[2178] }; const ND_TABLE_VEX_W gEvexTable_root_02_38_02_reg_w = @@ -3788,13 +3788,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_38_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2150] + (const void *)&gInstructions[2160] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2152] + (const void *)&gInstructions[2162] }; const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w = @@ -3809,13 +3809,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2163] + (const void *)&gInstructions[2173] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2171] + (const void *)&gInstructions[2181] }; const ND_TABLE_VEX_W gEvexTable_root_02_39_02_reg_w = @@ -3850,13 +3850,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_39_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2157] + (const void *)&gInstructions[2167] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2159] + (const void *)&gInstructions[2169] }; const ND_TABLE_VEX_W gEvexTable_root_02_3b_01_w = @@ -3882,7 +3882,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2164] + (const void *)&gInstructions[2174] }; const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w = @@ -3897,7 +3897,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2207] + (const void *)&gInstructions[2217] }; const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp = @@ -3914,7 +3914,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2165] + (const void *)&gInstructions[2175] }; const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w = @@ -3929,7 +3929,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2219] + (const void *)&gInstructions[2229] }; const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp = @@ -3946,13 +3946,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2166] + (const void *)&gInstructions[2176] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2169] + (const void *)&gInstructions[2179] }; const ND_TABLE_VEX_W gEvexTable_root_02_28_02_reg_w = @@ -3976,7 +3976,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_28_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2225] + (const void *)&gInstructions[2235] }; const ND_TABLE_VEX_W gEvexTable_root_02_28_01_w = @@ -4002,7 +4002,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_28_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2172] + (const void *)&gInstructions[2182] }; const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w = @@ -4017,7 +4017,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2210] + (const void *)&gInstructions[2220] }; const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp = @@ -4034,7 +4034,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2173] + (const void *)&gInstructions[2183] }; const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w = @@ -4049,7 +4049,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2216] + (const void *)&gInstructions[2226] }; const ND_TABLE_VEX_W gEvexTable_root_02_35_01_w = @@ -4075,7 +4075,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_35_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2174] + (const void *)&gInstructions[2184] }; const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w = @@ -4090,7 +4090,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2222] + (const void *)&gInstructions[2232] }; const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp = @@ -4107,7 +4107,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2175] + (const void *)&gInstructions[2185] }; const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w = @@ -4122,7 +4122,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2181] + (const void *)&gInstructions[2191] }; const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp = @@ -4139,7 +4139,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2176] + (const void *)&gInstructions[2186] }; const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w = @@ -4154,7 +4154,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2193] + (const void *)&gInstructions[2203] }; const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp = @@ -4171,7 +4171,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2177] + (const void *)&gInstructions[2187] }; const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w = @@ -4186,7 +4186,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2184] + (const void *)&gInstructions[2194] }; const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp = @@ -4203,7 +4203,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2178] + (const void *)&gInstructions[2188] }; const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w = @@ -4218,7 +4218,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2190] + (const void *)&gInstructions[2200] }; const ND_TABLE_VEX_W gEvexTable_root_02_25_01_w = @@ -4244,7 +4244,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_25_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2179] + (const void *)&gInstructions[2189] }; const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w = @@ -4259,7 +4259,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2196] + (const void *)&gInstructions[2206] }; const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp = @@ -4276,7 +4276,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2180] + (const void *)&gInstructions[2190] }; const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w = @@ -4291,7 +4291,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2187] + (const void *)&gInstructions[2197] }; const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp = @@ -4308,7 +4308,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2199] + (const void *)&gInstructions[2209] }; const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w = @@ -4323,7 +4323,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2344] + (const void *)&gInstructions[2354] }; const ND_TABLE_VEX_W gEvexTable_root_02_11_01_w = @@ -4349,7 +4349,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_11_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2201] + (const void *)&gInstructions[2211] }; const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w = @@ -4364,7 +4364,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2330] + (const void *)&gInstructions[2340] }; const ND_TABLE_VEX_W gEvexTable_root_02_12_01_w = @@ -4390,7 +4390,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_12_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2202] + (const void *)&gInstructions[2212] }; const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w = @@ -4405,13 +4405,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2252] + (const void *)&gInstructions[2262] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2253] + (const void *)&gInstructions[2263] }; const ND_TABLE_VEX_W gEvexTable_root_02_15_01_w = @@ -4437,7 +4437,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_15_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2203] + (const void *)&gInstructions[2213] }; const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w = @@ -4452,13 +4452,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2256] + (const void *)&gInstructions[2266] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2257] + (const void *)&gInstructions[2267] }; const ND_TABLE_VEX_W gEvexTable_root_02_14_01_w = @@ -4484,7 +4484,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_14_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2204] + (const void *)&gInstructions[2214] }; const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w = @@ -4499,7 +4499,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2363] + (const void *)&gInstructions[2373] }; const ND_TABLE_VEX_W gEvexTable_root_02_10_01_w = @@ -4525,7 +4525,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_10_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2206] + (const void *)&gInstructions[2216] }; const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w = @@ -4540,7 +4540,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2213] + (const void *)&gInstructions[2223] }; const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp = @@ -4557,7 +4557,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_0b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2227] + (const void *)&gInstructions[2237] }; const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp = @@ -4574,13 +4574,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2233] + (const void *)&gInstructions[2243] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2235] + (const void *)&gInstructions[2245] }; const ND_TABLE_VEX_W gEvexTable_root_02_40_01_w = @@ -4606,7 +4606,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_40_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_83_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2238] + (const void *)&gInstructions[2248] }; const ND_TABLE_VEX_W gEvexTable_root_02_83_01_w = @@ -4632,13 +4632,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_83_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2241] + (const void *)&gInstructions[2251] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2244] + (const void *)&gInstructions[2254] }; const ND_TABLE_VEX_W gEvexTable_root_02_54_01_w = @@ -4664,13 +4664,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_54_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2242] + (const void *)&gInstructions[2252] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2243] + (const void *)&gInstructions[2253] }; const ND_TABLE_VEX_W gEvexTable_root_02_55_01_w = @@ -4696,13 +4696,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_55_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2272] + (const void *)&gInstructions[2282] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2273] + (const void *)&gInstructions[2283] }; const ND_TABLE_VEX_W gEvexTable_root_02_a0_01_mem_w = @@ -4737,13 +4737,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a0_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2274] + (const void *)&gInstructions[2284] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2275] + (const void *)&gInstructions[2285] }; const ND_TABLE_VEX_W gEvexTable_root_02_a1_01_mem_w = @@ -4778,13 +4778,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a1_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2291] + (const void *)&gInstructions[2301] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2292] + (const void *)&gInstructions[2302] }; const ND_TABLE_VEX_W gEvexTable_root_02_71_01_w = @@ -4810,7 +4810,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_71_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_70_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2293] + (const void *)&gInstructions[2303] }; const ND_TABLE_VEX_W gEvexTable_root_02_70_01_w = @@ -4836,13 +4836,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_70_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2300] + (const void *)&gInstructions[2310] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2301] + (const void *)&gInstructions[2311] }; const ND_TABLE_VEX_W gEvexTable_root_02_73_01_w = @@ -4868,7 +4868,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_73_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2304] + (const void *)&gInstructions[2314] }; const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp = @@ -4885,7 +4885,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_8f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2306] + (const void *)&gInstructions[2316] }; const ND_TABLE_VEX_W gEvexTable_root_02_8f_01_w = @@ -4911,13 +4911,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2326] + (const void *)&gInstructions[2336] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2328] + (const void *)&gInstructions[2338] }; const ND_TABLE_VEX_W gEvexTable_root_02_47_01_w = @@ -4943,13 +4943,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_47_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2341] + (const void *)&gInstructions[2351] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2343] + (const void *)&gInstructions[2353] }; const ND_TABLE_VEX_W gEvexTable_root_02_46_01_w = @@ -4975,13 +4975,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_46_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2359] + (const void *)&gInstructions[2369] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2361] + (const void *)&gInstructions[2371] }; const ND_TABLE_VEX_W gEvexTable_root_02_45_01_w = @@ -5007,13 +5007,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_45_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2387] + (const void *)&gInstructions[2397] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2390] + (const void *)&gInstructions[2400] }; const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w = @@ -5028,13 +5028,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2391] + (const void *)&gInstructions[2401] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2394] + (const void *)&gInstructions[2404] }; const ND_TABLE_VEX_W gEvexTable_root_02_26_02_w = @@ -5060,13 +5060,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_26_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2388] + (const void *)&gInstructions[2398] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2389] + (const void *)&gInstructions[2399] }; const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w = @@ -5081,13 +5081,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2392] + (const void *)&gInstructions[2402] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2393] + (const void *)&gInstructions[2403] }; const ND_TABLE_VEX_W gEvexTable_root_02_27_02_w = @@ -5113,13 +5113,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_27_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2418] + (const void *)&gInstructions[2428] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2419] + (const void *)&gInstructions[2429] }; const ND_TABLE_VEX_W gEvexTable_root_02_4c_01_w = @@ -5145,13 +5145,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2420] + (const void *)&gInstructions[2430] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2421] + (const void *)&gInstructions[2431] }; const ND_TABLE_VEX_W gEvexTable_root_02_4d_01_w = @@ -5177,13 +5177,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2422] + (const void *)&gInstructions[2432] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2423] + (const void *)&gInstructions[2433] }; const ND_TABLE_VEX_W gEvexTable_root_02_ca_01_02_w = @@ -5220,13 +5220,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ca_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2424] + (const void *)&gInstructions[2434] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2425] + (const void *)&gInstructions[2435] }; const ND_TABLE_VEX_W gEvexTable_root_02_cb_01_w = @@ -5252,13 +5252,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2440] + (const void *)&gInstructions[2450] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2441] + (const void *)&gInstructions[2451] }; const ND_TABLE_VEX_W gEvexTable_root_02_4e_01_w = @@ -5284,13 +5284,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2442] + (const void *)&gInstructions[2452] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2443] + (const void *)&gInstructions[2453] }; const ND_TABLE_VEX_W gEvexTable_root_02_4f_01_w = @@ -5316,13 +5316,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2444] + (const void *)&gInstructions[2454] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2445] + (const void *)&gInstructions[2455] }; const ND_TABLE_VEX_W gEvexTable_root_02_cc_01_02_w = @@ -5359,13 +5359,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2446] + (const void *)&gInstructions[2456] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2447] + (const void *)&gInstructions[2457] }; const ND_TABLE_VEX_W gEvexTable_root_02_cd_01_w = @@ -5391,13 +5391,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2450] + (const void *)&gInstructions[2460] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2451] + (const void *)&gInstructions[2461] }; const ND_TABLE_VEX_W gEvexTable_root_02_2c_01_w = @@ -5423,13 +5423,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2452] + (const void *)&gInstructions[2462] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2453] + (const void *)&gInstructions[2463] }; const ND_TABLE_VEX_W gEvexTable_root_02_2d_01_w = @@ -5455,13 +5455,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2454] + (const void *)&gInstructions[2464] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2455] + (const void *)&gInstructions[2465] }; const ND_TABLE_VEX_W gEvexTable_root_02_a2_01_mem_w = @@ -5496,13 +5496,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2464] + (const void *)&gInstructions[2474] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2465] + (const void *)&gInstructions[2475] }; const ND_TABLE_VEX_W gEvexTable_root_02_a3_01_mem_w = @@ -5800,7 +5800,7 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode = const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1352] + (const void *)&gInstructions[1358] }; const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w = @@ -5815,7 +5815,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1354] + (const void *)&gInstructions[1360] }; const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w = @@ -5830,7 +5830,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1356] + (const void *)&gInstructions[1362] }; const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w = @@ -5845,7 +5845,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1358] + (const void *)&gInstructions[1364] }; const ND_TABLE_VEX_W gEvexTable_root_01_58_02_w = @@ -5871,7 +5871,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_58_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1374] + (const void *)&gInstructions[1380] }; const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w = @@ -5886,7 +5886,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1376] + (const void *)&gInstructions[1382] }; const ND_TABLE_VEX_W gEvexTable_root_01_55_00_w = @@ -5912,7 +5912,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_55_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1378] + (const void *)&gInstructions[1384] }; const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w = @@ -5927,7 +5927,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1380] + (const void *)&gInstructions[1386] }; const ND_TABLE_VEX_W gEvexTable_root_01_54_00_w = @@ -5953,7 +5953,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_54_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1404] + (const void *)&gInstructions[1410] }; const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w = @@ -5968,7 +5968,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1406] + (const void *)&gInstructions[1412] }; const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w = @@ -5983,7 +5983,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1408] + (const void *)&gInstructions[1414] }; const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w = @@ -5998,7 +5998,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1410] + (const void *)&gInstructions[1416] }; const ND_TABLE_VEX_W gEvexTable_root_01_c2_02_w = @@ -6024,7 +6024,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1412] + (const void *)&gInstructions[1418] }; const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w = @@ -6039,7 +6039,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1414] + (const void *)&gInstructions[1420] }; const ND_TABLE_VEX_W gEvexTable_root_01_2f_00_w = @@ -6065,13 +6065,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1418] + (const void *)&gInstructions[1424] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1447] + (const void *)&gInstructions[1453] }; const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w = @@ -6086,7 +6086,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1425] + (const void *)&gInstructions[1431] }; const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w = @@ -6101,7 +6101,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1464] + (const void *)&gInstructions[1470] }; const ND_TABLE_VEX_W gEvexTable_root_01_e6_01_w = @@ -6127,13 +6127,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1421] + (const void *)&gInstructions[1427] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1448] + (const void *)&gInstructions[1454] }; const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w = @@ -6148,7 +6148,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1436] + (const void *)&gInstructions[1442] }; const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w = @@ -6163,7 +6163,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1469] + (const void *)&gInstructions[1475] }; const ND_TABLE_VEX_W gEvexTable_root_01_5b_02_w = @@ -6189,7 +6189,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1427] + (const void *)&gInstructions[1433] }; const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w = @@ -6204,7 +6204,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1438] + (const void *)&gInstructions[1444] }; const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w = @@ -6219,7 +6219,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1451] + (const void *)&gInstructions[1457] }; const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w = @@ -6234,7 +6234,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1459] + (const void *)&gInstructions[1465] }; const ND_TABLE_VEX_W gEvexTable_root_01_5a_02_w = @@ -6260,13 +6260,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1430] + (const void *)&gInstructions[1436] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1444] + (const void *)&gInstructions[1450] }; const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w = @@ -6281,13 +6281,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1484] + (const void *)&gInstructions[1490] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1485] + (const void *)&gInstructions[1491] }; const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_w = @@ -6302,7 +6302,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1486] + (const void *)&gInstructions[1492] }; const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp = @@ -6319,13 +6319,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1431] + (const void *)&gInstructions[1437] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1445] + (const void *)&gInstructions[1451] }; const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w = @@ -6340,13 +6340,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1432] + (const void *)&gInstructions[1438] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1446] + (const void *)&gInstructions[1452] }; const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w = @@ -6361,13 +6361,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1453] + (const void *)&gInstructions[1459] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1463] + (const void *)&gInstructions[1469] }; const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp = @@ -6384,13 +6384,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1449] + (const void *)&gInstructions[1455] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1461] + (const void *)&gInstructions[1467] }; const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp = @@ -6407,13 +6407,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1454] + (const void *)&gInstructions[1460] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1455] + (const void *)&gInstructions[1461] }; const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_w = @@ -6428,7 +6428,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1457] + (const void *)&gInstructions[1463] }; const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp = @@ -6445,13 +6445,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1466] + (const void *)&gInstructions[1472] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1471] + (const void *)&gInstructions[1477] }; const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w = @@ -6466,13 +6466,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1480] + (const void *)&gInstructions[1486] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1482] + (const void *)&gInstructions[1488] }; const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w = @@ -6487,13 +6487,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1481] + (const void *)&gInstructions[1487] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1483] + (const void *)&gInstructions[1489] }; const ND_TABLE_VEX_W gEvexTable_root_01_7a_03_w = @@ -6519,13 +6519,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1467] + (const void *)&gInstructions[1473] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1472] + (const void *)&gInstructions[1478] }; const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w = @@ -6540,13 +6540,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1468] + (const void *)&gInstructions[1474] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1473] + (const void *)&gInstructions[1479] }; const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w = @@ -6561,13 +6561,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1476] + (const void *)&gInstructions[1482] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1479] + (const void *)&gInstructions[1485] }; const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp = @@ -6584,13 +6584,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1474] + (const void *)&gInstructions[1480] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1477] + (const void *)&gInstructions[1483] }; const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp = @@ -6607,7 +6607,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1488] + (const void *)&gInstructions[1494] }; const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w = @@ -6622,7 +6622,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1490] + (const void *)&gInstructions[1496] }; const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w = @@ -6637,7 +6637,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1492] + (const void *)&gInstructions[1498] }; const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w = @@ -6652,7 +6652,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1494] + (const void *)&gInstructions[1500] }; const ND_TABLE_VEX_W gEvexTable_root_01_5e_02_w = @@ -6678,7 +6678,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1746] + (const void *)&gInstructions[1752] }; const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w = @@ -6693,7 +6693,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1748] + (const void *)&gInstructions[1754] }; const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w = @@ -6708,7 +6708,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1750] + (const void *)&gInstructions[1756] }; const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w = @@ -6723,7 +6723,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1752] + (const void *)&gInstructions[1758] }; const ND_TABLE_VEX_W gEvexTable_root_01_5f_02_w = @@ -6749,7 +6749,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1759] + (const void *)&gInstructions[1765] }; const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w = @@ -6764,7 +6764,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1761] + (const void *)&gInstructions[1767] }; const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w = @@ -6779,7 +6779,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1763] + (const void *)&gInstructions[1769] }; const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w = @@ -6794,7 +6794,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1765] + (const void *)&gInstructions[1771] }; const ND_TABLE_VEX_W gEvexTable_root_01_5d_02_w = @@ -6820,7 +6820,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1771] + (const void *)&gInstructions[1777] }; const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w = @@ -6835,7 +6835,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1775] + (const void *)&gInstructions[1781] }; const ND_TABLE_VEX_W gEvexTable_root_01_28_00_w = @@ -6861,7 +6861,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_28_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1772] + (const void *)&gInstructions[1778] }; const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w = @@ -6876,7 +6876,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1776] + (const void *)&gInstructions[1782] }; const ND_TABLE_VEX_W gEvexTable_root_01_29_00_w = @@ -6902,13 +6902,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_29_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1779] + (const void *)&gInstructions[1785] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1834] + (const void *)&gInstructions[1840] }; const ND_TABLE_VEX_W gEvexTable_root_01_6e_01_00_w = @@ -6945,13 +6945,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1780] + (const void *)&gInstructions[1786] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1835] + (const void *)&gInstructions[1841] }; const ND_TABLE_VEX_W gEvexTable_root_01_7e_01_00_w = @@ -6977,7 +6977,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_7e_01_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_02_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1836] + (const void *)&gInstructions[1842] }; const ND_TABLE_VEX_W gEvexTable_root_01_7e_02_00_w = @@ -7014,7 +7014,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1783] + (const void *)&gInstructions[1789] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w = @@ -7029,7 +7029,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1784] + (const void *)&gInstructions[1790] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w = @@ -7044,7 +7044,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1785] + (const void *)&gInstructions[1791] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_03_02_w = @@ -7070,7 +7070,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_03_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1804] + (const void *)&gInstructions[1810] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_00_reg_00_w = @@ -7096,7 +7096,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_00_reg_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1820] + (const void *)&gInstructions[1826] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_00_mem_00_w = @@ -7131,7 +7131,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_00_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1816] + (const void *)&gInstructions[1822] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_01_mem_00_w = @@ -7166,7 +7166,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1852] + (const void *)&gInstructions[1858] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_02_w = @@ -7192,13 +7192,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_12_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1790] + (const void *)&gInstructions[1796] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1792] + (const void *)&gInstructions[1798] }; const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w = @@ -7213,13 +7213,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1796] + (const void *)&gInstructions[1802] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1802] + (const void *)&gInstructions[1808] }; const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w = @@ -7234,13 +7234,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1798] + (const void *)&gInstructions[1804] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1800] + (const void *)&gInstructions[1806] }; const ND_TABLE_VEX_W gEvexTable_root_01_6f_02_w = @@ -7266,13 +7266,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1791] + (const void *)&gInstructions[1797] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1793] + (const void *)&gInstructions[1799] }; const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w = @@ -7287,13 +7287,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1797] + (const void *)&gInstructions[1803] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1803] + (const void *)&gInstructions[1809] }; const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w = @@ -7308,13 +7308,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1799] + (const void *)&gInstructions[1805] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1801] + (const void *)&gInstructions[1807] }; const ND_TABLE_VEX_W gEvexTable_root_01_7f_02_w = @@ -7340,7 +7340,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1806] + (const void *)&gInstructions[1812] }; const ND_TABLE_VEX_W gEvexTable_root_01_16_01_mem_00_w = @@ -7375,7 +7375,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1810] + (const void *)&gInstructions[1816] }; const ND_TABLE_VEX_W gEvexTable_root_01_16_00_mem_00_w = @@ -7401,7 +7401,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_16_00_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1814] + (const void *)&gInstructions[1820] }; const ND_TABLE_VEX_W gEvexTable_root_01_16_00_reg_00_w = @@ -7436,7 +7436,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_00_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1850] + (const void *)&gInstructions[1856] }; const ND_TABLE_VEX_W gEvexTable_root_01_16_02_w = @@ -7462,7 +7462,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_16_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1807] + (const void *)&gInstructions[1813] }; const ND_TABLE_VEX_W gEvexTable_root_01_17_01_mem_00_w = @@ -7497,7 +7497,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1811] + (const void *)&gInstructions[1817] }; const ND_TABLE_VEX_W gEvexTable_root_01_17_00_mem_00_w = @@ -7543,7 +7543,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_17_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1817] + (const void *)&gInstructions[1823] }; const ND_TABLE_VEX_W gEvexTable_root_01_13_01_mem_00_w = @@ -7578,7 +7578,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1821] + (const void *)&gInstructions[1827] }; const ND_TABLE_VEX_W gEvexTable_root_01_13_00_mem_00_w = @@ -7624,7 +7624,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_13_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e7_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1826] + (const void *)&gInstructions[1832] }; const ND_TABLE_VEX_W gEvexTable_root_01_e7_01_mem_w = @@ -7659,7 +7659,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1830] + (const void *)&gInstructions[1836] }; const ND_TABLE_VEX_W gEvexTable_root_01_2b_01_mem_w = @@ -7683,7 +7683,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1832] + (const void *)&gInstructions[1838] }; const ND_TABLE_VEX_W gEvexTable_root_01_2b_00_mem_w = @@ -7718,7 +7718,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d6_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1837] + (const void *)&gInstructions[1843] }; const ND_TABLE_VEX_W gEvexTable_root_01_d6_01_00_w = @@ -7755,7 +7755,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1842] + (const void *)&gInstructions[1848] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w = @@ -7770,7 +7770,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1843] + (const void *)&gInstructions[1849] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_03_reg_w = @@ -7794,7 +7794,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1854] + (const void *)&gInstructions[1860] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w = @@ -7809,7 +7809,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1855] + (const void *)&gInstructions[1861] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_02_reg_w = @@ -7833,7 +7833,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1862] + (const void *)&gInstructions[1868] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w = @@ -7848,7 +7848,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1866] + (const void *)&gInstructions[1872] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_00_w = @@ -7874,7 +7874,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_10_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1844] + (const void *)&gInstructions[1850] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w = @@ -7889,7 +7889,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1845] + (const void *)&gInstructions[1851] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_03_reg_w = @@ -7913,7 +7913,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1856] + (const void *)&gInstructions[1862] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w = @@ -7928,7 +7928,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1857] + (const void *)&gInstructions[1863] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_02_reg_w = @@ -7952,7 +7952,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1863] + (const void *)&gInstructions[1869] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w = @@ -7967,7 +7967,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1867] + (const void *)&gInstructions[1873] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_00_w = @@ -7993,7 +7993,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_11_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1877] + (const void *)&gInstructions[1883] }; const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w = @@ -8008,7 +8008,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1879] + (const void *)&gInstructions[1885] }; const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w = @@ -8023,7 +8023,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1881] + (const void *)&gInstructions[1887] }; const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w = @@ -8038,7 +8038,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1883] + (const void *)&gInstructions[1889] }; const ND_TABLE_VEX_W gEvexTable_root_01_59_02_w = @@ -8064,7 +8064,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_59_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1888] + (const void *)&gInstructions[1894] }; const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w = @@ -8079,7 +8079,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1890] + (const void *)&gInstructions[1896] }; const ND_TABLE_VEX_W gEvexTable_root_01_56_00_w = @@ -8105,7 +8105,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_56_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1903] + (const void *)&gInstructions[1909] }; const ND_TABLE_VEX_W gEvexTable_root_01_6b_01_w = @@ -8131,7 +8131,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_63_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1905] + (const void *)&gInstructions[1911] }; const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp = @@ -8148,7 +8148,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_67_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1909] + (const void *)&gInstructions[1915] }; const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp = @@ -8165,7 +8165,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1911] + (const void *)&gInstructions[1917] }; const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp = @@ -8182,7 +8182,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fe_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1913] + (const void *)&gInstructions[1919] }; const ND_TABLE_VEX_W gEvexTable_root_01_fe_01_w = @@ -8208,7 +8208,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fe_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1915] + (const void *)&gInstructions[1921] }; const ND_TABLE_VEX_W gEvexTable_root_01_d4_01_w = @@ -8234,7 +8234,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ec_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1917] + (const void *)&gInstructions[1923] }; const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp = @@ -8251,7 +8251,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ed_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1919] + (const void *)&gInstructions[1925] }; const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp = @@ -8268,7 +8268,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_dc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1921] + (const void *)&gInstructions[1927] }; const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp = @@ -8285,7 +8285,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_dd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1923] + (const void *)&gInstructions[1929] }; const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp = @@ -8302,7 +8302,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1925] + (const void *)&gInstructions[1931] }; const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp = @@ -8319,13 +8319,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1930] + (const void *)&gInstructions[1936] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1934] + (const void *)&gInstructions[1940] }; const ND_TABLE_VEX_W gEvexTable_root_01_db_01_w = @@ -8351,13 +8351,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_db_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1932] + (const void *)&gInstructions[1938] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1933] + (const void *)&gInstructions[1939] }; const ND_TABLE_VEX_W gEvexTable_root_01_df_01_w = @@ -8383,7 +8383,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_df_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1935] + (const void *)&gInstructions[1941] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp = @@ -8400,7 +8400,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1937] + (const void *)&gInstructions[1943] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp = @@ -8417,7 +8417,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_74_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1966] + (const void *)&gInstructions[1972] }; const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp = @@ -8434,7 +8434,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_76_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1968] + (const void *)&gInstructions[1974] }; const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp = @@ -8451,7 +8451,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_75_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1972] + (const void *)&gInstructions[1978] }; const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp = @@ -8468,7 +8468,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_64_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1976] + (const void *)&gInstructions[1982] }; const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp = @@ -8485,7 +8485,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_66_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1978] + (const void *)&gInstructions[1984] }; const ND_TABLE_VEX_W gEvexTable_root_01_66_01_w = @@ -8511,7 +8511,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_66_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_65_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1982] + (const void *)&gInstructions[1988] }; const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp = @@ -8528,7 +8528,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c5_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2062] + (const void *)&gInstructions[2072] }; const ND_TABLE_VEX_L gEvexTable_root_01_c5_01_reg_l = @@ -8565,7 +8565,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2106] + (const void *)&gInstructions[2116] }; const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l = @@ -8582,7 +8582,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2107] + (const void *)&gInstructions[2117] }; const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_reg_l = @@ -8619,7 +8619,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2128] + (const void *)&gInstructions[2138] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp = @@ -8636,7 +8636,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ee_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2139] + (const void *)&gInstructions[2149] }; const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp = @@ -8653,7 +8653,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_de_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2141] + (const void *)&gInstructions[2151] }; const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp = @@ -8670,7 +8670,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ea_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2153] + (const void *)&gInstructions[2163] }; const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp = @@ -8687,7 +8687,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_da_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2155] + (const void *)&gInstructions[2165] }; const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp = @@ -8704,7 +8704,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e4_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2229] + (const void *)&gInstructions[2239] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp = @@ -8721,7 +8721,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2231] + (const void *)&gInstructions[2241] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp = @@ -8738,7 +8738,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2236] + (const void *)&gInstructions[2246] }; const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp = @@ -8755,7 +8755,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2239] + (const void *)&gInstructions[2249] }; const ND_TABLE_VEX_W gEvexTable_root_01_f4_01_w = @@ -8781,13 +8781,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2246] + (const void *)&gInstructions[2256] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2247] + (const void *)&gInstructions[2257] }; const ND_TABLE_VEX_W gEvexTable_root_01_eb_01_w = @@ -8813,13 +8813,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_eb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2250] + (const void *)&gInstructions[2260] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2251] + (const void *)&gInstructions[2261] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w = @@ -8834,13 +8834,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2254] + (const void *)&gInstructions[2264] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2255] + (const void *)&gInstructions[2265] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w = @@ -8855,7 +8855,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_06_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2316] + (const void *)&gInstructions[2326] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w = @@ -8870,13 +8870,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2335] + (const void *)&gInstructions[2345] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2339] + (const void *)&gInstructions[2349] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w = @@ -8891,7 +8891,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2349] + (const void *)&gInstructions[2359] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_02_w = @@ -8932,7 +8932,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_72_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2270] + (const void *)&gInstructions[2280] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp = @@ -8949,7 +8949,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2307] + (const void *)&gInstructions[2317] }; const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w = @@ -8964,13 +8964,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2309] + (const void *)&gInstructions[2319] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2311] + (const void *)&gInstructions[2321] }; const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp = @@ -8987,7 +8987,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f2_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2317] + (const void *)&gInstructions[2327] }; const ND_TABLE_VEX_W gEvexTable_root_01_f2_01_w = @@ -9013,13 +9013,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2320] + (const void *)&gInstructions[2330] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_06_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2322] + (const void *)&gInstructions[2332] }; const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w = @@ -9034,13 +9034,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2353] + (const void *)&gInstructions[2363] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2355] + (const void *)&gInstructions[2365] }; const ND_TABLE_VEX_W gEvexTable_root_01_73_01_02_w = @@ -9081,7 +9081,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_73_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f3_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2323] + (const void *)&gInstructions[2333] }; const ND_TABLE_VEX_W gEvexTable_root_01_f3_01_w = @@ -9107,19 +9107,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f3_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2331] + (const void *)&gInstructions[2341] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2345] + (const void *)&gInstructions[2355] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2364] + (const void *)&gInstructions[2374] }; const ND_TABLE_MODRM_REG gEvexTable_root_01_71_01_modrmreg = @@ -9151,7 +9151,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_71_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2332] + (const void *)&gInstructions[2342] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp = @@ -9168,13 +9168,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2336] + (const void *)&gInstructions[2346] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2340] + (const void *)&gInstructions[2350] }; const ND_TABLE_VEX_W gEvexTable_root_01_e2_01_w = @@ -9200,7 +9200,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2346] + (const void *)&gInstructions[2356] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp = @@ -9217,7 +9217,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d2_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2350] + (const void *)&gInstructions[2360] }; const ND_TABLE_VEX_W gEvexTable_root_01_d2_01_w = @@ -9243,7 +9243,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d3_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2356] + (const void *)&gInstructions[2366] }; const ND_TABLE_VEX_W gEvexTable_root_01_d3_01_w = @@ -9269,7 +9269,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d3_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2365] + (const void *)&gInstructions[2375] }; const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp = @@ -9286,7 +9286,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2368] + (const void *)&gInstructions[2378] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp = @@ -9303,7 +9303,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fa_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2370] + (const void *)&gInstructions[2380] }; const ND_TABLE_VEX_W gEvexTable_root_01_fa_01_w = @@ -9329,7 +9329,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fa_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2372] + (const void *)&gInstructions[2382] }; const ND_TABLE_VEX_W gEvexTable_root_01_fb_01_w = @@ -9355,7 +9355,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2374] + (const void *)&gInstructions[2384] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp = @@ -9372,7 +9372,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2376] + (const void *)&gInstructions[2386] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp = @@ -9389,7 +9389,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2378] + (const void *)&gInstructions[2388] }; const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp = @@ -9406,7 +9406,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2380] + (const void *)&gInstructions[2390] }; const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp = @@ -9423,7 +9423,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2382] + (const void *)&gInstructions[2392] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp = @@ -9440,7 +9440,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_68_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2395] + (const void *)&gInstructions[2405] }; const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp = @@ -9457,7 +9457,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2397] + (const void *)&gInstructions[2407] }; const ND_TABLE_VEX_W gEvexTable_root_01_6a_01_w = @@ -9483,7 +9483,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2399] + (const void *)&gInstructions[2409] }; const ND_TABLE_VEX_W gEvexTable_root_01_6d_01_w = @@ -9509,7 +9509,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_69_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2401] + (const void *)&gInstructions[2411] }; const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp = @@ -9526,7 +9526,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_60_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2403] + (const void *)&gInstructions[2413] }; const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp = @@ -9543,7 +9543,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_62_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2405] + (const void *)&gInstructions[2415] }; const ND_TABLE_VEX_W gEvexTable_root_01_62_01_w = @@ -9569,7 +9569,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_62_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2407] + (const void *)&gInstructions[2417] }; const ND_TABLE_VEX_W gEvexTable_root_01_6c_01_w = @@ -9595,7 +9595,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_61_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2409] + (const void *)&gInstructions[2419] }; const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp = @@ -9612,13 +9612,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2412] + (const void *)&gInstructions[2422] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2413] + (const void *)&gInstructions[2423] }; const ND_TABLE_VEX_W gEvexTable_root_01_ef_01_w = @@ -9644,7 +9644,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ef_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2470] + (const void *)&gInstructions[2480] }; const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w = @@ -9659,7 +9659,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2472] + (const void *)&gInstructions[2482] }; const ND_TABLE_VEX_W gEvexTable_root_01_c6_00_w = @@ -9685,7 +9685,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2474] + (const void *)&gInstructions[2484] }; const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w = @@ -9700,7 +9700,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2476] + (const void *)&gInstructions[2486] }; const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w = @@ -9715,7 +9715,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2478] + (const void *)&gInstructions[2488] }; const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w = @@ -9730,7 +9730,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2480] + (const void *)&gInstructions[2490] }; const ND_TABLE_VEX_W gEvexTable_root_01_51_02_w = @@ -9756,7 +9756,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_51_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2483] + (const void *)&gInstructions[2493] }; const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w = @@ -9771,7 +9771,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2485] + (const void *)&gInstructions[2495] }; const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w = @@ -9786,7 +9786,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2487] + (const void *)&gInstructions[2497] }; const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w = @@ -9801,7 +9801,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2489] + (const void *)&gInstructions[2499] }; const ND_TABLE_VEX_W gEvexTable_root_01_5c_02_w = @@ -9827,7 +9827,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2493] + (const void *)&gInstructions[2503] }; const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w = @@ -9842,7 +9842,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2495] + (const void *)&gInstructions[2505] }; const ND_TABLE_VEX_W gEvexTable_root_01_2e_00_w = @@ -9868,7 +9868,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2497] + (const void *)&gInstructions[2507] }; const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w = @@ -9883,7 +9883,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2499] + (const void *)&gInstructions[2509] }; const ND_TABLE_VEX_W gEvexTable_root_01_15_00_w = @@ -9909,7 +9909,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_15_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2501] + (const void *)&gInstructions[2511] }; const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w = @@ -9924,7 +9924,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2503] + (const void *)&gInstructions[2513] }; const ND_TABLE_VEX_W gEvexTable_root_01_14_00_w = @@ -9950,7 +9950,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_14_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2505] + (const void *)&gInstructions[2515] }; const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w = @@ -9965,7 +9965,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2507] + (const void *)&gInstructions[2517] }; const ND_TABLE_VEX_W gEvexTable_root_01_57_00_w = @@ -10254,13 +10254,13 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode = const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1372] + (const void *)&gInstructions[1378] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1373] + (const void *)&gInstructions[1379] }; const ND_TABLE_VEX_W gEvexTable_root_03_03_01_w = @@ -10286,7 +10286,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_03_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1441] + (const void *)&gInstructions[1447] }; const ND_TABLE_VEX_W gEvexTable_root_03_1d_01_w = @@ -10312,7 +10312,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_42_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1487] + (const void *)&gInstructions[1493] }; const ND_TABLE_VEX_W gEvexTable_root_03_42_01_w = @@ -10338,13 +10338,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_42_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1506] + (const void *)&gInstructions[1512] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1508] + (const void *)&gInstructions[1514] }; const ND_TABLE_VEX_W gEvexTable_root_03_19_01_w = @@ -10370,13 +10370,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_19_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1507] + (const void *)&gInstructions[1513] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1509] + (const void *)&gInstructions[1515] }; const ND_TABLE_VEX_W gEvexTable_root_03_1b_01_02_w = @@ -10413,13 +10413,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1511] + (const void *)&gInstructions[1517] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1513] + (const void *)&gInstructions[1519] }; const ND_TABLE_VEX_W gEvexTable_root_03_39_01_w = @@ -10445,13 +10445,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_39_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1512] + (const void *)&gInstructions[1518] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1514] + (const void *)&gInstructions[1520] }; const ND_TABLE_VEX_W gEvexTable_root_03_3b_01_02_w = @@ -10488,7 +10488,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1515] + (const void *)&gInstructions[1521] }; const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l = @@ -10505,7 +10505,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1516] + (const void *)&gInstructions[1522] }; const ND_TABLE_VEX_L gEvexTable_root_03_17_01_reg_l = @@ -10542,13 +10542,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_17_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1519] + (const void *)&gInstructions[1525] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1520] + (const void *)&gInstructions[1526] }; const ND_TABLE_VEX_W gEvexTable_root_03_54_01_w = @@ -10574,13 +10574,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_54_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1521] + (const void *)&gInstructions[1527] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1522] + (const void *)&gInstructions[1528] }; const ND_TABLE_VEX_W gEvexTable_root_03_55_01_w = @@ -10606,13 +10606,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_55_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1683] + (const void *)&gInstructions[1689] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1684] + (const void *)&gInstructions[1690] }; const ND_TABLE_VEX_W gEvexTable_root_03_66_01_w = @@ -10638,13 +10638,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_66_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1685] + (const void *)&gInstructions[1691] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1686] + (const void *)&gInstructions[1692] }; const ND_TABLE_VEX_W gEvexTable_root_03_67_01_w = @@ -10670,13 +10670,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_67_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1711] + (const void *)&gInstructions[1717] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1712] + (const void *)&gInstructions[1718] }; const ND_TABLE_VEX_W gEvexTable_root_03_26_01_w = @@ -10702,13 +10702,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_26_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1713] + (const void *)&gInstructions[1719] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1714] + (const void *)&gInstructions[1720] }; const ND_TABLE_VEX_W gEvexTable_root_03_27_01_w = @@ -10734,7 +10734,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_27_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_cf_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1715] + (const void *)&gInstructions[1721] }; const ND_TABLE_VEX_W gEvexTable_root_03_cf_01_w = @@ -10760,7 +10760,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_cf_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_ce_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1717] + (const void *)&gInstructions[1723] }; const ND_TABLE_VEX_W gEvexTable_root_03_ce_01_w = @@ -10786,13 +10786,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_ce_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1726] + (const void *)&gInstructions[1732] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1728] + (const void *)&gInstructions[1734] }; const ND_TABLE_VEX_W gEvexTable_root_03_18_01_w = @@ -10818,13 +10818,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_18_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1727] + (const void *)&gInstructions[1733] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1729] + (const void *)&gInstructions[1735] }; const ND_TABLE_VEX_W gEvexTable_root_03_1a_01_02_w = @@ -10861,13 +10861,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1731] + (const void *)&gInstructions[1737] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1733] + (const void *)&gInstructions[1739] }; const ND_TABLE_VEX_W gEvexTable_root_03_38_01_w = @@ -10893,13 +10893,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_38_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1732] + (const void *)&gInstructions[1738] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1734] + (const void *)&gInstructions[1740] }; const ND_TABLE_VEX_W gEvexTable_root_03_3a_01_02_w = @@ -10936,7 +10936,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1735] + (const void *)&gInstructions[1741] }; const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l = @@ -10953,7 +10953,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1736] + (const void *)&gInstructions[1742] }; const ND_TABLE_VEX_L gEvexTable_root_03_21_01_reg_l = @@ -10990,7 +10990,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_21_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_0f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1927] + (const void *)&gInstructions[1933] }; const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp = @@ -11007,7 +11007,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_44_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1960] + (const void *)&gInstructions[1966] }; const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp = @@ -11024,13 +11024,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1964] + (const void *)&gInstructions[1970] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1991] + (const void *)&gInstructions[1997] }; const ND_TABLE_VEX_W gEvexTable_root_03_3f_01_w = @@ -11056,13 +11056,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1965] + (const void *)&gInstructions[1971] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1986] + (const void *)&gInstructions[1992] }; const ND_TABLE_VEX_W gEvexTable_root_03_1f_01_w = @@ -11088,13 +11088,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1987] + (const void *)&gInstructions[1993] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1990] + (const void *)&gInstructions[1996] }; const ND_TABLE_VEX_W gEvexTable_root_03_3e_01_w = @@ -11120,13 +11120,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1988] + (const void *)&gInstructions[1994] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1989] + (const void *)&gInstructions[1995] }; const ND_TABLE_VEX_W gEvexTable_root_03_1e_01_w = @@ -11152,7 +11152,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_05_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2026] + (const void *)&gInstructions[2036] }; const ND_TABLE_VEX_W gEvexTable_root_03_05_01_w = @@ -11178,7 +11178,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_05_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_04_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2030] + (const void *)&gInstructions[2040] }; const ND_TABLE_VEX_W gEvexTable_root_03_04_01_w = @@ -11204,7 +11204,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_04_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2035] + (const void *)&gInstructions[2045] }; const ND_TABLE_VEX_W gEvexTable_root_03_01_01_w = @@ -11230,7 +11230,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_01_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_00_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2041] + (const void *)&gInstructions[2051] }; const ND_TABLE_VEX_W gEvexTable_root_03_00_01_w = @@ -11256,7 +11256,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_00_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2054] + (const void *)&gInstructions[2064] }; const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l = @@ -11273,7 +11273,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2055] + (const void *)&gInstructions[2065] }; const ND_TABLE_VEX_L gEvexTable_root_03_14_01_reg_l = @@ -11310,13 +11310,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_14_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2058] + (const void *)&gInstructions[2068] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2060] + (const void *)&gInstructions[2070] }; const ND_TABLE_VEX_W gEvexTable_root_03_16_01_00_w = @@ -11353,7 +11353,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_16_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2063] + (const void *)&gInstructions[2073] }; const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l = @@ -11370,7 +11370,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2064] + (const void *)&gInstructions[2074] }; const ND_TABLE_VEX_L gEvexTable_root_03_15_01_reg_l = @@ -11407,7 +11407,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_15_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2098] + (const void *)&gInstructions[2108] }; const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l = @@ -11424,7 +11424,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2099] + (const void *)&gInstructions[2109] }; const ND_TABLE_VEX_L gEvexTable_root_03_20_01_reg_l = @@ -11461,13 +11461,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_20_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2102] + (const void *)&gInstructions[2112] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2104] + (const void *)&gInstructions[2114] }; const ND_TABLE_VEX_W gEvexTable_root_03_22_01_00_w = @@ -11504,13 +11504,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_22_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2289] + (const void *)&gInstructions[2299] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2290] + (const void *)&gInstructions[2300] }; const ND_TABLE_VEX_W gEvexTable_root_03_71_01_w = @@ -11536,7 +11536,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_71_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_70_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2294] + (const void *)&gInstructions[2304] }; const ND_TABLE_VEX_W gEvexTable_root_03_70_01_w = @@ -11562,13 +11562,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_70_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2298] + (const void *)&gInstructions[2308] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2299] + (const void *)&gInstructions[2309] }; const ND_TABLE_VEX_W gEvexTable_root_03_73_01_w = @@ -11594,7 +11594,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_73_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_72_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2303] + (const void *)&gInstructions[2313] }; const ND_TABLE_VEX_W gEvexTable_root_03_72_01_w = @@ -11620,13 +11620,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_72_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2384] + (const void *)&gInstructions[2394] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2385] + (const void *)&gInstructions[2395] }; const ND_TABLE_VEX_W gEvexTable_root_03_25_01_w = @@ -11652,13 +11652,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_25_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2414] + (const void *)&gInstructions[2424] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2415] + (const void *)&gInstructions[2425] }; const ND_TABLE_VEX_W gEvexTable_root_03_50_01_w = @@ -11684,13 +11684,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_50_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2416] + (const void *)&gInstructions[2426] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2417] + (const void *)&gInstructions[2427] }; const ND_TABLE_VEX_W gEvexTable_root_03_51_01_w = @@ -11716,13 +11716,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_51_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2428] + (const void *)&gInstructions[2438] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2429] + (const void *)&gInstructions[2439] }; const ND_TABLE_VEX_W gEvexTable_root_03_56_01_w = @@ -11748,13 +11748,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_56_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2430] + (const void *)&gInstructions[2440] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2431] + (const void *)&gInstructions[2441] }; const ND_TABLE_VEX_W gEvexTable_root_03_57_01_w = @@ -11780,7 +11780,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_57_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_09_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2432] + (const void *)&gInstructions[2442] }; const ND_TABLE_VEX_W gEvexTable_root_03_09_01_w = @@ -11806,7 +11806,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_09_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2433] + (const void *)&gInstructions[2443] }; const ND_TABLE_VEX_W gEvexTable_root_03_08_01_w = @@ -11832,7 +11832,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_08_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_0b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2434] + (const void *)&gInstructions[2444] }; const ND_TABLE_VEX_W gEvexTable_root_03_0b_01_w = @@ -11858,7 +11858,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2435] + (const void *)&gInstructions[2445] }; const ND_TABLE_VEX_W gEvexTable_root_03_0a_01_w = @@ -11884,13 +11884,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2466] + (const void *)&gInstructions[2476] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2467] + (const void *)&gInstructions[2477] }; const ND_TABLE_VEX_W gEvexTable_root_03_23_01_w = @@ -11916,13 +11916,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_23_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2468] + (const void *)&gInstructions[2478] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2469] + (const void *)&gInstructions[2479] }; const ND_TABLE_VEX_W gEvexTable_root_03_43_01_w = diff --git a/bddisasm/include/table_root.h b/bddisasm/include/table_root.h index bbbac93..12c107f 100644 --- a/bddisasm/include/table_root.h +++ b/bddisasm/include/table_root.h @@ -82,31 +82,31 @@ const ND_TABLE_INSTRUCTION gRootTable_root_80_04_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_80_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[152] + (const void *)&gInstructions[153] }; const ND_TABLE_INSTRUCTION gRootTable_root_80_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[795] + (const void *)&gInstructions[797] }; const ND_TABLE_INSTRUCTION gRootTable_root_80_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1199] + (const void *)&gInstructions[1201] }; const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1297] + (const void *)&gInstructions[1301] }; const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2551] + (const void *)&gInstructions[2561] }; const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg = @@ -145,31 +145,31 @@ const ND_TABLE_INSTRUCTION gRootTable_root_81_04_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_81_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[153] + (const void *)&gInstructions[154] }; const ND_TABLE_INSTRUCTION gRootTable_root_81_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[796] + (const void *)&gInstructions[798] }; const ND_TABLE_INSTRUCTION gRootTable_root_81_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1200] + (const void *)&gInstructions[1202] }; const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1298] + (const void *)&gInstructions[1302] }; const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2552] + (const void *)&gInstructions[2562] }; const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg = @@ -208,31 +208,31 @@ const ND_TABLE_INSTRUCTION gRootTable_root_82_04_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_82_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[154] + (const void *)&gInstructions[155] }; const ND_TABLE_INSTRUCTION gRootTable_root_82_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[797] + (const void *)&gInstructions[799] }; const ND_TABLE_INSTRUCTION gRootTable_root_82_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1201] + (const void *)&gInstructions[1203] }; const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1299] + (const void *)&gInstructions[1303] }; const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2553] + (const void *)&gInstructions[2563] }; const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg = @@ -271,31 +271,31 @@ const ND_TABLE_INSTRUCTION gRootTable_root_83_04_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_83_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[155] + (const void *)&gInstructions[156] }; const ND_TABLE_INSTRUCTION gRootTable_root_83_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[798] + (const void *)&gInstructions[800] }; const ND_TABLE_INSTRUCTION gRootTable_root_83_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1202] + (const void *)&gInstructions[1204] }; const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1300] + (const void *)&gInstructions[1304] }; const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2554] + (const void *)&gInstructions[2564] }; const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg = @@ -328,13 +328,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_F3_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2519] + (const void *)&gInstructions[2529] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2520] + (const void *)&gInstructions[2530] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary = @@ -664,7 +664,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_reg_66_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[579] + (const void *)&gInstructions[581] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_reg_mprefix = @@ -741,13 +741,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_14_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_F2_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[178] + (const void *)&gInstructions[179] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_F2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[179] + (const void *)&gInstructions[180] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_F2_mprefix = @@ -764,13 +764,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_F2_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[653] + (const void *)&gInstructions[655] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[654] + (const void *)&gInstructions[656] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_mprefix = @@ -787,13 +787,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_reg_F2_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[178] + (const void *)&gInstructions[179] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_reg_F2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[179] + (const void *)&gInstructions[180] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_reg_F2_mprefix = @@ -830,13 +830,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f0_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_F2_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[180] + (const void *)&gInstructions[181] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_F2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[181] + (const void *)&gInstructions[182] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_F2_mprefix = @@ -853,13 +853,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_F2_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[655] + (const void *)&gInstructions[657] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[656] + (const void *)&gInstructions[658] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_mprefix = @@ -876,13 +876,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_reg_F2_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[180] + (const void *)&gInstructions[181] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_reg_F2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[181] + (const void *)&gInstructions[182] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_reg_F2_mprefix = @@ -919,7 +919,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f1_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fa_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[232] + (const void *)&gInstructions[233] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_fa_reg_mprefix = @@ -945,7 +945,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_fa_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fb_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[233] + (const void *)&gInstructions[234] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_fb_reg_mprefix = @@ -971,19 +971,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_fb_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[236] + (const void *)&gInstructions[237] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[237] + (const void *)&gInstructions[238] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[662] + (const void *)&gInstructions[664] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f8_mem_mprefix = @@ -1009,7 +1009,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f8_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cf_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[397] + (const void *)&gInstructions[398] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix = @@ -1026,7 +1026,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_80_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[441] + (const void *)&gInstructions[443] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_80_mem_mprefix = @@ -1052,7 +1052,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_80_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_82_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[445] + (const void *)&gInstructions[447] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_82_mem_mprefix = @@ -1078,7 +1078,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_82_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_81_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[446] + (const void *)&gInstructions[448] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_81_mem_mprefix = @@ -1104,7 +1104,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_81_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f9_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[663] + (const void *)&gInstructions[665] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_f9_mem_mprefix = @@ -1130,7 +1130,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f9_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_2a_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[681] + (const void *)&gInstructions[683] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_2a_mem_mprefix = @@ -1156,13 +1156,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_2a_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1c_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[811] + (const void *)&gInstructions[813] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1c_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[812] + (const void *)&gInstructions[814] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_1c_mprefix = @@ -1179,13 +1179,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1e_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[813] + (const void *)&gInstructions[815] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1e_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[814] + (const void *)&gInstructions[816] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_1e_mprefix = @@ -1202,13 +1202,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1d_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[815] + (const void *)&gInstructions[817] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1d_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[816] + (const void *)&gInstructions[818] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_1d_mprefix = @@ -1225,7 +1225,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1d_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_2b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[821] + (const void *)&gInstructions[823] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_2b_mprefix = @@ -1242,7 +1242,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_2b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_10_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[852] + (const void *)&gInstructions[854] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_10_mprefix = @@ -1259,7 +1259,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_10_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_29_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[859] + (const void *)&gInstructions[861] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix = @@ -1276,7 +1276,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_37_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[868] + (const void *)&gInstructions[870] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix = @@ -1293,13 +1293,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[906] + (const void *)&gInstructions[908] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[907] + (const void *)&gInstructions[909] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix = @@ -1316,13 +1316,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[908] + (const void *)&gInstructions[910] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[909] + (const void *)&gInstructions[911] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix = @@ -1339,13 +1339,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[910] + (const void *)&gInstructions[912] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[911] + (const void *)&gInstructions[913] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix = @@ -1362,7 +1362,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_41_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[912] + (const void *)&gInstructions[914] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix = @@ -1379,13 +1379,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[913] + (const void *)&gInstructions[915] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[914] + (const void *)&gInstructions[916] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix = @@ -1402,13 +1402,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[915] + (const void *)&gInstructions[917] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[916] + (const void *)&gInstructions[918] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix = @@ -1425,13 +1425,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[917] + (const void *)&gInstructions[919] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[918] + (const void *)&gInstructions[920] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix = @@ -1448,13 +1448,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[929] + (const void *)&gInstructions[931] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[930] + (const void *)&gInstructions[932] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix = @@ -1471,7 +1471,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3c_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[933] + (const void *)&gInstructions[935] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix = @@ -1488,7 +1488,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3d_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[934] + (const void *)&gInstructions[936] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix = @@ -1505,7 +1505,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3f_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[939] + (const void *)&gInstructions[941] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix = @@ -1522,7 +1522,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3e_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[940] + (const void *)&gInstructions[942] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix = @@ -1539,7 +1539,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_38_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[941] + (const void *)&gInstructions[943] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix = @@ -1556,7 +1556,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_39_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[942] + (const void *)&gInstructions[944] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix = @@ -1573,7 +1573,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[947] + (const void *)&gInstructions[949] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix = @@ -1590,7 +1590,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[948] + (const void *)&gInstructions[950] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix = @@ -1607,7 +1607,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_21_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[951] + (const void *)&gInstructions[953] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix = @@ -1624,7 +1624,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_22_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[952] + (const void *)&gInstructions[954] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix = @@ -1641,7 +1641,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_20_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[953] + (const void *)&gInstructions[955] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix = @@ -1658,7 +1658,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_25_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[954] + (const void *)&gInstructions[956] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix = @@ -1675,7 +1675,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_23_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[955] + (const void *)&gInstructions[957] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix = @@ -1692,7 +1692,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_24_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[956] + (const void *)&gInstructions[958] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix = @@ -1709,7 +1709,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_31_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[957] + (const void *)&gInstructions[959] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix = @@ -1726,7 +1726,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_32_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[958] + (const void *)&gInstructions[960] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix = @@ -1743,7 +1743,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_30_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[959] + (const void *)&gInstructions[961] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix = @@ -1760,7 +1760,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_35_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[960] + (const void *)&gInstructions[962] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix = @@ -1777,7 +1777,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_33_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[961] + (const void *)&gInstructions[963] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix = @@ -1794,7 +1794,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_34_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[962] + (const void *)&gInstructions[964] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix = @@ -1811,7 +1811,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_28_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[963] + (const void *)&gInstructions[965] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix = @@ -1828,13 +1828,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[964] + (const void *)&gInstructions[966] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[965] + (const void *)&gInstructions[967] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix = @@ -1851,7 +1851,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_40_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[971] + (const void *)&gInstructions[973] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix = @@ -1868,13 +1868,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1012] + (const void *)&gInstructions[1014] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1013] + (const void *)&gInstructions[1015] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix = @@ -1891,13 +1891,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1018] + (const void *)&gInstructions[1020] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1019] + (const void *)&gInstructions[1021] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix = @@ -1914,13 +1914,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1020] + (const void *)&gInstructions[1022] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1021] + (const void *)&gInstructions[1023] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix = @@ -1937,13 +1937,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1022] + (const void *)&gInstructions[1024] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1023] + (const void *)&gInstructions[1025] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix = @@ -1960,7 +1960,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_17_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1076] + (const void *)&gInstructions[1078] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix = @@ -1977,7 +1977,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c9_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1234] + (const void *)&gInstructions[1237] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix = @@ -1994,7 +1994,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_ca_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1235] + (const void *)&gInstructions[1238] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix = @@ -2011,7 +2011,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c8_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1236] + (const void *)&gInstructions[1239] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix = @@ -2028,7 +2028,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cc_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1238] + (const void *)&gInstructions[1241] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix = @@ -2045,7 +2045,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cd_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1239] + (const void *)&gInstructions[1242] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix = @@ -2062,7 +2062,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cb_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1240] + (const void *)&gInstructions[1243] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix = @@ -2079,13 +2079,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2521] + (const void *)&gInstructions[2531] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2522] + (const void *)&gInstructions[2532] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary = @@ -2496,7 +2496,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_41_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[226] + (const void *)&gInstructions[227] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_41_mprefix = @@ -2513,7 +2513,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_41_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_40_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[227] + (const void *)&gInstructions[228] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_40_mprefix = @@ -2530,7 +2530,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_40_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_17_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[239] + (const void *)&gInstructions[240] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_17_mprefix = @@ -2547,7 +2547,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_17_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cf_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[395] + (const void *)&gInstructions[396] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix = @@ -2564,7 +2564,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_ce_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[396] + (const void *)&gInstructions[397] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix = @@ -2578,43 +2578,99 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix = } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_mem_66_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_f0_reg_00_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[430] + (const void *)&gInstructions[402] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_f0_reg_00_00_mprefix = { ND_ILUT_MAN_PREFIX, { /* 00 */ NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_21_mem_66_leaf, - /* 02 */ NULL, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_3a_f0_reg_00_00_F3_leaf, /* 03 */ NULL, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[431] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_reg_mprefix = +const ND_TABLE_MODRM_RM gRootTable_root_0f_3a_f0_reg_00_modrmrm = { - ND_ILUT_MAN_PREFIX, + ND_ILUT_MODRM_RM, { - /* 00 */ NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_21_reg_66_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_3a_f0_reg_00_00_mprefix, + /* 01 */ NULL, /* 02 */ NULL, /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, } }; -const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_21_modrmmod = +const ND_TABLE_MODRM_REG gRootTable_root_0f_3a_f0_reg_modrmreg = { - ND_ILUT_MODRM_MOD, + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gRootTable_root_0f_3a_f0_reg_00_modrmrm, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ NULL, + /* 05 */ NULL, + /* 06 */ NULL, + /* 07 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_f0_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_f0_reg_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_mem_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[432] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_21_mem_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_reg_66_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[433] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_reg_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gRootTable_root_0f_3a_21_reg_66_leaf, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_21_modrmmod = +{ + ND_ILUT_MODRM_MOD, { /* 00 */ (const void *)&gRootTable_root_0f_3a_21_mem_mprefix, /* 01 */ (const void *)&gRootTable_root_0f_3a_21_reg_mprefix, @@ -2624,7 +2680,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_21_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_42_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[720] + (const void *)&gInstructions[722] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_42_mprefix = @@ -2641,13 +2697,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_42_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0f_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[840] + (const void *)&gInstructions[842] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0f_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[841] + (const void *)&gInstructions[843] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0f_mprefix = @@ -2664,7 +2720,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0f_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0e_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[853] + (const void *)&gInstructions[855] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0e_mprefix = @@ -2681,7 +2737,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_44_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[854] + (const void *)&gInstructions[856] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix = @@ -2698,7 +2754,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_61_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[862] + (const void *)&gInstructions[864] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix = @@ -2715,7 +2771,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_60_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[863] + (const void *)&gInstructions[865] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix = @@ -2732,7 +2788,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_63_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[871] + (const void *)&gInstructions[873] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix = @@ -2749,7 +2805,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_62_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[872] + (const void *)&gInstructions[874] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix = @@ -2766,7 +2822,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[877] + (const void *)&gInstructions[879] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix = @@ -2783,7 +2839,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[878] + (const void *)&gInstructions[880] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_reg_mprefix = @@ -2809,13 +2865,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_14_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_66_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[879] + (const void *)&gInstructions[881] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_66_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[880] + (const void *)&gInstructions[882] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_16_66_auxiliary = @@ -2845,7 +2901,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_16_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[883] + (const void *)&gInstructions[885] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix = @@ -2862,7 +2918,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[884] + (const void *)&gInstructions[886] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_reg_mprefix = @@ -2888,7 +2944,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_15_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[921] + (const void *)&gInstructions[923] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix = @@ -2905,7 +2961,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[922] + (const void *)&gInstructions[924] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_reg_mprefix = @@ -2931,13 +2987,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_20_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[923] + (const void *)&gInstructions[925] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[924] + (const void *)&gInstructions[926] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_22_66_auxiliary = @@ -2967,7 +3023,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_22_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_09_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1166] + (const void *)&gInstructions[1168] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix = @@ -2984,7 +3040,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_08_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1167] + (const void *)&gInstructions[1169] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix = @@ -3001,7 +3057,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1168] + (const void *)&gInstructions[1170] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix = @@ -3018,7 +3074,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1169] + (const void *)&gInstructions[1171] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix = @@ -3035,7 +3091,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cc_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1237] + (const void *)&gInstructions[1240] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cc_mprefix = @@ -3293,7 +3349,7 @@ const ND_TABLE_OPCODE gRootTable_root_0f_3a_opcode = /* ed */ NULL, /* ee */ NULL, /* ef */ NULL, - /* f0 */ NULL, + /* f0 */ (const void *)&gRootTable_root_0f_3a_f0_modrmmod, /* f1 */ NULL, /* f2 */ NULL, /* f3 */ NULL, @@ -3420,7 +3476,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_66_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[755] + (const void *)&gInstructions[757] }; const ND_TABLE_MPREFIX gRootTable_root_0f_1a_mpx_reg_mprefix = @@ -3446,7 +3502,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1a_mpx_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[749] + (const void *)&gInstructions[751] }; const ND_TABLE_FEATURE gRootTable_root_0f_1a_feature = @@ -3510,13 +3566,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_66_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[756] + (const void *)&gInstructions[758] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[757] + (const void *)&gInstructions[759] }; const ND_TABLE_MPREFIX gRootTable_root_0f_1b_mpx_reg_mprefix = @@ -3542,7 +3598,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1b_mpx_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[750] + (const void *)&gInstructions[752] }; const ND_TABLE_FEATURE gRootTable_root_0f_1b_feature = @@ -3565,7 +3621,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_None_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1335] + (const void *)&gInstructions[1340] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary = @@ -3590,7 +3646,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_bd_None_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_bd_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[597] + (const void *)&gInstructions[599] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_bd_auxiliary = @@ -3743,13 +3799,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[229] + (const void *)&gInstructions[230] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1211] + (const void *)&gInstructions[1213] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix = @@ -3766,7 +3822,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[610] + (const void *)&gInstructions[612] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_00_mprefix = @@ -3783,7 +3839,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_01_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[728] + (const void *)&gInstructions[730] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix = @@ -3800,7 +3856,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1212] + (const void *)&gInstructions[1214] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix = @@ -3817,7 +3873,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_05_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1213] + (const void *)&gInstructions[1215] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix = @@ -3834,7 +3890,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_03_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1274] + (const void *)&gInstructions[1277] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix = @@ -3851,7 +3907,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_04_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1314] + (const void *)&gInstructions[1318] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_04_mprefix = @@ -3889,43 +3945,43 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_05_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[443] + (const void *)&gInstructions[445] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1262] + (const void *)&gInstructions[1265] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1277] + (const void *)&gInstructions[1280] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1757] + (const void *)&gInstructions[1763] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1758] + (const void *)&gInstructions[1764] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1769] + (const void *)&gInstructions[1775] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1770] + (const void *)&gInstructions[1776] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix = @@ -3942,19 +3998,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1768] + (const void *)&gInstructions[1774] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1875] + (const void *)&gInstructions[1881] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1876] + (const void *)&gInstructions[1882] }; const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm = @@ -3972,455 +4028,501 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm = } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[128] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[444] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1151] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1152] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_06_None_leaf, - /* 01 */ NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_06_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_06_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_F3_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[604] + (const void *)&gInstructions[127] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_NP_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[611] + (const void *)&gInstructions[1137] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_02_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_02_NP_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_06_NP_leaf, /* 01 */ NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_02_F3_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_06_F3_leaf, /* 03 */ NULL, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_03_NP_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_02_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[729] + (const void *)&gInstructions[1194] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_03_NP_leaf, + /* 00 */ NULL, /* 01 */ NULL, - /* 02 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_02_F3_leaf, /* 03 */ NULL, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F3_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1037] + (const void *)&gInstructions[1217] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F2_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1114] + (const void *)&gInstructions[1233] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_None_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1333] + (const void *)&gInstructions[2584] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_07_None_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_00_NP_leaf, /* 01 */ NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_07_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_07_F2_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_00_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_05_00_F2_leaf, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1137] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_01_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1146] + (const void *)&gInstructions[1294] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_00_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1308] + (const void *)&gInstructions[2527] }; -const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix = { - ND_ILUT_MODRM_RM, + ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_07_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_02_mprefix, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_03_mprefix, - /* 04 */ (const void *)&gRootTable_root_0f_01_reg_07_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_01_reg_07_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_01_reg_07_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_01_reg_07_07_mprefix, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_07_NP_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_07_F3_leaf, + /* 03 */ NULL, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_07_NP_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_05_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[230] + (const void *)&gInstructions[1332] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_07_NP_leaf, + /* 00 */ NULL, /* 01 */ NULL, - /* 02 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_05_F3_leaf, /* 03 */ NULL, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_04_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1756] + (const void *)&gInstructions[1347] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_04_NP_leaf, + /* 00 */ NULL, /* 01 */ NULL, - /* 02 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_04_F3_leaf, /* 03 */ NULL, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2542] + (const void *)&gInstructions[2567] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_05_NP_leaf, + /* 00 */ NULL, /* 01 */ NULL, /* 02 */ NULL, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_05_01_F2_leaf, + } +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_05_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_00_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_01_reg_05_01_mprefix, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_02_mprefix, /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_01_reg_05_04_mprefix, + /* 05 */ (const void *)&gRootTable_root_0f_01_reg_05_05_mprefix, + /* 06 */ (const void *)&gRootTable_root_0f_01_reg_05_06_mprefix, + /* 07 */ (const void *)&gRootTable_root_0f_01_reg_05_07_mprefix, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2543] + (const void *)&gInstructions[129] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_None_leaf = { - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_00_NP_leaf, - /* 01 */ NULL, - /* 02 */ NULL, - /* 03 */ NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[446] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2570] + (const void *)&gInstructions[1153] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1154] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_01_NP_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_06_None_leaf, /* 01 */ NULL, - /* 02 */ NULL, - /* 03 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_06_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_06_F2_leaf, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2575] + (const void *)&gInstructions[606] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_NP_leaf = { - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_06_NP_leaf, - /* 01 */ NULL, - /* 02 */ NULL, - /* 03 */ NULL, - } + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[613] }; -const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_02_modrmrm = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_02_mprefix = { - ND_ILUT_MODRM_RM, + ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_00_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_02_01_mprefix, - /* 02 */ NULL, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_02_NP_leaf, + /* 01 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_02_F3_leaf, /* 03 */ NULL, - /* 04 */ (const void *)&gRootTable_root_0f_01_reg_02_04_mprefix, - /* 05 */ (const void *)&gRootTable_root_0f_01_reg_02_05_mprefix, - /* 06 */ (const void *)&gRootTable_root_0f_01_reg_02_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_01_reg_02_07_mprefix, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_00_NP_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_03_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[231] + (const void *)&gInstructions[731] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_00_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_00_NP_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_03_NP_leaf, /* 01 */ NULL, /* 02 */ NULL, /* 03 */ NULL, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_05_NP_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[874] + (const void *)&gInstructions[1039] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1116] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_None_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1338] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_05_NP_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_07_None_leaf, /* 01 */ NULL, - /* 02 */ NULL, - /* 03 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_07_F3_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_07_F2_leaf, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1754] + (const void *)&gInstructions[1139] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1767] + (const void *)&gInstructions[1148] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1874] + (const void *)&gInstructions[1312] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_leaf = +const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_00_leaf, + /* 01 */ (const void *)&gRootTable_root_0f_01_reg_07_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_02_mprefix, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_03_mprefix, + /* 04 */ (const void *)&gRootTable_root_0f_01_reg_07_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_01_reg_07_05_leaf, + /* 06 */ (const void *)&gRootTable_root_0f_01_reg_07_06_mprefix, + /* 07 */ (const void *)&gRootTable_root_0f_01_reg_07_07_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1886] + (const void *)&gInstructions[231] }; -const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix = { - ND_ILUT_MODRM_RM, + ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_00_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_00_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_00_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_00_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_01_reg_00_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_01_reg_00_05_mprefix, - /* 06 */ NULL, - /* 07 */ NULL, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_07_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_06_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[578] + (const void *)&gInstructions[1762] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_NP_leaf = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_04_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1135] + (const void *)&gInstructions[2552] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_06_NP_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_05_NP_leaf, /* 01 */ NULL, /* 02 */ NULL, /* 03 */ NULL, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_02_F3_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1192] + (const void *)&gInstructions[2553] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ NULL, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_00_NP_leaf, /* 01 */ NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_02_F3_leaf, + /* 02 */ NULL, /* 03 */ NULL, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_NP_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1214] + (const void *)&gInstructions[2580] }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix = { - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1230] + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_01_NP_leaf, + /* 01 */ NULL, + /* 02 */ NULL, + /* 03 */ NULL, + } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2574] + (const void *)&gInstructions[2585] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_00_NP_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_06_NP_leaf, /* 01 */ NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_00_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_05_00_F2_leaf, + /* 02 */ NULL, + /* 03 */ NULL, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf = +const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_02_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_00_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_01_reg_02_01_mprefix, + /* 02 */ NULL, + /* 03 */ NULL, + /* 04 */ (const void *)&gRootTable_root_0f_01_reg_02_04_mprefix, + /* 05 */ (const void *)&gRootTable_root_0f_01_reg_02_05_mprefix, + /* 06 */ (const void *)&gRootTable_root_0f_01_reg_02_06_mprefix, + /* 07 */ (const void *)&gRootTable_root_0f_01_reg_02_07_mprefix, + } +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2517] + (const void *)&gInstructions[232] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_00_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_07_NP_leaf, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_00_NP_leaf, /* 01 */ NULL, /* 02 */ NULL, /* 03 */ NULL, } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_05_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2557] + (const void *)&gInstructions[876] }; -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix = +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix = { ND_ILUT_MAN_PREFIX, { - /* 00 */ NULL, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_05_NP_leaf, /* 01 */ NULL, /* 02 */ NULL, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_05_01_F2_leaf, + /* 03 */ NULL, } }; -const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_05_modrmrm = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1760] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1773] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1880] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1892] +}; + +const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm = { ND_ILUT_MODRM_RM, { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_00_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_05_01_mprefix, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_02_mprefix, - /* 03 */ NULL, - /* 04 */ NULL, - /* 05 */ NULL, - /* 06 */ (const void *)&gRootTable_root_0f_01_reg_05_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_01_reg_05_07_mprefix, + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_00_mprefix, + /* 01 */ (const void *)&gRootTable_root_0f_01_reg_00_01_leaf, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_00_02_leaf, + /* 03 */ (const void *)&gRootTable_root_0f_01_reg_00_03_leaf, + /* 04 */ (const void *)&gRootTable_root_0f_01_reg_00_04_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_01_reg_00_05_mprefix, + /* 06 */ NULL, + /* 07 */ NULL, } }; +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[580] +}; + const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1268] + (const void *)&gInstructions[1271] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg = @@ -4441,31 +4543,31 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[442] + (const void *)&gInstructions[444] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[573] + (const void *)&gInstructions[575] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[575] + (const void *)&gInstructions[577] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[578] + (const void *)&gInstructions[580] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_05_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1175] + (const void *)&gInstructions[1177] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix = @@ -4482,19 +4584,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1233] + (const void *)&gInstructions[1236] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1261] + (const void *)&gInstructions[1264] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1267] + (const void *)&gInstructions[1270] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_01_mem_modrmreg = @@ -4530,19 +4632,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_NP_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[758] + (const void *)&gInstructions[760] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[759] + (const void *)&gInstructions[761] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[760] + (const void *)&gInstructions[762] }; const ND_TABLE_MPREFIX gRootTable_root_0f_1c_cldm_mem_00_mprefix = @@ -4559,43 +4661,43 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_1c_cldm_mem_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[762] + (const void *)&gInstructions[764] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[763] + (const void *)&gInstructions[765] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[764] + (const void *)&gInstructions[766] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[765] + (const void *)&gInstructions[767] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[766] + (const void *)&gInstructions[768] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[767] + (const void *)&gInstructions[769] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[768] + (const void *)&gInstructions[770] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_mem_modrmreg = @@ -4616,49 +4718,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[761] + (const void *)&gInstructions[763] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[762] + (const void *)&gInstructions[764] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[763] + (const void *)&gInstructions[765] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[764] + (const void *)&gInstructions[766] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[765] + (const void *)&gInstructions[767] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[766] + (const void *)&gInstructions[768] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[767] + (const void *)&gInstructions[769] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[768] + (const void *)&gInstructions[770] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_reg_modrmreg = @@ -4688,7 +4790,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1c_cldm_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[751] + (const void *)&gInstructions[753] }; const ND_TABLE_FEATURE gRootTable_root_0f_1c_feature = @@ -4734,19 +4836,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_F3_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[127] + (const void *)&gInstructions[128] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2566] + (const void *)&gInstructions[2576] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2567] + (const void *)&gInstructions[2577] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary = @@ -4776,13 +4878,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[387] + (const void *)&gInstructions[388] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[388] + (const void *)&gInstructions[389] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_01_NP_auxiliary = @@ -4812,13 +4914,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[389] + (const void *)&gInstructions[390] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[390] + (const void *)&gInstructions[391] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_00_NP_auxiliary = @@ -4848,7 +4950,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[565] + (const void *)&gInstructions[567] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix = @@ -4865,19 +4967,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1077] + (const void *)&gInstructions[1079] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2562] + (const void *)&gInstructions[2572] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2563] + (const void *)&gInstructions[2573] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary = @@ -4907,7 +5009,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_03_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1279] + (const void *)&gInstructions[1282] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix = @@ -4924,13 +5026,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2558] + (const void *)&gInstructions[2568] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2559] + (const void *)&gInstructions[2569] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary = @@ -4975,13 +5077,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_ae_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[424] + (const void *)&gInstructions[426] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[425] + (const void *)&gInstructions[427] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary = @@ -5000,7 +5102,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[571] + (const void *)&gInstructions[573] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_05_mprefix = @@ -5017,25 +5119,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[605] + (const void *)&gInstructions[607] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1334] + (const void *)&gInstructions[1339] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1342] + (const void *)&gInstructions[1348] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1343] + (const void *)&gInstructions[1349] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix = @@ -5052,13 +5154,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[873] + (const void *)&gInstructions[875] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1232] + (const void *)&gInstructions[1235] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix = @@ -5075,7 +5177,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_04_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1077] + (const void *)&gInstructions[1079] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix = @@ -5092,7 +5194,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_00_F3_64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1131] + (const void *)&gInstructions[1133] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_00_F3_auxiliary = @@ -5122,7 +5224,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_01_F3_64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1132] + (const void *)&gInstructions[1134] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_01_F3_auxiliary = @@ -5152,7 +5254,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_02_F3_64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2514] + (const void *)&gInstructions[2524] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary = @@ -5182,7 +5284,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_03_F3_64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2515] + (const void *)&gInstructions[2525] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary = @@ -5242,121 +5344,121 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_06_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_46_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[130] + (const void *)&gInstructions[131] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_42_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[131] + (const void *)&gInstructions[132] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_4c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[132] + (const void *)&gInstructions[133] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_4e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[133] + (const void *)&gInstructions[134] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_47_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[134] + (const void *)&gInstructions[135] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_43_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[135] + (const void *)&gInstructions[136] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_4d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[136] + (const void *)&gInstructions[137] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_4f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[137] + (const void *)&gInstructions[138] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_41_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[138] + (const void *)&gInstructions[139] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_4b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[139] + (const void *)&gInstructions[140] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_49_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[140] + (const void *)&gInstructions[141] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_45_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[141] + (const void *)&gInstructions[142] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_40_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[142] + (const void *)&gInstructions[143] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_4a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[143] + (const void *)&gInstructions[144] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_48_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[144] + (const void *)&gInstructions[145] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_44_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[145] + (const void *)&gInstructions[146] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[156] + (const void *)&gInstructions[157] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[157] + (const void *)&gInstructions[158] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[160] + (const void *)&gInstructions[161] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[165] + (const void *)&gInstructions[166] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c2_mprefix = @@ -5373,25 +5475,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c2_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_b0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[168] + (const void *)&gInstructions[169] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_b1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[169] + (const void *)&gInstructions[170] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_01_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[170] + (const void *)&gInstructions[171] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_01_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[171] + (const void *)&gInstructions[172] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary = @@ -5410,19 +5512,19 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1755] + (const void *)&gInstructions[1761] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1871] + (const void *)&gInstructions[1877] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1887] + (const void *)&gInstructions[1893] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix = @@ -5439,7 +5541,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1872] + (const void *)&gInstructions[1878] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix = @@ -5456,13 +5558,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2560] + (const void *)&gInstructions[2570] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2561] + (const void *)&gInstructions[2571] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary = @@ -5492,13 +5594,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2564] + (const void *)&gInstructions[2574] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2565] + (const void *)&gInstructions[2575] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary = @@ -5528,13 +5630,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2568] + (const void *)&gInstructions[2578] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2569] + (const void *)&gInstructions[2579] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary = @@ -5579,19 +5681,19 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_c7_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1134] + (const void *)&gInstructions[1136] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1140] + (const void *)&gInstructions[1142] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1141] + (const void *)&gInstructions[1143] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix = @@ -5608,13 +5710,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1138] + (const void *)&gInstructions[1140] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1139] + (const void *)&gInstructions[1141] +}; + +const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1216] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_06_mprefix = @@ -5623,7 +5731,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_06_mprefix = { /* 00 */ (const void *)&gRootTable_root_0f_c7_reg_06_None_leaf, /* 01 */ (const void *)&gRootTable_root_0f_c7_reg_06_66_leaf, - /* 02 */ NULL, + /* 02 */ (const void *)&gRootTable_root_0f_c7_reg_06_F3_leaf, /* 03 */ NULL, } }; @@ -5655,13 +5763,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_2f_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[172] + (const void *)&gInstructions[173] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2f_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[173] + (const void *)&gInstructions[174] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2f_mprefix = @@ -5678,37 +5786,37 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2f_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[174] + (const void *)&gInstructions[175] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_3d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[175] + (const void *)&gInstructions[176] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_3c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[176] + (const void *)&gInstructions[177] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[182] + (const void *)&gInstructions[183] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[184] + (const void *)&gInstructions[185] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[198] + (const void *)&gInstructions[199] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e6_mprefix = @@ -5725,19 +5833,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e6_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[183] + (const void *)&gInstructions[184] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[189] + (const void *)&gInstructions[190] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[200] + (const void *)&gInstructions[201] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5b_mprefix = @@ -5754,25 +5862,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[185] + (const void *)&gInstructions[186] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[191] + (const void *)&gInstructions[192] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[192] + (const void *)&gInstructions[193] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[197] + (const void *)&gInstructions[198] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2d_mprefix = @@ -5789,25 +5897,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2d_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[186] + (const void *)&gInstructions[187] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[190] + (const void *)&gInstructions[191] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[193] + (const void *)&gInstructions[194] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[196] + (const void *)&gInstructions[197] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5a_mprefix = @@ -5824,25 +5932,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[187] + (const void *)&gInstructions[188] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[188] + (const void *)&gInstructions[189] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[194] + (const void *)&gInstructions[195] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[195] + (const void *)&gInstructions[196] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2a_mprefix = @@ -5859,25 +5967,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[199] + (const void *)&gInstructions[200] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[201] + (const void *)&gInstructions[202] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[202] + (const void *)&gInstructions[203] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[203] + (const void *)&gInstructions[204] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2c_mprefix = @@ -5894,25 +6002,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[221] + (const void *)&gInstructions[222] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[222] + (const void *)&gInstructions[223] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[223] + (const void *)&gInstructions[224] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[224] + (const void *)&gInstructions[225] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5e_mprefix = @@ -5929,13 +6037,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_39_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[225] + (const void *)&gInstructions[226] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_77_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[228] + (const void *)&gInstructions[229] }; const ND_TABLE_MPREFIX gRootTable_root_0f_77_mprefix = @@ -5952,13 +6060,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_77_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_03_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[234] + (const void *)&gInstructions[235] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_03_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[781] + (const void *)&gInstructions[783] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_03_auxiliary = @@ -5977,13 +6085,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_03_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_02_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[235] + (const void *)&gInstructions[236] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_02_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[780] + (const void *)&gInstructions[782] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_02_auxiliary = @@ -6002,37 +6110,37 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_02_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[778] + (const void *)&gInstructions[780] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[779] + (const void *)&gInstructions[781] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[782] + (const void *)&gInstructions[784] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[783] + (const void *)&gInstructions[785] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[784] + (const void *)&gInstructions[786] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[785] + (const void *)&gInstructions[787] }; const ND_TABLE_MODRM_RM gRootTable_root_0f_1e_cet_reg_07_modrmrm = @@ -6053,25 +6161,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_1e_cet_reg_07_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[770] + (const void *)&gInstructions[772] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[771] + (const void *)&gInstructions[773] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_rexw_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[772] + (const void *)&gInstructions[774] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_rexw_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1144] + (const void *)&gInstructions[1146] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary = @@ -6090,7 +6198,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1143] + (const void *)&gInstructions[1145] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_auxiliary = @@ -6109,31 +6217,31 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[773] + (const void *)&gInstructions[775] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[774] + (const void *)&gInstructions[776] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[775] + (const void *)&gInstructions[777] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[776] + (const void *)&gInstructions[778] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[777] + (const void *)&gInstructions[779] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_1e_cet_reg_modrmreg = @@ -6154,7 +6262,7 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_1e_cet_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[769] + (const void *)&gInstructions[771] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_1e_cet_modrmmod = @@ -6169,7 +6277,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1e_cet_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[753] + (const void *)&gInstructions[755] }; const ND_TABLE_FEATURE gRootTable_root_0f_1e_feature = @@ -6186,7 +6294,7 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1e_feature = const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_66_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[240] + (const void *)&gInstructions[241] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_78_None_66_modrmreg = @@ -6207,13 +6315,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_78_None_66_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[432] + (const void *)&gInstructions[434] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1873] + (const void *)&gInstructions[1879] }; const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix = @@ -6230,7 +6338,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1305] + (const void *)&gInstructions[1309] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_78_cyrix_modrmmod = @@ -6258,19 +6366,19 @@ const ND_TABLE_VENDOR gRootTable_root_0f_78_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[241] + (const void *)&gInstructions[242] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[433] + (const void *)&gInstructions[435] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1885] + (const void *)&gInstructions[1891] }; const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix = @@ -6287,7 +6395,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1885] + (const void *)&gInstructions[1891] }; const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_mem_mprefix = @@ -6313,7 +6421,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_None_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1170] + (const void *)&gInstructions[1172] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_cyrix_modrmmod = @@ -6341,13 +6449,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_79_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[284] + (const void *)&gInstructions[285] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_None_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[394] + (const void *)&gInstructions[395] }; const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix = @@ -6364,7 +6472,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_cyrix_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2518] + (const void *)&gInstructions[2528] }; const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor = @@ -6383,13 +6491,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[398] + (const void *)&gInstructions[399] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[399] + (const void *)&gInstructions[400] }; const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix = @@ -6406,7 +6514,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1307] + (const void *)&gInstructions[1311] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_7c_cyrix_modrmmod = @@ -6434,13 +6542,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7c_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[401] + (const void *)&gInstructions[403] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[402] + (const void *)&gInstructions[404] }; const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix = @@ -6457,7 +6565,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1176] + (const void *)&gInstructions[1178] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_7d_cyrix_modrmmod = @@ -6485,79 +6593,79 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7d_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_af_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[405] + (const void *)&gInstructions[407] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[440] + (const void *)&gInstructions[442] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[450] + (const void *)&gInstructions[452] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_82_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[452] + (const void *)&gInstructions[454] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_8c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[456] + (const void *)&gInstructions[458] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_8e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[458] + (const void *)&gInstructions[460] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[463] + (const void *)&gInstructions[465] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[576] + (const void *)&gInstructions[578] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[594] + (const void *)&gInstructions[596] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1263] + (const void *)&gInstructions[1266] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1288] + (const void *)&gInstructions[1291] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1499] + (const void *)&gInstructions[1505] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1500] + (const void *)&gInstructions[1506] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg = @@ -6578,43 +6686,43 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[463] + (const void *)&gInstructions[465] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[576] + (const void *)&gInstructions[578] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[594] + (const void *)&gInstructions[596] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1264] + (const void *)&gInstructions[1267] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1289] + (const void *)&gInstructions[1292] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1499] + (const void *)&gInstructions[1505] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1500] + (const void *)&gInstructions[1506] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg = @@ -6644,13 +6752,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_00_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[464] + (const void *)&gInstructions[466] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[992] + (const void *)&gInstructions[994] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary = @@ -6669,85 +6777,85 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[467] + (const void *)&gInstructions[469] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_83_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[469] + (const void *)&gInstructions[471] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_8d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[471] + (const void *)&gInstructions[473] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_8f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[473] + (const void *)&gInstructions[475] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_81_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[475] + (const void *)&gInstructions[477] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_8b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[477] + (const void *)&gInstructions[479] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_89_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[479] + (const void *)&gInstructions[481] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[481] + (const void *)&gInstructions[483] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_80_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[483] + (const void *)&gInstructions[485] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_8a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[485] + (const void *)&gInstructions[487] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_88_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[488] + (const void *)&gInstructions[490] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_84_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[490] + (const void *)&gInstructions[492] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[562] + (const void *)&gInstructions[564] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[563] + (const void *)&gInstructions[565] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_02_modrmmod = @@ -6762,7 +6870,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_02_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f0_mem_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[564] + (const void *)&gInstructions[566] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f0_mem_mprefix = @@ -6788,7 +6896,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_f0_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_b4_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[572] + (const void *)&gInstructions[574] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod = @@ -6803,7 +6911,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_b5_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[574] + (const void *)&gInstructions[576] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod = @@ -6818,13 +6926,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[591] + (const void *)&gInstructions[593] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[592] + (const void *)&gInstructions[594] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_03_modrmmod = @@ -6839,7 +6947,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_03_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_b2_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[593] + (const void *)&gInstructions[595] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_b2_modrmmod = @@ -6854,13 +6962,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b2_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f7_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[598] + (const void *)&gInstructions[600] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f7_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[599] + (const void *)&gInstructions[601] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f7_reg_mprefix = @@ -6886,25 +6994,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_f7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[600] + (const void *)&gInstructions[602] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[601] + (const void *)&gInstructions[603] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[602] + (const void *)&gInstructions[604] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[603] + (const void *)&gInstructions[605] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5f_mprefix = @@ -6921,25 +7029,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5f_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[606] + (const void *)&gInstructions[608] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[607] + (const void *)&gInstructions[609] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[608] + (const void *)&gInstructions[610] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[609] + (const void *)&gInstructions[611] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5d_mprefix = @@ -6956,7 +7064,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5d_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_00_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[612] + (const void *)&gInstructions[614] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_00_00_mprefix = @@ -6988,7 +7096,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_00_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_01_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2571] + (const void *)&gInstructions[2581] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_01_00_mprefix = @@ -7020,7 +7128,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_01_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_02_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2572] + (const void *)&gInstructions[2582] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_02_00_mprefix = @@ -7076,49 +7184,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a6_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_20_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[613] + (const void *)&gInstructions[615] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_21_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[614] + (const void *)&gInstructions[616] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_22_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[615] + (const void *)&gInstructions[617] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_23_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[616] + (const void *)&gInstructions[618] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_24_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[617] + (const void *)&gInstructions[619] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_26_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[618] + (const void *)&gInstructions[620] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_28_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[649] + (const void *)&gInstructions[651] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_28_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[651] + (const void *)&gInstructions[653] }; const ND_TABLE_MPREFIX gRootTable_root_0f_28_mprefix = @@ -7135,13 +7243,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_28_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_29_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[650] + (const void *)&gInstructions[652] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_29_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[652] + (const void *)&gInstructions[654] }; const ND_TABLE_MPREFIX gRootTable_root_0f_29_mprefix = @@ -7158,13 +7266,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_29_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[657] + (const void *)&gInstructions[659] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[688] + (const void *)&gInstructions[690] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_NP_auxiliary = @@ -7183,13 +7291,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_NP_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_66_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[658] + (const void *)&gInstructions[660] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_66_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[689] + (const void *)&gInstructions[691] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_66_auxiliary = @@ -7219,13 +7327,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[659] + (const void *)&gInstructions[661] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[691] + (const void *)&gInstructions[693] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_NP_auxiliary = @@ -7244,13 +7352,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_NP_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_66_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[660] + (const void *)&gInstructions[662] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_66_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[692] + (const void *)&gInstructions[694] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_66_auxiliary = @@ -7269,7 +7377,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_66_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[693] + (const void *)&gInstructions[695] }; const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix = @@ -7286,7 +7394,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_cyrix_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1266] + (const void *)&gInstructions[1269] }; const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor = @@ -7305,25 +7413,25 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[661] + (const void *)&gInstructions[663] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[669] + (const void *)&gInstructions[671] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[675] + (const void *)&gInstructions[677] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[704] + (const void *)&gInstructions[706] }; const ND_TABLE_MPREFIX gRootTable_root_0f_12_mem_mprefix = @@ -7340,19 +7448,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_12_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[661] + (const void *)&gInstructions[663] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[669] + (const void *)&gInstructions[671] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[704] + (const void *)&gInstructions[706] }; const ND_TABLE_MPREFIX gRootTable_root_0f_12_reg_mprefix = @@ -7378,19 +7486,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_12_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[664] + (const void *)&gInstructions[666] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[695] + (const void *)&gInstructions[697] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[696] + (const void *)&gInstructions[698] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d6_reg_mprefix = @@ -7407,7 +7515,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d6_reg_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[695] + (const void *)&gInstructions[697] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d6_mem_mprefix = @@ -7433,19 +7541,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_d6_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[665] + (const void *)&gInstructions[667] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[667] + (const void *)&gInstructions[669] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[690] + (const void *)&gInstructions[692] }; const ND_TABLE_MPREFIX gRootTable_root_0f_6f_mprefix = @@ -7462,19 +7570,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6f_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[666] + (const void *)&gInstructions[668] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[668] + (const void *)&gInstructions[670] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[694] + (const void *)&gInstructions[696] }; const ND_TABLE_MPREFIX gRootTable_root_0f_7f_mprefix = @@ -7491,19 +7599,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7f_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[670] + (const void *)&gInstructions[672] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[672] + (const void *)&gInstructions[674] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[703] + (const void *)&gInstructions[705] }; const ND_TABLE_MPREFIX gRootTable_root_0f_16_mem_mprefix = @@ -7520,13 +7628,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_16_mem_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[674] + (const void *)&gInstructions[676] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[703] + (const void *)&gInstructions[705] }; const ND_TABLE_MPREFIX gRootTable_root_0f_16_reg_mprefix = @@ -7552,13 +7660,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_16_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[671] + (const void *)&gInstructions[673] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[673] + (const void *)&gInstructions[675] }; const ND_TABLE_MPREFIX gRootTable_root_0f_17_mem_mprefix = @@ -7584,13 +7692,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_17_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[676] + (const void *)&gInstructions[678] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[677] + (const void *)&gInstructions[679] }; const ND_TABLE_MPREFIX gRootTable_root_0f_13_mem_mprefix = @@ -7616,13 +7724,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_13_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_50_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[678] + (const void *)&gInstructions[680] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_50_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[679] + (const void *)&gInstructions[681] }; const ND_TABLE_MPREFIX gRootTable_root_0f_50_reg_mprefix = @@ -7648,13 +7756,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_50_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e7_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[680] + (const void *)&gInstructions[682] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e7_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[685] + (const void *)&gInstructions[687] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e7_mem_mprefix = @@ -7680,7 +7788,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_e7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c3_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[682] + (const void *)&gInstructions[684] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c3_mem_mprefix = @@ -7706,25 +7814,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c3_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[683] + (const void *)&gInstructions[685] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[684] + (const void *)&gInstructions[686] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[686] + (const void *)&gInstructions[688] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[687] + (const void *)&gInstructions[689] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2b_mem_mprefix = @@ -7750,25 +7858,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_2b_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[699] + (const void *)&gInstructions[701] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[707] + (const void *)&gInstructions[709] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[714] + (const void *)&gInstructions[716] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[716] + (const void *)&gInstructions[718] }; const ND_TABLE_MPREFIX gRootTable_root_0f_10_mprefix = @@ -7785,25 +7893,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_10_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[700] + (const void *)&gInstructions[702] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[708] + (const void *)&gInstructions[710] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[715] + (const void *)&gInstructions[717] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[717] + (const void *)&gInstructions[719] }; const ND_TABLE_MPREFIX gRootTable_root_0f_11_mprefix = @@ -7820,49 +7928,49 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_11_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_be_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[711] + (const void *)&gInstructions[713] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_bf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[712] + (const void *)&gInstructions[714] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[718] + (const void *)&gInstructions[720] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_b7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[719] + (const void *)&gInstructions[721] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[723] + (const void *)&gInstructions[725] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[724] + (const void *)&gInstructions[726] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[725] + (const void *)&gInstructions[727] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[726] + (const void *)&gInstructions[728] }; const ND_TABLE_MPREFIX gRootTable_root_0f_59_mprefix = @@ -7879,49 +7987,49 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_59_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[732] + (const void *)&gInstructions[734] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[733] + (const void *)&gInstructions[735] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[734] + (const void *)&gInstructions[736] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[735] + (const void *)&gInstructions[737] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[736] + (const void *)&gInstructions[738] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[737] + (const void *)&gInstructions[739] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[738] + (const void *)&gInstructions[740] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[739] + (const void *)&gInstructions[741] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_reg_modrmreg = @@ -7942,49 +8050,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[998] + (const void *)&gInstructions[1000] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[999] + (const void *)&gInstructions[1001] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1000] + (const void *)&gInstructions[1002] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1001] + (const void *)&gInstructions[1003] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1002] + (const void *)&gInstructions[1004] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1003] + (const void *)&gInstructions[1005] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1008] + (const void *)&gInstructions[1010] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1009] + (const void *)&gInstructions[1011] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_mem_modrmreg = @@ -8014,49 +8122,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_0d_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[740] + (const void *)&gInstructions[742] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[741] + (const void *)&gInstructions[743] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[742] + (const void *)&gInstructions[744] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[743] + (const void *)&gInstructions[745] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[744] + (const void *)&gInstructions[746] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[745] + (const void *)&gInstructions[747] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[746] + (const void *)&gInstructions[748] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[747] + (const void *)&gInstructions[749] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_18_reg_modrmreg = @@ -8077,49 +8185,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_18_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[744] + (const void *)&gInstructions[746] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[745] + (const void *)&gInstructions[747] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[746] + (const void *)&gInstructions[748] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[747] + (const void *)&gInstructions[749] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1004] + (const void *)&gInstructions[1006] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1005] + (const void *)&gInstructions[1007] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1006] + (const void *)&gInstructions[1008] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1007] + (const void *)&gInstructions[1009] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_18_mem_modrmreg = @@ -8149,31 +8257,31 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_18_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_19_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[748] + (const void *)&gInstructions[750] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[752] + (const void *)&gInstructions[754] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_1f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[754] + (const void *)&gInstructions[756] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_56_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[799] + (const void *)&gInstructions[801] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_56_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[800] + (const void *)&gInstructions[802] }; const ND_TABLE_MPREFIX gRootTable_root_0f_56_mprefix = @@ -8190,13 +8298,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_56_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6b_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[817] + (const void *)&gInstructions[819] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[818] + (const void *)&gInstructions[820] }; const ND_TABLE_MPREFIX gRootTable_root_0f_6b_mprefix = @@ -8213,13 +8321,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_63_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[819] + (const void *)&gInstructions[821] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_63_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[820] + (const void *)&gInstructions[822] }; const ND_TABLE_MPREFIX gRootTable_root_0f_63_mprefix = @@ -8236,13 +8344,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_63_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_67_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[822] + (const void *)&gInstructions[824] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_67_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[823] + (const void *)&gInstructions[825] }; const ND_TABLE_MPREFIX gRootTable_root_0f_67_mprefix = @@ -8259,13 +8367,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_67_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_fc_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[824] + (const void *)&gInstructions[826] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_fc_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[825] + (const void *)&gInstructions[827] }; const ND_TABLE_MPREFIX gRootTable_root_0f_fc_mprefix = @@ -8282,13 +8390,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fc_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_fe_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[826] + (const void *)&gInstructions[828] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_fe_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[827] + (const void *)&gInstructions[829] }; const ND_TABLE_MPREFIX gRootTable_root_0f_fe_mprefix = @@ -8305,13 +8413,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fe_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d4_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[828] + (const void *)&gInstructions[830] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d4_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[829] + (const void *)&gInstructions[831] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d4_mprefix = @@ -8328,13 +8436,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d4_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ec_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[830] + (const void *)&gInstructions[832] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ec_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[831] + (const void *)&gInstructions[833] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ec_mprefix = @@ -8351,13 +8459,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ec_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ed_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[832] + (const void *)&gInstructions[834] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ed_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[833] + (const void *)&gInstructions[835] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ed_mprefix = @@ -8374,13 +8482,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ed_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_dc_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[834] + (const void *)&gInstructions[836] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_dc_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[835] + (const void *)&gInstructions[837] }; const ND_TABLE_MPREFIX gRootTable_root_0f_dc_mprefix = @@ -8397,13 +8505,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_dc_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_dd_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[836] + (const void *)&gInstructions[838] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_dd_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[837] + (const void *)&gInstructions[839] }; const ND_TABLE_MPREFIX gRootTable_root_0f_dd_mprefix = @@ -8420,13 +8528,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_dd_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_fd_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[838] + (const void *)&gInstructions[840] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_fd_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[839] + (const void *)&gInstructions[841] }; const ND_TABLE_MPREFIX gRootTable_root_0f_fd_mprefix = @@ -8443,13 +8551,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fd_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_db_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[842] + (const void *)&gInstructions[844] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_db_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[843] + (const void *)&gInstructions[845] }; const ND_TABLE_MPREFIX gRootTable_root_0f_db_mprefix = @@ -8466,13 +8574,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_db_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_df_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[844] + (const void *)&gInstructions[846] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_df_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[845] + (const void *)&gInstructions[847] }; const ND_TABLE_MPREFIX gRootTable_root_0f_df_mprefix = @@ -8489,13 +8597,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_df_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e0_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[847] + (const void *)&gInstructions[849] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e0_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[848] + (const void *)&gInstructions[850] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e0_mprefix = @@ -8512,157 +8620,157 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e0_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[849] + (const void *)&gInstructions[851] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[885] + (const void *)&gInstructions[887] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[886] + (const void *)&gInstructions[888] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_ae_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[887] + (const void *)&gInstructions[889] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[888] + (const void *)&gInstructions[890] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[889] + (const void *)&gInstructions[891] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_90_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[890] + (const void *)&gInstructions[892] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[891] + (const void *)&gInstructions[893] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[892] + (const void *)&gInstructions[894] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[893] + (const void *)&gInstructions[895] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[894] + (const void *)&gInstructions[896] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[895] + (const void *)&gInstructions[897] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[896] + (const void *)&gInstructions[898] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[897] + (const void *)&gInstructions[899] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[898] + (const void *)&gInstructions[900] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[899] + (const void *)&gInstructions[901] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[900] + (const void *)&gInstructions[902] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[901] + (const void *)&gInstructions[903] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[902] + (const void *)&gInstructions[904] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[903] + (const void *)&gInstructions[905] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[904] + (const void *)&gInstructions[906] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_aa_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[905] + (const void *)&gInstructions[907] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[919] + (const void *)&gInstructions[921] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[920] + (const void *)&gInstructions[922] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[966] + (const void *)&gInstructions[968] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1075] + (const void *)&gInstructions[1077] }; const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow = @@ -8931,13 +9039,13 @@ const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e3_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[850] + (const void *)&gInstructions[852] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e3_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[851] + (const void *)&gInstructions[853] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e3_mprefix = @@ -8954,13 +9062,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e3_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[855] + (const void *)&gInstructions[857] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[856] + (const void *)&gInstructions[858] }; const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix = @@ -8977,13 +9085,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[857] + (const void *)&gInstructions[859] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[858] + (const void *)&gInstructions[860] }; const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix = @@ -9000,13 +9108,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[860] + (const void *)&gInstructions[862] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[861] + (const void *)&gInstructions[863] }; const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix = @@ -9023,13 +9131,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[864] + (const void *)&gInstructions[866] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[865] + (const void *)&gInstructions[867] }; const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix = @@ -9046,13 +9154,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[866] + (const void *)&gInstructions[868] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[867] + (const void *)&gInstructions[869] }; const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix = @@ -9069,13 +9177,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[869] + (const void *)&gInstructions[871] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[870] + (const void *)&gInstructions[872] }; const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix = @@ -9092,13 +9200,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[881] + (const void *)&gInstructions[883] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[882] + (const void *)&gInstructions[884] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c5_reg_mprefix = @@ -9124,13 +9232,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c5_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[925] + (const void *)&gInstructions[927] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[927] + (const void *)&gInstructions[929] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix = @@ -9147,13 +9255,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[926] + (const void *)&gInstructions[928] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[928] + (const void *)&gInstructions[930] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c4_mem_mprefix = @@ -9179,13 +9287,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c4_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[931] + (const void *)&gInstructions[933] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[932] + (const void *)&gInstructions[934] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix = @@ -9202,13 +9310,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[935] + (const void *)&gInstructions[937] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[936] + (const void *)&gInstructions[938] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix = @@ -9225,13 +9333,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[937] + (const void *)&gInstructions[939] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[938] + (const void *)&gInstructions[940] }; const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix = @@ -9248,13 +9356,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[943] + (const void *)&gInstructions[945] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[944] + (const void *)&gInstructions[946] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix = @@ -9271,13 +9379,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[945] + (const void *)&gInstructions[947] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[946] + (const void *)&gInstructions[948] }; const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix = @@ -9294,13 +9402,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[949] + (const void *)&gInstructions[951] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[950] + (const void *)&gInstructions[952] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d7_reg_mprefix = @@ -9326,13 +9434,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_d7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[967] + (const void *)&gInstructions[969] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[968] + (const void *)&gInstructions[970] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix = @@ -9349,13 +9457,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[969] + (const void *)&gInstructions[971] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[970] + (const void *)&gInstructions[972] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix = @@ -9372,13 +9480,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[972] + (const void *)&gInstructions[974] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[973] + (const void *)&gInstructions[975] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix = @@ -9395,13 +9503,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[974] + (const void *)&gInstructions[976] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[975] + (const void *)&gInstructions[977] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix = @@ -9418,25 +9526,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[976] + (const void *)&gInstructions[978] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[977] + (const void *)&gInstructions[979] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[996] + (const void *)&gInstructions[998] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[997] + (const void *)&gInstructions[999] }; const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix = @@ -9453,13 +9561,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1010] + (const void *)&gInstructions[1012] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1011] + (const void *)&gInstructions[1013] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix = @@ -9476,25 +9584,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1014] + (const void *)&gInstructions[1016] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1015] + (const void *)&gInstructions[1017] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1016] + (const void *)&gInstructions[1018] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1017] + (const void *)&gInstructions[1019] }; const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix = @@ -9511,13 +9619,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1024] + (const void *)&gInstructions[1026] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1025] + (const void *)&gInstructions[1027] }; const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix = @@ -9534,13 +9642,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1038] + (const void *)&gInstructions[1040] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1039] + (const void *)&gInstructions[1041] }; const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix = @@ -9557,13 +9665,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1046] + (const void *)&gInstructions[1048] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1047] + (const void *)&gInstructions[1049] }; const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_02_mprefix = @@ -9604,13 +9712,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_72_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1026] + (const void *)&gInstructions[1028] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1027] + (const void *)&gInstructions[1029] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix = @@ -9627,7 +9735,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_07_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1028] + (const void *)&gInstructions[1030] }; const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix = @@ -9644,13 +9752,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1029] + (const void *)&gInstructions[1031] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1030] + (const void *)&gInstructions[1032] }; const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix = @@ -9667,7 +9775,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_03_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1050] + (const void *)&gInstructions[1052] }; const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix = @@ -9684,13 +9792,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1051] + (const void *)&gInstructions[1053] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1052] + (const void *)&gInstructions[1054] }; const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_02_mprefix = @@ -9731,13 +9839,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_73_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1031] + (const void *)&gInstructions[1033] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1032] + (const void *)&gInstructions[1034] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix = @@ -9754,13 +9862,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1033] + (const void *)&gInstructions[1035] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1034] + (const void *)&gInstructions[1036] }; const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix = @@ -9777,13 +9885,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1042] + (const void *)&gInstructions[1044] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1043] + (const void *)&gInstructions[1045] }; const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix = @@ -9800,13 +9908,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1055] + (const void *)&gInstructions[1057] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1056] + (const void *)&gInstructions[1058] }; const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_02_mprefix = @@ -9847,13 +9955,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_71_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1035] + (const void *)&gInstructions[1037] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1036] + (const void *)&gInstructions[1038] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix = @@ -9870,13 +9978,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1040] + (const void *)&gInstructions[1042] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1041] + (const void *)&gInstructions[1043] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix = @@ -9893,13 +10001,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1044] + (const void *)&gInstructions[1046] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1045] + (const void *)&gInstructions[1047] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix = @@ -9916,13 +10024,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1048] + (const void *)&gInstructions[1050] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1049] + (const void *)&gInstructions[1051] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix = @@ -9939,13 +10047,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1053] + (const void *)&gInstructions[1055] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1054] + (const void *)&gInstructions[1056] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix = @@ -9962,13 +10070,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1057] + (const void *)&gInstructions[1059] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1058] + (const void *)&gInstructions[1060] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix = @@ -9985,13 +10093,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1059] + (const void *)&gInstructions[1061] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1060] + (const void *)&gInstructions[1062] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix = @@ -10008,13 +10116,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1061] + (const void *)&gInstructions[1063] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1062] + (const void *)&gInstructions[1064] }; const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix = @@ -10031,13 +10139,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1063] + (const void *)&gInstructions[1065] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1064] + (const void *)&gInstructions[1066] }; const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix = @@ -10054,13 +10162,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1065] + (const void *)&gInstructions[1067] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1066] + (const void *)&gInstructions[1068] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix = @@ -10077,13 +10185,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1067] + (const void *)&gInstructions[1069] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1068] + (const void *)&gInstructions[1070] }; const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix = @@ -10100,13 +10208,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1069] + (const void *)&gInstructions[1071] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1070] + (const void *)&gInstructions[1072] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix = @@ -10123,13 +10231,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1071] + (const void *)&gInstructions[1073] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1072] + (const void *)&gInstructions[1074] }; const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix = @@ -10146,13 +10254,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1073] + (const void *)&gInstructions[1075] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1074] + (const void *)&gInstructions[1076] }; const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix = @@ -10169,13 +10277,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1078] + (const void *)&gInstructions[1080] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1079] + (const void *)&gInstructions[1081] }; const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix = @@ -10192,13 +10300,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1080] + (const void *)&gInstructions[1082] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1081] + (const void *)&gInstructions[1083] }; const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix = @@ -10215,7 +10323,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6d_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1082] + (const void *)&gInstructions[1084] }; const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix = @@ -10232,13 +10340,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1083] + (const void *)&gInstructions[1085] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1084] + (const void *)&gInstructions[1086] }; const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix = @@ -10255,13 +10363,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1085] + (const void *)&gInstructions[1087] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1086] + (const void *)&gInstructions[1088] }; const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix = @@ -10278,13 +10386,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1087] + (const void *)&gInstructions[1089] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1088] + (const void *)&gInstructions[1090] }; const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix = @@ -10301,7 +10409,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_6c_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1089] + (const void *)&gInstructions[1091] }; const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix = @@ -10318,13 +10426,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1090] + (const void *)&gInstructions[1092] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1091] + (const void *)&gInstructions[1093] }; const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix = @@ -10341,25 +10449,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1092] + (const void *)&gInstructions[1094] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1093] + (const void *)&gInstructions[1095] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1115] + (const void *)&gInstructions[1117] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1116] + (const void *)&gInstructions[1118] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix = @@ -10376,13 +10484,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1123] + (const void *)&gInstructions[1125] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1124] + (const void *)&gInstructions[1126] }; const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix = @@ -10399,19 +10507,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1133] + (const void *)&gInstructions[1135] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_33_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1136] + (const void *)&gInstructions[1138] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_36_cyrix_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1142] + (const void *)&gInstructions[1144] }; const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor = @@ -10430,13 +10538,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_31_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1145] + (const void *)&gInstructions[1147] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_7b_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1171] + (const void *)&gInstructions[1173] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_7b_cyrix_modrmmod = @@ -10464,19 +10572,19 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7b_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_aa_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1172] + (const void *)&gInstructions[1174] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1173] + (const void *)&gInstructions[1175] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1174] + (const void *)&gInstructions[1176] }; const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix = @@ -10493,133 +10601,133 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1215] + (const void *)&gInstructions[1218] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_92_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1216] + (const void *)&gInstructions[1219] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1217] + (const void *)&gInstructions[1220] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1218] + (const void *)&gInstructions[1221] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1219] + (const void *)&gInstructions[1222] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_93_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1220] + (const void *)&gInstructions[1223] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1221] + (const void *)&gInstructions[1224] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1222] + (const void *)&gInstructions[1225] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_91_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1223] + (const void *)&gInstructions[1226] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1224] + (const void *)&gInstructions[1227] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_99_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1225] + (const void *)&gInstructions[1228] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1226] + (const void *)&gInstructions[1229] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_90_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1227] + (const void *)&gInstructions[1230] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1228] + (const void *)&gInstructions[1231] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_98_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1229] + (const void *)&gInstructions[1232] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1231] + (const void *)&gInstructions[1234] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1247] + (const void *)&gInstructions[1250] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1248] + (const void *)&gInstructions[1251] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ac_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1256] + (const void *)&gInstructions[1259] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ad_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1257] + (const void *)&gInstructions[1260] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1259] + (const void *)&gInstructions[1262] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1260] + (const void *)&gInstructions[1263] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix = @@ -10636,25 +10744,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1270] + (const void *)&gInstructions[1273] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1271] + (const void *)&gInstructions[1274] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1272] + (const void *)&gInstructions[1275] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1273] + (const void *)&gInstructions[1276] }; const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix = @@ -10671,25 +10779,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1301] + (const void *)&gInstructions[1305] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1302] + (const void *)&gInstructions[1306] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1303] + (const void *)&gInstructions[1307] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1304] + (const void *)&gInstructions[1308] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix = @@ -10706,7 +10814,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7a_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1306] + (const void *)&gInstructions[1310] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_7a_cyrix_modrmmod = @@ -10734,37 +10842,37 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7a_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1309] + (const void *)&gInstructions[1313] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_34_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1310] + (const void *)&gInstructions[1314] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_35_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1311] + (const void *)&gInstructions[1315] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1312] + (const void *)&gInstructions[1316] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1337] + (const void *)&gInstructions[1342] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1338] + (const void *)&gInstructions[1343] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix = @@ -10781,31 +10889,31 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ff_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1339] + (const void *)&gInstructions[1344] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_b9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1340] + (const void *)&gInstructions[1345] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1341] + (const void *)&gInstructions[1346] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1344] + (const void *)&gInstructions[1350] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1345] + (const void *)&gInstructions[1351] }; const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix = @@ -10822,13 +10930,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1346] + (const void *)&gInstructions[1352] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1347] + (const void *)&gInstructions[1353] }; const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix = @@ -10845,13 +10953,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2512] + (const void *)&gInstructions[2522] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2513] + (const void *)&gInstructions[2523] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary = @@ -10870,25 +10978,25 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_30_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2516] + (const void *)&gInstructions[2526] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2524] + (const void *)&gInstructions[2534] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2525] + (const void *)&gInstructions[2535] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_02_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2537] + (const void *)&gInstructions[2547] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_02_00_mprefix = @@ -10920,7 +11028,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_02_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_04_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2538] + (const void *)&gInstructions[2548] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_04_00_mprefix = @@ -10952,7 +11060,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_04_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_03_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2539] + (const void *)&gInstructions[2549] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_03_00_mprefix = @@ -10984,7 +11092,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_03_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_01_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2540] + (const void *)&gInstructions[2550] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_01_00_mprefix = @@ -11016,7 +11124,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_01_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_05_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2541] + (const void *)&gInstructions[2551] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_05_00_mprefix = @@ -11048,7 +11156,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_05_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2573] + (const void *)&gInstructions[2583] }; const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_00_modrmrm = @@ -11093,13 +11201,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2555] + (const void *)&gInstructions[2565] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2556] + (const void *)&gInstructions[2566] }; const ND_TABLE_MPREFIX gRootTable_root_0f_57_mprefix = @@ -11457,7 +11565,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_63_None_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_63_64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[713] + (const void *)&gInstructions[715] }; const ND_TABLE_AUXILIARY gRootTable_root_63_auxiliary = @@ -11509,31 +11617,31 @@ const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_03_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[217] + (const void *)&gInstructions[218] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[423] + (const void *)&gInstructions[425] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[462] + (const void *)&gInstructions[464] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[466] + (const void *)&gInstructions[468] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1108] + (const void *)&gInstructions[1110] }; const ND_TABLE_MODRM_REG gRootTable_root_ff_mem_modrmreg = @@ -11560,25 +11668,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_02_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[217] + (const void *)&gInstructions[218] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[423] + (const void *)&gInstructions[425] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[462] + (const void *)&gInstructions[464] }; const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1108] + (const void *)&gInstructions[1110] }; const ND_TABLE_MODRM_REG gRootTable_root_ff_reg_modrmreg = @@ -11626,7 +11734,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_98_ds64_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_98_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[205] + (const void *)&gInstructions[206] }; const ND_TABLE_DSIZE gRootTable_root_98_dsize = @@ -11651,13 +11759,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_99_ds32_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_99_ds64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[177] + (const void *)&gInstructions[178] }; const ND_TABLE_INSTRUCTION gRootTable_root_99_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[204] + (const void *)&gInstructions[205] }; const ND_TABLE_DSIZE gRootTable_root_99_dsize = @@ -11694,55 +11802,55 @@ const ND_TABLE_INSTRUCTION gRootTable_root_fa_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_f5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[129] + (const void *)&gInstructions[130] }; const ND_TABLE_INSTRUCTION gRootTable_root_38_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[146] + (const void *)&gInstructions[147] }; const ND_TABLE_INSTRUCTION gRootTable_root_39_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[147] + (const void *)&gInstructions[148] }; const ND_TABLE_INSTRUCTION gRootTable_root_3a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[148] + (const void *)&gInstructions[149] }; const ND_TABLE_INSTRUCTION gRootTable_root_3b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[149] + (const void *)&gInstructions[150] }; const ND_TABLE_INSTRUCTION gRootTable_root_3c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[150] + (const void *)&gInstructions[151] }; const ND_TABLE_INSTRUCTION gRootTable_root_3d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[151] + (const void *)&gInstructions[152] }; const ND_TABLE_INSTRUCTION gRootTable_root_a6_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[158] + (const void *)&gInstructions[159] }; const ND_TABLE_INSTRUCTION gRootTable_root_a6_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[159] + (const void *)&gInstructions[160] }; const ND_TABLE_AUXILIARY gRootTable_root_a6_auxiliary = @@ -11761,13 +11869,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a6_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds32_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[161] + (const void *)&gInstructions[162] }; const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds32_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[162] + (const void *)&gInstructions[163] }; const ND_TABLE_AUXILIARY gRootTable_root_a7_ds32_auxiliary = @@ -11786,13 +11894,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a7_ds32_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds64_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[163] + (const void *)&gInstructions[164] }; const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds64_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[164] + (const void *)&gInstructions[165] }; const ND_TABLE_AUXILIARY gRootTable_root_a7_ds64_auxiliary = @@ -11811,13 +11919,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a7_ds64_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[166] + (const void *)&gInstructions[167] }; const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[167] + (const void *)&gInstructions[168] }; const ND_TABLE_AUXILIARY gRootTable_root_a7_ds16_auxiliary = @@ -11849,73 +11957,73 @@ const ND_TABLE_DSIZE gRootTable_root_a7_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_27_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[206] + (const void *)&gInstructions[207] }; const ND_TABLE_INSTRUCTION gRootTable_root_2f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[207] + (const void *)&gInstructions[208] }; const ND_TABLE_INSTRUCTION gRootTable_root_48_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[208] + (const void *)&gInstructions[209] }; const ND_TABLE_INSTRUCTION gRootTable_root_49_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[209] + (const void *)&gInstructions[210] }; const ND_TABLE_INSTRUCTION gRootTable_root_4a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[210] + (const void *)&gInstructions[211] }; const ND_TABLE_INSTRUCTION gRootTable_root_4b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[211] + (const void *)&gInstructions[212] }; const ND_TABLE_INSTRUCTION gRootTable_root_4c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[212] + (const void *)&gInstructions[213] }; const ND_TABLE_INSTRUCTION gRootTable_root_4d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[213] + (const void *)&gInstructions[214] }; const ND_TABLE_INSTRUCTION gRootTable_root_4e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[214] + (const void *)&gInstructions[215] }; const ND_TABLE_INSTRUCTION gRootTable_root_4f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[215] + (const void *)&gInstructions[216] }; const ND_TABLE_INSTRUCTION gRootTable_root_fe_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[216] + (const void *)&gInstructions[217] }; const ND_TABLE_INSTRUCTION gRootTable_root_fe_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[422] + (const void *)&gInstructions[424] }; const ND_TABLE_MODRM_REG gRootTable_root_fe_modrmreg = @@ -11936,49 +12044,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_fe_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_f6_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[219] + (const void *)&gInstructions[220] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[403] + (const void *)&gInstructions[405] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[408] + (const void *)&gInstructions[410] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[721] + (const void *)&gInstructions[723] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[730] + (const void *)&gInstructions[732] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[787] + (const void *)&gInstructions[789] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1324] + (const void *)&gInstructions[1328] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1325] + (const void *)&gInstructions[1329] }; const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg = @@ -11999,49 +12107,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_f7_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[220] + (const void *)&gInstructions[221] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[404] + (const void *)&gInstructions[406] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[409] + (const void *)&gInstructions[411] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[722] + (const void *)&gInstructions[724] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[731] + (const void *)&gInstructions[733] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[788] + (const void *)&gInstructions[790] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1326] + (const void *)&gInstructions[1330] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1327] + (const void *)&gInstructions[1331] }; const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg = @@ -12062,55 +12170,55 @@ const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_c8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[238] + (const void *)&gInstructions[239] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[242] + (const void *)&gInstructions[243] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[273] + (const void *)&gInstructions[274] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[302] + (const void *)&gInstructions[303] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[344] + (const void *)&gInstructions[345] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[346] + (const void *)&gInstructions[347] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[347] + (const void *)&gInstructions[348] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[391] + (const void *)&gInstructions[392] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[392] + (const void *)&gInstructions[393] }; const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_06_modrmrm = @@ -12131,25 +12239,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_06_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[243] + (const void *)&gInstructions[244] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[251] + (const void *)&gInstructions[252] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[377] + (const void *)&gInstructions[378] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[383] + (const void *)&gInstructions[384] }; const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_04_modrmrm = @@ -12170,49 +12278,49 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_04_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[272] + (const void *)&gInstructions[273] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[345] + (const void *)&gInstructions[346] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[349] + (const void *)&gInstructions[350] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[351] + (const void *)&gInstructions[352] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[352] + (const void *)&gInstructions[353] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[353] + (const void *)&gInstructions[354] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[354] + (const void *)&gInstructions[355] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[393] + (const void *)&gInstructions[394] }; const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_07_modrmrm = @@ -12233,49 +12341,49 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_07_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[316] + (const void *)&gInstructions[317] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[319] + (const void *)&gInstructions[320] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[322] + (const void *)&gInstructions[323] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[323] + (const void *)&gInstructions[324] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[324] + (const void *)&gInstructions[325] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[325] + (const void *)&gInstructions[326] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[326] + (const void *)&gInstructions[327] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[327] + (const void *)&gInstructions[328] }; const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_05_modrmrm = @@ -12296,7 +12404,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_05_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[336] + (const void *)&gInstructions[337] }; const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_02_modrmrm = @@ -12317,13 +12425,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_02_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[365] + (const void *)&gInstructions[366] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[384] + (const void *)&gInstructions[385] }; const ND_TABLE_MODRM_REG gRootTable_root_d9_reg_modrmreg = @@ -12344,43 +12452,43 @@ const ND_TABLE_MODRM_REG gRootTable_root_d9_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[315] + (const void *)&gInstructions[316] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[320] + (const void *)&gInstructions[321] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[321] + (const void *)&gInstructions[322] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[340] + (const void *)&gInstructions[341] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[341] + (const void *)&gInstructions[342] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[355] + (const void *)&gInstructions[356] }; const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[359] + (const void *)&gInstructions[360] }; const ND_TABLE_MODRM_REG gRootTable_root_d9_mem_modrmreg = @@ -12410,49 +12518,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_d9_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[244] + (const void *)&gInstructions[245] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[260] + (const void *)&gInstructions[261] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[266] + (const void *)&gInstructions[267] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[274] + (const void *)&gInstructions[275] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[279] + (const void *)&gInstructions[280] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[328] + (const void *)&gInstructions[329] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[367] + (const void *)&gInstructions[368] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[372] + (const void *)&gInstructions[373] }; const ND_TABLE_MODRM_REG gRootTable_root_d8_mem_modrmreg = @@ -12473,49 +12581,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d8_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[245] + (const void *)&gInstructions[246] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[261] + (const void *)&gInstructions[262] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[267] + (const void *)&gInstructions[268] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[275] + (const void *)&gInstructions[276] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[280] + (const void *)&gInstructions[281] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[329] + (const void *)&gInstructions[330] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[368] + (const void *)&gInstructions[369] }; const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[373] + (const void *)&gInstructions[374] }; const ND_TABLE_MODRM_REG gRootTable_root_d8_reg_modrmreg = @@ -12545,49 +12653,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_d8_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[246] + (const void *)&gInstructions[247] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[262] + (const void *)&gInstructions[263] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[268] + (const void *)&gInstructions[269] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[276] + (const void *)&gInstructions[277] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[281] + (const void *)&gInstructions[282] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[330] + (const void *)&gInstructions[331] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[369] + (const void *)&gInstructions[370] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[374] + (const void *)&gInstructions[375] }; const ND_TABLE_MODRM_REG gRootTable_root_dc_mem_modrmreg = @@ -12608,49 +12716,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_dc_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[247] + (const void *)&gInstructions[248] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[263] + (const void *)&gInstructions[264] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[269] + (const void *)&gInstructions[270] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[277] + (const void *)&gInstructions[278] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[282] + (const void *)&gInstructions[283] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[331] + (const void *)&gInstructions[332] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[370] + (const void *)&gInstructions[371] }; const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[375] + (const void *)&gInstructions[376] }; const ND_TABLE_MODRM_REG gRootTable_root_dc_reg_modrmreg = @@ -12680,19 +12788,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_dc_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[248] + (const void *)&gInstructions[249] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[270] + (const void *)&gInstructions[271] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[271] + (const void *)&gInstructions[272] }; const ND_TABLE_MODRM_RM gRootTable_root_de_reg_03_modrmrm = @@ -12713,31 +12821,31 @@ const ND_TABLE_MODRM_RM gRootTable_root_de_reg_03_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[278] + (const void *)&gInstructions[279] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[283] + (const void *)&gInstructions[284] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[332] + (const void *)&gInstructions[333] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[371] + (const void *)&gInstructions[372] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[376] + (const void *)&gInstructions[377] }; const ND_TABLE_MODRM_REG gRootTable_root_de_reg_modrmreg = @@ -12758,49 +12866,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_de_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[288] + (const void *)&gInstructions[289] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[290] + (const void *)&gInstructions[291] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[292] + (const void *)&gInstructions[293] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[294] + (const void *)&gInstructions[295] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[296] + (const void *)&gInstructions[297] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[301] + (const void *)&gInstructions[302] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[312] + (const void *)&gInstructions[313] }; const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[314] + (const void *)&gInstructions[315] }; const ND_TABLE_MODRM_REG gRootTable_root_de_mem_modrmreg = @@ -12830,49 +12938,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_de_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[249] + (const void *)&gInstructions[250] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[250] + (const void *)&gInstructions[251] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[298] + (const void *)&gInstructions[299] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[299] + (const void *)&gInstructions[300] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[304] + (const void *)&gInstructions[305] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[306] + (const void *)&gInstructions[307] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[307] + (const void *)&gInstructions[308] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[310] + (const void *)&gInstructions[311] }; const ND_TABLE_MODRM_REG gRootTable_root_df_mem_modrmreg = @@ -12893,31 +13001,31 @@ const ND_TABLE_MODRM_REG gRootTable_root_df_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[265] + (const void *)&gInstructions[266] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[286] + (const void *)&gInstructions[287] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[343] + (const void *)&gInstructions[344] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[358] + (const void *)&gInstructions[359] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[366] + (const void *)&gInstructions[367] }; const ND_TABLE_MODRM_RM gRootTable_root_df_reg_04_modrmrm = @@ -12938,7 +13046,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_df_reg_04_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_07_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[348] + (const void *)&gInstructions[349] }; const ND_TABLE_MODRM_RM gRootTable_root_df_reg_07_modrmrm = @@ -12959,25 +13067,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_df_reg_07_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[363] + (const void *)&gInstructions[364] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[364] + (const void *)&gInstructions[365] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[380] + (const void *)&gInstructions[381] }; const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[386] + (const void *)&gInstructions[387] }; const ND_TABLE_MODRM_REG gRootTable_root_df_reg_modrmreg = @@ -13007,31 +13115,31 @@ const ND_TABLE_MODRM_MOD gRootTable_root_df_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[252] + (const void *)&gInstructions[253] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[253] + (const void *)&gInstructions[254] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[254] + (const void *)&gInstructions[255] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[259] + (const void *)&gInstructions[260] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_05_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[382] + (const void *)&gInstructions[383] }; const ND_TABLE_MODRM_RM gRootTable_root_da_reg_05_modrmrm = @@ -13067,49 +13175,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_da_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[287] + (const void *)&gInstructions[288] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[289] + (const void *)&gInstructions[290] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[291] + (const void *)&gInstructions[292] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[293] + (const void *)&gInstructions[294] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[295] + (const void *)&gInstructions[296] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[300] + (const void *)&gInstructions[301] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[311] + (const void *)&gInstructions[312] }; const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[313] + (const void *)&gInstructions[314] }; const ND_TABLE_MODRM_REG gRootTable_root_da_mem_modrmreg = @@ -13139,61 +13247,61 @@ const ND_TABLE_MODRM_MOD gRootTable_root_da_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[255] + (const void *)&gInstructions[256] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[256] + (const void *)&gInstructions[257] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[257] + (const void *)&gInstructions[258] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[258] + (const void *)&gInstructions[259] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[264] + (const void *)&gInstructions[265] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[333] + (const void *)&gInstructions[334] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[334] + (const void *)&gInstructions[335] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[335] + (const void *)&gInstructions[336] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[337] + (const void *)&gInstructions[338] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[338] + (const void *)&gInstructions[339] }; const ND_TABLE_MODRM_RM gRootTable_root_db_reg_04_modrmrm = @@ -13214,7 +13322,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_db_reg_04_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[379] + (const void *)&gInstructions[380] }; const ND_TABLE_MODRM_REG gRootTable_root_db_reg_modrmreg = @@ -13235,37 +13343,37 @@ const ND_TABLE_MODRM_REG gRootTable_root_db_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[297] + (const void *)&gInstructions[298] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[303] + (const void *)&gInstructions[304] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[305] + (const void *)&gInstructions[306] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[308] + (const void *)&gInstructions[309] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[317] + (const void *)&gInstructions[318] }; const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[360] + (const void *)&gInstructions[361] }; const ND_TABLE_MODRM_REG gRootTable_root_db_mem_modrmreg = @@ -13295,37 +13403,37 @@ const ND_TABLE_MODRM_MOD gRootTable_root_db_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[285] + (const void *)&gInstructions[286] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[357] + (const void *)&gInstructions[358] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[362] + (const void *)&gInstructions[363] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[378] + (const void *)&gInstructions[379] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[381] + (const void *)&gInstructions[382] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[385] + (const void *)&gInstructions[386] }; const ND_TABLE_MODRM_REG gRootTable_root_dd_reg_modrmreg = @@ -13346,43 +13454,43 @@ const ND_TABLE_MODRM_REG gRootTable_root_dd_reg_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[309] + (const void *)&gInstructions[310] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[318] + (const void *)&gInstructions[319] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[339] + (const void *)&gInstructions[340] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[342] + (const void *)&gInstructions[343] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[350] + (const void *)&gInstructions[351] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[356] + (const void *)&gInstructions[357] }; const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[361] + (const void *)&gInstructions[362] }; const ND_TABLE_MODRM_REG gRootTable_root_dd_mem_modrmreg = @@ -13412,103 +13520,103 @@ const ND_TABLE_MODRM_MOD gRootTable_root_dd_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_f4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[400] + (const void *)&gInstructions[401] }; const ND_TABLE_INSTRUCTION gRootTable_root_69_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[406] + (const void *)&gInstructions[408] }; const ND_TABLE_INSTRUCTION gRootTable_root_6b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[407] + (const void *)&gInstructions[409] }; const ND_TABLE_INSTRUCTION gRootTable_root_e4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[410] + (const void *)&gInstructions[412] }; const ND_TABLE_INSTRUCTION gRootTable_root_e5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[411] + (const void *)&gInstructions[413] }; const ND_TABLE_INSTRUCTION gRootTable_root_ec_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[412] + (const void *)&gInstructions[414] }; const ND_TABLE_INSTRUCTION gRootTable_root_ed_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[413] + (const void *)&gInstructions[415] }; const ND_TABLE_INSTRUCTION gRootTable_root_40_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[414] + (const void *)&gInstructions[416] }; const ND_TABLE_INSTRUCTION gRootTable_root_41_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[415] + (const void *)&gInstructions[417] }; const ND_TABLE_INSTRUCTION gRootTable_root_42_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[416] + (const void *)&gInstructions[418] }; const ND_TABLE_INSTRUCTION gRootTable_root_43_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[417] + (const void *)&gInstructions[419] }; const ND_TABLE_INSTRUCTION gRootTable_root_44_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[418] + (const void *)&gInstructions[420] }; const ND_TABLE_INSTRUCTION gRootTable_root_45_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[419] + (const void *)&gInstructions[421] }; const ND_TABLE_INSTRUCTION gRootTable_root_46_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[420] + (const void *)&gInstructions[422] }; const ND_TABLE_INSTRUCTION gRootTable_root_47_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[421] + (const void *)&gInstructions[423] }; const ND_TABLE_INSTRUCTION gRootTable_root_6c_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[426] + (const void *)&gInstructions[428] }; const ND_TABLE_INSTRUCTION gRootTable_root_6c_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[427] + (const void *)&gInstructions[429] }; const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary = @@ -13527,13 +13635,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[428] + (const void *)&gInstructions[430] }; const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[429] + (const void *)&gInstructions[431] }; const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary = @@ -13552,13 +13660,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[434] + (const void *)&gInstructions[436] }; const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[435] + (const void *)&gInstructions[437] }; const ND_TABLE_AUXILIARY gRootTable_root_6d_ds16_auxiliary = @@ -13590,43 +13698,43 @@ const ND_TABLE_DSIZE gRootTable_root_6d_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_cd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[436] + (const void *)&gInstructions[438] }; const ND_TABLE_INSTRUCTION gRootTable_root_f1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[437] + (const void *)&gInstructions[439] }; const ND_TABLE_INSTRUCTION gRootTable_root_cc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[438] + (const void *)&gInstructions[440] }; const ND_TABLE_INSTRUCTION gRootTable_root_ce_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[439] + (const void *)&gInstructions[441] }; const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[447] + (const void *)&gInstructions[449] }; const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[448] + (const void *)&gInstructions[450] }; const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[449] + (const void *)&gInstructions[451] }; const ND_TABLE_DSIZE gRootTable_root_cf_dsize = @@ -13645,31 +13753,31 @@ const ND_TABLE_DSIZE gRootTable_root_cf_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_76_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[451] + (const void *)&gInstructions[453] }; const ND_TABLE_INSTRUCTION gRootTable_root_72_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[453] + (const void *)&gInstructions[455] }; const ND_TABLE_INSTRUCTION gRootTable_root_e3_as16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[454] + (const void *)&gInstructions[456] }; const ND_TABLE_INSTRUCTION gRootTable_root_e3_as32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[455] + (const void *)&gInstructions[457] }; const ND_TABLE_INSTRUCTION gRootTable_root_e3_as64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[487] + (const void *)&gInstructions[489] }; const ND_TABLE_ASIZE gRootTable_root_e3_asize = @@ -13686,115 +13794,115 @@ const ND_TABLE_ASIZE gRootTable_root_e3_asize = const ND_TABLE_INSTRUCTION gRootTable_root_7c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[457] + (const void *)&gInstructions[459] }; const ND_TABLE_INSTRUCTION gRootTable_root_7e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[459] + (const void *)&gInstructions[461] }; const ND_TABLE_INSTRUCTION gRootTable_root_e9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[460] + (const void *)&gInstructions[462] }; const ND_TABLE_INSTRUCTION gRootTable_root_eb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[461] + (const void *)&gInstructions[463] }; const ND_TABLE_INSTRUCTION gRootTable_root_ea_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[465] + (const void *)&gInstructions[467] }; const ND_TABLE_INSTRUCTION gRootTable_root_77_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[468] + (const void *)&gInstructions[470] }; const ND_TABLE_INSTRUCTION gRootTable_root_73_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[470] + (const void *)&gInstructions[472] }; const ND_TABLE_INSTRUCTION gRootTable_root_7d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[472] + (const void *)&gInstructions[474] }; const ND_TABLE_INSTRUCTION gRootTable_root_7f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[474] + (const void *)&gInstructions[476] }; const ND_TABLE_INSTRUCTION gRootTable_root_71_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[476] + (const void *)&gInstructions[478] }; const ND_TABLE_INSTRUCTION gRootTable_root_7b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[478] + (const void *)&gInstructions[480] }; const ND_TABLE_INSTRUCTION gRootTable_root_79_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[480] + (const void *)&gInstructions[482] }; const ND_TABLE_INSTRUCTION gRootTable_root_75_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[482] + (const void *)&gInstructions[484] }; const ND_TABLE_INSTRUCTION gRootTable_root_70_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[484] + (const void *)&gInstructions[486] }; const ND_TABLE_INSTRUCTION gRootTable_root_7a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[486] + (const void *)&gInstructions[488] }; const ND_TABLE_INSTRUCTION gRootTable_root_78_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[489] + (const void *)&gInstructions[491] }; const ND_TABLE_INSTRUCTION gRootTable_root_74_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[491] + (const void *)&gInstructions[493] }; const ND_TABLE_INSTRUCTION gRootTable_root_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[561] + (const void *)&gInstructions[563] }; const ND_TABLE_INSTRUCTION gRootTable_root_c5_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[566] + (const void *)&gInstructions[568] }; const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod = @@ -13809,7 +13917,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_8d_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[568] + (const void *)&gInstructions[570] }; const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod = @@ -13824,13 +13932,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_c9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[569] + (const void *)&gInstructions[571] }; const ND_TABLE_INSTRUCTION gRootTable_root_c4_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[570] + (const void *)&gInstructions[572] }; const ND_TABLE_MODRM_MOD gRootTable_root_c4_modrmmod = @@ -13845,13 +13953,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c4_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_ac_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[580] + (const void *)&gInstructions[582] }; const ND_TABLE_INSTRUCTION gRootTable_root_ac_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[581] + (const void *)&gInstructions[583] }; const ND_TABLE_AUXILIARY gRootTable_root_ac_auxiliary = @@ -13870,13 +13978,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ac_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds32_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[582] + (const void *)&gInstructions[584] }; const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds32_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[583] + (const void *)&gInstructions[585] }; const ND_TABLE_AUXILIARY gRootTable_root_ad_ds32_auxiliary = @@ -13895,13 +14003,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ad_ds32_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds64_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[584] + (const void *)&gInstructions[586] }; const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds64_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[585] + (const void *)&gInstructions[587] }; const ND_TABLE_AUXILIARY gRootTable_root_ad_ds64_auxiliary = @@ -13920,13 +14028,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ad_ds64_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[586] + (const void *)&gInstructions[588] }; const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[587] + (const void *)&gInstructions[589] }; const ND_TABLE_AUXILIARY gRootTable_root_ad_ds16_auxiliary = @@ -13958,55 +14066,55 @@ const ND_TABLE_DSIZE gRootTable_root_ad_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_e2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[588] + (const void *)&gInstructions[590] }; const ND_TABLE_INSTRUCTION gRootTable_root_e0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[589] + (const void *)&gInstructions[591] }; const ND_TABLE_INSTRUCTION gRootTable_root_e1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[590] + (const void *)&gInstructions[592] }; const ND_TABLE_INSTRUCTION gRootTable_root_88_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[619] + (const void *)&gInstructions[621] }; const ND_TABLE_INSTRUCTION gRootTable_root_89_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[620] + (const void *)&gInstructions[622] }; const ND_TABLE_INSTRUCTION gRootTable_root_8a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[621] + (const void *)&gInstructions[623] }; const ND_TABLE_INSTRUCTION gRootTable_root_8b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[622] + (const void *)&gInstructions[624] }; const ND_TABLE_INSTRUCTION gRootTable_root_8c_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[623] + (const void *)&gInstructions[625] }; const ND_TABLE_INSTRUCTION gRootTable_root_8c_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[624] + (const void *)&gInstructions[626] }; const ND_TABLE_MODRM_MOD gRootTable_root_8c_modrmmod = @@ -14021,13 +14129,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8c_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_8e_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[625] + (const void *)&gInstructions[627] }; const ND_TABLE_INSTRUCTION gRootTable_root_8e_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[626] + (const void *)&gInstructions[628] }; const ND_TABLE_MODRM_MOD gRootTable_root_8e_modrmmod = @@ -14042,127 +14150,127 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8e_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_a0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[627] + (const void *)&gInstructions[629] }; const ND_TABLE_INSTRUCTION gRootTable_root_a1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[628] + (const void *)&gInstructions[630] }; const ND_TABLE_INSTRUCTION gRootTable_root_a2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[629] + (const void *)&gInstructions[631] }; const ND_TABLE_INSTRUCTION gRootTable_root_a3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[630] + (const void *)&gInstructions[632] }; const ND_TABLE_INSTRUCTION gRootTable_root_b0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[631] + (const void *)&gInstructions[633] }; const ND_TABLE_INSTRUCTION gRootTable_root_b1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[632] + (const void *)&gInstructions[634] }; const ND_TABLE_INSTRUCTION gRootTable_root_b2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[633] + (const void *)&gInstructions[635] }; const ND_TABLE_INSTRUCTION gRootTable_root_b3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[634] + (const void *)&gInstructions[636] }; const ND_TABLE_INSTRUCTION gRootTable_root_b4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[635] + (const void *)&gInstructions[637] }; const ND_TABLE_INSTRUCTION gRootTable_root_b5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[636] + (const void *)&gInstructions[638] }; const ND_TABLE_INSTRUCTION gRootTable_root_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[637] + (const void *)&gInstructions[639] }; const ND_TABLE_INSTRUCTION gRootTable_root_b7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[638] + (const void *)&gInstructions[640] }; const ND_TABLE_INSTRUCTION gRootTable_root_b8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[639] + (const void *)&gInstructions[641] }; const ND_TABLE_INSTRUCTION gRootTable_root_b9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[640] + (const void *)&gInstructions[642] }; const ND_TABLE_INSTRUCTION gRootTable_root_ba_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[641] + (const void *)&gInstructions[643] }; const ND_TABLE_INSTRUCTION gRootTable_root_bb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[642] + (const void *)&gInstructions[644] }; const ND_TABLE_INSTRUCTION gRootTable_root_bc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[643] + (const void *)&gInstructions[645] }; const ND_TABLE_INSTRUCTION gRootTable_root_bd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[644] + (const void *)&gInstructions[646] }; const ND_TABLE_INSTRUCTION gRootTable_root_be_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[645] + (const void *)&gInstructions[647] }; const ND_TABLE_INSTRUCTION gRootTable_root_bf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[646] + (const void *)&gInstructions[648] }; const ND_TABLE_INSTRUCTION gRootTable_root_c6_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[647] + (const void *)&gInstructions[649] }; const ND_TABLE_MODRM_REG gRootTable_root_c6_mem_modrmreg = @@ -14183,13 +14291,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_c6_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[647] + (const void *)&gInstructions[649] }; const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2523] + (const void *)&gInstructions[2533] }; const ND_TABLE_MODRM_RM gRootTable_root_c6_reg_07_modrmrm = @@ -14234,7 +14342,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c6_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_c7_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[648] + (const void *)&gInstructions[650] }; const ND_TABLE_MODRM_REG gRootTable_root_c7_mem_modrmreg = @@ -14255,13 +14363,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_c7_mem_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[648] + (const void *)&gInstructions[650] }; const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2526] + (const void *)&gInstructions[2536] }; const ND_TABLE_MODRM_RM gRootTable_root_c7_reg_07_modrmrm = @@ -14306,13 +14414,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_a4_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[697] + (const void *)&gInstructions[699] }; const ND_TABLE_INSTRUCTION gRootTable_root_a4_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[698] + (const void *)&gInstructions[700] }; const ND_TABLE_AUXILIARY gRootTable_root_a4_auxiliary = @@ -14331,13 +14439,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a4_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds32_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[701] + (const void *)&gInstructions[703] }; const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds32_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[702] + (const void *)&gInstructions[704] }; const ND_TABLE_AUXILIARY gRootTable_root_a5_ds32_auxiliary = @@ -14356,13 +14464,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a5_ds32_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds64_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[705] + (const void *)&gInstructions[707] }; const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds64_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[706] + (const void *)&gInstructions[708] }; const ND_TABLE_AUXILIARY gRootTable_root_a5_ds64_auxiliary = @@ -14381,13 +14489,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a5_ds64_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[709] + (const void *)&gInstructions[711] }; const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[710] + (const void *)&gInstructions[712] }; const ND_TABLE_AUXILIARY gRootTable_root_a5_ds16_auxiliary = @@ -14419,19 +14527,19 @@ const ND_TABLE_DSIZE gRootTable_root_a5_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_90_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[786] + (const void *)&gInstructions[788] }; const ND_TABLE_INSTRUCTION gRootTable_root_90_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[846] + (const void *)&gInstructions[848] }; const ND_TABLE_INSTRUCTION gRootTable_root_90_rex_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2529] + (const void *)&gInstructions[2539] }; const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary = @@ -14450,73 +14558,73 @@ const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[789] + (const void *)&gInstructions[791] }; const ND_TABLE_INSTRUCTION gRootTable_root_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[790] + (const void *)&gInstructions[792] }; const ND_TABLE_INSTRUCTION gRootTable_root_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[791] + (const void *)&gInstructions[793] }; const ND_TABLE_INSTRUCTION gRootTable_root_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[792] + (const void *)&gInstructions[794] }; const ND_TABLE_INSTRUCTION gRootTable_root_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[793] + (const void *)&gInstructions[795] }; const ND_TABLE_INSTRUCTION gRootTable_root_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[794] + (const void *)&gInstructions[796] }; const ND_TABLE_INSTRUCTION gRootTable_root_e6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[801] + (const void *)&gInstructions[803] }; const ND_TABLE_INSTRUCTION gRootTable_root_e7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[802] + (const void *)&gInstructions[804] }; const ND_TABLE_INSTRUCTION gRootTable_root_ee_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[803] + (const void *)&gInstructions[805] }; const ND_TABLE_INSTRUCTION gRootTable_root_ef_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[804] + (const void *)&gInstructions[806] }; const ND_TABLE_INSTRUCTION gRootTable_root_6e_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[805] + (const void *)&gInstructions[807] }; const ND_TABLE_INSTRUCTION gRootTable_root_6e_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[806] + (const void *)&gInstructions[808] }; const ND_TABLE_AUXILIARY gRootTable_root_6e_auxiliary = @@ -14535,13 +14643,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6e_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_6f_None_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[807] + (const void *)&gInstructions[809] }; const ND_TABLE_INSTRUCTION gRootTable_root_6f_None_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[808] + (const void *)&gInstructions[810] }; const ND_TABLE_AUXILIARY gRootTable_root_6f_None_auxiliary = @@ -14560,13 +14668,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6f_None_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_6f_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[809] + (const void *)&gInstructions[811] }; const ND_TABLE_INSTRUCTION gRootTable_root_6f_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[810] + (const void *)&gInstructions[812] }; const ND_TABLE_AUXILIARY gRootTable_root_6f_ds16_auxiliary = @@ -14598,73 +14706,73 @@ const ND_TABLE_DSIZE gRootTable_root_6f_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[978] + (const void *)&gInstructions[980] }; const ND_TABLE_INSTRUCTION gRootTable_root_17_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[979] + (const void *)&gInstructions[981] }; const ND_TABLE_INSTRUCTION gRootTable_root_1f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[980] + (const void *)&gInstructions[982] }; const ND_TABLE_INSTRUCTION gRootTable_root_58_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[981] + (const void *)&gInstructions[983] }; const ND_TABLE_INSTRUCTION gRootTable_root_59_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[982] + (const void *)&gInstructions[984] }; const ND_TABLE_INSTRUCTION gRootTable_root_5a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[983] + (const void *)&gInstructions[985] }; const ND_TABLE_INSTRUCTION gRootTable_root_5b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[984] + (const void *)&gInstructions[986] }; const ND_TABLE_INSTRUCTION gRootTable_root_5c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[985] + (const void *)&gInstructions[987] }; const ND_TABLE_INSTRUCTION gRootTable_root_5d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[986] + (const void *)&gInstructions[988] }; const ND_TABLE_INSTRUCTION gRootTable_root_5e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[987] + (const void *)&gInstructions[989] }; const ND_TABLE_INSTRUCTION gRootTable_root_5f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[988] + (const void *)&gInstructions[990] }; const ND_TABLE_INSTRUCTION gRootTable_root_8f_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[989] + (const void *)&gInstructions[991] }; const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg = @@ -14685,13 +14793,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_61_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[990] + (const void *)&gInstructions[992] }; const ND_TABLE_INSTRUCTION gRootTable_root_61_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[991] + (const void *)&gInstructions[993] }; const ND_TABLE_DSIZE gRootTable_root_61_dsize = @@ -14710,19 +14818,19 @@ const ND_TABLE_DSIZE gRootTable_root_61_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[993] + (const void *)&gInstructions[995] }; const ND_TABLE_INSTRUCTION gRootTable_root_9d_dds64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[994] + (const void *)&gInstructions[996] }; const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[995] + (const void *)&gInstructions[997] }; const ND_TABLE_DSIZE gRootTable_root_9d_dsize = @@ -14741,97 +14849,97 @@ const ND_TABLE_DSIZE gRootTable_root_9d_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1094] + (const void *)&gInstructions[1096] }; const ND_TABLE_INSTRUCTION gRootTable_root_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1095] + (const void *)&gInstructions[1097] }; const ND_TABLE_INSTRUCTION gRootTable_root_16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1096] + (const void *)&gInstructions[1098] }; const ND_TABLE_INSTRUCTION gRootTable_root_1e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1097] + (const void *)&gInstructions[1099] }; const ND_TABLE_INSTRUCTION gRootTable_root_50_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1098] + (const void *)&gInstructions[1100] }; const ND_TABLE_INSTRUCTION gRootTable_root_51_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1099] + (const void *)&gInstructions[1101] }; const ND_TABLE_INSTRUCTION gRootTable_root_52_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1100] + (const void *)&gInstructions[1102] }; const ND_TABLE_INSTRUCTION gRootTable_root_53_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1101] + (const void *)&gInstructions[1103] }; const ND_TABLE_INSTRUCTION gRootTable_root_54_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1102] + (const void *)&gInstructions[1104] }; const ND_TABLE_INSTRUCTION gRootTable_root_55_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1103] + (const void *)&gInstructions[1105] }; const ND_TABLE_INSTRUCTION gRootTable_root_56_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1104] + (const void *)&gInstructions[1106] }; const ND_TABLE_INSTRUCTION gRootTable_root_57_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1105] + (const void *)&gInstructions[1107] }; const ND_TABLE_INSTRUCTION gRootTable_root_68_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1106] + (const void *)&gInstructions[1108] }; const ND_TABLE_INSTRUCTION gRootTable_root_6a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1107] + (const void *)&gInstructions[1109] }; const ND_TABLE_INSTRUCTION gRootTable_root_60_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1109] + (const void *)&gInstructions[1111] }; const ND_TABLE_INSTRUCTION gRootTable_root_60_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1110] + (const void *)&gInstructions[1112] }; const ND_TABLE_DSIZE gRootTable_root_60_dsize = @@ -14850,19 +14958,19 @@ const ND_TABLE_DSIZE gRootTable_root_60_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1111] + (const void *)&gInstructions[1113] }; const ND_TABLE_INSTRUCTION gRootTable_root_9c_dds64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1112] + (const void *)&gInstructions[1114] }; const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1113] + (const void *)&gInstructions[1115] }; const ND_TABLE_DSIZE gRootTable_root_9c_dsize = @@ -14881,49 +14989,49 @@ const ND_TABLE_DSIZE gRootTable_root_9c_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_c0_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1117] + (const void *)&gInstructions[1119] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1125] + (const void *)&gInstructions[1127] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1153] + (const void *)&gInstructions[1155] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1159] + (const void *)&gInstructions[1161] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1178] + (const void *)&gInstructions[1180] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1185] + (const void *)&gInstructions[1187] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1241] + (const void *)&gInstructions[1244] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1250] + (const void *)&gInstructions[1253] }; const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg = @@ -14944,49 +15052,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_c1_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1118] + (const void *)&gInstructions[1120] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1126] + (const void *)&gInstructions[1128] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1154] + (const void *)&gInstructions[1156] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1160] + (const void *)&gInstructions[1162] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1179] + (const void *)&gInstructions[1181] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1186] + (const void *)&gInstructions[1188] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1242] + (const void *)&gInstructions[1245] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1251] + (const void *)&gInstructions[1254] }; const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg = @@ -15007,49 +15115,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_d0_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1119] + (const void *)&gInstructions[1121] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1127] + (const void *)&gInstructions[1129] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1155] + (const void *)&gInstructions[1157] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1161] + (const void *)&gInstructions[1163] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1180] + (const void *)&gInstructions[1182] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1187] + (const void *)&gInstructions[1189] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1243] + (const void *)&gInstructions[1246] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1252] + (const void *)&gInstructions[1255] }; const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg = @@ -15070,49 +15178,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_d1_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1120] + (const void *)&gInstructions[1122] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1128] + (const void *)&gInstructions[1130] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1156] + (const void *)&gInstructions[1158] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1162] + (const void *)&gInstructions[1164] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1181] + (const void *)&gInstructions[1183] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1188] + (const void *)&gInstructions[1190] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1244] + (const void *)&gInstructions[1247] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1253] + (const void *)&gInstructions[1256] }; const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg = @@ -15133,49 +15241,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_d2_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1121] + (const void *)&gInstructions[1123] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1129] + (const void *)&gInstructions[1131] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1157] + (const void *)&gInstructions[1159] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1163] + (const void *)&gInstructions[1165] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1182] + (const void *)&gInstructions[1184] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1189] + (const void *)&gInstructions[1191] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1245] + (const void *)&gInstructions[1248] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1254] + (const void *)&gInstructions[1257] }; const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg = @@ -15196,49 +15304,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_d3_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1122] + (const void *)&gInstructions[1124] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1130] + (const void *)&gInstructions[1132] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1158] + (const void *)&gInstructions[1160] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1164] + (const void *)&gInstructions[1166] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1183] + (const void *)&gInstructions[1185] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1190] + (const void *)&gInstructions[1192] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1246] + (const void *)&gInstructions[1249] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1255] + (const void *)&gInstructions[1258] }; const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg = @@ -15259,85 +15367,85 @@ const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg = const ND_TABLE_INSTRUCTION gRootTable_root_ca_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1147] + (const void *)&gInstructions[1149] }; const ND_TABLE_INSTRUCTION gRootTable_root_cb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1148] + (const void *)&gInstructions[1150] }; const ND_TABLE_INSTRUCTION gRootTable_root_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1149] + (const void *)&gInstructions[1151] }; const ND_TABLE_INSTRUCTION gRootTable_root_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1150] + (const void *)&gInstructions[1152] }; const ND_TABLE_INSTRUCTION gRootTable_root_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1177] + (const void *)&gInstructions[1179] }; const ND_TABLE_INSTRUCTION gRootTable_root_d6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1184] + (const void *)&gInstructions[1186] }; const ND_TABLE_INSTRUCTION gRootTable_root_18_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1193] + (const void *)&gInstructions[1195] }; const ND_TABLE_INSTRUCTION gRootTable_root_19_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1194] + (const void *)&gInstructions[1196] }; const ND_TABLE_INSTRUCTION gRootTable_root_1a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1195] + (const void *)&gInstructions[1197] }; const ND_TABLE_INSTRUCTION gRootTable_root_1b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1196] + (const void *)&gInstructions[1198] }; const ND_TABLE_INSTRUCTION gRootTable_root_1c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1197] + (const void *)&gInstructions[1199] }; const ND_TABLE_INSTRUCTION gRootTable_root_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1198] + (const void *)&gInstructions[1200] }; const ND_TABLE_INSTRUCTION gRootTable_root_ae_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1203] + (const void *)&gInstructions[1205] }; const ND_TABLE_INSTRUCTION gRootTable_root_ae_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1204] + (const void *)&gInstructions[1206] }; const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary = @@ -15356,13 +15464,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1205] + (const void *)&gInstructions[1207] }; const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1206] + (const void *)&gInstructions[1208] }; const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary = @@ -15381,13 +15489,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1207] + (const void *)&gInstructions[1209] }; const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1208] + (const void *)&gInstructions[1210] }; const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary = @@ -15406,13 +15514,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1209] + (const void *)&gInstructions[1211] }; const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1210] + (const void *)&gInstructions[1212] }; const ND_TABLE_AUXILIARY gRootTable_root_af_ds16_auxiliary = @@ -15444,31 +15552,31 @@ const ND_TABLE_DSIZE gRootTable_root_af_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_f9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1275] + (const void *)&gInstructions[1278] }; const ND_TABLE_INSTRUCTION gRootTable_root_fd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1276] + (const void *)&gInstructions[1279] }; const ND_TABLE_INSTRUCTION gRootTable_root_fb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1278] + (const void *)&gInstructions[1281] }; const ND_TABLE_INSTRUCTION gRootTable_root_aa_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1280] + (const void *)&gInstructions[1283] }; const ND_TABLE_INSTRUCTION gRootTable_root_aa_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1281] + (const void *)&gInstructions[1284] }; const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary = @@ -15487,13 +15595,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1282] + (const void *)&gInstructions[1285] }; const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1283] + (const void *)&gInstructions[1286] }; const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary = @@ -15512,13 +15620,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1284] + (const void *)&gInstructions[1287] }; const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1285] + (const void *)&gInstructions[1288] }; const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary = @@ -15537,13 +15645,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1286] + (const void *)&gInstructions[1289] }; const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1287] + (const void *)&gInstructions[1290] }; const ND_TABLE_AUXILIARY gRootTable_root_ab_ds16_auxiliary = @@ -15575,163 +15683,163 @@ const ND_TABLE_DSIZE gRootTable_root_ab_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_28_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1291] + (const void *)&gInstructions[1295] }; const ND_TABLE_INSTRUCTION gRootTable_root_29_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1292] + (const void *)&gInstructions[1296] }; const ND_TABLE_INSTRUCTION gRootTable_root_2a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1293] + (const void *)&gInstructions[1297] }; const ND_TABLE_INSTRUCTION gRootTable_root_2b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1294] + (const void *)&gInstructions[1298] }; const ND_TABLE_INSTRUCTION gRootTable_root_2c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1295] + (const void *)&gInstructions[1299] }; const ND_TABLE_INSTRUCTION gRootTable_root_2d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1296] + (const void *)&gInstructions[1300] }; const ND_TABLE_INSTRUCTION gRootTable_root_84_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1320] + (const void *)&gInstructions[1324] }; const ND_TABLE_INSTRUCTION gRootTable_root_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1321] + (const void *)&gInstructions[1325] }; const ND_TABLE_INSTRUCTION gRootTable_root_a8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1322] + (const void *)&gInstructions[1326] }; const ND_TABLE_INSTRUCTION gRootTable_root_a9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1323] + (const void *)&gInstructions[1327] }; const ND_TABLE_INSTRUCTION gRootTable_root_9b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2511] + (const void *)&gInstructions[2521] }; const ND_TABLE_INSTRUCTION gRootTable_root_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2527] + (const void *)&gInstructions[2537] }; const ND_TABLE_INSTRUCTION gRootTable_root_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2528] + (const void *)&gInstructions[2538] }; const ND_TABLE_INSTRUCTION gRootTable_root_91_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2530] + (const void *)&gInstructions[2540] }; const ND_TABLE_INSTRUCTION gRootTable_root_92_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2531] + (const void *)&gInstructions[2541] }; const ND_TABLE_INSTRUCTION gRootTable_root_93_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2532] + (const void *)&gInstructions[2542] }; const ND_TABLE_INSTRUCTION gRootTable_root_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2533] + (const void *)&gInstructions[2543] }; const ND_TABLE_INSTRUCTION gRootTable_root_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2534] + (const void *)&gInstructions[2544] }; const ND_TABLE_INSTRUCTION gRootTable_root_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2535] + (const void *)&gInstructions[2545] }; const ND_TABLE_INSTRUCTION gRootTable_root_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2536] + (const void *)&gInstructions[2546] }; const ND_TABLE_INSTRUCTION gRootTable_root_d7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2544] + (const void *)&gInstructions[2554] }; const ND_TABLE_INSTRUCTION gRootTable_root_30_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2545] + (const void *)&gInstructions[2555] }; const ND_TABLE_INSTRUCTION gRootTable_root_31_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2546] + (const void *)&gInstructions[2556] }; const ND_TABLE_INSTRUCTION gRootTable_root_32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2547] + (const void *)&gInstructions[2557] }; const ND_TABLE_INSTRUCTION gRootTable_root_33_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2548] + (const void *)&gInstructions[2558] }; const ND_TABLE_INSTRUCTION gRootTable_root_34_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2549] + (const void *)&gInstructions[2559] }; const ND_TABLE_INSTRUCTION gRootTable_root_35_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2550] + (const void *)&gInstructions[2560] }; const ND_TABLE_OPCODE gRootTable_root_opcode = diff --git a/bddisasm/include/table_vex.h b/bddisasm/include/table_vex.h index 98de335..55d3ab1 100644 --- a/bddisasm/include/table_vex.h +++ b/bddisasm/include/table_vex.h @@ -49,7 +49,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_00_l = const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1191] + (const void *)&gInstructions[1193] }; const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l = @@ -66,7 +66,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l = const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1249] + (const void *)&gInstructions[1252] }; const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l = @@ -83,7 +83,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l = const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1258] + (const void *)&gInstructions[1261] }; const ND_TABLE_VEX_L gVexTable_root_02_f7_03_l = @@ -205,7 +205,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f5_00_l = const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[875] + (const void *)&gInstructions[877] }; const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l = @@ -222,7 +222,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l = const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[876] + (const void *)&gInstructions[878] }; const ND_TABLE_VEX_L gVexTable_root_02_f5_02_l = @@ -250,7 +250,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_mem_00_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[567] + (const void *)&gInstructions[569] }; const ND_TABLE_VEX_W gVexTable_root_02_49_00_mem_00_00_w = @@ -291,7 +291,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_mem_modrmreg = const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_reg_00_00_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1330] + (const void *)&gInstructions[1335] }; const ND_TABLE_VEX_W gVexTable_root_02_49_00_reg_00_00_00_w = @@ -356,7 +356,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_00_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_49_01_mem_00_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1290] + (const void *)&gInstructions[1293] }; const ND_TABLE_VEX_W gVexTable_root_02_49_01_mem_00_00_w = @@ -406,7 +406,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_49_03_reg_00_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1332] + (const void *)&gInstructions[1337] }; const ND_TABLE_VEX_W gVexTable_root_02_49_03_reg_00_00_w = @@ -467,7 +467,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_49_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_f6_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[727] + (const void *)&gInstructions[729] }; const ND_TABLE_VEX_L gVexTable_root_02_f6_03_l = @@ -495,7 +495,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_02_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1315] + (const void *)&gInstructions[1319] }; const ND_TABLE_VEX_W gVexTable_root_02_5c_02_reg_00_w = @@ -541,7 +541,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_03_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1316] + (const void *)&gInstructions[1320] }; const ND_TABLE_VEX_W gVexTable_root_02_5e_03_reg_00_w = @@ -576,7 +576,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_02_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1317] + (const void *)&gInstructions[1321] }; const ND_TABLE_VEX_W gVexTable_root_02_5e_02_reg_00_w = @@ -611,7 +611,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1318] + (const void *)&gInstructions[1322] }; const ND_TABLE_VEX_W gVexTable_root_02_5e_01_reg_00_w = @@ -646,7 +646,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1319] + (const void *)&gInstructions[1323] }; const ND_TABLE_VEX_W gVexTable_root_02_5e_00_reg_00_w = @@ -692,7 +692,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_03_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1328] + (const void *)&gInstructions[1333] }; const ND_TABLE_VEX_W gVexTable_root_02_4b_03_mem_00_w = @@ -727,7 +727,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_01_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1329] + (const void *)&gInstructions[1334] }; const ND_TABLE_VEX_W gVexTable_root_02_4b_01_mem_00_w = @@ -762,7 +762,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_02_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1331] + (const void *)&gInstructions[1336] }; const ND_TABLE_VEX_W gVexTable_root_02_4b_02_mem_00_w = @@ -808,7 +808,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_4b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_de_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1363] + (const void *)&gInstructions[1369] }; const ND_TABLE_VEX_PP gVexTable_root_02_de_pp = @@ -825,7 +825,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_de_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_df_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1365] + (const void *)&gInstructions[1371] }; const ND_TABLE_VEX_PP gVexTable_root_02_df_pp = @@ -842,7 +842,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_df_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_dc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1367] + (const void *)&gInstructions[1373] }; const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp = @@ -859,7 +859,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_dd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1369] + (const void *)&gInstructions[1375] }; const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp = @@ -876,7 +876,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_db_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1370] + (const void *)&gInstructions[1376] }; const ND_TABLE_VEX_L gVexTable_root_02_db_01_l = @@ -904,7 +904,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_db_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_1a_01_mem_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1388] + (const void *)&gInstructions[1394] }; const ND_TABLE_VEX_W gVexTable_root_02_1a_01_mem_01_w = @@ -950,7 +950,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_5a_01_mem_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1394] + (const void *)&gInstructions[1400] }; const ND_TABLE_VEX_W gVexTable_root_02_5a_01_mem_01_w = @@ -996,7 +996,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_19_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1401] + (const void *)&gInstructions[1407] }; const ND_TABLE_VEX_W gVexTable_root_02_19_01_w = @@ -1022,7 +1022,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_19_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_18_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1403] + (const void *)&gInstructions[1409] }; const ND_TABLE_VEX_W gVexTable_root_02_18_01_w = @@ -1048,7 +1048,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_18_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1434] + (const void *)&gInstructions[1440] }; const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w = @@ -1063,7 +1063,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w = const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1435] + (const void *)&gInstructions[1441] }; const ND_TABLE_VEX_W gVexTable_root_02_13_01_01_w = @@ -1100,13 +1100,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_13_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1524] + (const void *)&gInstructions[1530] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1526] + (const void *)&gInstructions[1532] }; const ND_TABLE_VEX_W gVexTable_root_02_98_01_w = @@ -1132,13 +1132,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_98_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1528] + (const void *)&gInstructions[1534] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1530] + (const void *)&gInstructions[1536] }; const ND_TABLE_VEX_W gVexTable_root_02_99_01_w = @@ -1164,13 +1164,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_99_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1532] + (const void *)&gInstructions[1538] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1534] + (const void *)&gInstructions[1540] }; const ND_TABLE_VEX_W gVexTable_root_02_a8_01_w = @@ -1196,13 +1196,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1536] + (const void *)&gInstructions[1542] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1538] + (const void *)&gInstructions[1544] }; const ND_TABLE_VEX_W gVexTable_root_02_a9_01_w = @@ -1228,13 +1228,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1540] + (const void *)&gInstructions[1546] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1542] + (const void *)&gInstructions[1548] }; const ND_TABLE_VEX_W gVexTable_root_02_b8_01_w = @@ -1260,13 +1260,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1544] + (const void *)&gInstructions[1550] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1546] + (const void *)&gInstructions[1552] }; const ND_TABLE_VEX_W gVexTable_root_02_b9_01_w = @@ -1292,13 +1292,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1556] + (const void *)&gInstructions[1562] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1558] + (const void *)&gInstructions[1564] }; const ND_TABLE_VEX_W gVexTable_root_02_96_01_w = @@ -1324,13 +1324,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_96_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1560] + (const void *)&gInstructions[1566] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1562] + (const void *)&gInstructions[1568] }; const ND_TABLE_VEX_W gVexTable_root_02_a6_01_w = @@ -1356,13 +1356,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1564] + (const void *)&gInstructions[1570] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1566] + (const void *)&gInstructions[1572] }; const ND_TABLE_VEX_W gVexTable_root_02_b6_01_w = @@ -1388,13 +1388,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1572] + (const void *)&gInstructions[1578] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1574] + (const void *)&gInstructions[1580] }; const ND_TABLE_VEX_W gVexTable_root_02_9a_01_w = @@ -1420,13 +1420,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1576] + (const void *)&gInstructions[1582] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1578] + (const void *)&gInstructions[1584] }; const ND_TABLE_VEX_W gVexTable_root_02_9b_01_w = @@ -1452,13 +1452,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1580] + (const void *)&gInstructions[1586] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1582] + (const void *)&gInstructions[1588] }; const ND_TABLE_VEX_W gVexTable_root_02_aa_01_w = @@ -1484,13 +1484,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_aa_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1584] + (const void *)&gInstructions[1590] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1586] + (const void *)&gInstructions[1592] }; const ND_TABLE_VEX_W gVexTable_root_02_ab_01_w = @@ -1516,13 +1516,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ab_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1588] + (const void *)&gInstructions[1594] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1590] + (const void *)&gInstructions[1596] }; const ND_TABLE_VEX_W gVexTable_root_02_ba_01_w = @@ -1548,13 +1548,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ba_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1592] + (const void *)&gInstructions[1598] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1594] + (const void *)&gInstructions[1600] }; const ND_TABLE_VEX_W gVexTable_root_02_bb_01_w = @@ -1580,13 +1580,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bb_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1596] + (const void *)&gInstructions[1602] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1598] + (const void *)&gInstructions[1604] }; const ND_TABLE_VEX_W gVexTable_root_02_97_01_w = @@ -1612,13 +1612,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_97_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1600] + (const void *)&gInstructions[1606] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1602] + (const void *)&gInstructions[1608] }; const ND_TABLE_VEX_W gVexTable_root_02_a7_01_w = @@ -1644,13 +1644,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1604] + (const void *)&gInstructions[1610] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1606] + (const void *)&gInstructions[1612] }; const ND_TABLE_VEX_W gVexTable_root_02_b7_01_w = @@ -1676,13 +1676,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1620] + (const void *)&gInstructions[1626] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1622] + (const void *)&gInstructions[1628] }; const ND_TABLE_VEX_W gVexTable_root_02_9c_01_w = @@ -1708,13 +1708,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1624] + (const void *)&gInstructions[1630] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1626] + (const void *)&gInstructions[1632] }; const ND_TABLE_VEX_W gVexTable_root_02_9d_01_w = @@ -1740,13 +1740,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1628] + (const void *)&gInstructions[1634] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1630] + (const void *)&gInstructions[1636] }; const ND_TABLE_VEX_W gVexTable_root_02_ac_01_w = @@ -1772,13 +1772,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ac_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1632] + (const void *)&gInstructions[1638] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1634] + (const void *)&gInstructions[1640] }; const ND_TABLE_VEX_W gVexTable_root_02_ad_01_w = @@ -1804,13 +1804,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ad_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1636] + (const void *)&gInstructions[1642] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1638] + (const void *)&gInstructions[1644] }; const ND_TABLE_VEX_W gVexTable_root_02_bc_01_w = @@ -1836,13 +1836,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bc_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1640] + (const void *)&gInstructions[1646] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1642] + (const void *)&gInstructions[1648] }; const ND_TABLE_VEX_W gVexTable_root_02_bd_01_w = @@ -1868,13 +1868,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bd_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1652] + (const void *)&gInstructions[1658] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1654] + (const void *)&gInstructions[1660] }; const ND_TABLE_VEX_W gVexTable_root_02_9e_01_w = @@ -1900,13 +1900,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1656] + (const void *)&gInstructions[1662] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1658] + (const void *)&gInstructions[1664] }; const ND_TABLE_VEX_W gVexTable_root_02_9f_01_w = @@ -1932,13 +1932,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1660] + (const void *)&gInstructions[1666] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1662] + (const void *)&gInstructions[1668] }; const ND_TABLE_VEX_W gVexTable_root_02_ae_01_w = @@ -1964,13 +1964,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ae_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1664] + (const void *)&gInstructions[1670] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1666] + (const void *)&gInstructions[1672] }; const ND_TABLE_VEX_W gVexTable_root_02_af_01_w = @@ -1996,13 +1996,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_af_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1668] + (const void *)&gInstructions[1674] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1670] + (const void *)&gInstructions[1676] }; const ND_TABLE_VEX_W gVexTable_root_02_be_01_w = @@ -2028,13 +2028,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_be_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1672] + (const void *)&gInstructions[1678] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1674] + (const void *)&gInstructions[1680] }; const ND_TABLE_VEX_W gVexTable_root_02_bf_01_w = @@ -2060,13 +2060,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bf_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1692] + (const void *)&gInstructions[1698] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1694] + (const void *)&gInstructions[1700] }; const ND_TABLE_VEX_W gVexTable_root_02_92_01_mem_w = @@ -2101,13 +2101,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_92_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1704] + (const void *)&gInstructions[1710] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1706] + (const void *)&gInstructions[1712] }; const ND_TABLE_VEX_W gVexTable_root_02_93_01_mem_w = @@ -2142,7 +2142,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_93_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_cf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1720] + (const void *)&gInstructions[1726] }; const ND_TABLE_VEX_W gVexTable_root_02_cf_01_w = @@ -2168,7 +2168,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_cf_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2d_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1742] + (const void *)&gInstructions[1748] }; const ND_TABLE_VEX_W gVexTable_root_02_2d_01_mem_w = @@ -2203,7 +2203,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2f_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1743] + (const void *)&gInstructions[1749] }; const ND_TABLE_VEX_W gVexTable_root_02_2f_01_mem_w = @@ -2238,7 +2238,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2c_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1744] + (const void *)&gInstructions[1750] }; const ND_TABLE_VEX_W gVexTable_root_02_2c_01_mem_w = @@ -2273,7 +2273,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2e_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1745] + (const void *)&gInstructions[1751] }; const ND_TABLE_VEX_W gVexTable_root_02_2e_01_mem_w = @@ -2308,7 +2308,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2a_01_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1829] + (const void *)&gInstructions[1835] }; const ND_TABLE_MODRM_MOD gVexTable_root_02_2a_01_modrmmod = @@ -2334,7 +2334,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_1c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1897] + (const void *)&gInstructions[1903] }; const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp = @@ -2351,7 +2351,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_1e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1899] + (const void *)&gInstructions[1905] }; const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp = @@ -2368,7 +2368,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_1d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1902] + (const void *)&gInstructions[1908] }; const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp = @@ -2385,7 +2385,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1908] + (const void *)&gInstructions[1914] }; const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp = @@ -2402,7 +2402,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1948] + (const void *)&gInstructions[1954] }; const ND_TABLE_VEX_W gVexTable_root_02_78_01_w = @@ -2428,7 +2428,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_78_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_58_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1951] + (const void *)&gInstructions[1957] }; const ND_TABLE_VEX_W gVexTable_root_02_58_01_w = @@ -2454,7 +2454,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_58_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_59_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1956] + (const void *)&gInstructions[1962] }; const ND_TABLE_VEX_W gVexTable_root_02_59_01_w = @@ -2480,7 +2480,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_59_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1959] + (const void *)&gInstructions[1965] }; const ND_TABLE_VEX_W gVexTable_root_02_79_01_w = @@ -2506,7 +2506,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_79_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_29_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1971] + (const void *)&gInstructions[1977] }; const ND_TABLE_VEX_PP gVexTable_root_02_29_pp = @@ -2523,7 +2523,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_29_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_37_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1981] + (const void *)&gInstructions[1987] }; const ND_TABLE_VEX_PP gVexTable_root_02_37_pp = @@ -2537,10 +2537,114 @@ const ND_TABLE_VEX_PP gVexTable_root_02_37_pp = } }; +const ND_TABLE_INSTRUCTION gVexTable_root_02_50_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2013] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_50_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_50_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_50_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_50_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_51_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2015] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_51_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_51_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_51_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_51_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_52_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2017] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_52_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_52_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_52_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_52_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexTable_root_02_53_01_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[2019] +}; + +const ND_TABLE_VEX_W gVexTable_root_02_53_01_w = +{ + ND_ILUT_VEX_W, + { + /* 00 */ (const void *)&gVexTable_root_02_53_01_00_leaf, + /* 01 */ NULL, + } +}; + +const ND_TABLE_VEX_PP gVexTable_root_02_53_pp = +{ + ND_ILUT_VEX_PP, + { + /* 00 */ NULL, + /* 01 */ (const void *)&gVexTable_root_02_53_01_w, + /* 02 */ NULL, + /* 03 */ NULL, + } +}; + const ND_TABLE_INSTRUCTION gVexTable_root_02_36_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2014] + (const void *)&gInstructions[2024] }; const ND_TABLE_VEX_W gVexTable_root_02_36_01_01_w = @@ -2577,7 +2681,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_36_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2027] + (const void *)&gInstructions[2037] }; const ND_TABLE_VEX_W gVexTable_root_02_0d_01_w = @@ -2603,7 +2707,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2031] + (const void *)&gInstructions[2041] }; const ND_TABLE_VEX_W gVexTable_root_02_0c_01_w = @@ -2629,7 +2733,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_16_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2039] + (const void *)&gInstructions[2049] }; const ND_TABLE_VEX_W gVexTable_root_02_16_01_01_w = @@ -2666,13 +2770,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_16_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2069] + (const void *)&gInstructions[2079] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2071] + (const void *)&gInstructions[2081] }; const ND_TABLE_VEX_W gVexTable_root_02_90_01_mem_w = @@ -2707,13 +2811,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_90_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2073] + (const void *)&gInstructions[2083] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2075] + (const void *)&gInstructions[2085] }; const ND_TABLE_VEX_W gVexTable_root_02_91_01_mem_w = @@ -2748,7 +2852,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_91_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2079] + (const void *)&gInstructions[2089] }; const ND_TABLE_VEX_PP gVexTable_root_02_02_pp = @@ -2765,7 +2869,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_02_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2081] + (const void *)&gInstructions[2091] }; const ND_TABLE_VEX_PP gVexTable_root_02_03_pp = @@ -2782,7 +2886,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_03_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2088] + (const void *)&gInstructions[2098] }; const ND_TABLE_VEX_PP gVexTable_root_02_01_pp = @@ -2799,7 +2903,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_01_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_41_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2091] + (const void *)&gInstructions[2101] }; const ND_TABLE_VEX_L gVexTable_root_02_41_01_l = @@ -2827,7 +2931,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_41_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_06_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2093] + (const void *)&gInstructions[2103] }; const ND_TABLE_VEX_PP gVexTable_root_02_06_pp = @@ -2844,7 +2948,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_06_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_07_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2095] + (const void *)&gInstructions[2105] }; const ND_TABLE_VEX_PP gVexTable_root_02_07_pp = @@ -2861,7 +2965,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_07_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_05_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2096] + (const void *)&gInstructions[2106] }; const ND_TABLE_VEX_PP gVexTable_root_02_05_pp = @@ -2878,7 +2982,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_05_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2127] + (const void *)&gInstructions[2137] }; const ND_TABLE_VEX_PP gVexTable_root_02_04_pp = @@ -2895,13 +2999,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_04_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2130] + (const void *)&gInstructions[2140] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2132] + (const void *)&gInstructions[2142] }; const ND_TABLE_VEX_W gVexTable_root_02_8c_01_mem_w = @@ -2936,13 +3040,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2131] + (const void *)&gInstructions[2141] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2133] + (const void *)&gInstructions[2143] }; const ND_TABLE_VEX_W gVexTable_root_02_8e_01_mem_w = @@ -2977,7 +3081,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2135] + (const void *)&gInstructions[2145] }; const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp = @@ -2994,7 +3098,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2137] + (const void *)&gInstructions[2147] }; const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp = @@ -3011,7 +3115,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2144] + (const void *)&gInstructions[2154] }; const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp = @@ -3028,7 +3132,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2147] + (const void *)&gInstructions[2157] }; const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp = @@ -3045,7 +3149,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_38_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2149] + (const void *)&gInstructions[2159] }; const ND_TABLE_VEX_PP gVexTable_root_02_38_pp = @@ -3062,7 +3166,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_38_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_39_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2151] + (const void *)&gInstructions[2161] }; const ND_TABLE_VEX_PP gVexTable_root_02_39_pp = @@ -3079,7 +3183,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_39_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2158] + (const void *)&gInstructions[2168] }; const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp = @@ -3096,7 +3200,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2161] + (const void *)&gInstructions[2171] }; const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp = @@ -3113,13 +3217,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2182] + (const void *)&gInstructions[2192] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2183] + (const void *)&gInstructions[2193] }; const ND_TABLE_VEX_L gVexTable_root_02_21_01_l = @@ -3147,13 +3251,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_21_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2185] + (const void *)&gInstructions[2195] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2186] + (const void *)&gInstructions[2196] }; const ND_TABLE_VEX_L gVexTable_root_02_22_01_l = @@ -3181,13 +3285,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_22_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2188] + (const void *)&gInstructions[2198] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2189] + (const void *)&gInstructions[2199] }; const ND_TABLE_VEX_L gVexTable_root_02_20_01_l = @@ -3215,13 +3319,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_20_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2191] + (const void *)&gInstructions[2201] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2192] + (const void *)&gInstructions[2202] }; const ND_TABLE_VEX_L gVexTable_root_02_25_01_l = @@ -3249,13 +3353,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_25_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2194] + (const void *)&gInstructions[2204] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2195] + (const void *)&gInstructions[2205] }; const ND_TABLE_VEX_L gVexTable_root_02_23_01_l = @@ -3283,13 +3387,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_23_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2197] + (const void *)&gInstructions[2207] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2198] + (const void *)&gInstructions[2208] }; const ND_TABLE_VEX_L gVexTable_root_02_24_01_l = @@ -3317,13 +3421,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_24_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2208] + (const void *)&gInstructions[2218] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2209] + (const void *)&gInstructions[2219] }; const ND_TABLE_VEX_L gVexTable_root_02_31_01_l = @@ -3351,13 +3455,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_31_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2211] + (const void *)&gInstructions[2221] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2212] + (const void *)&gInstructions[2222] }; const ND_TABLE_VEX_L gVexTable_root_02_32_01_l = @@ -3385,13 +3489,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_32_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2214] + (const void *)&gInstructions[2224] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2215] + (const void *)&gInstructions[2225] }; const ND_TABLE_VEX_L gVexTable_root_02_30_01_l = @@ -3419,13 +3523,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_30_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2217] + (const void *)&gInstructions[2227] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2218] + (const void *)&gInstructions[2228] }; const ND_TABLE_VEX_L gVexTable_root_02_35_01_l = @@ -3453,13 +3557,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_35_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2220] + (const void *)&gInstructions[2230] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2221] + (const void *)&gInstructions[2231] }; const ND_TABLE_VEX_L gVexTable_root_02_33_01_l = @@ -3487,13 +3591,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_33_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2223] + (const void *)&gInstructions[2233] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2224] + (const void *)&gInstructions[2234] }; const ND_TABLE_VEX_L gVexTable_root_02_34_01_l = @@ -3521,7 +3625,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_34_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_28_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2226] + (const void *)&gInstructions[2236] }; const ND_TABLE_VEX_PP gVexTable_root_02_28_pp = @@ -3538,7 +3642,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_28_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2228] + (const void *)&gInstructions[2238] }; const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp = @@ -3555,7 +3659,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_40_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2234] + (const void *)&gInstructions[2244] }; const ND_TABLE_VEX_PP gVexTable_root_02_40_pp = @@ -3572,7 +3676,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_40_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2305] + (const void *)&gInstructions[2315] }; const ND_TABLE_VEX_PP gVexTable_root_02_00_pp = @@ -3589,7 +3693,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_00_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_08_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2313] + (const void *)&gInstructions[2323] }; const ND_TABLE_VEX_PP gVexTable_root_02_08_pp = @@ -3606,7 +3710,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_08_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2314] + (const void *)&gInstructions[2324] }; const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp = @@ -3623,7 +3727,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_09_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2315] + (const void *)&gInstructions[2325] }; const ND_TABLE_VEX_PP gVexTable_root_02_09_pp = @@ -3640,13 +3744,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_09_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2327] + (const void *)&gInstructions[2337] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2329] + (const void *)&gInstructions[2339] }; const ND_TABLE_VEX_W gVexTable_root_02_47_01_w = @@ -3672,7 +3776,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_47_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_46_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2342] + (const void *)&gInstructions[2352] }; const ND_TABLE_VEX_W gVexTable_root_02_46_01_w = @@ -3698,13 +3802,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_46_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2360] + (const void *)&gInstructions[2370] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2362] + (const void *)&gInstructions[2372] }; const ND_TABLE_VEX_W gVexTable_root_02_45_01_w = @@ -3730,7 +3834,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_45_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_17_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2386] + (const void *)&gInstructions[2396] }; const ND_TABLE_VEX_PP gVexTable_root_02_17_pp = @@ -3747,7 +3851,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_17_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2491] + (const void *)&gInstructions[2501] }; const ND_TABLE_VEX_W gVexTable_root_02_0f_01_w = @@ -3773,7 +3877,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2492] + (const void *)&gInstructions[2502] }; const ND_TABLE_VEX_W gVexTable_root_02_0e_01_w = @@ -3880,10 +3984,10 @@ const ND_TABLE_OPCODE gVexTable_root_02_opcode = /* 4d */ NULL, /* 4e */ NULL, /* 4f */ NULL, - /* 50 */ NULL, - /* 51 */ NULL, - /* 52 */ NULL, - /* 53 */ NULL, + /* 50 */ (const void *)&gVexTable_root_02_50_pp, + /* 51 */ (const void *)&gVexTable_root_02_51_pp, + /* 52 */ (const void *)&gVexTable_root_02_52_pp, + /* 53 */ (const void *)&gVexTable_root_02_53_pp, /* 54 */ NULL, /* 55 */ NULL, /* 56 */ NULL, @@ -4083,7 +4187,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_mem_modrmreg = const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1269] + (const void *)&gInstructions[1272] }; const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_reg_modrmreg = @@ -4134,7 +4238,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_mem_modrmreg = const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_02_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[218] + (const void *)&gInstructions[219] }; const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_reg_modrmreg = @@ -4164,13 +4268,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1740] + (const void *)&gInstructions[1746] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2482] + (const void *)&gInstructions[2492] }; const ND_TABLE_MODRM_REG gVexTable_root_01_ae_00_mem_modrmreg = @@ -4211,13 +4315,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ae_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[492] + (const void *)&gInstructions[494] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[493] + (const void *)&gInstructions[495] }; const ND_TABLE_VEX_W gVexTable_root_01_4a_01_reg_01_w = @@ -4252,13 +4356,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4a_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[494] + (const void *)&gInstructions[496] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[495] + (const void *)&gInstructions[497] }; const ND_TABLE_VEX_W gVexTable_root_01_4a_00_reg_01_w = @@ -4304,13 +4408,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_4a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[496] + (const void *)&gInstructions[498] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[497] + (const void *)&gInstructions[499] }; const ND_TABLE_VEX_W gVexTable_root_01_41_01_reg_01_w = @@ -4345,13 +4449,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_41_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[502] + (const void *)&gInstructions[504] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[503] + (const void *)&gInstructions[505] }; const ND_TABLE_VEX_W gVexTable_root_01_41_00_reg_01_w = @@ -4397,13 +4501,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_41_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[498] + (const void *)&gInstructions[500] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[499] + (const void *)&gInstructions[501] }; const ND_TABLE_VEX_W gVexTable_root_01_42_01_reg_01_w = @@ -4438,13 +4542,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_42_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[500] + (const void *)&gInstructions[502] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[501] + (const void *)&gInstructions[503] }; const ND_TABLE_VEX_W gVexTable_root_01_42_00_reg_01_w = @@ -4490,7 +4594,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_42_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_48_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[504] + (const void *)&gInstructions[506] }; const ND_TABLE_VEX_W gVexTable_root_01_48_00_reg_00_w = @@ -4536,7 +4640,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_48_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_49_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[505] + (const void *)&gInstructions[507] }; const ND_TABLE_VEX_W gVexTable_root_01_49_00_reg_00_w = @@ -4582,13 +4686,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_49_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[506] + (const void *)&gInstructions[508] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[511] + (const void *)&gInstructions[513] }; const ND_TABLE_VEX_W gVexTable_root_01_90_01_mem_00_w = @@ -4614,13 +4718,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[507] + (const void *)&gInstructions[509] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[512] + (const void *)&gInstructions[514] }; const ND_TABLE_VEX_W gVexTable_root_01_90_01_reg_00_w = @@ -4655,13 +4759,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_90_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[516] + (const void *)&gInstructions[518] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[521] + (const void *)&gInstructions[523] }; const ND_TABLE_VEX_W gVexTable_root_01_90_00_mem_00_w = @@ -4687,13 +4791,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_00_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[517] + (const void *)&gInstructions[519] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[522] + (const void *)&gInstructions[524] }; const ND_TABLE_VEX_W gVexTable_root_01_90_00_reg_00_w = @@ -4739,13 +4843,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_90_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[508] + (const void *)&gInstructions[510] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[513] + (const void *)&gInstructions[515] }; const ND_TABLE_VEX_W gVexTable_root_01_91_01_mem_00_w = @@ -4780,13 +4884,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_91_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[518] + (const void *)&gInstructions[520] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[523] + (const void *)&gInstructions[525] }; const ND_TABLE_VEX_W gVexTable_root_01_91_00_mem_00_w = @@ -4832,7 +4936,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_91_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_92_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[509] + (const void *)&gInstructions[511] }; const ND_TABLE_VEX_W gVexTable_root_01_92_01_reg_00_w = @@ -4867,13 +4971,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[514] + (const void *)&gInstructions[516] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[519] + (const void *)&gInstructions[521] }; const ND_TABLE_VEX_W gVexTable_root_01_92_03_reg_00_w = @@ -4908,7 +5012,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_92_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[524] + (const void *)&gInstructions[526] }; const ND_TABLE_VEX_W gVexTable_root_01_92_00_reg_00_w = @@ -4954,7 +5058,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_92_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_93_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[510] + (const void *)&gInstructions[512] }; const ND_TABLE_VEX_W gVexTable_root_01_93_01_reg_00_w = @@ -4989,13 +5093,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[515] + (const void *)&gInstructions[517] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[520] + (const void *)&gInstructions[522] }; const ND_TABLE_VEX_W gVexTable_root_01_93_03_reg_00_w = @@ -5030,7 +5134,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_93_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[525] + (const void *)&gInstructions[527] }; const ND_TABLE_VEX_W gVexTable_root_01_93_00_reg_00_w = @@ -5076,13 +5180,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_93_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[526] + (const void *)&gInstructions[528] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[527] + (const void *)&gInstructions[529] }; const ND_TABLE_VEX_W gVexTable_root_01_44_01_reg_00_w = @@ -5117,13 +5221,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_44_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[528] + (const void *)&gInstructions[530] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[529] + (const void *)&gInstructions[531] }; const ND_TABLE_VEX_W gVexTable_root_01_44_00_reg_00_w = @@ -5169,13 +5273,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_44_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[530] + (const void *)&gInstructions[532] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[531] + (const void *)&gInstructions[533] }; const ND_TABLE_VEX_W gVexTable_root_01_45_01_reg_01_w = @@ -5210,13 +5314,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_45_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[532] + (const void *)&gInstructions[534] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[537] + (const void *)&gInstructions[539] }; const ND_TABLE_VEX_W gVexTable_root_01_45_00_reg_01_w = @@ -5262,13 +5366,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_45_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[533] + (const void *)&gInstructions[535] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[534] + (const void *)&gInstructions[536] }; const ND_TABLE_VEX_W gVexTable_root_01_98_01_reg_00_w = @@ -5303,13 +5407,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_98_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[535] + (const void *)&gInstructions[537] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[536] + (const void *)&gInstructions[538] }; const ND_TABLE_VEX_W gVexTable_root_01_98_00_reg_00_w = @@ -5355,13 +5459,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_98_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[546] + (const void *)&gInstructions[548] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[547] + (const void *)&gInstructions[549] }; const ND_TABLE_VEX_W gVexTable_root_01_99_01_reg_00_w = @@ -5396,13 +5500,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_99_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[548] + (const void *)&gInstructions[550] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[549] + (const void *)&gInstructions[551] }; const ND_TABLE_VEX_W gVexTable_root_01_99_00_reg_00_w = @@ -5448,7 +5552,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_99_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[550] + (const void *)&gInstructions[552] }; const ND_TABLE_VEX_W gVexTable_root_01_4b_01_reg_01_w = @@ -5483,13 +5587,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4b_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[551] + (const void *)&gInstructions[553] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[552] + (const void *)&gInstructions[554] }; const ND_TABLE_VEX_W gVexTable_root_01_4b_00_reg_01_w = @@ -5535,13 +5639,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_4b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[553] + (const void *)&gInstructions[555] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[554] + (const void *)&gInstructions[556] }; const ND_TABLE_VEX_W gVexTable_root_01_46_01_reg_01_w = @@ -5576,13 +5680,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_46_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[555] + (const void *)&gInstructions[557] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[556] + (const void *)&gInstructions[558] }; const ND_TABLE_VEX_W gVexTable_root_01_46_00_reg_01_w = @@ -5628,13 +5732,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_46_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[557] + (const void *)&gInstructions[559] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[558] + (const void *)&gInstructions[560] }; const ND_TABLE_VEX_W gVexTable_root_01_47_01_reg_01_w = @@ -5669,13 +5773,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_47_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[559] + (const void *)&gInstructions[561] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[560] + (const void *)&gInstructions[562] }; const ND_TABLE_VEX_W gVexTable_root_01_47_00_reg_01_w = @@ -5721,25 +5825,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_47_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_58_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1353] + (const void *)&gInstructions[1359] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_58_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1355] + (const void *)&gInstructions[1361] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_58_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1357] + (const void *)&gInstructions[1363] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_58_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1359] + (const void *)&gInstructions[1365] }; const ND_TABLE_VEX_PP gVexTable_root_01_58_pp = @@ -5756,13 +5860,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_58_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1360] + (const void *)&gInstructions[1366] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1361] + (const void *)&gInstructions[1367] }; const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp = @@ -5779,13 +5883,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_55_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1375] + (const void *)&gInstructions[1381] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_55_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1377] + (const void *)&gInstructions[1383] }; const ND_TABLE_VEX_PP gVexTable_root_01_55_pp = @@ -5802,13 +5906,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_55_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_54_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1379] + (const void *)&gInstructions[1385] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_54_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1381] + (const void *)&gInstructions[1387] }; const ND_TABLE_VEX_PP gVexTable_root_01_54_pp = @@ -5825,25 +5929,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_54_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1405] + (const void *)&gInstructions[1411] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1407] + (const void *)&gInstructions[1413] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1409] + (const void *)&gInstructions[1415] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1411] + (const void *)&gInstructions[1417] }; const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp = @@ -5860,13 +5964,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1413] + (const void *)&gInstructions[1419] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1415] + (const void *)&gInstructions[1421] }; const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp = @@ -5883,13 +5987,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1419] + (const void *)&gInstructions[1425] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1420] + (const void *)&gInstructions[1426] }; const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l = @@ -5906,13 +6010,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1426] + (const void *)&gInstructions[1432] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1465] + (const void *)&gInstructions[1471] }; const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp = @@ -5929,19 +6033,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1422] + (const void *)&gInstructions[1428] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1437] + (const void *)&gInstructions[1443] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1470] + (const void *)&gInstructions[1476] }; const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp = @@ -5958,13 +6062,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1428] + (const void *)&gInstructions[1434] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1429] + (const void *)&gInstructions[1435] }; const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l = @@ -5981,13 +6085,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1439] + (const void *)&gInstructions[1445] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1440] + (const void *)&gInstructions[1446] }; const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l = @@ -6004,13 +6108,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1452] + (const void *)&gInstructions[1458] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1460] + (const void *)&gInstructions[1466] }; const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp = @@ -6027,13 +6131,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1450] + (const void *)&gInstructions[1456] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1462] + (const void *)&gInstructions[1468] }; const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp = @@ -6050,13 +6154,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1456] + (const void *)&gInstructions[1462] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1458] + (const void *)&gInstructions[1464] }; const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp = @@ -6073,13 +6177,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1475] + (const void *)&gInstructions[1481] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1478] + (const void *)&gInstructions[1484] }; const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp = @@ -6096,25 +6200,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1489] + (const void *)&gInstructions[1495] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1491] + (const void *)&gInstructions[1497] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1493] + (const void *)&gInstructions[1499] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1495] + (const void *)&gInstructions[1501] }; const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp = @@ -6131,13 +6235,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1721] + (const void *)&gInstructions[1727] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1722] + (const void *)&gInstructions[1728] }; const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp = @@ -6154,13 +6258,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1723] + (const void *)&gInstructions[1729] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1724] + (const void *)&gInstructions[1730] }; const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp = @@ -6177,7 +6281,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f0_03_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1739] + (const void *)&gInstructions[1745] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_f0_03_modrmmod = @@ -6203,7 +6307,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f7_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1741] + (const void *)&gInstructions[1747] }; const ND_TABLE_VEX_L gVexTable_root_01_f7_01_reg_l = @@ -6240,25 +6344,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1747] + (const void *)&gInstructions[1753] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1749] + (const void *)&gInstructions[1755] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1751] + (const void *)&gInstructions[1757] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1753] + (const void *)&gInstructions[1759] }; const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp = @@ -6275,25 +6379,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1760] + (const void *)&gInstructions[1766] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1762] + (const void *)&gInstructions[1768] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1764] + (const void *)&gInstructions[1770] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1766] + (const void *)&gInstructions[1772] }; const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp = @@ -6310,13 +6414,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_28_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1773] + (const void *)&gInstructions[1779] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_28_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1777] + (const void *)&gInstructions[1783] }; const ND_TABLE_VEX_PP gVexTable_root_01_28_pp = @@ -6333,13 +6437,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_28_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_29_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1774] + (const void *)&gInstructions[1780] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_29_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1778] + (const void *)&gInstructions[1784] }; const ND_TABLE_VEX_PP gVexTable_root_01_29_pp = @@ -6356,13 +6460,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_29_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1781] + (const void *)&gInstructions[1787] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1838] + (const void *)&gInstructions[1844] }; const ND_TABLE_VEX_W gVexTable_root_01_6e_01_00_w = @@ -6399,13 +6503,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1782] + (const void *)&gInstructions[1788] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1839] + (const void *)&gInstructions[1845] }; const ND_TABLE_VEX_W gVexTable_root_01_7e_01_00_w = @@ -6431,7 +6535,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_7e_01_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1840] + (const void *)&gInstructions[1846] }; const ND_TABLE_VEX_L gVexTable_root_01_7e_02_l = @@ -6459,13 +6563,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1786] + (const void *)&gInstructions[1792] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1787] + (const void *)&gInstructions[1793] }; const ND_TABLE_VEX_L gVexTable_root_01_12_03_l = @@ -6482,7 +6586,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_03_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1805] + (const void *)&gInstructions[1811] }; const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l = @@ -6499,7 +6603,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1822] + (const void *)&gInstructions[1828] }; const ND_TABLE_VEX_L gVexTable_root_01_12_00_mem_l = @@ -6525,7 +6629,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_00_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1818] + (const void *)&gInstructions[1824] }; const ND_TABLE_VEX_L gVexTable_root_01_12_01_mem_l = @@ -6551,7 +6655,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1853] + (const void *)&gInstructions[1859] }; const ND_TABLE_VEX_PP gVexTable_root_01_12_pp = @@ -6568,13 +6672,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_12_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1788] + (const void *)&gInstructions[1794] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1794] + (const void *)&gInstructions[1800] }; const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp = @@ -6591,13 +6695,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1789] + (const void *)&gInstructions[1795] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1795] + (const void *)&gInstructions[1801] }; const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp = @@ -6614,7 +6718,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_16_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1808] + (const void *)&gInstructions[1814] }; const ND_TABLE_VEX_L gVexTable_root_01_16_01_mem_l = @@ -6640,7 +6744,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1812] + (const void *)&gInstructions[1818] }; const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l = @@ -6657,7 +6761,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1815] + (const void *)&gInstructions[1821] }; const ND_TABLE_VEX_L gVexTable_root_01_16_00_reg_l = @@ -6683,7 +6787,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_00_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_16_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1851] + (const void *)&gInstructions[1857] }; const ND_TABLE_VEX_PP gVexTable_root_01_16_pp = @@ -6700,7 +6804,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_16_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_17_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1809] + (const void *)&gInstructions[1815] }; const ND_TABLE_VEX_L gVexTable_root_01_17_01_mem_l = @@ -6726,7 +6830,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_17_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_17_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1813] + (const void *)&gInstructions[1819] }; const ND_TABLE_VEX_L gVexTable_root_01_17_00_mem_l = @@ -6763,7 +6867,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_17_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_13_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1819] + (const void *)&gInstructions[1825] }; const ND_TABLE_VEX_L gVexTable_root_01_13_01_mem_l = @@ -6789,7 +6893,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_13_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_13_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1823] + (const void *)&gInstructions[1829] }; const ND_TABLE_VEX_L gVexTable_root_01_13_00_mem_l = @@ -6826,7 +6930,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_13_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_50_01_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1824] + (const void *)&gInstructions[1830] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod = @@ -6841,7 +6945,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_50_00_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1825] + (const void *)&gInstructions[1831] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_50_00_modrmmod = @@ -6867,7 +6971,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_50_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e7_01_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1827] + (const void *)&gInstructions[1833] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_e7_01_modrmmod = @@ -6893,7 +6997,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_01_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1831] + (const void *)&gInstructions[1837] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod = @@ -6908,7 +7012,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_00_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1833] + (const void *)&gInstructions[1839] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_00_modrmmod = @@ -6934,7 +7038,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1841] + (const void *)&gInstructions[1847] }; const ND_TABLE_VEX_L gVexTable_root_01_d6_01_l = @@ -6962,13 +7066,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1846] + (const void *)&gInstructions[1852] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1847] + (const void *)&gInstructions[1853] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod = @@ -6983,13 +7087,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1858] + (const void *)&gInstructions[1864] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1859] + (const void *)&gInstructions[1865] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod = @@ -7004,13 +7108,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_10_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1864] + (const void *)&gInstructions[1870] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_10_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1868] + (const void *)&gInstructions[1874] }; const ND_TABLE_VEX_PP gVexTable_root_01_10_pp = @@ -7027,13 +7131,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_10_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1848] + (const void *)&gInstructions[1854] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1849] + (const void *)&gInstructions[1855] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod = @@ -7048,13 +7152,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1860] + (const void *)&gInstructions[1866] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1861] + (const void *)&gInstructions[1867] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod = @@ -7069,13 +7173,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_11_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1865] + (const void *)&gInstructions[1871] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_11_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1869] + (const void *)&gInstructions[1875] }; const ND_TABLE_VEX_PP gVexTable_root_01_11_pp = @@ -7092,25 +7196,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_11_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_59_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1878] + (const void *)&gInstructions[1884] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_59_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1880] + (const void *)&gInstructions[1886] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_59_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1882] + (const void *)&gInstructions[1888] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_59_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1884] + (const void *)&gInstructions[1890] }; const ND_TABLE_VEX_PP gVexTable_root_01_59_pp = @@ -7127,13 +7231,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_59_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_56_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1889] + (const void *)&gInstructions[1895] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_56_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1891] + (const void *)&gInstructions[1897] }; const ND_TABLE_VEX_PP gVexTable_root_01_56_pp = @@ -7150,7 +7254,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_56_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1904] + (const void *)&gInstructions[1910] }; const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp = @@ -7167,7 +7271,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_63_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1906] + (const void *)&gInstructions[1912] }; const ND_TABLE_VEX_PP gVexTable_root_01_63_pp = @@ -7184,7 +7288,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_63_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_67_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1910] + (const void *)&gInstructions[1916] }; const ND_TABLE_VEX_PP gVexTable_root_01_67_pp = @@ -7201,7 +7305,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_67_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1912] + (const void *)&gInstructions[1918] }; const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp = @@ -7218,7 +7322,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fe_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1914] + (const void *)&gInstructions[1920] }; const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp = @@ -7235,7 +7339,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d4_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1916] + (const void *)&gInstructions[1922] }; const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp = @@ -7252,7 +7356,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ec_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1918] + (const void *)&gInstructions[1924] }; const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp = @@ -7269,7 +7373,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ed_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1920] + (const void *)&gInstructions[1926] }; const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp = @@ -7286,7 +7390,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_dc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1922] + (const void *)&gInstructions[1928] }; const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp = @@ -7303,7 +7407,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_dd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1924] + (const void *)&gInstructions[1930] }; const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp = @@ -7320,7 +7424,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1926] + (const void *)&gInstructions[1932] }; const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp = @@ -7337,7 +7441,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_db_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1929] + (const void *)&gInstructions[1935] }; const ND_TABLE_VEX_PP gVexTable_root_01_db_pp = @@ -7354,7 +7458,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_db_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_df_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1931] + (const void *)&gInstructions[1937] }; const ND_TABLE_VEX_PP gVexTable_root_01_df_pp = @@ -7371,7 +7475,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_df_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1936] + (const void *)&gInstructions[1942] }; const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp = @@ -7388,7 +7492,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1938] + (const void *)&gInstructions[1944] }; const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp = @@ -7405,7 +7509,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_74_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1967] + (const void *)&gInstructions[1973] }; const ND_TABLE_VEX_PP gVexTable_root_01_74_pp = @@ -7422,7 +7526,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_74_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_76_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1969] + (const void *)&gInstructions[1975] }; const ND_TABLE_VEX_PP gVexTable_root_01_76_pp = @@ -7439,7 +7543,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_76_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_75_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1973] + (const void *)&gInstructions[1979] }; const ND_TABLE_VEX_PP gVexTable_root_01_75_pp = @@ -7456,7 +7560,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_75_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_64_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1977] + (const void *)&gInstructions[1983] }; const ND_TABLE_VEX_PP gVexTable_root_01_64_pp = @@ -7473,7 +7577,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_64_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_66_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1979] + (const void *)&gInstructions[1985] }; const ND_TABLE_VEX_PP gVexTable_root_01_66_pp = @@ -7490,7 +7594,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_66_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_65_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1983] + (const void *)&gInstructions[1989] }; const ND_TABLE_VEX_PP gVexTable_root_01_65_pp = @@ -7507,7 +7611,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_65_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_c5_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2065] + (const void *)&gInstructions[2075] }; const ND_TABLE_VEX_L gVexTable_root_01_c5_01_reg_l = @@ -7544,7 +7648,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2108] + (const void *)&gInstructions[2118] }; const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l = @@ -7561,7 +7665,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2109] + (const void *)&gInstructions[2119] }; const ND_TABLE_VEX_L gVexTable_root_01_c4_01_reg_l = @@ -7598,7 +7702,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2129] + (const void *)&gInstructions[2139] }; const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp = @@ -7615,7 +7719,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ee_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2140] + (const void *)&gInstructions[2150] }; const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp = @@ -7632,7 +7736,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_de_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2142] + (const void *)&gInstructions[2152] }; const ND_TABLE_VEX_PP gVexTable_root_01_de_pp = @@ -7649,7 +7753,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_de_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ea_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2154] + (const void *)&gInstructions[2164] }; const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp = @@ -7666,7 +7770,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_da_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2156] + (const void *)&gInstructions[2166] }; const ND_TABLE_VEX_PP gVexTable_root_01_da_pp = @@ -7683,7 +7787,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_da_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d7_01_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2170] + (const void *)&gInstructions[2180] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_d7_01_modrmmod = @@ -7709,7 +7813,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e4_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2230] + (const void *)&gInstructions[2240] }; const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp = @@ -7726,7 +7830,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2232] + (const void *)&gInstructions[2242] }; const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp = @@ -7743,7 +7847,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2237] + (const void *)&gInstructions[2247] }; const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp = @@ -7760,7 +7864,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f4_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2240] + (const void *)&gInstructions[2250] }; const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp = @@ -7777,7 +7881,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_eb_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2245] + (const void *)&gInstructions[2255] }; const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp = @@ -7794,7 +7898,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2271] + (const void *)&gInstructions[2281] }; const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp = @@ -7811,19 +7915,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_70_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2308] + (const void *)&gInstructions[2318] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_70_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2310] + (const void *)&gInstructions[2320] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_70_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2312] + (const void *)&gInstructions[2322] }; const ND_TABLE_VEX_PP gVexTable_root_01_70_pp = @@ -7840,19 +7944,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_70_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2318] + (const void *)&gInstructions[2328] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2337] + (const void *)&gInstructions[2347] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2351] + (const void *)&gInstructions[2361] }; const ND_TABLE_MODRM_REG gVexTable_root_01_72_01_reg_modrmreg = @@ -7893,7 +7997,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_72_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2319] + (const void *)&gInstructions[2329] }; const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp = @@ -7910,25 +8014,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2321] + (const void *)&gInstructions[2331] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2324] + (const void *)&gInstructions[2334] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2354] + (const void *)&gInstructions[2364] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2357] + (const void *)&gInstructions[2367] }; const ND_TABLE_MODRM_REG gVexTable_root_01_73_01_reg_modrmreg = @@ -7969,7 +8073,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_73_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2325] + (const void *)&gInstructions[2335] }; const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp = @@ -7986,19 +8090,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2333] + (const void *)&gInstructions[2343] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2347] + (const void *)&gInstructions[2357] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2366] + (const void *)&gInstructions[2376] }; const ND_TABLE_MODRM_REG gVexTable_root_01_71_01_reg_modrmreg = @@ -8039,7 +8143,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_71_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2334] + (const void *)&gInstructions[2344] }; const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp = @@ -8056,7 +8160,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2338] + (const void *)&gInstructions[2348] }; const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp = @@ -8073,7 +8177,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2348] + (const void *)&gInstructions[2358] }; const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp = @@ -8090,7 +8194,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2352] + (const void *)&gInstructions[2362] }; const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp = @@ -8107,7 +8211,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2358] + (const void *)&gInstructions[2368] }; const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp = @@ -8124,7 +8228,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2367] + (const void *)&gInstructions[2377] }; const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp = @@ -8141,7 +8245,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2369] + (const void *)&gInstructions[2379] }; const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp = @@ -8158,7 +8262,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fa_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2371] + (const void *)&gInstructions[2381] }; const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp = @@ -8175,7 +8279,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fb_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2373] + (const void *)&gInstructions[2383] }; const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp = @@ -8192,7 +8296,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2375] + (const void *)&gInstructions[2385] }; const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp = @@ -8209,7 +8313,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2377] + (const void *)&gInstructions[2387] }; const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp = @@ -8226,7 +8330,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2379] + (const void *)&gInstructions[2389] }; const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp = @@ -8243,7 +8347,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2381] + (const void *)&gInstructions[2391] }; const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp = @@ -8260,7 +8364,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2383] + (const void *)&gInstructions[2393] }; const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp = @@ -8277,7 +8381,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_68_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2396] + (const void *)&gInstructions[2406] }; const ND_TABLE_VEX_PP gVexTable_root_01_68_pp = @@ -8294,7 +8398,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_68_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2398] + (const void *)&gInstructions[2408] }; const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp = @@ -8311,7 +8415,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2400] + (const void *)&gInstructions[2410] }; const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp = @@ -8328,7 +8432,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_69_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2402] + (const void *)&gInstructions[2412] }; const ND_TABLE_VEX_PP gVexTable_root_01_69_pp = @@ -8345,7 +8449,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_69_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_60_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2404] + (const void *)&gInstructions[2414] }; const ND_TABLE_VEX_PP gVexTable_root_01_60_pp = @@ -8362,7 +8466,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_60_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_62_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2406] + (const void *)&gInstructions[2416] }; const ND_TABLE_VEX_PP gVexTable_root_01_62_pp = @@ -8379,7 +8483,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_62_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2408] + (const void *)&gInstructions[2418] }; const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp = @@ -8396,7 +8500,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_61_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2410] + (const void *)&gInstructions[2420] }; const ND_TABLE_VEX_PP gVexTable_root_01_61_pp = @@ -8413,7 +8517,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_61_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ef_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2411] + (const void *)&gInstructions[2421] }; const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp = @@ -8430,13 +8534,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_53_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2426] + (const void *)&gInstructions[2436] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_53_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2427] + (const void *)&gInstructions[2437] }; const ND_TABLE_VEX_PP gVexTable_root_01_53_pp = @@ -8453,13 +8557,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_53_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_52_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2448] + (const void *)&gInstructions[2458] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_52_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2449] + (const void *)&gInstructions[2459] }; const ND_TABLE_VEX_PP gVexTable_root_01_52_pp = @@ -8476,13 +8580,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_52_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2471] + (const void *)&gInstructions[2481] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2473] + (const void *)&gInstructions[2483] }; const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp = @@ -8499,25 +8603,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_51_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2475] + (const void *)&gInstructions[2485] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_51_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2477] + (const void *)&gInstructions[2487] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_51_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2479] + (const void *)&gInstructions[2489] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_51_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2481] + (const void *)&gInstructions[2491] }; const ND_TABLE_VEX_PP gVexTable_root_01_51_pp = @@ -8534,25 +8638,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_51_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2484] + (const void *)&gInstructions[2494] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2486] + (const void *)&gInstructions[2496] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2488] + (const void *)&gInstructions[2498] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2490] + (const void *)&gInstructions[2500] }; const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp = @@ -8569,13 +8673,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2494] + (const void *)&gInstructions[2504] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2496] + (const void *)&gInstructions[2506] }; const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp = @@ -8592,13 +8696,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_15_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2498] + (const void *)&gInstructions[2508] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_15_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2500] + (const void *)&gInstructions[2510] }; const ND_TABLE_VEX_PP gVexTable_root_01_15_pp = @@ -8615,13 +8719,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_15_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_14_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2502] + (const void *)&gInstructions[2512] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_14_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2504] + (const void *)&gInstructions[2514] }; const ND_TABLE_VEX_PP gVexTable_root_01_14_pp = @@ -8638,13 +8742,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_14_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_57_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2506] + (const void *)&gInstructions[2516] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_57_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2508] + (const void *)&gInstructions[2518] }; const ND_TABLE_VEX_PP gVexTable_root_01_57_pp = @@ -8661,13 +8765,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_57_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2509] + (const void *)&gInstructions[2519] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2510] + (const void *)&gInstructions[2520] }; const ND_TABLE_VEX_L gVexTable_root_01_77_00_l = @@ -8958,13 +9062,13 @@ const ND_TABLE_OPCODE gVexTable_root_01_opcode = const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[538] + (const void *)&gInstructions[540] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[541] + (const void *)&gInstructions[543] }; const ND_TABLE_VEX_W gVexTable_root_03_32_01_reg_00_w = @@ -9010,13 +9114,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_32_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[539] + (const void *)&gInstructions[541] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[540] + (const void *)&gInstructions[542] }; const ND_TABLE_VEX_W gVexTable_root_03_33_01_reg_00_w = @@ -9062,13 +9166,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_33_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[542] + (const void *)&gInstructions[544] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[545] + (const void *)&gInstructions[547] }; const ND_TABLE_VEX_W gVexTable_root_03_30_01_reg_00_w = @@ -9114,13 +9218,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_30_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[543] + (const void *)&gInstructions[545] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[544] + (const void *)&gInstructions[546] }; const ND_TABLE_VEX_W gVexTable_root_03_31_01_reg_00_w = @@ -9166,7 +9270,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_31_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_f0_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1165] + (const void *)&gInstructions[1167] }; const ND_TABLE_VEX_L gVexTable_root_03_f0_03_l = @@ -9194,7 +9298,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_f0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_df_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1371] + (const void *)&gInstructions[1377] }; const ND_TABLE_VEX_L gVexTable_root_03_df_01_l = @@ -9222,7 +9326,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_df_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1384] + (const void *)&gInstructions[1390] }; const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp = @@ -9239,7 +9343,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1385] + (const void *)&gInstructions[1391] }; const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp = @@ -9256,7 +9360,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_4b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1386] + (const void *)&gInstructions[1392] }; const ND_TABLE_VEX_W gVexTable_root_03_4b_01_w = @@ -9282,7 +9386,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_4a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1387] + (const void *)&gInstructions[1393] }; const ND_TABLE_VEX_W gVexTable_root_03_4a_01_w = @@ -9308,7 +9412,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1442] + (const void *)&gInstructions[1448] }; const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w = @@ -9323,7 +9427,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w = const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1443] + (const void *)&gInstructions[1449] }; const ND_TABLE_VEX_W gVexTable_root_03_1d_01_01_w = @@ -9360,7 +9464,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_1d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_41_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1497] + (const void *)&gInstructions[1503] }; const ND_TABLE_VEX_L gVexTable_root_03_41_01_l = @@ -9388,7 +9492,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_41_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_40_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1498] + (const void *)&gInstructions[1504] }; const ND_TABLE_VEX_PP gVexTable_root_03_40_pp = @@ -9405,7 +9509,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_40_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_19_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1505] + (const void *)&gInstructions[1511] }; const ND_TABLE_VEX_W gVexTable_root_03_19_01_01_w = @@ -9442,7 +9546,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_19_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_39_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1510] + (const void *)&gInstructions[1516] }; const ND_TABLE_VEX_W gVexTable_root_03_39_01_01_w = @@ -9479,7 +9583,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_39_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1517] + (const void *)&gInstructions[1523] }; const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l = @@ -9496,7 +9600,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1518] + (const void *)&gInstructions[1524] }; const ND_TABLE_VEX_L gVexTable_root_03_17_01_reg_l = @@ -9533,13 +9637,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_17_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1547] + (const void *)&gInstructions[1553] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1548] + (const void *)&gInstructions[1554] }; const ND_TABLE_VEX_W gVexTable_root_03_69_01_w = @@ -9565,13 +9669,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_69_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1549] + (const void *)&gInstructions[1555] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1550] + (const void *)&gInstructions[1556] }; const ND_TABLE_VEX_W gVexTable_root_03_68_01_w = @@ -9597,13 +9701,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_68_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1551] + (const void *)&gInstructions[1557] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1552] + (const void *)&gInstructions[1558] }; const ND_TABLE_VEX_W gVexTable_root_03_6b_01_w = @@ -9629,13 +9733,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1553] + (const void *)&gInstructions[1559] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1554] + (const void *)&gInstructions[1560] }; const ND_TABLE_VEX_W gVexTable_root_03_6a_01_w = @@ -9661,13 +9765,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1567] + (const void *)&gInstructions[1573] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1568] + (const void *)&gInstructions[1574] }; const ND_TABLE_VEX_W gVexTable_root_03_5d_01_w = @@ -9693,13 +9797,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1569] + (const void *)&gInstructions[1575] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1570] + (const void *)&gInstructions[1576] }; const ND_TABLE_VEX_W gVexTable_root_03_5c_01_w = @@ -9725,13 +9829,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1607] + (const void *)&gInstructions[1613] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1608] + (const void *)&gInstructions[1614] }; const ND_TABLE_VEX_W gVexTable_root_03_5f_01_w = @@ -9757,13 +9861,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1609] + (const void *)&gInstructions[1615] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1610] + (const void *)&gInstructions[1616] }; const ND_TABLE_VEX_W gVexTable_root_03_5e_01_w = @@ -9789,13 +9893,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1611] + (const void *)&gInstructions[1617] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1612] + (const void *)&gInstructions[1618] }; const ND_TABLE_VEX_W gVexTable_root_03_6d_01_w = @@ -9821,13 +9925,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1613] + (const void *)&gInstructions[1619] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1614] + (const void *)&gInstructions[1620] }; const ND_TABLE_VEX_W gVexTable_root_03_6c_01_w = @@ -9853,13 +9957,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1615] + (const void *)&gInstructions[1621] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1616] + (const void *)&gInstructions[1622] }; const ND_TABLE_VEX_W gVexTable_root_03_6f_01_w = @@ -9885,13 +9989,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1617] + (const void *)&gInstructions[1623] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1618] + (const void *)&gInstructions[1624] }; const ND_TABLE_VEX_W gVexTable_root_03_6e_01_w = @@ -9917,13 +10021,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1643] + (const void *)&gInstructions[1649] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1644] + (const void *)&gInstructions[1650] }; const ND_TABLE_VEX_W gVexTable_root_03_79_01_w = @@ -9949,13 +10053,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_79_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1645] + (const void *)&gInstructions[1651] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1646] + (const void *)&gInstructions[1652] }; const ND_TABLE_VEX_W gVexTable_root_03_78_01_w = @@ -9981,13 +10085,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_78_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1647] + (const void *)&gInstructions[1653] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1648] + (const void *)&gInstructions[1654] }; const ND_TABLE_VEX_W gVexTable_root_03_7b_01_w = @@ -10013,13 +10117,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1649] + (const void *)&gInstructions[1655] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1650] + (const void *)&gInstructions[1656] }; const ND_TABLE_VEX_W gVexTable_root_03_7a_01_w = @@ -10045,13 +10149,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1675] + (const void *)&gInstructions[1681] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1676] + (const void *)&gInstructions[1682] }; const ND_TABLE_VEX_W gVexTable_root_03_7d_01_w = @@ -10077,13 +10181,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1677] + (const void *)&gInstructions[1683] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1678] + (const void *)&gInstructions[1684] }; const ND_TABLE_VEX_W gVexTable_root_03_7c_01_w = @@ -10109,13 +10213,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1679] + (const void *)&gInstructions[1685] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1680] + (const void *)&gInstructions[1686] }; const ND_TABLE_VEX_W gVexTable_root_03_7f_01_w = @@ -10141,13 +10245,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1681] + (const void *)&gInstructions[1687] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1682] + (const void *)&gInstructions[1688] }; const ND_TABLE_VEX_W gVexTable_root_03_7e_01_w = @@ -10173,7 +10277,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_cf_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1716] + (const void *)&gInstructions[1722] }; const ND_TABLE_VEX_W gVexTable_root_03_cf_01_w = @@ -10199,7 +10303,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_cf_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_ce_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1718] + (const void *)&gInstructions[1724] }; const ND_TABLE_VEX_W gVexTable_root_03_ce_01_w = @@ -10225,7 +10329,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_ce_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_18_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1725] + (const void *)&gInstructions[1731] }; const ND_TABLE_VEX_W gVexTable_root_03_18_01_01_w = @@ -10262,7 +10366,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_18_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_38_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1730] + (const void *)&gInstructions[1736] }; const ND_TABLE_VEX_W gVexTable_root_03_38_01_01_w = @@ -10299,7 +10403,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_38_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1737] + (const void *)&gInstructions[1743] }; const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l = @@ -10316,7 +10420,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1738] + (const void *)&gInstructions[1744] }; const ND_TABLE_VEX_L gVexTable_root_03_21_01_reg_l = @@ -10353,7 +10457,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_21_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_42_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1870] + (const void *)&gInstructions[1876] }; const ND_TABLE_VEX_PP gVexTable_root_03_42_pp = @@ -10370,7 +10474,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_42_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1928] + (const void *)&gInstructions[1934] }; const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp = @@ -10387,7 +10491,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_02_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1939] + (const void *)&gInstructions[1945] }; const ND_TABLE_VEX_W gVexTable_root_03_02_01_w = @@ -10413,7 +10517,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_02_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_4c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1944] + (const void *)&gInstructions[1950] }; const ND_TABLE_VEX_W gVexTable_root_03_4c_01_w = @@ -10439,7 +10543,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1945] + (const void *)&gInstructions[1951] }; const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp = @@ -10456,7 +10560,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_44_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1961] + (const void *)&gInstructions[1967] }; const ND_TABLE_VEX_PP gVexTable_root_03_44_pp = @@ -10473,7 +10577,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_44_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_61_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1974] + (const void *)&gInstructions[1980] }; const ND_TABLE_VEX_L gVexTable_root_03_61_01_l = @@ -10501,7 +10605,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_61_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_60_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1975] + (const void *)&gInstructions[1981] }; const ND_TABLE_VEX_L gVexTable_root_03_60_01_l = @@ -10529,7 +10633,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_60_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_63_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1984] + (const void *)&gInstructions[1990] }; const ND_TABLE_VEX_L gVexTable_root_03_63_01_l = @@ -10557,7 +10661,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_63_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_62_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1985] + (const void *)&gInstructions[1991] }; const ND_TABLE_VEX_L gVexTable_root_03_62_01_l = @@ -10585,7 +10689,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_62_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_06_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2010] + (const void *)&gInstructions[2020] }; const ND_TABLE_VEX_W gVexTable_root_03_06_01_01_w = @@ -10622,7 +10726,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_06_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_46_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2011] + (const void *)&gInstructions[2021] }; const ND_TABLE_VEX_W gVexTable_root_03_46_01_01_w = @@ -10659,13 +10763,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_46_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2021] + (const void *)&gInstructions[2031] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2022] + (const void *)&gInstructions[2032] }; const ND_TABLE_VEX_W gVexTable_root_03_49_01_w = @@ -10691,13 +10795,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_49_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2023] + (const void *)&gInstructions[2033] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2024] + (const void *)&gInstructions[2034] }; const ND_TABLE_VEX_W gVexTable_root_03_48_01_w = @@ -10723,7 +10827,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_48_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_05_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2028] + (const void *)&gInstructions[2038] }; const ND_TABLE_VEX_W gVexTable_root_03_05_01_w = @@ -10749,7 +10853,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_05_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_04_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2032] + (const void *)&gInstructions[2042] }; const ND_TABLE_VEX_W gVexTable_root_03_04_01_w = @@ -10775,7 +10879,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_04_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_01_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2036] + (const void *)&gInstructions[2046] }; const ND_TABLE_VEX_W gVexTable_root_03_01_01_01_w = @@ -10812,7 +10916,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_01_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_00_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2042] + (const void *)&gInstructions[2052] }; const ND_TABLE_VEX_W gVexTable_root_03_00_01_01_w = @@ -10849,7 +10953,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_00_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2056] + (const void *)&gInstructions[2066] }; const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l = @@ -10866,7 +10970,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2057] + (const void *)&gInstructions[2067] }; const ND_TABLE_VEX_L gVexTable_root_03_14_01_reg_l = @@ -10903,13 +11007,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_14_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2059] + (const void *)&gInstructions[2069] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2061] + (const void *)&gInstructions[2071] }; const ND_TABLE_VEX_W gVexTable_root_03_16_01_00_w = @@ -10946,7 +11050,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_16_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2066] + (const void *)&gInstructions[2076] }; const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l = @@ -10963,7 +11067,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2067] + (const void *)&gInstructions[2077] }; const ND_TABLE_VEX_L gVexTable_root_03_15_01_reg_l = @@ -11000,7 +11104,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_15_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2100] + (const void *)&gInstructions[2110] }; const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l = @@ -11017,7 +11121,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2101] + (const void *)&gInstructions[2111] }; const ND_TABLE_VEX_L gVexTable_root_03_20_01_reg_l = @@ -11054,13 +11158,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_20_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2103] + (const void *)&gInstructions[2113] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2105] + (const void *)&gInstructions[2115] }; const ND_TABLE_VEX_W gVexTable_root_03_22_01_00_w = @@ -11097,7 +11201,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_22_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_09_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2436] + (const void *)&gInstructions[2446] }; const ND_TABLE_VEX_PP gVexTable_root_03_09_pp = @@ -11114,7 +11218,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_09_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_08_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2437] + (const void *)&gInstructions[2447] }; const ND_TABLE_VEX_PP gVexTable_root_03_08_pp = @@ -11131,7 +11235,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_08_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2438] + (const void *)&gInstructions[2448] }; const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp = @@ -11148,7 +11252,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2439] + (const void *)&gInstructions[2449] }; const ND_TABLE_VEX_PP gVexTable_root_03_0a_pp = diff --git a/bddisasm/include/table_xop.h b/bddisasm/include/table_xop.h index 5bbe35d..b7ee67e 100644 --- a/bddisasm/include/table_xop.h +++ b/bddisasm/include/table_xop.h @@ -10,13 +10,13 @@ const ND_TABLE_INSTRUCTION gXopTable_root_0a_10_leaf = const ND_TABLE_INSTRUCTION gXopTable_root_0a_12_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[595] + (const void *)&gInstructions[597] }; const ND_TABLE_INSTRUCTION gXopTable_root_0a_12_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[596] + (const void *)&gInstructions[598] }; const ND_TABLE_MODRM_REG gXopTable_root_0a_12_modrmreg = @@ -330,13 +330,13 @@ const ND_TABLE_INSTRUCTION gXopTable_root_09_01_06_leaf = const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1313] + (const void *)&gInstructions[1317] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1336] + (const void *)&gInstructions[1341] }; const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg = @@ -384,13 +384,13 @@ const ND_TABLE_MODRM_REG gXopTable_root_09_02_modrmreg = const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[577] + (const void *)&gInstructions[579] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1265] + (const void *)&gInstructions[1268] }; const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg = @@ -420,127 +420,127 @@ const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod = const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1687] + (const void *)&gInstructions[1693] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1688] + (const void *)&gInstructions[1694] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1689] + (const void *)&gInstructions[1695] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1690] + (const void *)&gInstructions[1696] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2076] + (const void *)&gInstructions[2086] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2077] + (const void *)&gInstructions[2087] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2078] + (const void *)&gInstructions[2088] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2080] + (const void *)&gInstructions[2090] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2082] + (const void *)&gInstructions[2092] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2083] + (const void *)&gInstructions[2093] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2084] + (const void *)&gInstructions[2094] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2085] + (const void *)&gInstructions[2095] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2086] + (const void *)&gInstructions[2096] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2087] + (const void *)&gInstructions[2097] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2089] + (const void *)&gInstructions[2099] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2090] + (const void *)&gInstructions[2100] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2092] + (const void *)&gInstructions[2102] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2094] + (const void *)&gInstructions[2104] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2097] + (const void *)&gInstructions[2107] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2259] + (const void *)&gInstructions[2269] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2260] + (const void *)&gInstructions[2270] }; const ND_TABLE_VEX_W gXopTable_root_09_90_w = @@ -555,13 +555,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_90_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2262] + (const void *)&gInstructions[2272] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2263] + (const void *)&gInstructions[2273] }; const ND_TABLE_VEX_W gXopTable_root_09_92_w = @@ -576,13 +576,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_92_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2265] + (const void *)&gInstructions[2275] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2266] + (const void *)&gInstructions[2276] }; const ND_TABLE_VEX_W gXopTable_root_09_93_w = @@ -597,13 +597,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_93_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2268] + (const void *)&gInstructions[2278] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2269] + (const void *)&gInstructions[2279] }; const ND_TABLE_VEX_W gXopTable_root_09_91_w = @@ -618,13 +618,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_91_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2276] + (const void *)&gInstructions[2286] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2277] + (const void *)&gInstructions[2287] }; const ND_TABLE_VEX_W gXopTable_root_09_98_w = @@ -639,13 +639,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_98_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2278] + (const void *)&gInstructions[2288] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2279] + (const void *)&gInstructions[2289] }; const ND_TABLE_VEX_W gXopTable_root_09_9a_w = @@ -660,13 +660,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9a_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2280] + (const void *)&gInstructions[2290] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2281] + (const void *)&gInstructions[2291] }; const ND_TABLE_VEX_W gXopTable_root_09_9b_w = @@ -681,13 +681,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9b_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2282] + (const void *)&gInstructions[2292] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2283] + (const void *)&gInstructions[2293] }; const ND_TABLE_VEX_W gXopTable_root_09_99_w = @@ -702,13 +702,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_99_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2284] + (const void *)&gInstructions[2294] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2285] + (const void *)&gInstructions[2295] }; const ND_TABLE_VEX_W gXopTable_root_09_94_w = @@ -723,13 +723,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_94_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2286] + (const void *)&gInstructions[2296] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2297] + (const void *)&gInstructions[2307] }; const ND_TABLE_VEX_W gXopTable_root_09_95_w = @@ -744,13 +744,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_95_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2287] + (const void *)&gInstructions[2297] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2288] + (const void *)&gInstructions[2298] }; const ND_TABLE_VEX_W gXopTable_root_09_96_w = @@ -765,13 +765,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_96_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2295] + (const void *)&gInstructions[2305] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2296] + (const void *)&gInstructions[2306] }; const ND_TABLE_VEX_W gXopTable_root_09_97_w = @@ -1049,13 +1049,13 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode = const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1962] + (const void *)&gInstructions[1968] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1963] + (const void *)&gInstructions[1969] }; const ND_TABLE_VEX_W gXopTable_root_08_a2_w = @@ -1070,133 +1070,133 @@ const ND_TABLE_VEX_W gXopTable_root_08_a2_w = const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1992] + (const void *)&gInstructions[1998] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1993] + (const void *)&gInstructions[1999] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1998] + (const void *)&gInstructions[2004] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1999] + (const void *)&gInstructions[2005] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2000] + (const void *)&gInstructions[2006] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2001] + (const void *)&gInstructions[2007] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2002] + (const void *)&gInstructions[2008] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2003] + (const void *)&gInstructions[2009] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2112] + (const void *)&gInstructions[2122] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2113] + (const void *)&gInstructions[2123] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2114] + (const void *)&gInstructions[2124] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2115] + (const void *)&gInstructions[2125] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2116] + (const void *)&gInstructions[2126] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2117] + (const void *)&gInstructions[2127] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2118] + (const void *)&gInstructions[2128] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2119] + (const void *)&gInstructions[2129] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2120] + (const void *)&gInstructions[2130] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2121] + (const void *)&gInstructions[2131] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2122] + (const void *)&gInstructions[2132] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2123] + (const void *)&gInstructions[2133] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2248] + (const void *)&gInstructions[2258] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2249] + (const void *)&gInstructions[2259] }; const ND_TABLE_VEX_W gXopTable_root_08_a3_w = @@ -1211,25 +1211,25 @@ const ND_TABLE_VEX_W gXopTable_root_08_a3_w = const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2258] + (const void *)&gInstructions[2268] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2261] + (const void *)&gInstructions[2271] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2264] + (const void *)&gInstructions[2274] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2267] + (const void *)&gInstructions[2277] }; const ND_TABLE_OPCODE gXopTable_root_08_opcode = diff --git a/bddisasm/include/tabledefs.h b/bddisasm/include/tabledefs.h index d52d206..c522b5b 100644 --- a/bddisasm/include/tabledefs.h +++ b/bddisasm/include/tabledefs.h @@ -398,6 +398,7 @@ typedef enum _ND_OPERAND_TYPE_SPEC ND_OPT_MXCSR, ND_OPT_PKRU, ND_OPT_SSP, + ND_OPT_UIF, // General Purpose REgisters. ND_OPT_GPR_AH, diff --git a/bddisasm_test/avx/avxvnni_64 b/bddisasm_test/avx/avxvnni_64 new file mode 100644 index 0000000..42fb709 --- /dev/null +++ b/bddisasm_test/avx/avxvnni_64 @@ -0,0 +1 @@ +ÄâyP#Äâ}P#ÄâyQ#Äâ}Q#ÄâyR#Äâ}R#ÄâyS#Äâ}S# \ No newline at end of file diff --git a/bddisasm_test/avx/avxvnni_64.asm b/bddisasm_test/avx/avxvnni_64.asm new file mode 100644 index 0000000..66b73e4 --- /dev/null +++ b/bddisasm_test/avx/avxvnni_64.asm @@ -0,0 +1,10 @@ + bits 64 + + db 0xc4, 0xe2, 0x79, 0x50, 0x23 ; VPDPBUSD xmm4, xmm0, xmmword ptr [rbx] + db 0xc4, 0xe2, 0x7d, 0x50, 0x23 ; VPDPBUSD ymm4, ymm0, ymmword ptr [rbx] + db 0xc4, 0xe2, 0x79, 0x51, 0x23 ; VPDPBUSDS xmm4, xmm0, xmmword ptr [rbx] + db 0xc4, 0xe2, 0x7d, 0x51, 0x23 ; VPDPBUSDS ymm4, ymm0, ymmword ptr [rbx] + db 0xc4, 0xe2, 0x79, 0x52, 0x23 ; VPDPWSSD xmm4, xmm0, xmmword ptr [rbx] + db 0xc4, 0xe2, 0x7d, 0x52, 0x23 ; VPDPWSSD ymm4, ymm0, ymmword ptr [rbx] + db 0xc4, 0xe2, 0x79, 0x53, 0x23 ; VPDPWSSDS xmm4, xmm0, xmmword ptr [rbx] + db 0xc4, 0xe2, 0x7d, 0x53, 0x23 ; VPDPWSSDS ymm4, ymm0, ymmword ptr [rbx] \ No newline at end of file diff --git a/bddisasm_test/avx/avxvnni_64.result b/bddisasm_test/avx/avxvnni_64.result new file mode 100644 index 0000000..37b851f --- /dev/null +++ b/bddisasm_test/avx/avxvnni_64.result @@ -0,0 +1,152 @@ +0000000000000000 c4e2795023 VPDPBUSD xmm4, xmm0, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVXVNNI, Ins cat: AVXVNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 4 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000005 c4e27d5023 VPDPBUSD ymm4, ymm0, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVXVNNI, Ins cat: AVXVNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 4 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000000A c4e2795123 VPDPBUSDS xmm4, xmm0, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVXVNNI, Ins cat: AVXVNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 4 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +000000000000000F c4e27d5123 VPDPBUSDS ymm4, ymm0, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVXVNNI, Ins cat: AVXVNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 4 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +0000000000000014 c4e2795223 VPDPWSSD xmm4, xmm0, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVXVNNI, Ins cat: AVXVNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 4 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000019 c4e27d5223 VPDPWSSD ymm4, ymm0, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVXVNNI, Ins cat: AVXVNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 4 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + +000000000000001E c4e2795323 VPDPWSSDS xmm4, xmm0, xmmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: AVXVNNI, Ins cat: AVXVNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 4 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 3, + +0000000000000023 c4e27d5323 VPDPWSSDS ymm4, ymm0, ymmword ptr [rbx] + DSIZE: 32, ASIZE: 64, VLEN: 256 + ISA Set: AVXVNNI, Ins cat: AVXVNNI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 4 + Exception class: SSE/VEX, exception type: 4 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 4, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M, + Segment: 3, Base: 3, + diff --git a/bddisasm_test/basic/system_64 b/bddisasm_test/basic/system_64 index cd6788eed273735264340be451d680d4fe3f36f8..863b9dd3ae3af1c0474349f3340334cba871b094 100644 GIT binary patch delta 13 UcmZo?>}8zL&i0w#>cfG(03vY(-2eap delta 6 NcmeBWY-gO%4gd!q0xkdm diff --git a/bddisasm_test/basic/system_64.asm b/bddisasm_test/basic/system_64.asm index 698b891..9c57482 100644 --- a/bddisasm_test/basic/system_64.asm +++ b/bddisasm_test/basic/system_64.asm @@ -53,4 +53,6 @@ invd wbinvd - db 0x0F, 0x01, 0xE8 ; serialize \ No newline at end of file + db 0x0F, 0x01, 0xE8 ; serialize + + db 0xF3, 0x0F, 0x3A, 0xF0, 0xC0, 0xBD ; hreset \ No newline at end of file diff --git a/bddisasm_test/basic/system_64.result b/bddisasm_test/basic/system_64.result index 550cf02..d774351 100644 --- a/bddisasm_test/basic/system_64.result +++ b/bddisasm_test/basic/system_64.result @@ -661,3 +661,19 @@ HLE: no, XACQUIRE only: no, XRELEASE only: no BND: no, BHINT: no, DNT: no +0000000000000087 f30f3af0c0bd HRESET 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: HRESET, Ins cat: HRESET, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 22 + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: yes, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: --, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/uintr/uintr_64 b/bddisasm_test/uintr/uintr_64 new file mode 100644 index 0000000..f2e6060 --- /dev/null +++ b/bddisasm_test/uintr/uintr_64 @@ -0,0 +1 @@ +óìóíóîóïóÇñ \ No newline at end of file diff --git a/bddisasm_test/uintr/uintr_64.asm b/bddisasm_test/uintr/uintr_64.asm new file mode 100644 index 0000000..e9663c8 --- /dev/null +++ b/bddisasm_test/uintr/uintr_64.asm @@ -0,0 +1,7 @@ + bits 64 + + db 0xf3, 0x0f, 0x01, 0xec ; uiret + db 0xf3, 0x0f, 0x01, 0xed ; testui + db 0xf3, 0x0f, 0x01, 0xee ; clui + db 0xf3, 0x0f, 0x01, 0xef ; stui + db 0xf3, 0x0f, 0xc7, 0xf1 ; senduipi rcx \ No newline at end of file diff --git a/bddisasm_test/uintr/uintr_64.result b/bddisasm_test/uintr/uintr_64.result new file mode 100644 index 0000000..bda44b5 --- /dev/null +++ b/bddisasm_test/uintr/uintr_64.result @@ -0,0 +1,87 @@ +0000000000000000 f30f01ec UIRET + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: UINTR, Ins cat: UINTR, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 5 + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: IP, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 4, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: UIF, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 4, Acc: R-, Type: Memory, Size: 24, RawSize: 24, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + Operand: 5, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: S, Shadow stack: 3, + + +0000000000000004 f30f01ed TESTUI + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: UINTR, Ins cat: UINTR, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 5 + FLAGS access + CF: m, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: UIF, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000008 f30f01ee CLUI + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: UINTR, Ins cat: UINTR, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: UIF, RegSize: 1, RegId: 0, RegCount: 1 + +000000000000000C f30f01ef STUI + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: UINTR, Ins cat: UINTR, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: UIF, RegSize: 1, RegId: 0, RegCount: 1 + +0000000000000010 f30fc7f1 SENDUIPI rcx + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: UINTR, Ins cat: UINTR, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: edx, bit: 5 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + diff --git a/disasmtool/disasmtool.c b/disasmtool/disasmtool.c index 610e929..727fb75 100644 --- a/disasmtool/disasmtool.c +++ b/disasmtool/disasmtool.c @@ -115,6 +115,7 @@ const char* set_to_string( case ND_SET_AVX512VNNI: return "AVX512VNNI"; case ND_SET_AVX512VP2INTERSECT: return "AVX512VP2INTERSECT"; case ND_SET_AVX512VPOPCNTDQ: return "AVX512VPOPCNTDQ"; + case ND_SET_AVXVNNI: return "AVXVNNI"; case ND_SET_BMI1: return "BMI1"; case ND_SET_BMI2: return "BMI2"; case ND_SET_CET_SS: return "CET_SS"; @@ -133,6 +134,7 @@ const char* set_to_string( case ND_SET_FMA4: return "FMA4"; case ND_SET_FXSAVE: return "FXSAVE"; case ND_SET_GFNI: return "GFNI"; + case ND_SET_HRESET: return "HRESET"; case ND_SET_I186: return "I186"; case ND_SET_I286PROT: return "I286PROT"; case ND_SET_I286REAL: return "I286REAL"; @@ -191,6 +193,7 @@ const char* set_to_string( case ND_SET_TSX: return "TSX"; case ND_SET_TSXLDTRK: return "TSXLDTRK"; case ND_SET_UD: return "UD"; + case ND_SET_UINTR: return "UINTR"; case ND_SET_UNKNOWN: return "UNKNOWN"; case ND_SET_VAES: return "VAES"; case ND_SET_VPCLMULQDQ: return "VPCLMULQDQ"; @@ -228,6 +231,7 @@ const char* category_to_string( case ND_CAT_AVX512BF16: return "AVX512BF16"; case ND_CAT_AVX512VBMI: return "AVX512VBMI"; case ND_CAT_AVX512VP2INTERSECT: return "AVX512VP2INTERSECT"; + case ND_CAT_AVXVNNI: return "AVXVNNI"; case ND_CAT_BITBYTE: return "BITBYTE"; case ND_CAT_BLEND: return "BLEND"; case ND_CAT_BMI1: return "BMI1"; @@ -249,6 +253,7 @@ const char* category_to_string( case ND_CAT_FMA4: return "FMA4"; case ND_CAT_GATHER: return "GATHER"; case ND_CAT_GFNI: return "GFNI"; + case ND_CAT_HRESET: return "HRESET"; case ND_CAT_I386: return "I386"; case ND_CAT_IFMA: return "IFMA"; case ND_CAT_INTERRUPT: return "INTERRUPT"; @@ -297,6 +302,7 @@ const char* category_to_string( case ND_CAT_SYSTEM: return "SYSTEM"; case ND_CAT_TDX: return "TDX"; case ND_CAT_UD: return "UD"; + case ND_CAT_UINTR: return "UINTR"; case ND_CAT_UNCOND_BR: return "UNCOND_BR"; case ND_CAT_UNKNOWN: return "UNKNOWN"; case ND_CAT_VAES: return "VAES"; @@ -368,6 +374,7 @@ const char* regtype_to_string( case ND_REG_SSP: return "SSP"; case ND_REG_FLG: return "Flags"; case ND_REG_RIP: return "IP"; + case ND_REG_UIF: return "UIF"; default: return "???"; } } diff --git a/disasmtool_lix/dumpers.cpp b/disasmtool_lix/dumpers.cpp index 775e297..00877d8 100644 --- a/disasmtool_lix/dumpers.cpp +++ b/disasmtool_lix/dumpers.cpp @@ -1540,6 +1540,14 @@ std::string ins_class_to_str(const ND_INS_CLASS cls) case ND_INS_XSUSLDTRK: return "xsusldtrk"; case ND_INS_XSTORE: return "xstore"; case ND_INS_XTEST: return "xtest"; + + case ND_INS_HRESET: return "hreset"; + + case ND_INS_CLUI: return "clui"; + case ND_INS_STUI: return "stui"; + case ND_INS_TESTUI: return "testui"; + case ND_INS_UIRET: return "uiret"; + case ND_INS_SENDUIPI: return "senduipi"; } return ""; @@ -1562,6 +1570,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category) case ND_CAT_AVX512BF16: return "avx512bf16"; case ND_CAT_AVX512VBMI: return "avx512vbmi"; case ND_CAT_AVX512VP2INTERSECT: return "avx512vp2intersect"; + case ND_CAT_AVXVNNI: return "avxvnni"; case ND_CAT_BITBYTE: return "bitbyte"; case ND_CAT_BLEND: return "blend"; case ND_CAT_BMI1: return "bmi1"; @@ -1583,6 +1592,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category) case ND_CAT_FMA4: return "fma4"; case ND_CAT_GATHER: return "gather"; case ND_CAT_GFNI: return "gfni"; + case ND_CAT_HRESET: return "hreset"; case ND_CAT_I386: return "i386"; case ND_CAT_IFMA: return "ifma"; case ND_CAT_INTERRUPT: return "interrupt"; @@ -1631,6 +1641,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category) case ND_CAT_SYSTEM: return "system"; case ND_CAT_TDX: return "tdx"; case ND_CAT_UD: return "ud"; + case ND_CAT_UINTR: return "uintr"; case ND_CAT_UNCOND_BR: return "uncond_br"; case ND_CAT_UNKNOWN: return "unknown"; case ND_CAT_VAES: return "vaes"; @@ -1684,6 +1695,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set) case ND_SET_AVX512VNNI: return "avx512vnni"; case ND_SET_AVX512VP2INTERSECT: return "avx512vp2intersect"; case ND_SET_AVX512VPOPCNTDQ: return "avx512vpopcntdq"; + case ND_SET_AVXVNNI: return "avxvnni"; case ND_SET_BMI1: return "bmi1"; case ND_SET_BMI2: return "bmi2"; case ND_SET_CET_SS: return "cet_ss"; @@ -1702,6 +1714,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set) case ND_SET_FMA4: return "fma4"; case ND_SET_FXSAVE: return "fxsave"; case ND_SET_GFNI: return "gfni"; + case ND_SET_HRESET: return "hreset"; case ND_SET_I186: return "i186"; case ND_SET_INVLPGB: return "invlpgb"; case ND_SET_I286PROT: return "i286prot"; @@ -1760,6 +1773,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set) case ND_SET_TSX: return "tsx"; case ND_SET_TSXLDTRK: return "tsxldtrk"; case ND_SET_UD: return "ud"; + case ND_SET_UINTR: return "uintr"; case ND_SET_UNKNOWN: return "unknown"; case ND_SET_VAES: return "vaes"; case ND_SET_VPCLMULQDQ: return "vpclmulqdq"; @@ -1855,6 +1869,8 @@ std::string reg_to_str(const int reg, const ND_REG_TYPE type) return "flg"; case ND_REG_RIP: return "rip"; + case ND_REG_UIF: + return "uif"; } return ""; @@ -1906,6 +1922,8 @@ std::string reg_type_to_str(const ND_REG_TYPE type) return "flg"; case ND_REG_RIP: return "rip"; + case ND_REG_UIF: + return "uif"; } return ""; diff --git a/inc/bddisasm.h b/inc/bddisasm.h index 5cfc477..72d3bfb 100644 --- a/inc/bddisasm.h +++ b/inc/bddisasm.h @@ -376,11 +376,11 @@ typedef uint32_t ND_REG_SIZE; // // Sign extend 8 bit to 64 bit. -#define ND_SIGN_EX_8(x) ((x) & 0x00000080 ? 0xFFFFFFFFFFFFFF00 | (x) : (x)) +#define ND_SIGN_EX_8(x) (((x) & 0x00000080) ? (0xFFFFFFFFFFFFFF00 | (x)) : (x)) // Sign extend 16 bit to 64 bit. -#define ND_SIGN_EX_16(x) ((x) & 0x00008000 ? 0xFFFFFFFFFFFF0000 | (x) : (x)) +#define ND_SIGN_EX_16(x) (((x) & 0x00008000) ? (0xFFFFFFFFFFFF0000 | (x)) : (x)) // Sign extend 32 bit to 64 bit. -#define ND_SIGN_EX_32(x) ((x) & 0x80000000 ? 0xFFFFFFFF00000000 | (x) : (x)) +#define ND_SIGN_EX_32(x) (((x) & 0x80000000) ? (0xFFFFFFFF00000000 | (x)) : (x)) // Wrapper for for ND_SIGN_EX_8/ND_SIGN_EX_16/ND_SIGN_EX_32. Sign extend sz bytes to 64 bits. #define ND_SIGN_EX(sz, x) ((sz) == 1 ? ND_SIGN_EX_8(x) : (sz) == 2 ? ND_SIGN_EX_16(x) : \ (sz) == 4 ? ND_SIGN_EX_32(x) : (x)) @@ -511,6 +511,7 @@ typedef enum _ND_REG_TYPE ND_REG_SSP, // The register is the SSP (Shadow Stack Pointer) register. ND_REG_FLG, // The register is the FLAGS register. ND_REG_RIP, // The register is the instruction pointer register. + ND_REG_UIF, // The register is the User Interrupt Flag. } ND_REG_TYPE; diff --git a/inc/constants.h b/inc/constants.h index c93171d..12db93d 100644 --- a/inc/constants.h +++ b/inc/constants.h @@ -96,6 +96,7 @@ typedef enum _ND_INS_CLASS ND_INS_CLI, ND_INS_CLRSSBSY, ND_INS_CLTS, + ND_INS_CLUI, ND_INS_CLWB, ND_INS_CLZERO, ND_INS_CMC, @@ -268,6 +269,7 @@ typedef enum _ND_INS_CLASS ND_INS_HADDPD, ND_INS_HADDPS, ND_INS_HLT, + ND_INS_HRESET, ND_INS_HSUBPD, ND_INS_HSUBPS, ND_INS_IDIV, @@ -636,6 +638,7 @@ typedef enum _ND_INS_CLASS ND_INS_SEAMCALL, ND_INS_SEAMOPS, ND_INS_SEAMRET, + ND_INS_SENDUIPI, ND_INS_SERIALIZE, ND_INS_SETSSBSY, ND_INS_SETcc, @@ -676,6 +679,7 @@ typedef enum _ND_INS_CLASS ND_INS_STOS, ND_INS_STR, ND_INS_STTILECFG, + ND_INS_STUI, ND_INS_SUB, ND_INS_SUBPD, ND_INS_SUBPS, @@ -697,6 +701,7 @@ typedef enum _ND_INS_CLASS ND_INS_TDPBUSD, ND_INS_TDPBUUD, ND_INS_TEST, + ND_INS_TESTUI, ND_INS_TILELOADD, ND_INS_TILELOADDT1, ND_INS_TILERELEASE, @@ -711,6 +716,7 @@ typedef enum _ND_INS_CLASS ND_INS_UD0, ND_INS_UD1, ND_INS_UD2, + ND_INS_UIRET, ND_INS_UMONITOR, ND_INS_UMWAIT, ND_INS_UNPCKHPD, @@ -1514,6 +1520,7 @@ typedef enum _ND_INS_SET ND_SET_AVX512VNNI, ND_SET_AVX512VP2INTERSECT, ND_SET_AVX512VPOPCNTDQ, + ND_SET_AVXVNNI, ND_SET_BMI1, ND_SET_BMI2, ND_SET_CET_IBT, @@ -1532,6 +1539,7 @@ typedef enum _ND_INS_SET ND_SET_FMA4, ND_SET_FXSAVE, ND_SET_GFNI, + ND_SET_HRESET, ND_SET_I186, ND_SET_I286PROT, ND_SET_I286REAL, @@ -1590,6 +1598,7 @@ typedef enum _ND_INS_SET ND_SET_TSX, ND_SET_TSXLDTRK, ND_SET_UD, + ND_SET_UINTR, ND_SET_UNKNOWN, ND_SET_VAES, ND_SET_VPCLMULQDQ, @@ -1620,6 +1629,7 @@ typedef enum _ND_INS_TYPE ND_CAT_AVX512BF16, ND_CAT_AVX512VBMI, ND_CAT_AVX512VP2INTERSECT, + ND_CAT_AVXVNNI, ND_CAT_BITBYTE, ND_CAT_BLEND, ND_CAT_BMI1, @@ -1641,6 +1651,7 @@ typedef enum _ND_INS_TYPE ND_CAT_FMA4, ND_CAT_GATHER, ND_CAT_GFNI, + ND_CAT_HRESET, ND_CAT_I386, ND_CAT_IFMA, ND_CAT_INTERRUPT, @@ -1689,6 +1700,7 @@ typedef enum _ND_INS_TYPE ND_CAT_SYSTEM, ND_CAT_TDX, ND_CAT_UD, + ND_CAT_UINTR, ND_CAT_UNCOND_BR, ND_CAT_UNKNOWN, ND_CAT_VAES, diff --git a/inc/cpuidflags.h b/inc/cpuidflags.h index 810095f..42868b8 100644 --- a/inc/cpuidflags.h +++ b/inc/cpuidflags.h @@ -76,15 +76,19 @@ #define ND_CFF_ENQCMD ND_CFF(0x00000007, 0x00000000, NDR_ECX, 29) #define ND_CFF_AVX5124VNNIW ND_CFF(0x00000007, 0x00000000, NDR_EDX, 2) #define ND_CFF_AVX5124FMAPS ND_CFF(0x00000007, 0x00000000, NDR_EDX, 3) +#define ND_CFF_UINTR ND_CFF(0x00000007, 0x00000000, NDR_EDX, 5) #define ND_CFF_AVX512VP2INTERSECT ND_CFF(0x00000007, 0x00000000, NDR_EDX, 8) #define ND_CFF_SERIALIZE ND_CFF(0x00000007, 0x00000000, NDR_EDX, 14) #define ND_CFF_TSXLDTRK ND_CFF(0x00000007, 0x00000000, NDR_EDX, 16) #define ND_CFF_PCONFIG ND_CFF(0x00000007, 0x00000000, NDR_EDX, 18) #define ND_CFF_CET_IBT ND_CFF(0x00000007, 0x00000000, NDR_EDX, 20) #define ND_CFF_AMXBF16 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 22) +#define ND_CFF_AVX512FP16 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 23) #define ND_CFF_AMXTILE ND_CFF(0x00000007, 0x00000000, NDR_EDX, 24) #define ND_CFF_AMXINT8 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 25) +#define ND_CFF_AVXVNNI ND_CFF(0x00000007, 0x00000001, NDR_EAX, 4) #define ND_CFF_AVX512BF16 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 5) +#define ND_CFF_HRESET ND_CFF(0x00000007, 0x00000001, NDR_EAX, 22) #define ND_CFF_XSAVEOPT ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 0) #define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1) #define ND_CFF_XSAVES ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 3) diff --git a/inc/version.h b/inc/version.h index 94d7bcf..8fed6ca 100644 --- a/inc/version.h +++ b/inc/version.h @@ -6,7 +6,7 @@ #define DISASM_VER_H #define DISASM_VERSION_MAJOR 1 -#define DISASM_VERSION_MINOR 30 +#define DISASM_VERSION_MINOR 31 #define DISASM_VERSION_REVISION 0 #endif // DISASM_VER_H diff --git a/isagenerator/disasmlib.py b/isagenerator/disasmlib.py index d25c256..47ed671 100644 --- a/isagenerator/disasmlib.py +++ b/isagenerator/disasmlib.py @@ -302,6 +302,8 @@ valid_impops = {# register size 'SHS2' : ('SHSP', 'v2'), # Shadow stack push/pop, 2 words. 'SHS3' : ('SHSP', 'v3'), # Shadow stack push/pop, 3 words. 'SHS4' : ('SHSP', 'v4'), # Shadow stack push/pop, 4 words. + # User Interrupt Flag. + 'UIF' : ('UIF', 'b'), # User Interrupt Flag, stored with size of 1 byte, although it is 1 bit. } # If an operand type is not present here, than that operand is implicit & it's not encoded inside the instruction. diff --git a/isagenerator/generate_tables.py b/isagenerator/generate_tables.py index 48da078..63f416f 100644 --- a/isagenerator/generate_tables.py +++ b/isagenerator/generate_tables.py @@ -181,6 +181,7 @@ optype = { 'MXCSR' : 'ND_OPT_MXCSR', 'PKRU' : 'ND_OPT_PKRU', 'SSP' : 'ND_OPT_SSP', + 'UIF' : 'ND_OPT_UIF' } opsize = { diff --git a/isagenerator/instructions/cpuid.dat b/isagenerator/instructions/cpuid.dat index aad5cac..94db9e8 100644 --- a/isagenerator/instructions/cpuid.dat +++ b/isagenerator/instructions/cpuid.dat @@ -76,17 +76,20 @@ MOVDIR64B : 0x00000007, 0x00000000, ECX, 28 ENQCMD : 0x00000007, 0x00000000, ECX, 29 AVX5124VNNIW : 0x00000007, 0x00000000, EDX, 2 AVX5124FMAPS : 0x00000007, 0x00000000, EDX, 3 +UINTR : 0x00000007, 0x00000000, EDX, 5 AVX512VP2INTERSECT : 0x00000007, 0x00000000, EDX, 8 SERIALIZE : 0x00000007, 0x00000000, EDX, 14 TSXLDTRK : 0x00000007, 0x00000000, EDX, 16 PCONFIG : 0x00000007, 0x00000000, EDX, 18 CET_IBT : 0x00000007, 0x00000000, EDX, 20 AMXBF16 : 0x00000007, 0x00000000, EDX, 22 +AVX512FP16 : 0x00000007, 0x00000000, EDX, 23 AMXTILE : 0x00000007, 0x00000000, EDX, 24 AMXINT8 : 0x00000007, 0x00000000, EDX, 25 - +AVXVNNI : 0x00000007, 0x00000001, EAX, 4 AVX512BF16 : 0x00000007, 0x00000001, EAX, 5 +HRESET : 0x00000007, 0x00000001, EAX, 22 XSAVEOPT : 0x0000000D, 0x00000001, EAX, 0 XSAVEC : 0x0000000D, 0x00000001, EAX, 1 diff --git a/isagenerator/instructions/flags.dat b/isagenerator/instructions/flags.dat index a5f66a6..f9017ef 100644 --- a/isagenerator/instructions/flags.dat +++ b/isagenerator/instructions/flags.dat @@ -105,3 +105,6 @@ AESKL : CF=0|PF=0|AF=0|ZF=m|SF=0|OF=0 # All flags are zeroed. ZERO : CF=0|PF=0|AF=0|ZF=0|SF=0|OF=0 + +# UINTR flags access, as done by TESTUI. +UINTR : CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 diff --git a/isagenerator/instructions/table_0F.dat b/isagenerator/instructions/table_0F.dat index 029361d..8a5a008 100644 --- a/isagenerator/instructions/table_0F.dat +++ b/isagenerator/instructions/table_0F.dat @@ -56,8 +56,12 @@ SETSSBSY nil SHS0,SSP [ 0xF3 0x0F 0x01 /0 XSUSLDTRK nil nil [ 0xF2 0x0F 0x01 /0xE8] s:TSXLDTRK, t:MISC XRESLDTRK nil nil [ 0xF2 0x0F 0x01 /0xE9] s:TSXLDTRK, t:MISC SAVEPREVSSP nil SHSS,SSP [ 0xF3 0x0F 0x01 /0xEA] s:CET_SS, t:CET, w:RW|R, f:CF=t +UIRET nil rIP,Fv,sSP,UIF,Kv3,SHS1 [ 0xF3 0x0F 0x01 /0xEC] s:UINTR, t:UINTR, a:F64, w:W|W|W|W|R|R, m:O64|NOTSX|NOSGX +TESTUI nil UIF,Fv [ 0xF3 0x0F 0x01 /0xED] s:UINTR, t:UINTR, w:R|W, f:UINTR, m:O64|NOSGX RDPKRU nil EDX,EAX,ECX,PKRU [ NP 0x0F 0x01 /0xEE] s:PKU, t:MISC, w:W|W|R|R +CLUI nil UIF [ 0xF3 0x0F 0x01 /0xEE] s:UINTR, t:UINTR, w:W, m:O64|NOTSX|NOSGX WRPKRU nil EDX,EAX,ECX,PKRU [ NP 0x0F 0x01 /0xEF] s:PKU, t:MISC, w:R|R|R|W +STUI nil UIF [ 0xF3 0x0F 0x01 /0xEF] s:UINTR, t:UINTR, w:W, m:O64|NOTSX|NOSGX SWAPGS nil GSBASE,KGSBASE [ 0x0F 0x01 /0xF8] s:LONGMODE, t:SYSTEM, w:RW|RW, m:KERNEL|O64 RDTSCP nil EAX,EDX,ECX,TSC,TSCAUX [ 0x0F 0x01 /0xF9] s:RDTSCP, t:SYSTEM, w:W|W|W|R|R MONITORX nil EAX,ECX,EDX [ NP 0x0F 0x01 /0xFA] s:MWAITT, t:SYSTEM, w:R|R|R, m:KERNEL|NOV86 @@ -570,6 +574,7 @@ VMXON Mq Fv [ 0xF3 0x0F 0xC7 /6 VMPTRST Mq Fv [ NP 0x0F 0xC7 /7:mem] s:VTX, t:VTX, w:W|W, f:VMX, m:VMXROOT RDRAND Rv Fv [ 0x0F 0xC7 /6:reg] s:RDRAND, t:RDRAND, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 RDRAND Rv Fv [ 0x66 0x0F 0xC7 /6:reg] s:RDRAND, t:RDRAND, a:S66, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 +SENDUIPI Rq nil [ 0xF3 0x0F 0xC7 /6:reg] s:UINTR, t:UINTR, w:RW, m:O64|NOTSX|NOSGX RDSEED Rv Fv [ 0x0F 0xC7 /7:reg] s:RDSEED, t:RDSEED, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 RDSEED Rv Fv [ 0x66 0x0F 0xC7 /7:reg] s:RDSEED, t:RDSEED, a:S66, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 RDPID Ryf TSCAUX [ 0xF3 0x0F 0xC7 /7:reg] s:RDPID, t:RDPID, w:W|R diff --git a/isagenerator/instructions/table_0F_3A.dat b/isagenerator/instructions/table_0F_3A.dat index 8c76440..b9adc29 100644 --- a/isagenerator/instructions/table_0F_3A.dat +++ b/isagenerator/instructions/table_0F_3A.dat @@ -66,3 +66,4 @@ AESKEYGENASSIST Vdq,Wdq,Ib nil [ 0x66 0x0F 0x # 0xE0 - 0xEF # 0xF0 - 0xFF +HRESET Ib EAX [ 0xF3 0x0F 0x3A 0xF0 /0xC0 ib] s:HRESET, t:HRESET, w:N|R, m:KERNEL|NOV86|NOTSX diff --git a/isagenerator/instructions/table_vex2.dat b/isagenerator/instructions/table_vex2.dat index 4df1342..dd45ed5 100644 --- a/isagenerator/instructions/table_vex2.dat +++ b/isagenerator/instructions/table_vex2.dat @@ -94,6 +94,11 @@ TILERELEASE nil nil [vex m:2 p:0 l:0 w:0 TILEZERO rTt nil [vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0] s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E5 # 0x50 - 0x5F +VPDPBUSD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x50 /r] s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 +VPDPBUSDS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x51 /r] s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 +VPDPWSSD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x52 /r] s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 +VPDPWSSDS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x53 /r] s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 + VPBROADCASTD Vx,Wd nil [vex m:2 p:1 l:x w:0 0x58 /r] s:AVX2, t:BROADCAST, w:W|R, e:6 VPBROADCASTQ Vx,Wq nil [vex m:2 p:1 l:x w:0 0x59 /r] s:AVX2, t:BROADCAST, w:W|R, e:6 VBROADCASTI128 Vqq,Mdq nil [vex m:2 p:1 l:1 w:0 0x5A /r:mem] s:AVX2, t:BROADCAST, w:W|R, e:6 diff --git a/pybddisasm/_pybddisasm/_pybddisasm.c b/pybddisasm/_pybddisasm/_pybddisasm.c index fed9d71..0a4f9ed 100644 --- a/pybddisasm/_pybddisasm/_pybddisasm.c +++ b/pybddisasm/_pybddisasm/_pybddisasm.c @@ -82,6 +82,7 @@ static char *RegTypeToString(ND_REG_TYPE RegType) case ND_REG_SSP: return "SSP"; case ND_REG_FLG: return "FLG"; case ND_REG_RIP: return "RIP"; + case ND_REG_UIF: return "UIF"; } return "unknown"; diff --git a/pybddisasm/setup.py b/pybddisasm/setup.py index 16118f7..7a7a1fe 100644 --- a/pybddisasm/setup.py +++ b/pybddisasm/setup.py @@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution from codecs import open VERSION = (0, 1, 3) -LIBRARY_VERSION = (1, 30, 0) +LIBRARY_VERSION = (1, 31, 0) LIBRARY_INSTRUX_SIZE = 864 packages = ['pybddisasm']