mirror of
https://github.com/bitdefender/bddisasm.git
synced 2025-01-03 11:50:55 +00:00
Use the documented byte granularity for cache-line accesses.
Fixed CET CPUID feature flag - split into CET_SS and CET_IBT.
This commit is contained in:
Andrei Vlad LUTAS
parent
9ff2543660
commit
8392c97f97
@ -1496,7 +1496,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0),
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},
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// Pos:110 Instruction:"CLDEMOTE Mcl" Encoding:"NP 0x0F 0x1C /0:mem"/"M"
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// Pos:110 Instruction:"CLDEMOTE Mb" Encoding:"NP 0x0F 0x1C /0:mem"/"M"
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{
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ND_INS_CLDEMOTE, ND_CAT_CLDEMOTE, ND_SET_CLDEMOTE, 68,
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ND_MOD_ANY,
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@ -1505,7 +1505,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_W, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_W, 0, 0),
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},
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// Pos:111 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M"
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@ -1532,7 +1532,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_N, 0, 0),
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},
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// Pos:113 Instruction:"CLFLUSH Mcl" Encoding:"NP 0x0F 0xAE /7:mem"/"M"
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// Pos:113 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M"
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{
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ND_INS_CLFLUSH, ND_CAT_MISC, ND_SET_CLFSH, 71,
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ND_MOD_ANY,
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@ -1541,10 +1541,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:114 Instruction:"CLFLUSHOPT Mcl" Encoding:"0x66 0x0F 0xAE /7:mem"/"M"
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// Pos:114 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M"
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{
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ND_INS_CLFLUSHOPT, ND_CAT_MISC, ND_SET_CLFSHOPT, 72,
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ND_MOD_ANY,
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@ -1553,7 +1553,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:115 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/""
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@ -1581,9 +1581,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:117 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M"
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{
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ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET, 75,
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ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET_SS, 75,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
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0,
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0|REG_RFLAG_CF,
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0,
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@ -1604,7 +1604,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_W, 0, 0),
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},
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// Pos:119 Instruction:"CLWB Mcl" Encoding:"0x66 0x0F 0xAE /6:mem"/"M"
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// Pos:119 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M"
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{
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ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 77,
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ND_MOD_ANY,
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@ -1613,7 +1613,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_W, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_W, 0, 0),
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},
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// Pos:120 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/""
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@ -3046,9 +3046,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:224 Instruction:"ENDBR32" Encoding:"a0xF3 0x0F 0x1E /0xFB"/""
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{
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ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET, 154,
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ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 154,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT,
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0,
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0,
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0,
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@ -3057,9 +3057,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:225 Instruction:"ENDBR64" Encoding:"a0xF3 0x0F 0x1E /0xFA"/""
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{
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ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET, 155,
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ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 155,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT,
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0,
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0,
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0,
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@ -5583,9 +5583,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:412 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M"
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{
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ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET, 269,
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ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 269,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS,
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0,
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0,
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0,
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@ -5597,9 +5597,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:413 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M"
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{
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ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET, 270,
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ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 270,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS,
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0,
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0,
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0,
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@ -13232,7 +13232,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0),
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},
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// Pos:982 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /4:mem"/"M"
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// Pos:982 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M"
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{
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ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591,
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ND_MOD_ANY,
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@ -13241,10 +13241,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:983 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /5:mem"/"M"
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// Pos:983 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M"
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{
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ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591,
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ND_MOD_ANY,
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@ -13253,10 +13253,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:984 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /6:mem"/"M"
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// Pos:984 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M"
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{
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ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591,
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ND_MOD_ANY,
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@ -13265,10 +13265,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:985 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /7:mem"/"M"
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// Pos:985 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M"
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{
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ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591,
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ND_MOD_ANY,
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@ -13277,10 +13277,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:986 Instruction:"PREFETCHE Mcl" Encoding:"0x0F 0x0D /0:mem"/"M"
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// Pos:986 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M"
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{
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ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 592,
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ND_MOD_ANY,
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@ -13289,10 +13289,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:987 Instruction:"PREFETCHM Mcl" Encoding:"0x0F 0x0D /3:mem"/"M"
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// Pos:987 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M"
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{
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ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 593,
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ND_MOD_ANY,
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@ -13301,10 +13301,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:988 Instruction:"PREFETCHNTA Mcl" Encoding:"0x0F 0x18 /0:mem"/"M"
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// Pos:988 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M"
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{
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ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 594,
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ND_MOD_ANY,
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@ -13313,10 +13313,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:989 Instruction:"PREFETCHT0 Mcl" Encoding:"0x0F 0x18 /1:mem"/"M"
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// Pos:989 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M"
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{
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ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 595,
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ND_MOD_ANY,
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@ -13325,10 +13325,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:990 Instruction:"PREFETCHT1 Mcl" Encoding:"0x0F 0x18 /2:mem"/"M"
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// Pos:990 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M"
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{
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ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 596,
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ND_MOD_ANY,
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@ -13337,10 +13337,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:991 Instruction:"PREFETCHT2 Mcl" Encoding:"0x0F 0x18 /3:mem"/"M"
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// Pos:991 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M"
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{
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ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 597,
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ND_MOD_ANY,
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@ -13349,10 +13349,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:992 Instruction:"PREFETCHW Mcl" Encoding:"0x0F 0x0D /1:mem"/"M"
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// Pos:992 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M"
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{
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ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 598,
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ND_MOD_ANY,
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@ -13361,10 +13361,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:993 Instruction:"PREFETCHWT1 Mcl" Encoding:"0x0F 0x0D /2:mem"/"M"
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// Pos:993 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M"
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{
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ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 599,
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ND_MOD_ANY,
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@ -13373,7 +13373,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:994 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM"
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@ -15119,9 +15119,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:1126 Instruction:"RDSSPD Rd" Encoding:"a0xF3 0x0F 0x1E /1:reg"/"M"
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{
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ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET, 660,
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ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 660,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS,
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0,
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0,
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0,
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@ -15132,9 +15132,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:1127 Instruction:"RDSSPQ Rq" Encoding:"a0xF3 rexw 0x0F 0x1E /1:reg"/"M"
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{
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ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET, 661,
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ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 661,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS,
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0,
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0,
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0,
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@ -15568,9 +15568,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:1158 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M"
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{
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ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET, 680,
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ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 680,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
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0,
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0|REG_RFLAG_CF,
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0,
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@ -15801,9 +15801,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:1175 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/""
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{
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ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET, 687,
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ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 687,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
|
||||
0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS,
|
||||
0|REG_RFLAG_CF,
|
||||
0,
|
||||
0,
|
||||
@ -16284,9 +16284,9 @@ const ND_INSTRUCTION gInstructions[2554] =
|
||||
|
||||
// Pos:1210 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/""
|
||||
{
|
||||
ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET, 709,
|
||||
ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 709,
|
||||
ND_MOD_ANY,
|
||||
0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
|
||||
0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
@ -34591,9 +34591,9 @@ const ND_INSTRUCTION gInstructions[2554] =
|
||||
|
||||
// Pos:2497 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR"
|
||||
{
|
||||
ND_INS_WRSS, ND_CAT_CET, ND_SET_CET, 1523,
|
||||
ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1523,
|
||||
ND_MOD_ANY,
|
||||
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
|
||||
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
@ -34604,9 +34604,9 @@ const ND_INSTRUCTION gInstructions[2554] =
|
||||
|
||||
// Pos:2498 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR"
|
||||
{
|
||||
ND_INS_WRSS, ND_CAT_CET, ND_SET_CET, 1524,
|
||||
ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1524,
|
||||
ND_MOD_ANY,
|
||||
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
|
||||
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
@ -34617,9 +34617,9 @@ const ND_INSTRUCTION gInstructions[2554] =
|
||||
|
||||
// Pos:2499 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
|
||||
{
|
||||
ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET, 1525,
|
||||
ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1525,
|
||||
ND_MOD_ANY,
|
||||
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
|
||||
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
@ -34630,9 +34630,9 @@ const ND_INSTRUCTION gInstructions[2554] =
|
||||
|
||||
// Pos:2500 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
|
||||
{
|
||||
ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET, 1526,
|
||||
ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1526,
|
||||
ND_MOD_ANY,
|
||||
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
|
||||
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
@ -116,7 +116,8 @@ const char* set_to_string(
|
||||
case ND_SET_AVX512VPOPCNTDQ: return "AVX512VPOPCNTDQ";
|
||||
case ND_SET_BMI1: return "BMI1";
|
||||
case ND_SET_BMI2: return "BMI2";
|
||||
case ND_SET_CET: return "CET";
|
||||
case ND_SET_CET_SS: return "CET_SS";
|
||||
case ND_SET_CET_IBT: return "CET_IBT";
|
||||
case ND_SET_CLDEMOTE: return "CLDEMOTE";
|
||||
case ND_SET_CLFSH: return "CLFSH";
|
||||
case ND_SET_CLFSHOPT: return "CLFSHOPT";
|
||||
|
||||
@ -1495,7 +1495,8 @@ typedef enum _ND_INS_SET
|
||||
ND_SET_AVX512VPOPCNTDQ,
|
||||
ND_SET_BMI1,
|
||||
ND_SET_BMI2,
|
||||
ND_SET_CET,
|
||||
ND_SET_CET_IBT,
|
||||
ND_SET_CET_SS,
|
||||
ND_SET_CLDEMOTE,
|
||||
ND_SET_CLFSH,
|
||||
ND_SET_CLFSHOPT,
|
||||
|
||||
@ -61,7 +61,7 @@
|
||||
#define ND_CFF_PKU ND_CFF(0x00000007, 0x00000000, REG_ECX, 3)
|
||||
#define ND_CFF_WAITPKG ND_CFF(0x00000007, 0x00000000, REG_ECX, 5)
|
||||
#define ND_CFF_AVX512VBMI2 ND_CFF(0x00000007, 0x00000000, REG_ECX, 6)
|
||||
#define ND_CFF_CET ND_CFF(0x00000007, 0x00000000, REG_ECX, 7)
|
||||
#define ND_CFF_CET_SS ND_CFF(0x00000007, 0x00000000, REG_ECX, 7)
|
||||
#define ND_CFF_GFNI ND_CFF(0x00000007, 0x00000000, REG_ECX, 8)
|
||||
#define ND_CFF_VAES ND_CFF(0x00000007, 0x00000000, REG_ECX, 9)
|
||||
#define ND_CFF_VPCLMULQDQ ND_CFF(0x00000007, 0x00000000, REG_ECX, 10)
|
||||
@ -79,6 +79,7 @@
|
||||
#define ND_CFF_SERIALIZE ND_CFF(0x00000007, 0x00000000, REG_EDX, 14)
|
||||
#define ND_CFF_TSXLDTRK ND_CFF(0x00000007, 0x00000000, REG_EDX, 16)
|
||||
#define ND_CFF_PCONFIG ND_CFF(0x00000007, 0x00000000, REG_EDX, 18)
|
||||
#define ND_CFF_CET_IBT ND_CFF(0x00000007, 0x00000000, REG_EDX, 20)
|
||||
#define ND_CFF_AMXBF16 ND_CFF(0x00000007, 0x00000000, REG_EDX, 22)
|
||||
#define ND_CFF_AMXTILE ND_CFF(0x00000007, 0x00000000, REG_EDX, 24)
|
||||
#define ND_CFF_AMXINT8 ND_CFF(0x00000007, 0x00000000, REG_EDX, 25)
|
||||
|
||||
@ -7,6 +7,6 @@
|
||||
|
||||
#define DISASM_VERSION_MAJOR 1
|
||||
#define DISASM_VERSION_MINOR 25
|
||||
#define DISASM_VERSION_REVISION 1
|
||||
#define DISASM_VERSION_REVISION 2
|
||||
|
||||
#endif // _DISASM_VER_H_
|
||||
|
||||
@ -61,7 +61,7 @@ AVX512VBMI : 0x00000007, 0x00000000, ECX, 1
|
||||
PKU : 0x00000007, 0x00000000, ECX, 3
|
||||
WAITPKG : 0x00000007, 0x00000000, ECX, 5
|
||||
AVX512VBMI2 : 0x00000007, 0x00000000, ECX, 6
|
||||
CET : 0x00000007, 0x00000000, ECX, 7
|
||||
CET_SS : 0x00000007, 0x00000000, ECX, 7
|
||||
GFNI : 0x00000007, 0x00000000, ECX, 8
|
||||
VAES : 0x00000007, 0x00000000, ECX, 9
|
||||
VPCLMULQDQ : 0x00000007, 0x00000000, ECX, 10
|
||||
@ -79,6 +79,7 @@ AVX512VP2INTERSECT : 0x00000007, 0x00000000, EDX, 8
|
||||
SERIALIZE : 0x00000007, 0x00000000, EDX, 14
|
||||
TSXLDTRK : 0x00000007, 0x00000000, EDX, 16
|
||||
PCONFIG : 0x00000007, 0x00000000, EDX, 18
|
||||
CET_IBT : 0x00000007, 0x00000000, EDX, 20
|
||||
AMXBF16 : 0x00000007, 0x00000000, EDX, 22
|
||||
AMXTILE : 0x00000007, 0x00000000, EDX, 24
|
||||
AMXINT8 : 0x00000007, 0x00000000, EDX, 25
|
||||
|
||||
@ -18,7 +18,7 @@ SMSW Mw CR0 [ 0x0F 0x01 /4
|
||||
SMSW Rv CR0 [ 0x0F 0x01 /4:reg] s:I286REAL, t:SYSTEM, w:W|R, m:NOSGX
|
||||
LMSW Ew CR0 [ 0x0F 0x01 /6] s:I286REAL, t:SYSTEM, w:R|W, a:SERIAL, m:KERNEL
|
||||
INVLPG Mb nil [ 0x0F 0x01 /7:mem] s:I486REAL, t:SYSTEM, w:R, a:AG, m:KERNEL|NOV86
|
||||
RSTORSSP Mq SSP [ 0xF3 0x0F 0x01 /5:mem] s:CET, t:CET, a:SHS, w:RW|RW, f:CF=m|ZF=0|PF=0|AF=0|OF=0|SF=0
|
||||
RSTORSSP Mq SSP [ 0xF3 0x0F 0x01 /5:mem] s:CET_SS, t:CET, a:SHS, w:RW|RW, f:CF=m|ZF=0|PF=0|AF=0|OF=0|SF=0
|
||||
ENCLV nil EAX,RBX,RCX,RDX [ NP 0x0F 0x01 /0xC0] s:SGX, t:SGX, w:R|CRW|CRW|CRW, m:KERNEL|NOSMM|NOTSX|VMX
|
||||
VMCALL nil nil [ 0x0F 0x01 /0xC1] s:VTX, t:VTX, m:VMX|NOSGX
|
||||
VMLAUNCH nil Fv [ 0x0F 0x01 /0xC2] s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT
|
||||
@ -39,7 +39,7 @@ ENCLU nil EAX,RBX,RCX,RDX [ NP 0x0F 0x01 /0
|
||||
SERIALIZE nil nil [ NP 0x0F 0x01 /0xE8] s:SERIALIZE, t:MISC
|
||||
XSUSLDTRK nil nil [ 0xF2 0x0F 0x01 /0xE8] s:TSXLDTRK, t:MISC
|
||||
XRESLDTRK nil nil [ 0xF2 0x0F 0x01 /0xE9] s:TSXLDTRK, t:MISC
|
||||
SAVEPREVSSP nil SHSS,SSP [ 0xF3 0x0F 0x01 /0xEA] s:CET, t:CET, w:RW|R, f:CF=t
|
||||
SAVEPREVSSP nil SHSS,SSP [ 0xF3 0x0F 0x01 /0xEA] s:CET_SS, t:CET, w:RW|R, f:CF=t
|
||||
RDPKRU nil EDX,EAX,ECX,PKRU [ NP 0x0F 0x01 /0xEE] s:PKU, t:MISC, w:W|W|R|R
|
||||
WRPKRU nil EDX,EAX,ECX,PKRU [ NP 0x0F 0x01 /0xEF] s:PKU, t:MISC, w:R|R|R|W
|
||||
SWAPGS nil GSBASE,KGSBASE [ 0x0F 0x01 /0xF8] s:LONGMODE, t:SYSTEM, w:RW|RW, m:KERNEL|O64
|
||||
@ -59,7 +59,7 @@ STGI nil nil [ 0x0F 0x01 /0
|
||||
CLGI nil nil [ 0x0F 0x01 /0xDD] s:SVM, t:SYSTEM, m:VMXROOT
|
||||
SKINIT nil EAX [ 0x0F 0x01 /0xDE] s:SVM, t:SYSTEM, w:R, m:VMXROOT
|
||||
INVLPGA nil rAX,ECX [ 0x0F 0x01 /0xDF] s:SVM, t:SYSTEM, w:R|R, m:VMXROOT
|
||||
SETSSBSY nil SHS0,SSP [ 0xF3 0x0F 0x01 /0xE8] s:CET, t:CET, a:SHS, w:RW|RW
|
||||
SETSSBSY nil SHS0,SSP [ 0xF3 0x0F 0x01 /0xE8] s:CET_SS, t:CET, a:SHS, w:RW|RW
|
||||
INVLPGB nil rAX,ECX,EDX [ 0x0F 0x01 /0xFE] s:INVLPGB, t:SYSTEM, w:R|R|R, m:NOREAL|KERNEL
|
||||
RMPADJUST nil RAX,RCX,RDX,Fv [ 0xF3 0x0F 0x01 /0xFE] s:SNP, t:SYSTEM, w:RW|R|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, m:O64|KERNEL
|
||||
RMPUPDATE nil RAX,RCX,Fv [ 0xF2 0x0F 0x01 /0xFE] s:SNP, t:SYSTEM, w:RW|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, m:O64|KERNEL
|
||||
@ -80,21 +80,21 @@ WBINVD nil nil [ NP 0x0F 0x09]
|
||||
WBNOINVD nil nil [ 0xF3 0x0F 0x09] s:WBNOINVD, t:WBNOINVD, m:KERNEL|NOV86
|
||||
CL1INVMB nil nil [ 0x0F 0x0A] s:SCC, t:SYSTEM
|
||||
UD2 nil nil [ 0x0F 0x0B] s:PPRO, t:MISC
|
||||
PREFETCHE Mcl nil [ 0x0F 0x0D /0:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
PREFETCHE Mb nil [ 0x0F 0x0D /0:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
NOP Ev,Gv nil [ 0x0F 0x0D /0:reg] s:PPRO, t:NOP, w:R|R
|
||||
PREFETCHW Mcl nil [ 0x0F 0x0D /1:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
PREFETCHW Mb nil [ 0x0F 0x0D /1:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
NOP Ev,Gv nil [ 0x0F 0x0D /1:reg] s:PPRO, t:NOP, w:R|R
|
||||
PREFETCHWT1 Mcl nil [ 0x0F 0x0D /2:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
PREFETCHWT1 Mb nil [ 0x0F 0x0D /2:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
NOP Ev,Gv nil [ 0x0F 0x0D /2:reg] s:PPRO, t:NOP, w:R|R
|
||||
PREFETCHM Mcl nil [ 0x0F 0x0D /3:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
PREFETCHM Mb nil [ 0x0F 0x0D /3:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
NOP Ev,Gv nil [ 0x0F 0x0D /3:reg] s:PPRO, t:NOP, w:R|R
|
||||
PREFETCH Mcl nil [ 0x0F 0x0D /4:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
PREFETCH Mb nil [ 0x0F 0x0D /4:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
NOP Ev,Gv nil [ 0x0F 0x0D /4:reg] s:PPRO, t:NOP, w:R|R
|
||||
PREFETCH Mcl nil [ 0x0F 0x0D /5:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
PREFETCH Mb nil [ 0x0F 0x0D /5:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
NOP Ev,Gv nil [ 0x0F 0x0D /5:reg] s:PPRO, t:NOP, w:R|R
|
||||
PREFETCH Mcl nil [ 0x0F 0x0D /6:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
PREFETCH Mb nil [ 0x0F 0x0D /6:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
NOP Ev,Gv nil [ 0x0F 0x0D /6:reg] s:PPRO, t:NOP, w:R|R
|
||||
PREFETCH Mcl nil [ 0x0F 0x0D /7:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
PREFETCH Mb nil [ 0x0F 0x0D /7:mem] s:PREFETCH_NOP, t:PREFETCH, w:R
|
||||
NOP Ev,Gv nil [ 0x0F 0x0D /7:reg] s:PPRO, t:NOP, w:R|R
|
||||
|
||||
FEMMS nil nil [ 0x0F 0x0E] s:3DNOW, t:MMX, c:FEMMS
|
||||
@ -124,13 +124,13 @@ MOVHPD Vq,Mq nil [ 0x66 0x0F 0x16 /r
|
||||
MOVSHDUP Vx,Wx nil [ 0xF3 0x0F 0x16 /r] s:SSE3, t:DATAXFER, w:W|R, e:4
|
||||
MOVHPS Mq,Vq nil [ NP 0x0F 0x17 /r:mem] s:SSE, t:DATAXFER, w:W|R, e:5
|
||||
MOVHPD Mq,Vq nil [ 0x66 0x0F 0x17 /r:mem] s:SSE2, t:DATAXFER, w:W|R, e:5
|
||||
PREFETCHNTA Mcl nil [ 0x0F 0x18 /0:mem] s:SSE, t:PREFETCH, w:R
|
||||
PREFETCHNTA Mb nil [ 0x0F 0x18 /0:mem] s:SSE, t:PREFETCH, w:R
|
||||
NOP Ev nil [ 0x0F 0x18 /0:reg] s:PPRO, t:WIDENOP, w:R
|
||||
PREFETCHT0 Mcl nil [ 0x0F 0x18 /1:mem] s:SSE, t:PREFETCH, w:R
|
||||
PREFETCHT0 Mb nil [ 0x0F 0x18 /1:mem] s:SSE, t:PREFETCH, w:R
|
||||
NOP Ev nil [ 0x0F 0x18 /1:reg] s:PPRO, t:WIDENOP, w:R
|
||||
PREFETCHT1 Mcl nil [ 0x0F 0x18 /2:mem] s:SSE, t:PREFETCH, w:R
|
||||
PREFETCHT1 Mb nil [ 0x0F 0x18 /2:mem] s:SSE, t:PREFETCH, w:R
|
||||
NOP Ev nil [ 0x0F 0x18 /2:reg] s:PPRO, t:WIDENOP, w:R
|
||||
PREFETCHT2 Mcl nil [ 0x0F 0x18 /3:mem] s:SSE, t:PREFETCH, w:R
|
||||
PREFETCHT2 Mb nil [ 0x0F 0x18 /3:mem] s:SSE, t:PREFETCH, w:R
|
||||
NOP Ev nil [ 0x0F 0x18 /3:reg] s:PPRO, t:WIDENOP, w:R
|
||||
NOP Ev nil [ 0x0F 0x18 /4] s:PPRO, t:WIDENOP, w:R
|
||||
NOP Ev nil [ 0x0F 0x18 /5] s:PPRO, t:WIDENOP, w:R
|
||||
@ -154,7 +154,7 @@ BNDMK rBl,My nil [ 0xF3 0x0F 0x1B /r
|
||||
NOP Gv,Ev nil [ 0xF3 0x0F 0x1B /r:reg] s:PPRO, t:WIDENOP, w:R|R
|
||||
BNDCN rBl,Ey nil [ 0xF2 0x0F 0x1B /r] s:MPX, t:MPX, w:R|R, a:AG|F64
|
||||
|
||||
CLDEMOTE Mcl nil [ NP 0x0F 0x1C /0:mem] s:CLDEMOTE, t:CLDEMOTE, w:W
|
||||
CLDEMOTE Mb nil [ NP 0x0F 0x1C /0:mem] s:CLDEMOTE, t:CLDEMOTE, w:W
|
||||
NOP Ev,Gv nil [ 0x66 0x0F 0x1C /0:mem] s:PPRO, t:WIDENOP, w:R|R
|
||||
NOP Ev,Gv nil [ 0xF3 0x0F 0x1C /0:mem] s:PPRO, t:WIDENOP, w:R|R
|
||||
NOP Ev,Gv nil [ 0xF2 0x0F 0x1C /0:mem] s:PPRO, t:WIDENOP, w:R|R
|
||||
@ -172,8 +172,8 @@ NOP Mv,Gv nil [ 0x0F 0x1E /r
|
||||
NOP Rv,Gv nil [ 0x0F 0x1E /0:reg] s:PPRO, t:WIDENOP, w:R|R
|
||||
NOP Rv,Gv nil [ 0x0F 0x1E /1:reg] s:PPRO, t:WIDENOP, w:R|R
|
||||
NOP Rv,Gv nil [ rexw 0x0F 0x1E /1:reg] s:PPRO, t:WIDENOP, w:R|R
|
||||
RDSSPD Rd SSP [ a0xF3 0x0F 0x1E /1:reg] s:CET, t:CET, c:RSSSP, w:W|R
|
||||
RDSSPQ Rq SSP [ a0xF3 rexw 0x0F 0x1E /1:reg] s:CET, t:CET, c:RSSSP, w:W|R
|
||||
RDSSPD Rd SSP [ a0xF3 0x0F 0x1E /1:reg] s:CET_SS, t:CET, c:RSSSP, w:W|R
|
||||
RDSSPQ Rq SSP [ a0xF3 rexw 0x0F 0x1E /1:reg] s:CET_SS, t:CET, c:RSSSP, w:W|R
|
||||
NOP Rv,Gv nil [ 0x0F 0x1E /2:reg] s:PPRO, t:WIDENOP, w:R|R
|
||||
NOP Rv,Gv nil [ 0x0F 0x1E /3:reg] s:PPRO, t:WIDENOP, w:R|R
|
||||
NOP Rv,Gv nil [ 0x0F 0x1E /4:reg] s:PPRO, t:WIDENOP, w:R|R
|
||||
@ -187,8 +187,8 @@ NOP Rv,Gv nil [ 0x0F 0x1E /0
|
||||
NOP Rv,Gv nil [ 0x0F 0x1E /0xFD] s:PPRO, t:WIDENOP, w:R|R
|
||||
NOP Rv,Gv nil [ 0x0F 0x1E /0xFE] s:PPRO, t:WIDENOP, w:R|R
|
||||
NOP Rv,Gv nil [ 0x0F 0x1E /0xFF] s:PPRO, t:WIDENOP, w:R|R
|
||||
ENDBR64 nil nil [ a0xF3 0x0F 0x1E /0xFA] s:CET, t:CET, c:ENDBR
|
||||
ENDBR32 nil nil [ a0xF3 0x0F 0x1E /0xFB] s:CET, t:CET, c:ENDBR
|
||||
ENDBR64 nil nil [ a0xF3 0x0F 0x1E /0xFA] s:CET_IBT, t:CET, c:ENDBR
|
||||
ENDBR32 nil nil [ a0xF3 0x0F 0x1E /0xFB] s:CET_IBT, t:CET, c:ENDBR
|
||||
|
||||
NOP Ev,Gv nil [ 0x0F 0x1F /r] s:PPRO, t:WIDENOP, w:R|R
|
||||
|
||||
@ -474,10 +474,10 @@ XRSTOR M? EDX,EAX,XCR0,BANK [ NP 0x0F 0xAE /5
|
||||
XRSTOR64 M? EDX,EAX,XCR0,BANK [ rexw NP 0x0F 0xAE /5:mem] s:XSAVE, t:XSAVE, c:XRSTOR, w:R|R|R|R|W
|
||||
XSAVEOPT M? EDX,EAX,XCR0,BANK [ NP 0x0F 0xAE /6:mem] s:XSAVE, t:XSAVE, c:XSAVEOPT, w:W|R|R|R|R
|
||||
XSAVEOPT64 M? EDX,EAX,XCR0,BANK [ rexw NP 0x0F 0xAE /6:mem] s:XSAVE, t:XSAVE, c:XSAVEOPT, w:W|R|R|R|R
|
||||
CLWB Mcl nil [ 0x66 0x0F 0xAE /6:mem] s:CLWB, t:MISC, w:W
|
||||
CLRSSBSY Mq SSP [ 0xF3 0x0F 0xAE /6:mem] s:CET, t:CET, a:SHS, w:RW|RW, f:CF=m|ZF=0|PF=0|AF=0|OF=0|SF=0
|
||||
CLFLUSH Mcl nil [ NP 0x0F 0xAE /7:mem] s:CLFSH, t:MISC, w:R
|
||||
CLFLUSHOPT Mcl nil [ 0x66 0x0F 0xAE /7:mem] s:CLFSHOPT, t:MISC, w:R
|
||||
CLWB Mb nil [ 0x66 0x0F 0xAE /6:mem] s:CLWB, t:MISC, w:W
|
||||
CLRSSBSY Mq SSP [ 0xF3 0x0F 0xAE /6:mem] s:CET_SS, t:CET, a:SHS, w:RW|RW, f:CF=m|ZF=0|PF=0|AF=0|OF=0|SF=0
|
||||
CLFLUSH Mb nil [ NP 0x0F 0xAE /7:mem] s:CLFSH, t:MISC, w:R
|
||||
CLFLUSHOPT Mb nil [ 0x66 0x0F 0xAE /7:mem] s:CLFSHOPT, t:MISC, w:R
|
||||
|
||||
PTWRITE Ey nil [ 0xF3 0x0F 0xAE /4] s:PTWRITE, t:PTWRITE, w:R, a:NO66
|
||||
|
||||
@ -485,8 +485,8 @@ RDFSBASE Ry FSBASE [ o64 0xF3 0x0F 0xAE /0
|
||||
RDGSBASE Ry GSBASE [ o64 0xF3 0x0F 0xAE /1:reg] s:RDWRFSGS, t:RDWRFSGS, w:W|R, m:O64
|
||||
WRFSBASE Ry FSBASE [ o64 0xF3 0x0F 0xAE /2:reg] s:RDWRFSGS, t:RDWRFSGS, w:R|W, m:O64
|
||||
WRGSBASE Ry GSBASE [ o64 0xF3 0x0F 0xAE /3:reg] s:RDWRFSGS, t:RDWRFSGS, w:R|W, m:O64
|
||||
INCSSPD Rd SHSI,SSP [ 0xF3 0x0F 0xAE /5:reg] s:CET, t:CET, c:INCSSP, w:R|R|RW
|
||||
INCSSPQ Rq SHSI,SSP [ 0xF3 rexw 0x0F 0xAE /5:reg] s:CET, t:CET, c:INCSSP, w:R|R|RW
|
||||
INCSSPD Rd SHSI,SSP [ 0xF3 0x0F 0xAE /5:reg] s:CET_SS, t:CET, c:INCSSP, w:R|R|RW
|
||||
INCSSPQ Rq SHSI,SSP [ 0xF3 rexw 0x0F 0xAE /5:reg] s:CET_SS, t:CET, c:INCSSP, w:R|R|RW
|
||||
LFENCE nil nil [ NP 0x0F 0xAE /5:reg] s:SSE2, t:MISC
|
||||
UMONITOR mMb Fv [ 0xF3 0x0F 0xAE /6:reg] s:WAITPKG, t:WAITPKG, w:R|W, f:WAITPKG, m:NOTSX
|
||||
UMWAIT Ry EDX,EAX [ 0xF2 0x0F 0xAE /6:reg] s:WAITPKG, t:WAITPKG, w:R|R|R, m:NOTSX
|
||||
|
||||
@ -116,10 +116,10 @@ MOVBE Mv,Gv nil [ 0x0F 0x
|
||||
MOVBE Mv,Gv nil [ 0x66 0x0F 0x38 0xF1 /r:mem] s:MOVBE, t:DATAXFER, w:W|R, a:S66
|
||||
CRC32 Gy,Ev nil [ 0xF2 0x0F 0x38 0xF1 /r] s:SSE42, t:SSE, w:RW|R
|
||||
CRC32 Gy,Ev nil [ 0x66 0xF2 0x0F 0x38 0xF1 /r] s:SSE42, t:SSE, w:RW|R, a:S66
|
||||
WRUSSD My,Gy nil [ 0x66 0x0F 0x38 0xF5 /r:mem] s:CET, t:CET, c:WRUSS, a:SHS, w:W|R
|
||||
WRUSSQ My,Gy nil [ rexw 0x66 0x0F 0x38 0xF5 /r:mem] s:CET, t:CET, c:WRUSS, a:SHS, w:W|R
|
||||
WRSSD My,Gy nil [ NP 0x0F 0x38 0xF6 /r:mem] s:CET, t:CET, c:WRSS, a:SHS, w:W|R
|
||||
WRSSQ My,Gy nil [ rexw NP 0x0F 0x38 0xF6 /r:mem] s:CET, t:CET, c:WRSS, a:SHS, w:W|R
|
||||
WRUSSD My,Gy nil [ 0x66 0x0F 0x38 0xF5 /r:mem] s:CET_SS, t:CET, c:WRUSS, a:SHS, w:W|R
|
||||
WRUSSQ My,Gy nil [ rexw 0x66 0x0F 0x38 0xF5 /r:mem] s:CET_SS, t:CET, c:WRUSS, a:SHS, w:W|R
|
||||
WRSSD My,Gy nil [ NP 0x0F 0x38 0xF6 /r:mem] s:CET_SS, t:CET, c:WRSS, a:SHS, w:W|R
|
||||
WRSSQ My,Gy nil [ rexw NP 0x0F 0x38 0xF6 /r:mem] s:CET_SS, t:CET, c:WRSS, a:SHS, w:W|R
|
||||
ADCX Gy,Ey Fv [ 0x66 0x0F 0x38 0xF6 /r] s:ADX, t:ARITH, w:RW|R|RW, f:CF=m
|
||||
ADOX Gy,Ey Fv [ 0xF3 0x0F 0x38 0xF6 /r] s:ADX, t:ARITH, w:RW|R|RW, f:OF=m
|
||||
MOVDIR64B rMoq,Moq nil [ 0x66 0x0F 0x38 0xF8 /r:mem] s:MOVDIR64B, t:MOVDIR64B, w:W|R
|
||||
|
||||
Loading…
Reference in New Issue
Block a user