From 7a254037b017ddac329cfff6a5da626c8cbd429a Mon Sep 17 00:00:00 2001 From: "BITDEFENDER\\vlutas" Date: Thu, 27 Oct 2022 12:37:02 +0300 Subject: [PATCH] Added support for AMD RMPQUERY instruction. --- bddisasm/include/instructions.h | 6377 ++++++++++++------------ bddisasm/include/mnemonics.h | 193 +- bddisasm/include/table_evex.h | 1462 +++--- bddisasm/include/table_root.h | 565 ++- bddisasm/include/table_vex.h | 986 ++-- bddisasm/include/table_xop.h | 148 +- bddisasm_test/x86/basic/snp_64.asm | 3 +- bddisasm_test/x86/basic/snp_64.result | 22 + bddisasm_test/x86/basic/snp_64.test | 2 +- bindings/pybddisasm/setup.py | 2 +- disasmtool_lix/dumpers.cpp | 1 + inc/constants.h | 1 + inc/cpuidflags.h | 1 + inc/version.h | 2 +- isagenerator/instructions/cpuid.dat | 1 + isagenerator/instructions/table_0F.dat | 1 + 16 files changed, 4916 insertions(+), 4851 deletions(-) diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h index b54ea69..4216335 100644 --- a/bddisasm/include/instructions.h +++ b/bddisasm/include/instructions.h @@ -10,7 +10,7 @@ #ifndef INSTRUCTIONS_H #define INSTRUCTIONS_H -const ND_INSTRUCTION gInstructions[2762] = +const ND_INSTRUCTION gInstructions[2763] = { // Pos:0 Instruction:"AAA" Encoding:"0x37"/"" { @@ -19693,9 +19693,28 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1195 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" + // Pos:1195 Instruction:"RMPQUERY" Encoding:"0xF3 0x0F 0x01 /0xFD"/"" { - ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 708, + ND_INS_RMPQUERY, ND_CAT_SYSTEM, ND_SET_SNP, 708, + 0, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RMPQUERY, + 0, + 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, + 0, + 0, + { + OP(ND_OPT_MEM_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1196 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" + { + ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 709, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, @@ -19710,9 +19729,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1196 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" + // Pos:1197 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 709, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19727,9 +19746,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1197 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" + // Pos:1198 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 709, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19744,9 +19763,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1198 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" + // Pos:1199 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 709, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19761,9 +19780,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1199 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" + // Pos:1200 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 709, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19778,9 +19797,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1200 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" + // Pos:1201 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 709, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19795,9 +19814,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1201 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" + // Pos:1202 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 709, + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19812,9 +19831,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1202 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" + // Pos:1203 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 710, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19829,9 +19848,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1203 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" + // Pos:1204 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 710, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19846,9 +19865,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1204 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" + // Pos:1205 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 710, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19863,9 +19882,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1205 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" + // Pos:1206 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 710, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19880,9 +19899,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1206 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" + // Pos:1207 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 710, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19897,9 +19916,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1207 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" + // Pos:1208 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 710, + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -19914,9 +19933,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1208 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" + // Pos:1209 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" { - ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 711, + ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 712, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -19931,9 +19950,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1209 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" + // Pos:1210 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" { - ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 712, + ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 713, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -19948,9 +19967,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1210 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" + // Pos:1211 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" { - ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 713, + ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 714, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -19965,9 +19984,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1211 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" + // Pos:1212 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" { - ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 714, + ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 715, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -19982,9 +20001,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1212 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" + // Pos:1213 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" { - ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 715, + ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 716, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, @@ -19999,9 +20018,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1213 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM" + // Pos:1214 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM" { - ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 716, + ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 717, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20015,9 +20034,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1214 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M" + // Pos:1215 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M" { - ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 717, + ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 718, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20030,9 +20049,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1215 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" + // Pos:1216 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" { - ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 718, + ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 719, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -20047,9 +20066,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1216 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" + // Pos:1217 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" { - ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 719, + ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 720, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -20063,9 +20082,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1217 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" + // Pos:1218 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" { - ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 720, + ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 721, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -20079,9 +20098,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1218 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" + // Pos:1219 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" { - ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 721, + ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 722, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -20095,9 +20114,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1219 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M" + // Pos:1220 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M" { - ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 722, + ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 723, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20110,9 +20129,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1220 Instruction:"SAHF" Encoding:"0x9E"/"" + // Pos:1221 Instruction:"SAHF" Encoding:"0x9E"/"" { - ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 723, + ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 724, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20126,9 +20145,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1221 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" + // Pos:1222 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 724, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 725, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20143,9 +20162,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1222 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" + // Pos:1223 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 724, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 725, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20160,9 +20179,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1223 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" + // Pos:1224 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 724, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 725, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20177,9 +20196,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1224 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" + // Pos:1225 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 724, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 725, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20194,9 +20213,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1225 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" + // Pos:1226 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 724, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 725, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20211,9 +20230,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1226 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" + // Pos:1227 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 724, + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 725, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20228,9 +20247,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1227 Instruction:"SALC" Encoding:"0xD6"/"" + // Pos:1228 Instruction:"SALC" Encoding:"0xD6"/"" { - ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 725, + ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20244,9 +20263,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1228 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" + // Pos:1229 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 726, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 727, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20261,9 +20280,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1229 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" + // Pos:1230 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 726, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 727, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20278,9 +20297,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1230 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" + // Pos:1231 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 726, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 727, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20295,9 +20314,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1231 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" + // Pos:1232 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 726, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 727, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20312,9 +20331,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1232 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" + // Pos:1233 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 726, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 727, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20329,9 +20348,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1233 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" + // Pos:1234 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 726, + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 727, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20346,9 +20365,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1234 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" + // Pos:1235 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" { - ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 727, + ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 728, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -20363,9 +20382,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1235 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" + // Pos:1236 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" { - ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 728, + ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 729, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -20379,9 +20398,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1236 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" + // Pos:1237 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20396,9 +20415,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1237 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" + // Pos:1238 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20413,9 +20432,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1238 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" + // Pos:1239 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20430,9 +20449,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1239 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" + // Pos:1240 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20447,9 +20466,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1240 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" + // Pos:1241 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20464,9 +20483,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1241 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" + // Pos:1242 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20481,9 +20500,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1242 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" + // Pos:1243 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20498,9 +20517,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1243 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" + // Pos:1244 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20515,9 +20534,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1244 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" + // Pos:1245 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -20532,9 +20551,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1245 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" + // Pos:1246 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 729, + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -20549,9 +20568,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1246 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" + // Pos:1247 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 730, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 731, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20567,9 +20586,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1247 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" + // Pos:1248 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 730, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 731, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20586,9 +20605,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1248 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" + // Pos:1249 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 731, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20604,9 +20623,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1249 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" + // Pos:1250 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 731, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20623,9 +20642,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1250 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" + // Pos:1251 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20641,9 +20660,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1251 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" + // Pos:1252 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20660,9 +20679,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1252 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" + // Pos:1253 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 734, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20678,9 +20697,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1253 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" + // Pos:1254 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 734, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -20697,9 +20716,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1254 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" + // Pos:1255 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" { - ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 734, + ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 735, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -20712,9 +20731,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1255 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" + // Pos:1256 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" { - ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 735, + ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 736, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -20731,9 +20750,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1256 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" + // Pos:1257 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" { - ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 736, + ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 737, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -20746,9 +20765,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1257 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M" + // Pos:1258 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M" { - ND_INS_SENDUIPI, ND_CAT_UINTR, ND_SET_UINTR, 737, + ND_INS_SENDUIPI, ND_CAT_UINTR, ND_SET_UINTR, 738, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, @@ -20761,9 +20780,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1258 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" + // Pos:1259 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" { - ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 738, + ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 739, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_SERIALIZE, @@ -20776,28 +20795,28 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1259 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 739, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1260 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" + // Pos:1260 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 740, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + 0, + 0, + 0, + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1261 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 741, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0, 0, @@ -20808,9 +20827,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1261 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" + // Pos:1262 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 741, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 742, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20824,9 +20843,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1262 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" + // Pos:1263 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 742, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 743, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20840,9 +20859,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1263 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" + // Pos:1264 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 743, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 744, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20856,9 +20875,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1264 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" + // Pos:1265 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 744, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 745, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20872,9 +20891,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1265 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" + // Pos:1266 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 745, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 746, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20888,9 +20907,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1266 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" + // Pos:1267 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 746, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 747, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20904,9 +20923,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1267 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" + // Pos:1268 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 747, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 748, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20920,9 +20939,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1268 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" + // Pos:1269 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 748, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 749, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20936,9 +20955,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1269 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" + // Pos:1270 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 749, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 750, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20952,9 +20971,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1270 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" + // Pos:1271 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 750, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 751, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20968,9 +20987,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1271 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" + // Pos:1272 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 751, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 752, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -20984,9 +21003,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1272 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" + // Pos:1273 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 752, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 753, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -21000,9 +21019,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1273 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" + // Pos:1274 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 753, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 754, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -21016,9 +21035,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1274 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" + // Pos:1275 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" { - ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 754, + ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 755, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, @@ -21032,9 +21051,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1275 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" + // Pos:1276 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 755, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 756, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, @@ -21048,9 +21067,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1276 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" + // Pos:1277 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" { - ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 756, + ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 757, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, @@ -21063,9 +21082,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1277 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" + // Pos:1278 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" { - ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 757, + ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 758, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21079,9 +21098,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1278 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" + // Pos:1279 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" { - ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 758, + ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 759, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -21095,9 +21114,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1279 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" + // Pos:1280 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" { - ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 759, + ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 760, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -21111,9 +21130,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1280 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" + // Pos:1281 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" { - ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 760, + ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 761, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -21127,9 +21146,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1281 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" + // Pos:1282 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" { - ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 761, + ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 762, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -21144,9 +21163,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1282 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" + // Pos:1283 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" { - ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 762, + ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 763, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -21160,9 +21179,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1283 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" + // Pos:1284 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" { - ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 763, + ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 764, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -21176,9 +21195,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1284 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" + // Pos:1285 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" { - ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 764, + ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 765, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, @@ -21193,9 +21212,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1285 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" + // Pos:1286 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 765, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 766, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21210,9 +21229,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1286 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" + // Pos:1287 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 765, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 766, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21227,9 +21246,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1287 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" + // Pos:1288 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 765, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 766, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21244,9 +21263,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1288 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" + // Pos:1289 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 765, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 766, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21261,9 +21280,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1289 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" + // Pos:1290 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 765, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 766, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21278,9 +21297,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1290 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" + // Pos:1291 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 765, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 766, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21295,9 +21314,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1291 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" + // Pos:1292 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" { - ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 766, + ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 767, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21313,9 +21332,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1292 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" + // Pos:1293 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" { - ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 766, + ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 767, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21331,9 +21350,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1293 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" + // Pos:1294 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" { - ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 767, + ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 768, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -21348,9 +21367,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1294 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" + // Pos:1295 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 768, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 769, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21365,9 +21384,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1295 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" + // Pos:1296 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 768, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 769, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21382,9 +21401,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1296 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" + // Pos:1297 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 768, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 769, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21399,9 +21418,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1297 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" + // Pos:1298 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 768, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 769, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21416,9 +21435,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1298 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" + // Pos:1299 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 768, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 769, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21433,9 +21452,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1299 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" + // Pos:1300 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 768, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 769, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21450,9 +21469,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1300 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" + // Pos:1301 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" { - ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 769, + ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 770, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21468,9 +21487,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1301 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" + // Pos:1302 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" { - ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 769, + ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 770, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21486,9 +21505,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1302 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" + // Pos:1303 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" { - ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 770, + ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 771, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, @@ -21503,9 +21522,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1303 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" + // Pos:1304 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" { - ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 771, + ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 772, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -21520,9 +21539,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1304 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" + // Pos:1305 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" { - ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 772, + ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 773, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -21537,9 +21556,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1305 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" + // Pos:1306 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" { - ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 773, + ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 774, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21553,9 +21572,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1306 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" + // Pos:1307 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" { - ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 774, + ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 775, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -21568,9 +21587,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1307 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" + // Pos:1308 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" { - ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 775, + ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 776, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21584,9 +21603,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1308 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" + // Pos:1309 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" { - ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 775, + ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 776, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21600,9 +21619,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1309 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" + // Pos:1310 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" { - ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 776, + ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 777, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, @@ -21615,9 +21634,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1310 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/"" + // Pos:1311 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/"" { - ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 777, + ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 778, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21630,9 +21649,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1311 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" + // Pos:1312 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" { - ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 778, + ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 779, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21646,9 +21665,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1312 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" + // Pos:1313 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" { - ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 778, + ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 779, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21662,9 +21681,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1313 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" + // Pos:1314 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" { - ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 779, + ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 780, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21677,9 +21696,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1314 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" + // Pos:1315 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 780, + ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 781, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -21693,9 +21712,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1315 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" + // Pos:1316 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 781, + ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 782, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -21709,9 +21728,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1316 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" + // Pos:1317 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 782, + ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 783, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -21725,9 +21744,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1317 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" + // Pos:1318 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 783, + ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 784, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -21741,9 +21760,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1318 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" + // Pos:1319 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" { - ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 784, + ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 785, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, @@ -21756,9 +21775,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1319 Instruction:"STC" Encoding:"0xF9"/"" + // Pos:1320 Instruction:"STC" Encoding:"0xF9"/"" { - ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 785, + ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 786, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21771,9 +21790,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1320 Instruction:"STD" Encoding:"0xFD"/"" + // Pos:1321 Instruction:"STD" Encoding:"0xFD"/"" { - ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 786, + ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 787, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21786,9 +21805,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1321 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" + // Pos:1322 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" { - ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 787, + ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 788, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -21801,9 +21820,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1322 Instruction:"STI" Encoding:"0xFB"/"" + // Pos:1323 Instruction:"STI" Encoding:"0xFB"/"" { - ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 788, + ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 789, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21816,9 +21835,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1323 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" + // Pos:1324 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" { - ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 789, + ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 790, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, @@ -21832,9 +21851,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1324 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" + // Pos:1325 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 790, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 791, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21850,9 +21869,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1325 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" + // Pos:1326 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 790, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 791, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21869,9 +21888,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1326 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" + // Pos:1327 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 791, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21887,9 +21906,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1327 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" + // Pos:1328 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 791, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21906,9 +21925,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1328 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" + // Pos:1329 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21924,9 +21943,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1329 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" + // Pos:1330 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21943,9 +21962,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1330 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" + // Pos:1331 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 794, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21961,9 +21980,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1331 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" + // Pos:1332 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 794, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, @@ -21980,9 +21999,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1332 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" + // Pos:1333 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" { - ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 794, + ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 795, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -21996,9 +22015,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1333 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" + // Pos:1334 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" { - ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 794, + ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 795, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22012,9 +22031,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1334 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" + // Pos:1335 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" { - ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 795, + ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 796, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -22027,9 +22046,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1335 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/"" + // Pos:1336 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/"" { - ND_INS_STUI, ND_CAT_UINTR, ND_SET_UINTR, 796, + ND_INS_STUI, ND_CAT_UINTR, ND_SET_UINTR, 797, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, @@ -22042,9 +22061,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1336 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" + // Pos:1337 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22059,9 +22078,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1337 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" + // Pos:1338 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22076,9 +22095,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1338 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" + // Pos:1339 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22093,9 +22112,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1339 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" + // Pos:1340 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22110,9 +22129,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1340 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" + // Pos:1341 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -22127,9 +22146,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1341 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" + // Pos:1342 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -22144,9 +22163,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1342 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" + // Pos:1343 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22161,9 +22180,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1343 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" + // Pos:1344 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22178,9 +22197,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1344 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" + // Pos:1345 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -22195,9 +22214,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1345 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" + // Pos:1346 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 797, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22212,9 +22231,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1346 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" + // Pos:1347 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" { - ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 798, + ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 799, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -22228,9 +22247,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1347 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" + // Pos:1348 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" { - ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 799, + ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 800, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -22244,9 +22263,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1348 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" + // Pos:1349 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" { - ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 800, + ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 801, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -22260,9 +22279,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1349 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" + // Pos:1350 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" { - ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 801, + ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 802, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -22276,9 +22295,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1350 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR" + // Pos:1351 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR" { - ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 802, + ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 803, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22292,9 +22311,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1351 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M" + // Pos:1352 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M" { - ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 803, + ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 804, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22307,9 +22326,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1352 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M" + // Pos:1353 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M" { - ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 804, + ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 805, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22322,9 +22341,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1353 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" + // Pos:1354 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" { - ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 805, + ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 806, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, @@ -22338,9 +22357,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1354 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" + // Pos:1355 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" { - ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 806, + ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 807, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 10), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT, ND_CFF_FSC, @@ -22362,9 +22381,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1355 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" + // Pos:1356 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" { - ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 807, + ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 808, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT, ND_CFF_SEP, @@ -22385,9 +22404,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1356 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" + // Pos:1357 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" { - ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 808, + ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 809, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_SEP, @@ -22404,9 +22423,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1357 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" + // Pos:1358 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" { - ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 809, + ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 810, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_FSC, @@ -22426,9 +22445,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1358 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" + // Pos:1359 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" { - ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 810, + ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 811, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -22442,9 +22461,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1359 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" + // Pos:1360 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" { - ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 811, + ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 812, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22457,9 +22476,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1360 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" + // Pos:1361 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" { - ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 812, + ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 813, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, @@ -22474,9 +22493,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1361 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" + // Pos:1362 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 813, + ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 814, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, @@ -22491,9 +22510,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1362 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" + // Pos:1363 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 814, + ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 815, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, @@ -22508,9 +22527,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1363 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" + // Pos:1364 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 815, + ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 816, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, @@ -22525,9 +22544,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1364 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" + // Pos:1365 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 816, + ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 817, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, @@ -22542,9 +22561,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1365 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/"" + // Pos:1366 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/"" { - ND_INS_TDPFP16PS, ND_CAT_AMX, ND_SET_AMXFP16, 817, + ND_INS_TDPFP16PS, ND_CAT_AMX, ND_SET_AMXFP16, 818, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXFP16, @@ -22559,9 +22578,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1366 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" + // Pos:1367 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 819, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22576,9 +22595,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1367 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" + // Pos:1368 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 819, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22593,9 +22612,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1368 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" + // Pos:1369 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 819, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -22610,9 +22629,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1369 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" + // Pos:1370 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 819, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -22627,9 +22646,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1370 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" + // Pos:1371 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 819, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22644,9 +22663,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1371 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" + // Pos:1372 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 819, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22661,9 +22680,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1372 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" + // Pos:1373 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 819, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22678,9 +22697,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1373 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" + // Pos:1374 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 818, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 819, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22695,9 +22714,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1374 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/"" + // Pos:1375 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/"" { - ND_INS_TESTUI, ND_CAT_UINTR, ND_SET_UINTR, 819, + ND_INS_TESTUI, ND_CAT_UINTR, ND_SET_UINTR, 820, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, @@ -22711,9 +22730,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1375 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:1376 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" { - ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 820, + ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 821, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -22727,9 +22746,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1376 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:1377 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" { - ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 821, + ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 822, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -22743,9 +22762,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1377 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" + // Pos:1378 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" { - ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 822, + ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 823, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -22758,9 +22777,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1378 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:1379 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" { - ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 823, + ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 824, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -22774,9 +22793,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1379 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" + // Pos:1380 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" { - ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 824, + ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 825, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, @@ -22789,9 +22808,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1380 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/"" + // Pos:1381 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/"" { - ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 825, + ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 826, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, @@ -22804,9 +22823,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1381 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" + // Pos:1382 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" { - ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 826, + ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 827, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, @@ -22822,9 +22841,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1382 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM" + // Pos:1383 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM" { - ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 827, + ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 828, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, @@ -22839,9 +22858,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1383 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" + // Pos:1384 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" { - ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 828, + ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 829, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, @@ -22855,9 +22874,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1384 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" + // Pos:1385 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" { - ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 829, + ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 830, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -22872,9 +22891,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1385 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" + // Pos:1386 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" { - ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 830, + ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 831, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -22889,9 +22908,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1386 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" + // Pos:1387 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" { - ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 831, + ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 832, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22905,9 +22924,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1387 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" + // Pos:1388 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" { - ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 832, + ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 833, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -22921,9 +22940,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1388 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" + // Pos:1389 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" { - ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 833, + ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 834, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -22936,9 +22955,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1389 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/"" + // Pos:1390 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/"" { - ND_INS_UIRET, ND_CAT_RET, ND_SET_UINTR, 834, + ND_INS_UIRET, ND_CAT_RET, ND_SET_UINTR, 835, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 6), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, @@ -22956,9 +22975,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1390 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" + // Pos:1391 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" { - ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 835, + ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 836, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, @@ -22972,9 +22991,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1391 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" + // Pos:1392 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" { - ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 836, + ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 837, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, @@ -22989,9 +23008,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1392 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" + // Pos:1393 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" { - ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 837, + ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 838, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -23005,9 +23024,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1393 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" + // Pos:1394 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" { - ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 838, + ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 839, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -23021,9 +23040,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1394 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" + // Pos:1395 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" { - ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 839, + ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 840, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -23037,9 +23056,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1395 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" + // Pos:1396 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" { - ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 840, + ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 841, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -23053,9 +23072,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1396 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" + // Pos:1397 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" { - ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 841, + ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 842, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, @@ -23071,9 +23090,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1397 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" + // Pos:1398 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" { - ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 842, + ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 843, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, @@ -23089,9 +23108,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1398 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" + // Pos:1399 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" { - ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 843, + ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 844, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, @@ -23107,9 +23126,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1399 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" + // Pos:1400 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" { - ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 844, + ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 845, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, @@ -23125,9 +23144,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1400 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" + // Pos:1401 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" { - ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 845, + ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 846, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23143,9 +23162,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1401 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" + // Pos:1402 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" { - ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 845, + ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 846, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23160,9 +23179,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1402 Instruction:"VADDPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM" + // Pos:1403 Instruction:"VADDPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM" { - ND_INS_VADDPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 846, + ND_INS_VADDPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 847, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -23178,9 +23197,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1403 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" + // Pos:1404 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" { - ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 847, + ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 848, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23196,9 +23215,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1404 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" + // Pos:1405 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" { - ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 847, + ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 848, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23213,9 +23232,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1405 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" + // Pos:1406 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" { - ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 848, + ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 849, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23231,9 +23250,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1406 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" + // Pos:1407 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" { - ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 848, + ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 849, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23248,9 +23267,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1407 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM" + // Pos:1408 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM" { - ND_INS_VADDSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 849, + ND_INS_VADDSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 850, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -23266,9 +23285,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1408 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" + // Pos:1409 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" { - ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 850, + ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 851, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23284,9 +23303,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1409 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" + // Pos:1410 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" { - ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 850, + ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 851, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23301,9 +23320,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1410 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" + // Pos:1411 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" { - ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 851, + ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 852, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23318,9 +23337,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1411 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" + // Pos:1412 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" { - ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 852, + ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 853, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23335,9 +23354,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1412 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:1413 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { - ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 853, + ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 854, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, @@ -23352,9 +23371,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1413 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:1414 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { - ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 853, + ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 854, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -23369,9 +23388,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1414 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:1415 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { - ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 854, + ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 855, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, @@ -23386,9 +23405,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1415 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:1416 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { - ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 854, + ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 855, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -23403,9 +23422,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1416 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:1417 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { - ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 855, + ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 856, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, @@ -23420,9 +23439,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1417 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:1418 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { - ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 855, + ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 856, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -23437,9 +23456,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1418 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:1419 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { - ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 856, + ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 857, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, @@ -23454,9 +23473,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1419 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:1420 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { - ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 856, + ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 857, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -23471,9 +23490,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1420 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" + // Pos:1421 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" { - ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 857, + ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 858, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -23487,9 +23506,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1421 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" + // Pos:1422 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" { - ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 858, + ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 859, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, @@ -23504,9 +23523,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1422 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" + // Pos:1423 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" { - ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 859, + ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 860, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23523,9 +23542,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1423 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" + // Pos:1424 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" { - ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 860, + ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 861, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23542,9 +23561,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1424 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" + // Pos:1425 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" { - ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 861, + ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 862, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23560,9 +23579,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1425 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" + // Pos:1426 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" { - ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 861, + ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 862, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23577,9 +23596,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1426 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" + // Pos:1427 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" { - ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 862, + ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 863, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23595,9 +23614,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1427 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" + // Pos:1428 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" { - ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 862, + ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 863, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23612,9 +23631,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1428 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" + // Pos:1429 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" { - ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 863, + ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 864, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23630,9 +23649,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1429 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" + // Pos:1430 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" { - ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 863, + ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 864, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23647,9 +23666,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1430 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" + // Pos:1431 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" { - ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 864, + ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 865, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23665,9 +23684,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1431 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" + // Pos:1432 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" { - ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 864, + ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 865, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23682,9 +23701,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1432 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM" + // Pos:1433 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM" { - ND_INS_VBCSTNEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 865, + ND_INS_VBCSTNEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 866, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, @@ -23698,9 +23717,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1433 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM" + // Pos:1434 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM" { - ND_INS_VBCSTNESH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 866, + ND_INS_VBCSTNESH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 867, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, @@ -23714,9 +23733,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1434 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" + // Pos:1435 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" { - ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 867, + ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 868, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23732,9 +23751,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1435 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" + // Pos:1436 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" { - ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 868, + ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 869, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23750,9 +23769,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1436 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" + // Pos:1437 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" { - ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 869, + ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 870, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23768,9 +23787,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1437 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" + // Pos:1438 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" { - ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 870, + ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 871, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23786,9 +23805,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1438 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" + // Pos:1439 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" { - ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 871, + ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 872, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23804,9 +23823,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1439 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" + // Pos:1440 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" { - ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 872, + ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 873, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23822,9 +23841,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1440 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" + // Pos:1441 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" { - ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 873, + ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 874, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -23838,9 +23857,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1441 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" + // Pos:1442 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" { - ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 874, + ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 875, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23855,9 +23874,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1442 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" + // Pos:1443 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" { - ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 875, + ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 876, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23872,9 +23891,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1443 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" + // Pos:1444 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" { - ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 876, + ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 877, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23889,9 +23908,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1444 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" + // Pos:1445 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" { - ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 877, + ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 878, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23906,9 +23925,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1445 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" + // Pos:1446 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" { - ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 878, + ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 879, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23923,9 +23942,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1446 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" + // Pos:1447 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" { - ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 879, + ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 880, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -23939,9 +23958,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1447 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" + // Pos:1448 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" { - ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 880, + ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 881, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23956,9 +23975,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1448 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" + // Pos:1449 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" { - ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 881, + ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 882, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -23973,9 +23992,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1449 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" + // Pos:1450 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" { - ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 882, + ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 883, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -23990,9 +24009,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1450 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" + // Pos:1451 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" { - ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 883, + ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 884, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24007,9 +24026,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1451 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" + // Pos:1452 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" { - ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 884, + ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 885, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24024,9 +24043,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1452 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" + // Pos:1453 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" { - ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 885, + ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 886, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24041,9 +24060,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1453 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" + // Pos:1454 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" { - ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 885, + ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 886, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24057,9 +24076,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1454 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" + // Pos:1455 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" { - ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 886, + ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 887, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24074,9 +24093,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1455 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" + // Pos:1456 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" { - ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 886, + ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 887, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24090,9 +24109,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1456 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" + // Pos:1457 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 887, + ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 888, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24109,9 +24128,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1457 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" + // Pos:1458 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 887, + ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 888, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24127,9 +24146,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1458 Instruction:"VCMPPH rK{K},aKq,Hn,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:1459 Instruction:"VCMPPH rK{K},aKq,Hn,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 888, + ND_INS_VCMPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 889, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24146,9 +24165,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1459 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:1460 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 889, + ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 890, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24165,9 +24184,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1460 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:1461 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 889, + ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 890, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24183,9 +24202,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1461 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" + // Pos:1462 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 890, + ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 891, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24202,9 +24221,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1462 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:1463 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 890, + ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 891, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24220,9 +24239,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1463 Instruction:"VCMPSH rK{K},aKq,Hn,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI" + // Pos:1464 Instruction:"VCMPSH rK{K},aKq,Hn,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 891, + ND_INS_VCMPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 892, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24239,9 +24258,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1464 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:1465 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 892, + ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 893, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24258,9 +24277,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1465 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:1466 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 892, + ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 893, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24276,9 +24295,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1466 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" + // Pos:1467 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" { - ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 893, + ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 894, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24293,9 +24312,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1467 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" + // Pos:1468 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" { - ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 893, + ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 894, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24310,9 +24329,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1468 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM" + // Pos:1469 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM" { - ND_INS_VCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 894, + ND_INS_VCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 895, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24327,9 +24346,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1469 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" + // Pos:1470 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" { - ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 895, + ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 896, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24344,9 +24363,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1470 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" + // Pos:1471 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" { - ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 895, + ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 896, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24361,9 +24380,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1471 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" + // Pos:1472 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" { - ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 896, + ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 897, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24378,9 +24397,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1472 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" + // Pos:1473 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" { - ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 897, + ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 898, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24395,9 +24414,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1473 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" + // Pos:1474 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 898, + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 899, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24412,9 +24431,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1474 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" + // Pos:1475 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 898, + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 899, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24428,9 +24447,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1475 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" + // Pos:1476 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 898, + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 899, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24444,9 +24463,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1476 Instruction:"VCVTDQ2PH Vh{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM" + // Pos:1477 Instruction:"VCVTDQ2PH Vh{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 899, + ND_INS_VCVTDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 900, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24461,9 +24480,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1477 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" + // Pos:1478 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 900, + ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 901, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24478,9 +24497,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1478 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" + // Pos:1479 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" { - ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 900, + ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 901, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24494,9 +24513,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1479 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" + // Pos:1480 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" { - ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 901, + ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 902, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, @@ -24512,9 +24531,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1480 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM" + // Pos:1481 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM" { - ND_INS_VCVTNEEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 902, + ND_INS_VCVTNEEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 903, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, @@ -24528,9 +24547,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1481 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM" + // Pos:1482 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM" { - ND_INS_VCVTNEEPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 903, + ND_INS_VCVTNEEPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 904, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, @@ -24544,9 +24563,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1482 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM" + // Pos:1483 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM" { - ND_INS_VCVTNEOBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 904, + ND_INS_VCVTNEOBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 905, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, @@ -24560,9 +24579,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1483 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM" + // Pos:1484 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM" { - ND_INS_VCVTNEOPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 905, + ND_INS_VCVTNEOPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 906, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, @@ -24576,9 +24595,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1484 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" + // Pos:1485 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" { - ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 906, + ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 907, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, @@ -24593,9 +24612,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1485 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM" + // Pos:1486 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM" { - ND_INS_VCVTNEPS2BF16, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 906, + ND_INS_VCVTNEPS2BF16, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 907, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, @@ -24609,9 +24628,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1486 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" + // Pos:1487 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" { - ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 907, + ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 908, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24626,9 +24645,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1487 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" + // Pos:1488 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" { - ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 907, + ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 908, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24642,9 +24661,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1488 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM" + // Pos:1489 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM" { - ND_INS_VCVTPD2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 908, + ND_INS_VCVTPD2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 909, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24659,9 +24678,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1489 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" + // Pos:1490 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 909, + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 910, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24676,9 +24695,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1490 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" + // Pos:1491 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 909, + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 910, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24692,9 +24711,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1491 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" + // Pos:1492 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 909, + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 910, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24708,9 +24727,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1492 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" + // Pos:1493 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" { - ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 910, + ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 911, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24725,9 +24744,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1493 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" + // Pos:1494 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" { - ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 911, + ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 912, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24742,9 +24761,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1494 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" + // Pos:1495 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" { - ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 912, + ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 913, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -24759,9 +24778,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1495 Instruction:"VCVTPH2DQ Vn{K}{z},aKq,Wh|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM" + // Pos:1496 Instruction:"VCVTPH2DQ Vn{K}{z},aKq,Wh|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 913, + ND_INS_VCVTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 914, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24776,9 +24795,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1496 Instruction:"VCVTPH2PD Vn{K}{z},aKq,Wf|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM" + // Pos:1497 Instruction:"VCVTPH2PD Vn{K}{z},aKq,Wf|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM" { - ND_INS_VCVTPH2PD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 914, + ND_INS_VCVTPH2PD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 915, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24793,9 +24812,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1497 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" + // Pos:1498 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 915, + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 916, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24810,9 +24829,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1498 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" + // Pos:1499 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 915, + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 916, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, @@ -24826,9 +24845,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1499 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" + // Pos:1500 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 915, + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 916, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, @@ -24842,9 +24861,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1500 Instruction:"VCVTPH2PSX Vn{K}{z},aKq,Wh|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM" + // Pos:1501 Instruction:"VCVTPH2PSX Vn{K}{z},aKq,Wh|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM" { - ND_INS_VCVTPH2PSX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 916, + ND_INS_VCVTPH2PSX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 917, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24859,9 +24878,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1501 Instruction:"VCVTPH2QQ Vn{K}{z},aKq,Wf|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM" + // Pos:1502 Instruction:"VCVTPH2QQ Vn{K}{z},aKq,Wf|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM" { - ND_INS_VCVTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 917, + ND_INS_VCVTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 918, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24876,9 +24895,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1502 Instruction:"VCVTPH2UDQ Vn{K}{z},aKq,Wh|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM" + // Pos:1503 Instruction:"VCVTPH2UDQ Vn{K}{z},aKq,Wh|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VCVTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 918, + ND_INS_VCVTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 919, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24893,9 +24912,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1503 Instruction:"VCVTPH2UQQ Vn{K}{z},aKq,Wf|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:1504 Instruction:"VCVTPH2UQQ Vn{K}{z},aKq,Wf|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VCVTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 919, + ND_INS_VCVTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 920, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24910,9 +24929,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1504 Instruction:"VCVTPH2UW Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM" + // Pos:1505 Instruction:"VCVTPH2UW Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM" { - ND_INS_VCVTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 920, + ND_INS_VCVTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 921, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24927,9 +24946,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1505 Instruction:"VCVTPH2W Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM" + // Pos:1506 Instruction:"VCVTPH2W Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM" { - ND_INS_VCVTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 921, + ND_INS_VCVTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 922, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -24944,9 +24963,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1506 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" + // Pos:1507 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 922, + ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 923, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24961,9 +24980,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1507 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" + // Pos:1508 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" { - ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 922, + ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 923, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -24977,9 +24996,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1508 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" + // Pos:1509 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 923, + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 924, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -24994,9 +25013,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1509 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" + // Pos:1510 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 923, + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 924, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25010,9 +25029,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1510 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" + // Pos:1511 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 923, + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 924, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25026,9 +25045,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1511 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" + // Pos:1512 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 924, + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 925, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25044,9 +25063,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1512 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" + // Pos:1513 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 924, + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 925, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, @@ -25061,9 +25080,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1513 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" + // Pos:1514 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 924, + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 925, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, @@ -25078,9 +25097,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1514 Instruction:"VCVTPS2PHX Vh{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM" + // Pos:1515 Instruction:"VCVTPS2PHX Vh{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM" { - ND_INS_VCVTPS2PHX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 925, + ND_INS_VCVTPS2PHX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 926, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25095,9 +25114,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1515 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" + // Pos:1516 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" { - ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 926, + ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 927, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25112,9 +25131,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1516 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" + // Pos:1517 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 927, + ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 928, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25129,9 +25148,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1517 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:1518 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 928, + ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 929, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25146,9 +25165,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1518 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" + // Pos:1519 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" { - ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 929, + ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 930, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25163,9 +25182,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1519 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM" + // Pos:1520 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM" { - ND_INS_VCVTQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 930, + ND_INS_VCVTQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 931, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25180,9 +25199,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1520 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" + // Pos:1521 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" { - ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 931, + ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 932, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25197,9 +25216,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1521 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM" + // Pos:1522 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM" { - ND_INS_VCVTSD2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 932, + ND_INS_VCVTSD2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 933, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25215,9 +25234,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1522 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" + // Pos:1523 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 933, + ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 934, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25231,9 +25250,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1523 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" + // Pos:1524 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 933, + ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 934, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25247,9 +25266,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1524 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" + // Pos:1525 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" { - ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 934, + ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 935, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25265,9 +25284,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1525 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" + // Pos:1526 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" { - ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 934, + ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 935, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25282,9 +25301,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1526 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" + // Pos:1527 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" { - ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 935, + ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 936, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25298,9 +25317,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1527 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM" + // Pos:1528 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM" { - ND_INS_VCVTSH2SD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 936, + ND_INS_VCVTSH2SD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 937, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25316,9 +25335,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1528 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:1529 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 937, + ND_INS_VCVTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 938, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25332,9 +25351,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1529 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM" + // Pos:1530 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM" { - ND_INS_VCVTSH2SS, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 938, + ND_INS_VCVTSH2SS, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 939, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25350,9 +25369,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1530 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM" + // Pos:1531 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM" { - ND_INS_VCVTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 939, + ND_INS_VCVTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 940, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25366,9 +25385,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1531 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" + // Pos:1532 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 940, + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 941, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25383,9 +25402,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1532 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" + // Pos:1533 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 940, + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 941, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25400,9 +25419,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1533 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" + // Pos:1534 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 940, + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 941, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25417,9 +25436,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1534 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:1535 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 941, + ND_INS_VCVTSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 942, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25434,9 +25453,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1535 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:1536 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 942, + ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 943, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25451,9 +25470,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1536 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:1537 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 942, + ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 943, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25468,9 +25487,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1537 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" + // Pos:1538 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" { - ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 943, + ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 944, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25486,9 +25505,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1538 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" + // Pos:1539 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" { - ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 943, + ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 944, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25503,9 +25522,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1539 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM" + // Pos:1540 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM" { - ND_INS_VCVTSS2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 944, + ND_INS_VCVTSS2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 945, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25521,9 +25540,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1540 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:1541 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 945, + ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 946, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25537,9 +25556,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1541 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:1542 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 945, + ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 946, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25553,9 +25572,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1542 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" + // Pos:1543 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" { - ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 946, + ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 947, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25569,9 +25588,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1543 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" + // Pos:1544 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" { - ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 947, + ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 948, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25586,9 +25605,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1544 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" + // Pos:1545 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" { - ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 947, + ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 948, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25602,9 +25621,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1545 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" + // Pos:1546 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 948, + ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 949, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25619,9 +25638,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1546 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" + // Pos:1547 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" { - ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 949, + ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 950, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25636,9 +25655,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1547 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" + // Pos:1548 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" { - ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 950, + ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 951, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25653,9 +25672,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1548 Instruction:"VCVTTPH2DQ Vn{K}{z},aKq,Wh|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM" + // Pos:1549 Instruction:"VCVTTPH2DQ Vn{K}{z},aKq,Wh|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 951, + ND_INS_VCVTTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 952, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25670,9 +25689,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1549 Instruction:"VCVTTPH2QQ Vn{K}{z},aKq,Wf|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM" + // Pos:1550 Instruction:"VCVTTPH2QQ Vn{K}{z},aKq,Wf|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 952, + ND_INS_VCVTTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 953, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25687,9 +25706,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1550 Instruction:"VCVTTPH2UDQ Vn{K}{z},aKq,Wh|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM" + // Pos:1551 Instruction:"VCVTTPH2UDQ Vn{K}{z},aKq,Wh|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VCVTTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 953, + ND_INS_VCVTTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 954, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25704,9 +25723,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1551 Instruction:"VCVTTPH2UQQ Vn{K}{z},aKq,Wf|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:1552 Instruction:"VCVTTPH2UQQ Vn{K}{z},aKq,Wf|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VCVTTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 954, + ND_INS_VCVTTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 955, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25721,9 +25740,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1552 Instruction:"VCVTTPH2UW Vn{K}{z},aKq,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM" + // Pos:1553 Instruction:"VCVTTPH2UW Vn{K}{z},aKq,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM" { - ND_INS_VCVTTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 955, + ND_INS_VCVTTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 956, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25738,9 +25757,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1553 Instruction:"VCVTTPH2W Vn{K}{z},aKq,Wn|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM" + // Pos:1554 Instruction:"VCVTTPH2W Vn{K}{z},aKq,Wn|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM" { - ND_INS_VCVTTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 956, + ND_INS_VCVTTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 957, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25755,9 +25774,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1554 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" + // Pos:1555 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 957, + ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 958, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25772,9 +25791,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1555 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" + // Pos:1556 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" { - ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 957, + ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 958, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25788,9 +25807,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1556 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" + // Pos:1557 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 958, + ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 959, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25805,9 +25824,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1557 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" + // Pos:1558 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 959, + ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 960, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25822,9 +25841,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1558 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:1559 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 960, + ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 961, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -25839,9 +25858,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1559 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" + // Pos:1560 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 961, + ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 962, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25855,9 +25874,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1560 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" + // Pos:1561 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 961, + ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 962, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25871,9 +25890,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1561 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" + // Pos:1562 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" { - ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 962, + ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 963, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25887,9 +25906,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1562 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:1563 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 963, + ND_INS_VCVTTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 964, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25903,9 +25922,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1563 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM" + // Pos:1564 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM" { - ND_INS_VCVTTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 964, + ND_INS_VCVTTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 965, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -25919,9 +25938,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1564 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:1565 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 965, + ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 966, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25935,9 +25954,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1565 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:1566 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 965, + ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 966, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -25951,9 +25970,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1566 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" + // Pos:1567 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" { - ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 966, + ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 967, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25967,9 +25986,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1567 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" + // Pos:1568 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 967, + ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 968, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -25984,9 +26003,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1568 Instruction:"VCVTUDQ2PH Vh{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM" + // Pos:1569 Instruction:"VCVTUDQ2PH Vh{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTUDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 968, + ND_INS_VCVTUDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 969, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26001,9 +26020,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1569 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" + // Pos:1570 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 969, + ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 970, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26018,9 +26037,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1570 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" + // Pos:1571 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 970, + ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 971, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -26035,9 +26054,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1571 Instruction:"VCVTUQQ2PH Vf{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM" + // Pos:1572 Instruction:"VCVTUQQ2PH Vf{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTUQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 971, + ND_INS_VCVTUQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 972, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26052,9 +26071,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1572 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" + // Pos:1573 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 972, + ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 973, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -26069,9 +26088,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1573 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" + // Pos:1574 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 973, + ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 974, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26086,9 +26105,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1574 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" + // Pos:1575 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 973, + ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 974, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26103,9 +26122,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1575 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM" + // Pos:1576 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 974, + ND_INS_VCVTUSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 975, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26120,9 +26139,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1576 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" + // Pos:1577 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 975, + ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 976, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26137,9 +26156,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1577 Instruction:"VCVTUW2PH Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM" + // Pos:1578 Instruction:"VCVTUW2PH Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM" { - ND_INS_VCVTUW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 976, + ND_INS_VCVTUW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 977, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26154,9 +26173,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1578 Instruction:"VCVTW2PH Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM" + // Pos:1579 Instruction:"VCVTW2PH Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM" { - ND_INS_VCVTW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 977, + ND_INS_VCVTW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 978, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26171,9 +26190,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1579 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" + // Pos:1580 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" { - ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 978, + ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 979, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -26190,9 +26209,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1580 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" + // Pos:1581 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" { - ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 979, + ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 980, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26208,9 +26227,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1581 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" + // Pos:1582 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" { - ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 979, + ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 980, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -26225,9 +26244,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1582 Instruction:"VDIVPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM" + // Pos:1583 Instruction:"VDIVPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM" { - ND_INS_VDIVPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 980, + ND_INS_VDIVPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 981, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26243,9 +26262,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1583 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" + // Pos:1584 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" { - ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 981, + ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 982, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26261,9 +26280,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1584 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" + // Pos:1585 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" { - ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 981, + ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 982, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -26278,9 +26297,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1585 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" + // Pos:1586 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" { - ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 982, + ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 983, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26296,9 +26315,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1586 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" + // Pos:1587 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" { - ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 982, + ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 983, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -26313,9 +26332,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1587 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM" + // Pos:1588 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM" { - ND_INS_VDIVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 983, + ND_INS_VDIVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 984, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26331,9 +26350,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1588 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" + // Pos:1589 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" { - ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 984, + ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 985, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26349,9 +26368,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1589 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" + // Pos:1590 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" { - ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 984, + ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 985, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -26366,9 +26385,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1590 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" + // Pos:1591 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" { - ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 985, + ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 986, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, @@ -26384,9 +26403,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1591 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" + // Pos:1592 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" { - ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 986, + ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 987, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -26402,9 +26421,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1592 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" + // Pos:1593 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" { - ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 987, + ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 988, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -26420,9 +26439,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1593 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" + // Pos:1594 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" { - ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 988, + ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 989, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -26436,9 +26455,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1594 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" + // Pos:1595 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" { - ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 989, + ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 990, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -26452,9 +26471,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1595 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" + // Pos:1596 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" { - ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 990, + ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 991, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -26469,9 +26488,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1596 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" + // Pos:1597 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" { - ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 991, + ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 992, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -26486,9 +26505,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1597 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" + // Pos:1598 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" { - ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 992, + ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 993, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26503,9 +26522,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1598 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" + // Pos:1599 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" { - ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 993, + ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 994, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26520,9 +26539,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1599 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" + // Pos:1600 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" { - ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 994, + ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 995, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -26537,9 +26556,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1600 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" + // Pos:1601 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" { - ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 995, + ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 996, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26555,9 +26574,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1601 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" + // Pos:1602 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" { - ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 996, + ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 997, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -26573,9 +26592,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1602 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" + // Pos:1603 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" { - ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 997, + ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 998, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -26591,9 +26610,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1603 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" + // Pos:1604 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" { - ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 998, + ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 999, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26609,9 +26628,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1604 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" + // Pos:1605 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" { - ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 999, + ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 1000, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -26626,9 +26645,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1605 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" + // Pos:1606 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" { - ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1000, + ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1001, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26644,9 +26663,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1606 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" + // Pos:1607 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" { - ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1001, + ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1002, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -26662,9 +26681,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1607 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" + // Pos:1608 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" { - ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1002, + ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1003, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -26680,9 +26699,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1608 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" + // Pos:1609 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" { - ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1003, + ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1004, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26698,9 +26717,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1609 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + // Pos:1610 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1004, + ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1005, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26715,9 +26734,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1610 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + // Pos:1611 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1004, + ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1005, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26732,9 +26751,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1611 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + // Pos:1612 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1004, + ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1005, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -26749,9 +26768,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1612 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + // Pos:1613 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1004, + ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1005, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -26766,9 +26785,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1613 Instruction:"VFCMADDCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM" + // Pos:1614 Instruction:"VFCMADDCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM" { - ND_INS_VFCMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1005, + ND_INS_VFCMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1006, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26784,9 +26803,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1614 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM" + // Pos:1615 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM" { - ND_INS_VFCMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1006, + ND_INS_VFCMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1007, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26802,9 +26821,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1615 Instruction:"VFCMULCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM" + // Pos:1616 Instruction:"VFCMULCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM" { - ND_INS_VFCMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1007, + ND_INS_VFCMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1008, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26820,9 +26839,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1616 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM" + // Pos:1617 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM" { - ND_INS_VFCMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1008, + ND_INS_VFCMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1009, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26838,9 +26857,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1617 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" + // Pos:1618 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1009, + ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1010, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26857,9 +26876,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1618 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" + // Pos:1619 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1010, + ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1011, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26876,9 +26895,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1619 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" + // Pos:1620 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 1011, + ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 1012, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26895,9 +26914,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1620 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" + // Pos:1621 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 1012, + ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 1013, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26914,9 +26933,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1621 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" + // Pos:1622 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" { - ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1013, + ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1014, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26932,9 +26951,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1622 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" + // Pos:1623 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" { - ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1013, + ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1014, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -26949,9 +26968,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1623 Instruction:"VFMADD132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM" + // Pos:1624 Instruction:"VFMADD132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM" { - ND_INS_VFMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1014, + ND_INS_VFMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1015, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -26967,9 +26986,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1624 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" + // Pos:1625 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" { - ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1015, + ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1016, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -26985,9 +27004,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1625 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" + // Pos:1626 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" { - ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1015, + ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1016, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27002,9 +27021,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1626 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" + // Pos:1627 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" { - ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1016, + ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1017, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27020,9 +27039,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1627 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" + // Pos:1628 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" { - ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1016, + ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1017, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27037,9 +27056,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1628 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM" + // Pos:1629 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM" { - ND_INS_VFMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1017, + ND_INS_VFMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1018, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27055,9 +27074,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1629 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" + // Pos:1630 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" { - ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1018, + ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1019, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27073,9 +27092,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1630 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" + // Pos:1631 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" { - ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1018, + ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1019, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27090,9 +27109,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1631 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" + // Pos:1632 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" { - ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1019, + ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1020, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27108,9 +27127,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1632 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" + // Pos:1633 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" { - ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1019, + ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1020, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27125,9 +27144,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1633 Instruction:"VFMADD213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM" + // Pos:1634 Instruction:"VFMADD213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM" { - ND_INS_VFMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1020, + ND_INS_VFMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1021, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27143,9 +27162,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1634 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" + // Pos:1635 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" { - ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1021, + ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1022, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27161,9 +27180,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1635 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" + // Pos:1636 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" { - ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1021, + ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1022, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27178,9 +27197,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1636 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" + // Pos:1637 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" { - ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1022, + ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1023, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27196,9 +27215,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1637 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" + // Pos:1638 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" { - ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1022, + ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1023, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27213,9 +27232,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1638 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM" + // Pos:1639 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM" { - ND_INS_VFMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1023, + ND_INS_VFMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1024, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27231,9 +27250,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1639 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" + // Pos:1640 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" { - ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1024, + ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1025, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27249,9 +27268,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1640 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" + // Pos:1641 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" { - ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1024, + ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1025, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27266,9 +27285,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1641 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" + // Pos:1642 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" { - ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1025, + ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1026, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27284,9 +27303,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1642 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" + // Pos:1643 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" { - ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1025, + ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1026, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27301,9 +27320,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1643 Instruction:"VFMADD231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM" + // Pos:1644 Instruction:"VFMADD231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM" { - ND_INS_VFMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1026, + ND_INS_VFMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1027, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27319,9 +27338,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1644 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" + // Pos:1645 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" { - ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1027, + ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1028, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27337,9 +27356,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1645 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" + // Pos:1646 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" { - ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1027, + ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1028, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27354,9 +27373,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1646 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" + // Pos:1647 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" { - ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1028, + ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1029, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27372,9 +27391,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1647 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" + // Pos:1648 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" { - ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1028, + ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1029, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27389,9 +27408,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1648 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM" + // Pos:1649 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM" { - ND_INS_VFMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1029, + ND_INS_VFMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1030, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27407,9 +27426,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1649 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" + // Pos:1650 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" { - ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1030, + ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1031, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27425,9 +27444,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1650 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" + // Pos:1651 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" { - ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1030, + ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1031, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27442,9 +27461,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1651 Instruction:"VFMADDCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM" + // Pos:1652 Instruction:"VFMADDCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM" { - ND_INS_VFMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1031, + ND_INS_VFMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1032, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27460,9 +27479,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1652 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM" + // Pos:1653 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM" { - ND_INS_VFMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1032, + ND_INS_VFMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1033, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27478,9 +27497,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1653 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" + // Pos:1654 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" { - ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1033, + ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1034, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27496,9 +27515,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1654 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" + // Pos:1655 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" { - ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1033, + ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1034, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27514,9 +27533,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1655 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" + // Pos:1656 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" { - ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1034, + ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1035, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27532,9 +27551,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1656 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" + // Pos:1657 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" { - ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1034, + ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1035, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27550,9 +27569,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1657 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" + // Pos:1658 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" { - ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1035, + ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1036, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27568,9 +27587,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1658 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" + // Pos:1659 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" { - ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1035, + ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1036, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27586,9 +27605,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1659 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" + // Pos:1660 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" { - ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1036, + ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1037, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27604,9 +27623,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1660 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" + // Pos:1661 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" { - ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1036, + ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1037, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27622,9 +27641,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1661 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" + // Pos:1662 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" { - ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1037, + ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1038, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27640,9 +27659,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1662 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" + // Pos:1663 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" { - ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1037, + ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1038, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27657,9 +27676,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1663 Instruction:"VFMADDSUB132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM" + // Pos:1664 Instruction:"VFMADDSUB132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM" { - ND_INS_VFMADDSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1038, + ND_INS_VFMADDSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1039, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27675,9 +27694,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1664 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" + // Pos:1665 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" { - ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1039, + ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1040, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27693,9 +27712,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1665 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" + // Pos:1666 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" { - ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1039, + ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1040, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27710,9 +27729,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1666 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" + // Pos:1667 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" { - ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1040, + ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1041, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27728,9 +27747,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1667 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" + // Pos:1668 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" { - ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1040, + ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1041, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27745,9 +27764,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1668 Instruction:"VFMADDSUB213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM" + // Pos:1669 Instruction:"VFMADDSUB213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM" { - ND_INS_VFMADDSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1041, + ND_INS_VFMADDSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1042, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27763,9 +27782,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1669 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" + // Pos:1670 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" { - ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1042, + ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1043, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27781,9 +27800,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1670 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" + // Pos:1671 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" { - ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1042, + ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1043, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27798,9 +27817,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1671 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" + // Pos:1672 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" { - ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1043, + ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1044, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27816,9 +27835,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1672 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" + // Pos:1673 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" { - ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1043, + ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1044, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27833,9 +27852,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1673 Instruction:"VFMADDSUB231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM" + // Pos:1674 Instruction:"VFMADDSUB231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM" { - ND_INS_VFMADDSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1044, + ND_INS_VFMADDSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1045, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -27851,9 +27870,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1674 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" + // Pos:1675 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" { - ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1045, + ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1046, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27869,9 +27888,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1675 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" + // Pos:1676 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" { - ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1045, + ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1046, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27886,9 +27905,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1676 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" + // Pos:1677 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" { - ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1046, + ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1047, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27904,9 +27923,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1677 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" + // Pos:1678 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" { - ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1046, + ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1047, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27922,9 +27941,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1678 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" + // Pos:1679 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" { - ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1047, + ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1048, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27940,9 +27959,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1679 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" + // Pos:1680 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" { - ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1047, + ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1048, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -27958,9 +27977,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1680 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" + // Pos:1681 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" { - ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1048, + ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1049, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -27976,9 +27995,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1681 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" + // Pos:1682 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" { - ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1048, + ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1049, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -27993,9 +28012,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1682 Instruction:"VFMSUB132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM" + // Pos:1683 Instruction:"VFMSUB132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM" { - ND_INS_VFMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1049, + ND_INS_VFMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1050, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28011,9 +28030,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1683 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" + // Pos:1684 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" { - ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1050, + ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1051, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28029,9 +28048,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1684 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" + // Pos:1685 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" { - ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1050, + ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1051, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28046,9 +28065,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1685 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" + // Pos:1686 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" { - ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1051, + ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1052, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28064,9 +28083,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1686 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" + // Pos:1687 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" { - ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1051, + ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1052, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28081,9 +28100,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1687 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM" + // Pos:1688 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM" { - ND_INS_VFMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1052, + ND_INS_VFMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1053, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28099,9 +28118,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1688 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" + // Pos:1689 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" { - ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1053, + ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1054, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28117,9 +28136,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1689 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" + // Pos:1690 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" { - ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1053, + ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1054, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28134,9 +28153,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1690 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" + // Pos:1691 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" { - ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1054, + ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1055, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28152,9 +28171,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1691 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" + // Pos:1692 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" { - ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1054, + ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1055, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28169,9 +28188,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1692 Instruction:"VFMSUB213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM" + // Pos:1693 Instruction:"VFMSUB213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM" { - ND_INS_VFMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1055, + ND_INS_VFMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1056, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28187,9 +28206,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1693 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" + // Pos:1694 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" { - ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1056, + ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1057, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28205,9 +28224,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1694 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" + // Pos:1695 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" { - ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1056, + ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1057, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28222,9 +28241,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1695 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" + // Pos:1696 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" { - ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1057, + ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1058, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28240,9 +28259,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1696 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" + // Pos:1697 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" { - ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1057, + ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1058, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28257,9 +28276,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1697 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM" + // Pos:1698 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM" { - ND_INS_VFMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1058, + ND_INS_VFMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1059, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28275,9 +28294,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1698 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" + // Pos:1699 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" { - ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1059, + ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1060, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28293,9 +28312,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1699 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" + // Pos:1700 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" { - ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1059, + ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1060, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28310,9 +28329,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1700 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" + // Pos:1701 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" { - ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1060, + ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1061, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28328,9 +28347,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1701 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" + // Pos:1702 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" { - ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1060, + ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1061, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28345,9 +28364,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1702 Instruction:"VFMSUB231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM" + // Pos:1703 Instruction:"VFMSUB231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM" { - ND_INS_VFMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1061, + ND_INS_VFMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1062, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28363,9 +28382,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1703 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" + // Pos:1704 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" { - ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1062, + ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1063, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28381,9 +28400,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1704 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" + // Pos:1705 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" { - ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1062, + ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1063, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28398,9 +28417,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1705 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" + // Pos:1706 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" { - ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1063, + ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1064, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28416,9 +28435,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1706 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" + // Pos:1707 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" { - ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1063, + ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1064, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28433,9 +28452,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1707 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM" + // Pos:1708 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM" { - ND_INS_VFMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1064, + ND_INS_VFMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1065, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28451,9 +28470,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1708 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" + // Pos:1709 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" { - ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1065, + ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1066, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28469,9 +28488,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1709 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" + // Pos:1710 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" { - ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1065, + ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1066, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28486,9 +28505,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1710 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" + // Pos:1711 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" { - ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1066, + ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1067, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28504,9 +28523,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1711 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" + // Pos:1712 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" { - ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1066, + ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1067, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28521,9 +28540,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1712 Instruction:"VFMSUBADD132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM" + // Pos:1713 Instruction:"VFMSUBADD132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM" { - ND_INS_VFMSUBADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1067, + ND_INS_VFMSUBADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1068, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28539,9 +28558,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1713 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" + // Pos:1714 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" { - ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1068, + ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1069, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28557,9 +28576,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1714 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" + // Pos:1715 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" { - ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1068, + ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1069, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28574,9 +28593,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1715 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" + // Pos:1716 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" { - ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1069, + ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1070, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28592,9 +28611,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1716 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" + // Pos:1717 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" { - ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1069, + ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1070, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28609,9 +28628,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1717 Instruction:"VFMSUBADD213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM" + // Pos:1718 Instruction:"VFMSUBADD213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM" { - ND_INS_VFMSUBADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1070, + ND_INS_VFMSUBADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1071, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28627,9 +28646,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1718 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" + // Pos:1719 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" { - ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1071, + ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1072, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28645,9 +28664,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1719 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" + // Pos:1720 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" { - ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1071, + ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1072, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28662,9 +28681,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1720 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" + // Pos:1721 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" { - ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1072, + ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1073, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28680,9 +28699,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1721 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" + // Pos:1722 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" { - ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1072, + ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1073, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28697,9 +28716,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1722 Instruction:"VFMSUBADD231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM" + // Pos:1723 Instruction:"VFMSUBADD231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM" { - ND_INS_VFMSUBADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1073, + ND_INS_VFMSUBADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1074, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28715,9 +28734,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1723 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" + // Pos:1724 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" { - ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1074, + ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1075, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -28733,9 +28752,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1724 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" + // Pos:1725 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" { - ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1074, + ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1075, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -28750,9 +28769,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1725 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" + // Pos:1726 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" { - ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1075, + ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1076, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28768,9 +28787,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1726 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" + // Pos:1727 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" { - ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1075, + ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1076, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28786,9 +28805,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1727 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" + // Pos:1728 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" { - ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1076, + ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1077, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28804,9 +28823,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1728 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" + // Pos:1729 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" { - ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1076, + ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1077, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28822,9 +28841,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1729 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" + // Pos:1730 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" { - ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1077, + ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1078, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28840,9 +28859,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1730 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" + // Pos:1731 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" { - ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1077, + ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1078, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28858,9 +28877,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1731 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" + // Pos:1732 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" { - ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1078, + ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1079, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28876,9 +28895,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1732 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" + // Pos:1733 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" { - ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1078, + ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1079, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28894,9 +28913,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1733 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" + // Pos:1734 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" { - ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1079, + ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1080, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28912,9 +28931,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1734 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" + // Pos:1735 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" { - ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1079, + ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1080, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28930,9 +28949,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1735 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" + // Pos:1736 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" { - ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1080, + ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1081, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28948,9 +28967,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1736 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" + // Pos:1737 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" { - ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1080, + ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1081, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -28966,9 +28985,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1737 Instruction:"VFMULCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM" + // Pos:1738 Instruction:"VFMULCPH Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM" { - ND_INS_VFMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1081, + ND_INS_VFMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1082, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -28984,9 +29003,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1738 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM" + // Pos:1739 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM" { - ND_INS_VFMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1082, + ND_INS_VFMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1083, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29002,9 +29021,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1739 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" + // Pos:1740 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" { - ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1083, + ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1084, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29020,9 +29039,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1740 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" + // Pos:1741 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" { - ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1083, + ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1084, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29037,9 +29056,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1741 Instruction:"VFNMADD132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM" + // Pos:1742 Instruction:"VFNMADD132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM" { - ND_INS_VFNMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1084, + ND_INS_VFNMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1085, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29055,9 +29074,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1742 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" + // Pos:1743 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" { - ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1085, + ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1086, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29073,9 +29092,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1743 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" + // Pos:1744 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" { - ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1085, + ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1086, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29090,9 +29109,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1744 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" + // Pos:1745 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" { - ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1086, + ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1087, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29108,9 +29127,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1745 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" + // Pos:1746 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" { - ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1086, + ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1087, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29125,9 +29144,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1746 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM" + // Pos:1747 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM" { - ND_INS_VFNMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1087, + ND_INS_VFNMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1088, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29143,9 +29162,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1747 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" + // Pos:1748 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" { - ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1088, + ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1089, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29161,9 +29180,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1748 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" + // Pos:1749 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" { - ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1088, + ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1089, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29178,9 +29197,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1749 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" + // Pos:1750 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" { - ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1089, + ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1090, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29196,9 +29215,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1750 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" + // Pos:1751 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" { - ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1089, + ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1090, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29213,9 +29232,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1751 Instruction:"VFNMADD213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM" + // Pos:1752 Instruction:"VFNMADD213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM" { - ND_INS_VFNMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1090, + ND_INS_VFNMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1091, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29231,9 +29250,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1752 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" + // Pos:1753 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" { - ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1091, + ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1092, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29249,9 +29268,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1753 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" + // Pos:1754 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" { - ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1091, + ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1092, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29266,9 +29285,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1754 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" + // Pos:1755 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" { - ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1092, + ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1093, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29284,9 +29303,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1755 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" + // Pos:1756 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" { - ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1092, + ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1093, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29301,9 +29320,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1756 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM" + // Pos:1757 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM" { - ND_INS_VFNMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1093, + ND_INS_VFNMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1094, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29319,9 +29338,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1757 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" + // Pos:1758 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" { - ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1094, + ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1095, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29337,9 +29356,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1758 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" + // Pos:1759 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" { - ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1094, + ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1095, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29354,9 +29373,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1759 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" + // Pos:1760 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" { - ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1095, + ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1096, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29372,9 +29391,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1760 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" + // Pos:1761 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" { - ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1095, + ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1096, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29389,9 +29408,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1761 Instruction:"VFNMADD231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM" + // Pos:1762 Instruction:"VFNMADD231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM" { - ND_INS_VFNMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1096, + ND_INS_VFNMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1097, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29407,9 +29426,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1762 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" + // Pos:1763 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" { - ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1097, + ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1098, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29425,9 +29444,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1763 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" + // Pos:1764 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" { - ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1097, + ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1098, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29442,9 +29461,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1764 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" + // Pos:1765 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" { - ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1098, + ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1099, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29460,9 +29479,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1765 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" + // Pos:1766 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" { - ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1098, + ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1099, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29477,9 +29496,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1766 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM" + // Pos:1767 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM" { - ND_INS_VFNMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1099, + ND_INS_VFNMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1100, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29495,9 +29514,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1767 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" + // Pos:1768 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" { - ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1100, + ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1101, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29513,9 +29532,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1768 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" + // Pos:1769 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" { - ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1100, + ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1101, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29530,9 +29549,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1769 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" + // Pos:1770 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" { - ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1101, + ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1102, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29548,9 +29567,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1770 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" + // Pos:1771 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" { - ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1101, + ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1102, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29566,9 +29585,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1771 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" + // Pos:1772 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" { - ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1102, + ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1103, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29584,9 +29603,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1772 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" + // Pos:1773 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" { - ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1102, + ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1103, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29602,9 +29621,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1773 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" + // Pos:1774 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" { - ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1103, + ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1104, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29620,9 +29639,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1774 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" + // Pos:1775 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" { - ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1103, + ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1104, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29638,9 +29657,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1775 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" + // Pos:1776 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" { - ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1104, + ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1105, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29656,9 +29675,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1776 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" + // Pos:1777 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" { - ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1104, + ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1105, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -29674,9 +29693,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1777 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" + // Pos:1778 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" { - ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1105, + ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1106, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29692,9 +29711,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1778 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" + // Pos:1779 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" { - ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1105, + ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1106, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29709,9 +29728,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1779 Instruction:"VFNMSUB132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM" + // Pos:1780 Instruction:"VFNMSUB132PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM" { - ND_INS_VFNMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1106, + ND_INS_VFNMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1107, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29727,9 +29746,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1780 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" + // Pos:1781 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" { - ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1107, + ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1108, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29745,9 +29764,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1781 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" + // Pos:1782 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" { - ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1107, + ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1108, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29762,9 +29781,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1782 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" + // Pos:1783 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" { - ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1108, + ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29780,9 +29799,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1783 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" + // Pos:1784 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" { - ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1108, + ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29797,9 +29816,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1784 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM" + // Pos:1785 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM" { - ND_INS_VFNMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1109, + ND_INS_VFNMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29815,9 +29834,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1785 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" + // Pos:1786 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" { - ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1110, + ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1111, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29833,9 +29852,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1786 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" + // Pos:1787 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" { - ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1110, + ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1111, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29850,9 +29869,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1787 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" + // Pos:1788 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" { - ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1111, + ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1112, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29868,9 +29887,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1788 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" + // Pos:1789 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" { - ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1111, + ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1112, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29885,9 +29904,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1789 Instruction:"VFNMSUB213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM" + // Pos:1790 Instruction:"VFNMSUB213PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM" { - ND_INS_VFNMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1112, + ND_INS_VFNMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29903,9 +29922,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1790 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" + // Pos:1791 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" { - ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1113, + ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1114, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29921,9 +29940,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1791 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" + // Pos:1792 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" { - ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1113, + ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1114, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29938,9 +29957,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1792 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" + // Pos:1793 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" { - ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1114, + ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1115, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -29956,9 +29975,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1793 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" + // Pos:1794 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" { - ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1114, + ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1115, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -29973,9 +29992,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1794 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM" + // Pos:1795 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM" { - ND_INS_VFNMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1115, + ND_INS_VFNMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1116, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -29991,9 +30010,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1795 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" + // Pos:1796 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" { - ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1116, + ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1117, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30009,9 +30028,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1796 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" + // Pos:1797 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" { - ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1116, + ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1117, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -30026,9 +30045,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1797 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" + // Pos:1798 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" { - ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1117, + ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1118, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30044,9 +30063,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1798 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" + // Pos:1799 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" { - ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1117, + ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1118, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -30061,9 +30080,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1799 Instruction:"VFNMSUB231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM" + // Pos:1800 Instruction:"VFNMSUB231PH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM" { - ND_INS_VFNMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1118, + ND_INS_VFNMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1119, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30079,9 +30098,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1800 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" + // Pos:1801 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" { - ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1119, + ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1120, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30097,9 +30116,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1801 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" + // Pos:1802 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" { - ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1119, + ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1120, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -30114,9 +30133,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1802 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" + // Pos:1803 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" { - ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1120, + ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1121, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30132,9 +30151,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1803 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" + // Pos:1804 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" { - ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1120, + ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1121, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -30149,9 +30168,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1804 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM" + // Pos:1805 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM" { - ND_INS_VFNMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1121, + ND_INS_VFNMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1122, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30167,9 +30186,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1805 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" + // Pos:1806 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" { - ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1122, + ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1123, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30185,9 +30204,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1806 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" + // Pos:1807 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" { - ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1122, + ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1123, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, @@ -30202,9 +30221,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1807 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" + // Pos:1808 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" { - ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1123, + ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1124, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -30220,9 +30239,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1808 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" + // Pos:1809 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" { - ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1123, + ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1124, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -30238,9 +30257,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1809 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" + // Pos:1810 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" { - ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1124, + ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1125, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -30256,9 +30275,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1810 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" + // Pos:1811 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" { - ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1124, + ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1125, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -30274,9 +30293,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1811 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" + // Pos:1812 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" { - ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1125, + ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1126, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -30292,9 +30311,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1812 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" + // Pos:1813 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" { - ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1125, + ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1126, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -30310,9 +30329,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1813 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" + // Pos:1814 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" { - ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1126, + ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1127, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -30328,9 +30347,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1814 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" + // Pos:1815 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" { - ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1126, + ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1127, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, @@ -30346,9 +30365,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1815 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" + // Pos:1816 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" { - ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1127, + ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1128, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -30364,9 +30383,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1816 Instruction:"VFPCLASSPH rKq{K},aKq,Wn|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI" + // Pos:1817 Instruction:"VFPCLASSPH rKq{K},aKq,Wn|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI" { - ND_INS_VFPCLASSPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1128, + ND_INS_VFPCLASSPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1129, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30382,9 +30401,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1817 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" + // Pos:1818 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" { - ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1129, + ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1130, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -30400,9 +30419,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1818 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" + // Pos:1819 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" { - ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1130, + ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1131, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -30418,9 +30437,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1819 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI" + // Pos:1820 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI" { - ND_INS_VFPCLASSSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1131, + ND_INS_VFPCLASSSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1132, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30436,9 +30455,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1820 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" + // Pos:1821 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" { - ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1132, + ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1133, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -30454,9 +30473,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1821 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" + // Pos:1822 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" { - ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1133, + ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1134, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -30470,9 +30489,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1822 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" + // Pos:1823 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" { - ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1134, + ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1135, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -30486,9 +30505,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1823 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" + // Pos:1824 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" { - ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1135, + ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1136, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -30502,9 +30521,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1824 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" + // Pos:1825 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" { - ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1136, + ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1137, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -30518,9 +30537,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1825 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" + // Pos:1826 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" { - ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1137, + ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1138, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30535,9 +30554,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1826 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" + // Pos:1827 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" { - ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1137, + ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1138, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -30552,9 +30571,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1827 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" + // Pos:1828 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" { - ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1138, + ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1139, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30569,9 +30588,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1828 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" + // Pos:1829 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" { - ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1138, + ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1139, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -30586,9 +30605,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1829 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" + // Pos:1830 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" { - ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1139, + ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1140, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -30602,9 +30621,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1830 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" + // Pos:1831 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" { - ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1140, + ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1141, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -30618,9 +30637,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1831 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" + // Pos:1832 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" { - ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1141, + ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1142, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -30634,9 +30653,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1832 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" + // Pos:1833 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" { - ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1142, + ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1143, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -30650,9 +30669,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1833 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" + // Pos:1834 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" { - ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1143, + ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1144, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -30666,9 +30685,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1834 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" + // Pos:1835 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" { - ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1144, + ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1145, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -30682,9 +30701,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1835 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" + // Pos:1836 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" { - ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1145, + ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1146, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -30698,9 +30717,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1836 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" + // Pos:1837 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" { - ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1146, + ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1147, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -30714,9 +30733,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1837 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" + // Pos:1838 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" { - ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1147, + ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1148, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30731,9 +30750,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1838 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" + // Pos:1839 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" { - ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1147, + ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1148, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -30748,9 +30767,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1839 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" + // Pos:1840 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" { - ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1148, + ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30765,9 +30784,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1840 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" + // Pos:1841 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" { - ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1148, + ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -30782,9 +30801,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1841 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" + // Pos:1842 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" { - ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1149, + ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1150, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30799,9 +30818,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1842 Instruction:"VGETEXPPH Vn{K}{z},aKq,Wn|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM" + // Pos:1843 Instruction:"VGETEXPPH Vn{K}{z},aKq,Wn|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM" { - ND_INS_VGETEXPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1150, + ND_INS_VGETEXPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1151, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30816,9 +30835,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1843 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" + // Pos:1844 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" { - ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1151, + ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1152, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30833,9 +30852,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1844 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" + // Pos:1845 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" { - ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1152, + ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1153, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30851,9 +30870,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1845 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM" + // Pos:1846 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM" { - ND_INS_VGETEXPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1153, + ND_INS_VGETEXPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1154, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30869,9 +30888,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1846 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" + // Pos:1847 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" { - ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1154, + ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1155, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30887,9 +30906,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1847 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" + // Pos:1848 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" { - ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1155, + ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1156, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30905,9 +30924,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1848 Instruction:"VGETMANTPH Vn{K}{z},aKq,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI" + // Pos:1849 Instruction:"VGETMANTPH Vn{K}{z},aKq,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI" { - ND_INS_VGETMANTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1156, + ND_INS_VGETMANTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1157, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30923,9 +30942,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1849 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" + // Pos:1850 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" { - ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1157, + ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1158, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30941,9 +30960,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1850 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" + // Pos:1851 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" { - ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1158, + ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1159, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30960,9 +30979,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1851 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI" + // Pos:1852 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI" { - ND_INS_VGETMANTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1159, + ND_INS_VGETMANTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1160, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -30979,9 +30998,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1852 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" + // Pos:1853 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" { - ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1160, + ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1161, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -30998,9 +31017,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1853 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" + // Pos:1854 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" { - ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1161, + ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1162, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -31017,9 +31036,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1854 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" + // Pos:1855 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" { - ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1161, + ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1162, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -31035,9 +31054,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1855 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" + // Pos:1856 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" { - ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1162, + ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1163, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -31054,9 +31073,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1856 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" + // Pos:1857 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" { - ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1162, + ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1163, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -31072,9 +31091,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1857 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" + // Pos:1858 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" { - ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1163, + ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1164, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -31090,9 +31109,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1858 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" + // Pos:1859 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" { - ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1163, + ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1164, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, @@ -31107,9 +31126,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1859 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" + // Pos:1860 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" { - ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1164, + ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1165, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31124,9 +31143,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1860 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" + // Pos:1861 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" { - ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1165, + ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1166, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31141,9 +31160,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1861 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" + // Pos:1862 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" { - ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1166, + ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1167, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31158,9 +31177,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1862 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" + // Pos:1863 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" { - ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1167, + ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31175,9 +31194,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1863 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" + // Pos:1864 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" { - ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1168, + ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1169, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31193,9 +31212,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1864 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" + // Pos:1865 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" { - ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1169, + ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1170, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31212,9 +31231,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1865 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" + // Pos:1866 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" { - ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1170, + ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1171, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -31231,9 +31250,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1866 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" + // Pos:1867 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" { - ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1171, + ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1172, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -31250,9 +31269,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1867 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" + // Pos:1868 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" { - ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1172, + ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1173, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31269,9 +31288,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1868 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" + // Pos:1869 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" { - ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1173, + ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1174, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -31287,9 +31306,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1869 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" + // Pos:1870 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" { - ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1174, + ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1175, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31306,9 +31325,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1870 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" + // Pos:1871 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" { - ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1175, + ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1176, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -31325,9 +31344,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1871 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" + // Pos:1872 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" { - ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1176, + ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1177, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -31344,9 +31363,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1872 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" + // Pos:1873 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" { - ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1177, + ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1178, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31363,9 +31382,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1873 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + // Pos:1874 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" { - ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1178, + ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1179, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31381,9 +31400,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1874 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + // Pos:1875 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" { - ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1178, + ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1179, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31399,9 +31418,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1875 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + // Pos:1876 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" { - ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1178, + ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1179, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31417,9 +31436,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1876 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + // Pos:1877 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" { - ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1178, + ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1179, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31435,9 +31454,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1877 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" + // Pos:1878 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" { - ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1179, + ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1180, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31451,9 +31470,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1878 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" + // Pos:1879 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" { - ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1180, + ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1181, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, @@ -31467,9 +31486,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1879 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" + // Pos:1880 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" { - ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1181, + ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1182, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31484,9 +31503,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1880 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" + // Pos:1881 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" { - ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1182, + ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1183, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31501,9 +31520,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1881 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" + // Pos:1882 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" { - ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1182, + ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1183, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31518,9 +31537,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1882 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" + // Pos:1883 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" { - ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1183, + ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1184, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31535,9 +31554,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1883 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" + // Pos:1884 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" { - ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1183, + ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1184, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31552,9 +31571,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1884 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" + // Pos:1885 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" { - ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1184, + ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1185, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31570,9 +31589,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1885 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" + // Pos:1886 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" { - ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1184, + ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1185, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31587,9 +31606,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1886 Instruction:"VMAXPH Vn{K}{z},aKq,Hn,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM" + // Pos:1887 Instruction:"VMAXPH Vn{K}{z},aKq,Hn,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM" { - ND_INS_VMAXPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1185, + ND_INS_VMAXPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1186, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -31605,9 +31624,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1887 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" + // Pos:1888 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" { - ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1186, + ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1187, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31623,9 +31642,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1888 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" + // Pos:1889 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" { - ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1186, + ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1187, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31640,9 +31659,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1889 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" + // Pos:1890 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" { - ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1187, + ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1188, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31658,9 +31677,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1890 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" + // Pos:1891 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" { - ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1187, + ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1188, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31675,9 +31694,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1891 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM" + // Pos:1892 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM" { - ND_INS_VMAXSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1188, + ND_INS_VMAXSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1189, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -31693,9 +31712,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1892 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" + // Pos:1893 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" { - ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1189, + ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1190, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31711,9 +31730,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1893 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" + // Pos:1894 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" { - ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1189, + ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1190, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31728,9 +31747,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1894 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/"" + // Pos:1895 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/"" { - ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1190, + ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1191, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -31743,9 +31762,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1895 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" + // Pos:1896 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" { - ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1191, + ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1192, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -31759,9 +31778,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1896 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" + // Pos:1897 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" { - ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1192, + ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1193, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -31774,9 +31793,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1897 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" + // Pos:1898 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" { - ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1193, + ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1194, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -31789,9 +31808,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1898 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" + // Pos:1899 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" { - ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1193, + ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1194, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -31804,9 +31823,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1899 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" + // Pos:1900 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" { - ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1194, + ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1195, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31822,9 +31841,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1900 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" + // Pos:1901 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" { - ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1194, + ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1195, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31839,9 +31858,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1901 Instruction:"VMINPH Vn{K}{z},aKq,Hn,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM" + // Pos:1902 Instruction:"VMINPH Vn{K}{z},aKq,Hn,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM" { - ND_INS_VMINPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1195, + ND_INS_VMINPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1196, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -31857,9 +31876,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1902 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" + // Pos:1903 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" { - ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1196, + ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1197, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31875,9 +31894,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1903 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" + // Pos:1904 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" { - ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1196, + ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1197, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31892,9 +31911,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1904 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" + // Pos:1905 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" { - ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1197, + ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1198, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31910,9 +31929,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1905 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" + // Pos:1906 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" { - ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1197, + ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1198, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31927,9 +31946,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1906 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM" + // Pos:1907 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM" { - ND_INS_VMINSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1198, + ND_INS_VMINSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1199, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -31945,9 +31964,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1907 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" + // Pos:1908 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" { - ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1199, + ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1200, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -31963,9 +31982,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1908 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" + // Pos:1909 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" { - ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1199, + ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1200, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -31980,9 +31999,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1909 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/"" + // Pos:1910 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/"" { - ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1200, + ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1201, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -31995,9 +32014,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1910 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" + // Pos:1911 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" { - ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1201, + ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1202, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -32010,9 +32029,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1911 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/"" + // Pos:1912 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/"" { - ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1202, + ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1203, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -32025,9 +32044,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1912 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" + // Pos:1913 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" { - ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1202, + ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1203, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -32040,9 +32059,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1913 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" + // Pos:1914 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1203, + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1204, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32057,9 +32076,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1914 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" + // Pos:1915 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1203, + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1204, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32074,9 +32093,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1915 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" + // Pos:1916 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1203, + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1204, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32090,9 +32109,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1916 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" + // Pos:1917 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1203, + ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1204, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32106,9 +32125,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1917 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" + // Pos:1918 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1204, + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1205, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32123,9 +32142,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1918 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" + // Pos:1919 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1204, + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1205, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32140,9 +32159,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1919 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" + // Pos:1920 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1204, + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1205, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32156,9 +32175,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1920 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" + // Pos:1921 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1204, + ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1205, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32172,9 +32191,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1921 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + // Pos:1922 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1205, + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1206, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32188,9 +32207,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1922 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + // Pos:1923 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1205, + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1206, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32204,9 +32223,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1923 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + // Pos:1924 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1205, + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1206, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32220,9 +32239,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1924 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + // Pos:1925 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1205, + ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1206, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32236,9 +32255,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1925 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" + // Pos:1926 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1206, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1207, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32253,9 +32272,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1926 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" + // Pos:1927 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1206, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1207, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32270,9 +32289,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1927 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" + // Pos:1928 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1206, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1207, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32287,9 +32306,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1928 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" + // Pos:1929 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1206, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1207, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32303,9 +32322,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1929 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" + // Pos:1930 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1206, + ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1207, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32319,9 +32338,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1930 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" + // Pos:1931 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" { - ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1207, + ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1208, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32335,9 +32354,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1931 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" + // Pos:1932 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" { - ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1207, + ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1208, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32351,9 +32370,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1932 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" + // Pos:1933 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" { - ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1208, + ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32368,9 +32387,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1933 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" + // Pos:1934 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" { - ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1208, + ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32385,9 +32404,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1934 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" + // Pos:1935 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" { - ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, + ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1210, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32402,9 +32421,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1935 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" + // Pos:1936 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" { - ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, + ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1210, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32419,9 +32438,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1936 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" + // Pos:1937 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" { - ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1210, + ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1211, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32435,9 +32454,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1937 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" + // Pos:1938 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" { - ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1210, + ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1211, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32451,9 +32470,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1938 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" + // Pos:1939 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" { - ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1211, + ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1212, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32468,9 +32487,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1939 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" + // Pos:1940 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" { - ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1211, + ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1212, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32485,9 +32504,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1940 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" + // Pos:1941 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" { - ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1212, + ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1213, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32502,9 +32521,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1941 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" + // Pos:1942 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" { - ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1212, + ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1213, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32519,9 +32538,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1942 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" + // Pos:1943 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" { - ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1213, + ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1214, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32536,9 +32555,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1943 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" + // Pos:1944 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" { - ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1213, + ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1214, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32553,9 +32572,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1944 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" + // Pos:1945 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" { - ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1214, + ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1215, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32570,9 +32589,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1945 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" + // Pos:1946 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" { - ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1214, + ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1215, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -32587,9 +32606,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1946 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" + // Pos:1947 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" { - ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1215, + ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32604,9 +32623,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1947 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" + // Pos:1948 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" { - ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1215, + ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1216, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32621,9 +32640,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1948 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" + // Pos:1949 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1217, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32638,9 +32657,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1949 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" + // Pos:1950 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1217, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32654,9 +32673,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1950 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" + // Pos:1951 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1216, + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1217, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32671,9 +32690,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1951 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" + // Pos:1952 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1216, + ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1217, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32687,9 +32706,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1952 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" + // Pos:1953 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1217, + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1218, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32704,9 +32723,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1953 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" + // Pos:1954 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1217, + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1218, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32720,9 +32739,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1954 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" + // Pos:1955 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1217, + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1218, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32737,9 +32756,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1955 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" + // Pos:1956 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1217, + ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1218, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32753,9 +32772,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1956 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" + // Pos:1957 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" { - ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1218, + ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1219, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32770,9 +32789,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1957 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" + // Pos:1958 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" { - ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1218, + ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1219, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32787,9 +32806,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1958 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" + // Pos:1959 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1219, + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32804,9 +32823,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1959 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" + // Pos:1960 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1219, + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32820,9 +32839,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1960 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" + // Pos:1961 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1219, + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32837,9 +32856,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1961 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" + // Pos:1962 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1219, + ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32853,9 +32872,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1962 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" + // Pos:1963 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1221, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32870,9 +32889,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1963 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" + // Pos:1964 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1221, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32886,9 +32905,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1964 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" + // Pos:1965 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1220, + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1221, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32903,9 +32922,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1965 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" + // Pos:1966 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1220, + ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1221, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32919,9 +32938,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1966 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" + // Pos:1967 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" { - ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1221, + ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1222, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32935,9 +32954,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1967 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" + // Pos:1968 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" { - ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1222, + ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1223, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32951,9 +32970,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1968 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" + // Pos:1969 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" { - ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1223, + ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1224, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32967,9 +32986,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1969 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" + // Pos:1970 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" { - ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1223, + ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1224, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -32983,9 +33002,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1970 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" + // Pos:1971 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" { - ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1224, + ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1225, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -32999,9 +33018,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1971 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" + // Pos:1972 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" { - ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1224, + ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1225, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33015,9 +33034,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1972 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" + // Pos:1973 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" { - ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1225, + ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1226, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33031,9 +33050,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1973 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" + // Pos:1974 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" { - ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1225, + ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1226, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33047,9 +33066,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1974 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" + // Pos:1975 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" { - ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1226, + ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33063,9 +33082,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1975 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" + // Pos:1976 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" { - ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1226, + ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33079,9 +33098,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1976 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + // Pos:1977 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33095,9 +33114,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1977 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + // Pos:1978 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33111,9 +33130,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1978 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" + // Pos:1979 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33127,9 +33146,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1979 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" + // Pos:1980 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33143,9 +33162,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1980 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + // Pos:1981 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1227, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33159,9 +33178,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1981 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + // Pos:1982 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1227, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33175,9 +33194,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1982 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" + // Pos:1983 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1227, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33191,9 +33210,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1983 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" + // Pos:1984 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1227, + ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33207,9 +33226,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1984 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" + // Pos:1985 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33224,9 +33243,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1985 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" + // Pos:1986 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33242,9 +33261,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1986 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" + // Pos:1987 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33259,9 +33278,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1987 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" + // Pos:1988 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33277,9 +33296,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1988 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" + // Pos:1989 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1228, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33294,9 +33313,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1989 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" + // Pos:1990 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1228, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33310,9 +33329,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1990 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" + // Pos:1991 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1228, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33327,9 +33346,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1991 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" + // Pos:1992 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1228, + ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33343,9 +33362,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1992 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM" + // Pos:1993 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM" { - ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1229, + ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1230, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33360,9 +33379,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1993 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM" + // Pos:1994 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM" { - ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1229, + ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1230, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), 0, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33378,9 +33397,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1994 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR" + // Pos:1995 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR" { - ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1229, + ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1230, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33395,9 +33414,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1995 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR" + // Pos:1996 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR" { - ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1229, + ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1230, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), 0, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33413,9 +33432,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1996 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" + // Pos:1997 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" { - ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1230, + ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33430,9 +33449,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1997 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" + // Pos:1998 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" { - ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1230, + ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33446,9 +33465,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1998 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" + // Pos:1999 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" { - ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, + ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33463,9 +33482,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:1999 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" + // Pos:2000 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" { - ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1231, + ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33479,9 +33498,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2000 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" + // Pos:2001 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33496,9 +33515,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2001 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" + // Pos:2002 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33514,9 +33533,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2002 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" + // Pos:2003 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33531,9 +33550,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2003 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" + // Pos:2004 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33549,9 +33568,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2004 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" + // Pos:2005 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1232, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33566,9 +33585,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2005 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" + // Pos:2006 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1232, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33582,9 +33601,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2006 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" + // Pos:2007 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1232, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33599,9 +33618,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2007 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" + // Pos:2008 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1232, + ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33615,9 +33634,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2008 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" + // Pos:2009 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1233, + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1234, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33632,9 +33651,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2009 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" + // Pos:2010 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1233, + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1234, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33649,9 +33668,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2010 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" + // Pos:2011 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1233, + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1234, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33665,9 +33684,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2011 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" + // Pos:2012 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1233, + ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1234, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33681,9 +33700,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2012 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" + // Pos:2013 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1234, + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1235, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33698,9 +33717,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2013 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" + // Pos:2014 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1234, + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1235, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33715,9 +33734,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2014 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" + // Pos:2015 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1234, + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1235, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33731,9 +33750,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2015 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" + // Pos:2016 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1234, + ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1235, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33747,9 +33766,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2016 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM" + // Pos:2017 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM" { - ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1235, + ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33763,9 +33782,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2017 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM" + // Pos:2018 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM" { - ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1235, + ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33779,9 +33798,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2018 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR" + // Pos:2019 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR" { - ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1235, + ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33795,9 +33814,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2019 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR" + // Pos:2020 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR" { - ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1235, + ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33811,9 +33830,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2020 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" + // Pos:2021 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" { - ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1236, + ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1237, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33829,9 +33848,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2021 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" + // Pos:2022 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" { - ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1237, + ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1238, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -33845,9 +33864,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2022 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" + // Pos:2023 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" { - ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1238, + ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1239, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -33861,9 +33880,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2023 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" + // Pos:2024 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" { - ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1239, + ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1240, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, @@ -33878,9 +33897,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2024 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/"" + // Pos:2025 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/"" { - ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1240, + ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1241, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -33893,9 +33912,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2025 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" + // Pos:2026 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" { - ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1241, + ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1242, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -33908,9 +33927,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2026 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" + // Pos:2027 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" { - ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1242, + ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1243, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, @@ -33923,9 +33942,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2027 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" + // Pos:2028 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" { - ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1243, + ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1244, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33941,9 +33960,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2028 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" + // Pos:2029 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" { - ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1243, + ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1244, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -33958,9 +33977,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2029 Instruction:"VMULPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM" + // Pos:2030 Instruction:"VMULPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM" { - ND_INS_VMULPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1244, + ND_INS_VMULPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1245, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -33976,9 +33995,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2030 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" + // Pos:2031 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" { - ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1245, + ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1246, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -33994,9 +34013,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2031 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" + // Pos:2032 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" { - ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1245, + ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1246, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34011,9 +34030,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2032 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" + // Pos:2033 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" { - ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1246, + ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1247, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34029,9 +34048,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2033 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" + // Pos:2034 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" { - ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1246, + ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1247, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34046,9 +34065,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2034 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM" + // Pos:2035 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM" { - ND_INS_VMULSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1247, + ND_INS_VMULSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1248, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -34064,9 +34083,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2035 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" + // Pos:2036 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" { - ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1248, + ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1249, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34082,9 +34101,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2036 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" + // Pos:2037 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" { - ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1248, + ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1249, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34099,9 +34118,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2037 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" + // Pos:2038 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" { - ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1249, + ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1250, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, @@ -34116,9 +34135,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2038 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/"" + // Pos:2039 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/"" { - ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1250, + ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1251, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -34131,9 +34150,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2039 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" + // Pos:2040 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" { - ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1251, + ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1252, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, @@ -34147,9 +34166,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2040 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" + // Pos:2041 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" { - ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1252, + ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1253, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -34165,9 +34184,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2041 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" + // Pos:2042 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" { - ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1252, + ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1253, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34182,9 +34201,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2042 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" + // Pos:2043 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" { - ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1253, + ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1254, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -34200,9 +34219,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2043 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" + // Pos:2044 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" { - ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1253, + ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1254, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34217,9 +34236,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2044 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" + // Pos:2045 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" { - ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1254, + ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1255, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, @@ -34234,9 +34253,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2045 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" + // Pos:2046 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" { - ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1255, + ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1256, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, @@ -34251,9 +34270,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2046 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" + // Pos:2047 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" { - ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1256, + ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1257, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, @@ -34269,9 +34288,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2047 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" + // Pos:2048 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" { - ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1257, + ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1258, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, @@ -34287,9 +34306,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2048 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" + // Pos:2049 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" { - ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1258, + ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1259, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34304,9 +34323,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2049 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" + // Pos:2050 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" { - ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1258, + ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1259, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34320,9 +34339,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2050 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" + // Pos:2051 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" { - ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1259, + ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1260, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34337,9 +34356,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2051 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" + // Pos:2052 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" { - ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1259, + ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1260, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34353,9 +34372,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2052 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" + // Pos:2053 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" { - ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1260, + ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1261, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34370,9 +34389,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2053 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" + // Pos:2054 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" { - ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1261, + ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1262, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34387,9 +34406,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2054 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" + // Pos:2055 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" { - ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1261, + ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1262, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34403,9 +34422,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2055 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" + // Pos:2056 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" { - ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1262, + ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1263, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34421,9 +34440,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2056 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" + // Pos:2057 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" { - ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1262, + ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1263, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34438,9 +34457,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2057 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" + // Pos:2058 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" { - ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1263, + ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1264, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34456,9 +34475,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2058 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" + // Pos:2059 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" { - ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1263, + ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1264, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34473,9 +34492,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2059 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" + // Pos:2060 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" { - ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1264, + ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1265, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34491,9 +34510,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2060 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" + // Pos:2061 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" { - ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1264, + ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1265, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34508,9 +34527,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2061 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" + // Pos:2062 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" { - ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1265, + ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1266, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34526,9 +34545,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2062 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" + // Pos:2063 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" { - ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1265, + ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1266, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34543,9 +34562,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2063 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" + // Pos:2064 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" { - ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1266, + ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1267, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34561,9 +34580,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2064 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" + // Pos:2065 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" { - ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1266, + ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1267, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34578,9 +34597,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2065 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" + // Pos:2066 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" { - ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1267, + ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1268, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34596,9 +34615,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2066 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" + // Pos:2067 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" { - ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1267, + ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1268, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34613,9 +34632,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2067 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" + // Pos:2068 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" { - ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1268, + ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1269, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34631,9 +34650,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2068 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" + // Pos:2069 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" { - ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1268, + ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1269, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34648,9 +34667,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2069 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" + // Pos:2070 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" { - ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1269, + ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1270, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34666,9 +34685,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2070 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" + // Pos:2071 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" { - ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1269, + ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1270, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34683,9 +34702,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2071 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" + // Pos:2072 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" { - ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1270, + ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1271, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34701,9 +34720,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2072 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" + // Pos:2073 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" { - ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1270, + ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1271, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34718,9 +34737,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2073 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" + // Pos:2074 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" { - ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1271, + ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1272, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34736,9 +34755,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2074 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:2075 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" { - ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1271, + ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1272, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34753,9 +34772,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2075 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" + // Pos:2076 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" { - ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1272, + ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1273, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34771,9 +34790,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2076 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:2077 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" { - ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1272, + ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1273, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34788,9 +34807,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2077 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" + // Pos:2078 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" { - ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1273, + ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1274, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34806,9 +34825,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2078 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" + // Pos:2079 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" { - ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1273, + ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1274, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34823,9 +34842,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2079 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" + // Pos:2080 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" { - ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1274, + ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1275, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34842,9 +34861,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2080 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" + // Pos:2081 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" { - ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1274, + ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1275, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34860,9 +34879,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2081 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" + // Pos:2082 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" { - ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1275, + ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1276, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34877,9 +34896,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2082 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" + // Pos:2083 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" { - ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1276, + ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1277, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34895,9 +34914,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2083 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:2084 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" { - ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1277, + ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1278, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -34912,9 +34931,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2084 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" + // Pos:2085 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" { - ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1278, + ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1279, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34930,9 +34949,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2085 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" + // Pos:2086 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" { - ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1279, + ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1280, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34948,9 +34967,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2086 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" + // Pos:2087 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" { - ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1280, + ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1281, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -34966,9 +34985,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2087 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" + // Pos:2088 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" { - ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1281, + ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -34984,9 +35003,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2088 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" + // Pos:2089 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" { - ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1281, + ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35001,9 +35020,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2089 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" + // Pos:2090 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" { - ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1282, + ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1283, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35019,9 +35038,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2090 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" + // Pos:2091 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" { - ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1282, + ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1283, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35036,9 +35055,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2091 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" + // Pos:2092 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" { - ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1283, + ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1284, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -35054,9 +35073,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2092 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" + // Pos:2093 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" { - ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1284, + ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1285, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35072,9 +35091,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2093 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" + // Pos:2094 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" { - ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1285, + ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1286, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35090,9 +35109,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2094 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" + // Pos:2095 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" { - ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1286, + ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1287, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35108,9 +35127,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2095 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" + // Pos:2096 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" { - ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1287, + ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1288, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35126,9 +35145,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2096 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" + // Pos:2097 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" { - ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1288, + ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1289, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35144,9 +35163,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2097 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" + // Pos:2098 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" { - ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1289, + ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1290, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35162,9 +35181,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2098 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:2099 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1290, + ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1291, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35179,9 +35198,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2099 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" + // Pos:2100 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" { - ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1290, + ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1291, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35196,9 +35215,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2100 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" + // Pos:2101 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" { - ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1290, + ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1291, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -35212,9 +35231,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2101 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" + // Pos:2102 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" { - ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1291, + ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1292, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35229,9 +35248,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2102 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" + // Pos:2103 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" { - ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1291, + ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1292, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35246,9 +35265,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2103 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" + // Pos:2104 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" { - ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1291, + ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1292, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -35262,9 +35281,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2104 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" + // Pos:2105 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" { - ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1292, + ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1293, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -35278,9 +35297,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2105 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" + // Pos:2106 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" { - ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1293, + ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1294, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -35294,9 +35313,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2106 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" + // Pos:2107 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" { - ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1294, + ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1295, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35311,9 +35330,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2107 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" + // Pos:2108 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" { - ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1294, + ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1295, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35328,9 +35347,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2108 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" + // Pos:2109 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" { - ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1294, + ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1295, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -35344,9 +35363,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2109 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:2110 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1295, + ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1296, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35361,9 +35380,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2110 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" + // Pos:2111 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" { - ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1295, + ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1296, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35378,9 +35397,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2111 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" + // Pos:2112 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" { - ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1295, + ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1296, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -35394,9 +35413,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2112 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + // Pos:2113 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" { - ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1296, + ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1297, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, @@ -35412,9 +35431,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2113 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + // Pos:2114 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" { - ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1296, + ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1297, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, @@ -35430,9 +35449,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2114 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" + // Pos:2115 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" { - ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1297, + ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1298, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35448,9 +35467,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2115 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" + // Pos:2116 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" { - ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1297, + ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1298, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35466,9 +35485,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2116 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" + // Pos:2117 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" { - ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1298, + ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1299, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35485,9 +35504,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2117 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" + // Pos:2118 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" { - ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1299, + ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1300, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35504,9 +35523,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2118 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" + // Pos:2119 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" { - ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1300, + ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1301, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35522,9 +35541,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2119 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" + // Pos:2120 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" { - ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1300, + ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1301, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35539,9 +35558,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2120 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" + // Pos:2121 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" { - ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1301, + ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35557,9 +35576,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2121 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" + // Pos:2122 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" { - ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1301, + ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35574,9 +35593,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2122 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" + // Pos:2123 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" { - ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1302, + ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35592,9 +35611,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2123 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" + // Pos:2124 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" { - ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1302, + ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35609,9 +35628,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2124 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" + // Pos:2125 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" { - ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1303, + ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1304, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35627,9 +35646,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2125 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" + // Pos:2126 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" { - ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1303, + ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1304, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35644,9 +35663,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2126 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" + // Pos:2127 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" { - ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1304, + ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1305, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35665,9 +35684,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2127 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" + // Pos:2128 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" { - ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1305, + ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1306, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35686,9 +35705,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2128 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" + // Pos:2129 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" { - ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1306, + ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1307, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35704,9 +35723,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2129 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" + // Pos:2130 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" { - ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1306, + ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1307, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35721,9 +35740,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2130 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" + // Pos:2131 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" { - ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1307, + ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1308, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35739,9 +35758,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2131 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" + // Pos:2132 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" { - ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1307, + ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1308, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35756,9 +35775,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2132 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" + // Pos:2133 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" { - ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1308, + ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1309, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35774,9 +35793,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2133 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" + // Pos:2134 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" { - ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1308, + ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1309, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35791,9 +35810,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2134 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" + // Pos:2135 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" { - ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1309, + ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1310, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35809,9 +35828,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2135 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" + // Pos:2136 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" { - ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1309, + ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1310, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35826,9 +35845,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2136 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" + // Pos:2137 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" { - ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1310, + ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1311, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35845,9 +35864,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2137 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" + // Pos:2138 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" { - ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1311, + ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1312, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -35864,9 +35883,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2138 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" + // Pos:2139 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" { - ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1312, + ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1313, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35883,9 +35902,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2139 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" + // Pos:2140 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" { - ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1313, + ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1314, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35902,9 +35921,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2140 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" + // Pos:2141 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" { - ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1314, + ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1315, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35921,9 +35940,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2141 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" + // Pos:2142 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" { - ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1315, + ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1316, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -35940,9 +35959,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2142 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" + // Pos:2143 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" { - ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1316, + ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1317, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35959,9 +35978,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2143 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" + // Pos:2144 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" { - ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1317, + ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1318, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -35978,9 +35997,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2144 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" + // Pos:2145 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" { - ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1318, + ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1319, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -35996,9 +36015,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2145 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" + // Pos:2146 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" { - ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1319, + ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1320, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36014,9 +36033,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2146 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" + // Pos:2147 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" { - ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1320, + ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1321, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -36031,9 +36050,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2147 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" + // Pos:2148 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" { - ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1321, + ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1322, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36048,9 +36067,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2148 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" + // Pos:2149 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" { - ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1322, + ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1323, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36065,9 +36084,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2149 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" + // Pos:2150 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" { - ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1323, + ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1324, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -36082,9 +36101,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2150 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" + // Pos:2151 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" { - ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1324, + ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1325, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36100,9 +36119,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2151 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" + // Pos:2152 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" { - ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1325, + ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1326, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36118,9 +36137,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2152 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" + // Pos:2153 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" { - ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1326, + ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1327, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36136,9 +36155,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2153 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" + // Pos:2154 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" { - ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1327, + ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1328, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36154,9 +36173,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2154 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" + // Pos:2155 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" { - ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1328, + ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1329, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36172,9 +36191,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2155 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" + // Pos:2156 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" { - ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1329, + ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1330, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36190,9 +36209,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2156 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" + // Pos:2157 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" { - ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1330, + ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1331, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -36207,9 +36226,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2157 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" + // Pos:2158 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" { - ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1331, + ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1332, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -36224,9 +36243,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2158 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM" + // Pos:2159 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM" { - ND_INS_VPDPBSSD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1332, + ND_INS_VPDPBSSD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1333, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, @@ -36241,9 +36260,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2159 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM" + // Pos:2160 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM" { - ND_INS_VPDPBSSDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1333, + ND_INS_VPDPBSSDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1334, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, @@ -36258,9 +36277,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2160 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM" + // Pos:2161 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM" { - ND_INS_VPDPBSUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1334, + ND_INS_VPDPBSUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1335, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, @@ -36275,9 +36294,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2161 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM" + // Pos:2162 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM" { - ND_INS_VPDPBSUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1335, + ND_INS_VPDPBSUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1336, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, @@ -36292,9 +36311,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2162 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" + // Pos:2163 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" { - ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1336, + ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1337, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, @@ -36310,9 +36329,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2163 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM" + // Pos:2164 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM" { - ND_INS_VPDPBUSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1336, + ND_INS_VPDPBUSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1337, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, @@ -36327,9 +36346,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2164 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" + // Pos:2165 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" { - ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1337, + ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1338, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, @@ -36345,9 +36364,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2165 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM" + // Pos:2166 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM" { - ND_INS_VPDPBUSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1337, + ND_INS_VPDPBUSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1338, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, @@ -36362,9 +36381,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2166 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM" + // Pos:2167 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM" { - ND_INS_VPDPBUUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1338, + ND_INS_VPDPBUUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1339, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, @@ -36379,9 +36398,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2167 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM" + // Pos:2168 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM" { - ND_INS_VPDPBUUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1339, + ND_INS_VPDPBUUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1340, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, @@ -36396,9 +36415,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2168 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" + // Pos:2169 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" { - ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1340, + ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1341, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, @@ -36414,9 +36433,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2169 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM" + // Pos:2170 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM" { - ND_INS_VPDPWSSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1340, + ND_INS_VPDPWSSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1341, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, @@ -36431,9 +36450,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2170 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" + // Pos:2171 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" { - ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1341, + ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1342, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, @@ -36449,9 +36468,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2171 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM" + // Pos:2172 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM" { - ND_INS_VPDPWSSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1341, + ND_INS_VPDPWSSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1342, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, @@ -36466,9 +36485,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2172 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" + // Pos:2173 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" { - ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1342, + ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1343, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36484,9 +36503,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2173 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" + // Pos:2174 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" { - ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1343, + ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1344, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -36502,9 +36521,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2174 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" + // Pos:2175 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" { - ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1344, + ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1345, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, @@ -36520,9 +36539,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2175 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" + // Pos:2176 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" { - ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1345, + ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1346, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36538,9 +36557,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2176 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" + // Pos:2177 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" { - ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1345, + ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1346, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -36555,9 +36574,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2177 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" + // Pos:2178 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" { - ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1346, + ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1347, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, @@ -36573,9 +36592,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2178 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" + // Pos:2179 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" { - ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1347, + ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1348, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36591,9 +36610,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2179 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" + // Pos:2180 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" { - ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1348, + ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1349, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36609,9 +36628,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2180 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" + // Pos:2181 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" { - ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1349, + ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1350, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36627,9 +36646,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2181 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" + // Pos:2182 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" { - ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1350, + ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1351, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36645,9 +36664,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2182 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" + // Pos:2183 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" { - ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1351, + ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1352, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -36663,9 +36682,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2183 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML" + // Pos:2184 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML" { - ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1352, + ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1353, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36682,9 +36701,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2184 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM" + // Pos:2185 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM" { - ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1352, + ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1353, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36701,9 +36720,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2185 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML" + // Pos:2186 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML" { - ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1353, + ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1354, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36720,9 +36739,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2186 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM" + // Pos:2187 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM" { - ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1353, + ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1354, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -36739,9 +36758,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2187 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" + // Pos:2188 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" { - ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1354, + ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36757,9 +36776,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2188 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" + // Pos:2189 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" { - ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1354, + ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36775,9 +36794,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2189 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" + // Pos:2190 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" { - ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1354, + ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36792,9 +36811,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2190 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" + // Pos:2191 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" { - ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1354, + ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36809,9 +36828,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2191 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" + // Pos:2192 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" { - ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1355, + ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36827,9 +36846,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2192 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" + // Pos:2193 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" { - ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1355, + ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36845,9 +36864,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2193 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" + // Pos:2194 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" { - ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1355, + ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36862,9 +36881,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2194 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" + // Pos:2195 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" { - ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1355, + ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -36879,9 +36898,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2195 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" + // Pos:2196 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" { - ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1356, + ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36897,9 +36916,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2196 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" + // Pos:2197 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" { - ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1356, + ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36915,9 +36934,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2197 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" + // Pos:2198 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" { - ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1356, + ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36933,9 +36952,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2198 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" + // Pos:2199 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" { - ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1356, + ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -36950,9 +36969,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2199 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" + // Pos:2200 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" { - ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1357, + ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1358, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36968,9 +36987,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2200 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" + // Pos:2201 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" { - ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1357, + ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1358, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -36986,9 +37005,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2201 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" + // Pos:2202 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" { - ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1357, + ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1358, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -37003,9 +37022,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2202 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" + // Pos:2203 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" { - ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1358, + ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1359, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37021,9 +37040,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2203 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" + // Pos:2204 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" { - ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1358, + ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1359, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37039,9 +37058,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2204 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" + // Pos:2205 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" { - ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1358, + ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1359, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -37056,9 +37075,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2205 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" + // Pos:2206 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" { - ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1359, + ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1360, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, @@ -37074,9 +37093,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2206 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" + // Pos:2207 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" { - ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1360, + ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37092,9 +37111,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2207 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" + // Pos:2208 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" { - ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1361, + ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37110,9 +37129,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2208 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" + // Pos:2209 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" { - ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1362, + ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37128,9 +37147,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2209 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" + // Pos:2210 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" { - ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1363, + ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37146,9 +37165,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2210 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" + // Pos:2211 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" { - ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1364, + ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1365, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37164,9 +37183,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2211 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" + // Pos:2212 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" { - ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1365, + ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1366, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37182,9 +37201,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2212 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" + // Pos:2213 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" { - ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1366, + ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1367, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -37199,9 +37218,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2213 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" + // Pos:2214 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" { - ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1367, + ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1368, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37216,9 +37235,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2214 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" + // Pos:2215 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" { - ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1368, + ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1369, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37233,9 +37252,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2215 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" + // Pos:2216 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" { - ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1369, + ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1370, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -37250,9 +37269,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2216 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + // Pos:2217 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" { - ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1370, + ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1371, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37267,9 +37286,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2217 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + // Pos:2218 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" { - ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1370, + ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1371, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37284,9 +37303,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2218 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + // Pos:2219 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" { - ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1370, + ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1371, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37301,9 +37320,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2219 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + // Pos:2220 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" { - ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1370, + ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1371, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37318,9 +37337,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2220 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" + // Pos:2221 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" { - ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1371, + ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1372, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -37335,9 +37354,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2221 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" + // Pos:2222 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" { - ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1371, + ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1372, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -37352,9 +37371,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2222 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" + // Pos:2223 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" { - ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1371, + ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1372, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37369,9 +37388,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2223 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" + // Pos:2224 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" { - ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1371, + ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1372, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37386,9 +37405,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2224 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" + // Pos:2225 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" { - ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1372, + ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -37403,9 +37422,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2225 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" + // Pos:2226 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" { - ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1372, + ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -37420,9 +37439,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2226 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" + // Pos:2227 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" { - ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1372, + ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37437,9 +37456,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2227 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" + // Pos:2228 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" { - ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1372, + ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37454,9 +37473,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2228 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + // Pos:2229 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" { - ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1373, + ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37471,9 +37490,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2229 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + // Pos:2230 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1373, + ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37488,9 +37507,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2230 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + // Pos:2231 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1373, + ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -37505,9 +37524,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2231 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + // Pos:2232 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" { - ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1373, + ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37522,9 +37541,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2232 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + // Pos:2233 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1373, + ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37539,9 +37558,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2233 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + // Pos:2234 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" { - ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1373, + ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37556,9 +37575,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2234 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" + // Pos:2235 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" { - ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1374, + ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1375, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37573,9 +37592,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2235 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" + // Pos:2236 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" { - ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1374, + ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1375, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -37590,9 +37609,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2236 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" + // Pos:2237 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" { - ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1375, + ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1376, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37607,9 +37626,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2237 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" + // Pos:2238 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" { - ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1375, + ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1376, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -37624,9 +37643,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2238 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" + // Pos:2239 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" { - ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1376, + ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1377, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37641,9 +37660,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2239 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" + // Pos:2240 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" { - ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1376, + ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1377, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -37658,9 +37677,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2240 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" + // Pos:2241 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" { - ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1377, + ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1378, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -37675,9 +37694,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2241 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" + // Pos:2242 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" { - ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1377, + ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1378, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, @@ -37692,9 +37711,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2242 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" + // Pos:2243 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" { - ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1378, + ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1379, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37708,9 +37727,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2243 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" + // Pos:2244 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" { - ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1379, + ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1380, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37724,9 +37743,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2244 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" + // Pos:2245 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" { - ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1380, + ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1381, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37740,9 +37759,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2245 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" + // Pos:2246 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" { - ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1381, + ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1382, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37757,9 +37776,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2246 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" + // Pos:2247 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" { - ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1382, + ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1383, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37773,9 +37792,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2247 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" + // Pos:2248 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" { - ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1383, + ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1384, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37790,9 +37809,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2248 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" + // Pos:2249 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" { - ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1384, + ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1385, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37806,9 +37825,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2249 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" + // Pos:2250 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" { - ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1385, + ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1386, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37822,9 +37841,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2250 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" + // Pos:2251 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" { - ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1386, + ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1387, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37838,9 +37857,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2251 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" + // Pos:2252 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" { - ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1387, + ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1388, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37854,9 +37873,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2252 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" + // Pos:2253 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" { - ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1388, + ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1389, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37870,9 +37889,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2253 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" + // Pos:2254 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" { - ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1389, + ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1390, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37886,9 +37905,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2254 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" + // Pos:2255 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" { - ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1390, + ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1391, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37903,9 +37922,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2255 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" + // Pos:2256 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" { - ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1391, + ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1392, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37919,9 +37938,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2256 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" + // Pos:2257 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" { - ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1392, + ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1393, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37935,9 +37954,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2257 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" + // Pos:2258 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" { - ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1393, + ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1394, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37951,9 +37970,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2258 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" + // Pos:2259 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" { - ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1394, + ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1395, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -37967,9 +37986,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2259 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" + // Pos:2260 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" { - ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1395, + ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1396, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -37984,9 +38003,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2260 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" + // Pos:2261 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" { - ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1396, + ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1397, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38000,9 +38019,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2261 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" + // Pos:2262 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" { - ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1397, + ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1398, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38017,9 +38036,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2262 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" + // Pos:2263 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" { - ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1398, + ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1399, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38034,9 +38053,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2263 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" + // Pos:2264 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" { - ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1399, + ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1400, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38050,9 +38069,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2264 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + // Pos:2265 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" { - ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1400, + ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1401, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38068,9 +38087,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2265 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + // Pos:2266 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" { - ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1400, + ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1401, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38086,9 +38105,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2266 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + // Pos:2267 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" { - ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1400, + ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1401, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38104,9 +38123,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2267 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + // Pos:2268 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" { - ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1400, + ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1401, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38122,9 +38141,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2268 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + // Pos:2269 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" { - ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1401, + ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1402, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -38140,9 +38159,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2269 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + // Pos:2270 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" { - ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1401, + ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1402, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38158,9 +38177,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2270 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + // Pos:2271 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" { - ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1402, + ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1403, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -38176,9 +38195,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2271 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + // Pos:2272 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" { - ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1402, + ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1403, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38194,9 +38213,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2272 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + // Pos:2273 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" { - ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1403, + ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1404, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38212,9 +38231,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2273 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + // Pos:2274 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" { - ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1403, + ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1404, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38230,9 +38249,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2274 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + // Pos:2275 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" { - ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1403, + ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1404, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38248,9 +38267,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2275 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + // Pos:2276 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" { - ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1403, + ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1404, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38266,9 +38285,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2276 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" + // Pos:2277 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" { - ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1404, + ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1405, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -38283,9 +38302,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2277 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" + // Pos:2278 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" { - ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1405, + ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1406, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, @@ -38300,9 +38319,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2278 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" + // Pos:2279 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" { - ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1406, + ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1407, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38318,9 +38337,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2279 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" + // Pos:2280 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" { - ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1407, + ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1408, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38336,9 +38355,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2280 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" + // Pos:2281 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" { - ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1408, + ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1409, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38354,9 +38373,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2281 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" + // Pos:2282 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" { - ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1409, + ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1410, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38372,9 +38391,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2282 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" + // Pos:2283 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" { - ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1410, + ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1411, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38390,9 +38409,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2283 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" + // Pos:2284 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" { - ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1411, + ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1412, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38408,9 +38427,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2284 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" + // Pos:2285 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" { - ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1412, + ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1413, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38426,9 +38445,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2285 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" + // Pos:2286 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" { - ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1413, + ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1414, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38444,9 +38463,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2286 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" + // Pos:2287 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" { - ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1414, + ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1415, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38462,9 +38481,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2287 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" + // Pos:2288 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" { - ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1415, + ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1416, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38480,9 +38499,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2288 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" + // Pos:2289 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" { - ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1416, + ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1417, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38498,9 +38517,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2289 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" + // Pos:2290 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" { - ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1417, + ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1418, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -38516,9 +38535,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2290 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" + // Pos:2291 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" { - ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1418, + ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1419, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, @@ -38534,9 +38553,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2291 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM" + // Pos:2292 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM" { - ND_INS_VPMADD52HUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1418, + ND_INS_VPMADD52HUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1419, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXIFMA, @@ -38551,9 +38570,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2292 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" + // Pos:2293 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" { - ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1419, + ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1420, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, @@ -38569,9 +38588,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2293 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM" + // Pos:2294 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM" { - ND_INS_VPMADD52LUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1419, + ND_INS_VPMADD52LUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1420, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXIFMA, @@ -38586,9 +38605,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2294 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" + // Pos:2295 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" { - ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1420, + ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1421, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38604,9 +38623,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2295 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" + // Pos:2296 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" { - ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1420, + ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1421, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38621,9 +38640,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2296 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" + // Pos:2297 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" { - ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1421, + ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1422, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38639,9 +38658,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2297 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" + // Pos:2298 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" { - ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1421, + ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1422, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38656,9 +38675,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2298 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" + // Pos:2299 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" { - ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1422, + ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1423, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -38673,9 +38692,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2299 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" + // Pos:2300 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" { - ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1422, + ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1423, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -38690,9 +38709,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2300 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" + // Pos:2301 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" { - ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1423, + ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1424, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -38707,9 +38726,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2301 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" + // Pos:2302 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" { - ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1423, + ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1424, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -38724,9 +38743,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2302 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" + // Pos:2303 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" { - ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1424, + ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1425, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38742,9 +38761,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2303 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" + // Pos:2304 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" { - ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1424, + ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1425, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38759,9 +38778,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2304 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" + // Pos:2305 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" { - ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1425, + ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1426, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38777,9 +38796,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2305 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" + // Pos:2306 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" { - ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1425, + ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1426, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38794,9 +38813,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2306 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" + // Pos:2307 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" { - ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1426, + ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1427, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38812,9 +38831,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2307 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" + // Pos:2308 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" { - ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1427, + ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1428, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38830,9 +38849,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2308 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" + // Pos:2309 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" { - ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1427, + ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1428, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38847,9 +38866,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2309 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" + // Pos:2310 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" { - ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1428, + ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1429, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38865,9 +38884,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2310 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:2311 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" { - ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1428, + ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1429, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38882,9 +38901,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2311 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" + // Pos:2312 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" { - ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1429, + ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1430, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38900,9 +38919,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2312 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" + // Pos:2313 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" { - ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1429, + ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1430, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38917,9 +38936,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2313 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" + // Pos:2314 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" { - ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1430, + ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1431, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -38935,9 +38954,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2314 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" + // Pos:2315 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" { - ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1431, + ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1432, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38953,9 +38972,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2315 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" + // Pos:2316 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" { - ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1431, + ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1432, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -38970,9 +38989,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2316 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" + // Pos:2317 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" { - ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1432, + ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1433, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -38988,9 +39007,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2317 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" + // Pos:2318 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" { - ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1432, + ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1433, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39005,9 +39024,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2318 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" + // Pos:2319 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" { - ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1433, + ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1434, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39023,9 +39042,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2319 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" + // Pos:2320 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" { - ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1433, + ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1434, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39040,9 +39059,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2320 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" + // Pos:2321 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" { - ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1434, + ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1435, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39058,9 +39077,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2321 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" + // Pos:2322 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" { - ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1435, + ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1436, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39076,9 +39095,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2322 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" + // Pos:2323 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" { - ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1435, + ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1436, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39093,9 +39112,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2323 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" + // Pos:2324 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" { - ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1436, + ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1437, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39111,9 +39130,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2324 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" + // Pos:2325 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" { - ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1436, + ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1437, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39128,9 +39147,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2325 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" + // Pos:2326 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" { - ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1437, + ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1438, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39146,9 +39165,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2326 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" + // Pos:2327 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" { - ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1437, + ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1438, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39163,9 +39182,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2327 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" + // Pos:2328 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" { - ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1438, + ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1439, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39181,9 +39200,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2328 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" + // Pos:2329 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" { - ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1439, + ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1440, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39199,9 +39218,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2329 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" + // Pos:2330 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" { - ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1439, + ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1440, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39216,9 +39235,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2330 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" + // Pos:2331 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" { - ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1440, + ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1441, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39232,9 +39251,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2331 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" + // Pos:2332 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" { - ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1441, + ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1442, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -39248,9 +39267,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2332 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" + // Pos:2333 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" { - ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1442, + ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1443, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39265,9 +39284,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2333 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" + // Pos:2334 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" { - ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1443, + ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1444, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39282,9 +39301,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2334 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" + // Pos:2335 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" { - ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1444, + ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1445, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39298,9 +39317,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2335 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" + // Pos:2336 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" { - ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1445, + ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1446, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -39314,9 +39333,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2336 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" + // Pos:2337 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" { - ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1446, + ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1447, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -39330,9 +39349,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2337 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" + // Pos:2338 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" { - ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1447, + ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1448, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39346,9 +39365,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2338 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" + // Pos:2339 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" { - ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1448, + ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1449, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39362,9 +39381,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2339 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" + // Pos:2340 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" { - ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1449, + ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1450, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -39378,9 +39397,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2340 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" + // Pos:2341 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" { - ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1450, + ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1451, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39395,9 +39414,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2341 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" + // Pos:2342 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" { - ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1451, + ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1452, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39412,9 +39431,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2342 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" + // Pos:2343 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" { - ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1452, + ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1453, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39429,9 +39448,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2343 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" + // Pos:2344 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" { - ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1453, + ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1454, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39446,9 +39465,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2344 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" + // Pos:2345 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" { - ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1454, + ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1455, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39463,9 +39482,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2345 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" + // Pos:2346 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" { - ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1455, + ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1456, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39480,9 +39499,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2346 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" + // Pos:2347 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" { - ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1456, + ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1457, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39497,9 +39516,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2347 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" + // Pos:2348 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" { - ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1457, + ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1458, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39514,9 +39533,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2348 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" + // Pos:2349 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" { - ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1458, + ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1459, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39531,9 +39550,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2349 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" + // Pos:2350 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" { - ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1459, + ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1460, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39548,9 +39567,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2350 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" + // Pos:2351 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" { - ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1459, + ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1460, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39564,9 +39583,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2351 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" + // Pos:2352 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" { - ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1459, + ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1460, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39580,9 +39599,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2352 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" + // Pos:2353 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" { - ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1460, + ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1461, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39597,9 +39616,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2353 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" + // Pos:2354 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" { - ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1460, + ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1461, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39613,9 +39632,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2354 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" + // Pos:2355 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" { - ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1460, + ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1461, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39629,9 +39648,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2355 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" + // Pos:2356 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" { - ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1461, + ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1462, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39646,9 +39665,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2356 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" + // Pos:2357 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" { - ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1461, + ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1462, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39662,9 +39681,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2357 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" + // Pos:2358 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" { - ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1461, + ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1462, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39678,9 +39697,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2358 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" + // Pos:2359 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" { - ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1462, + ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1463, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39695,9 +39714,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2359 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" + // Pos:2360 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" { - ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1462, + ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1463, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39711,9 +39730,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2360 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" + // Pos:2361 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" { - ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1462, + ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1463, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39727,9 +39746,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2361 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" + // Pos:2362 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" { - ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1463, + ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1464, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39744,9 +39763,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2362 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" + // Pos:2363 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" { - ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1463, + ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1464, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39760,9 +39779,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2363 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" + // Pos:2364 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" { - ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1463, + ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1464, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39776,9 +39795,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2364 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" + // Pos:2365 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" { - ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1464, + ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1465, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39793,9 +39812,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2365 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" + // Pos:2366 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" { - ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1464, + ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1465, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39809,9 +39828,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2366 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" + // Pos:2367 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" { - ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1464, + ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1465, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -39825,9 +39844,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2367 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" + // Pos:2368 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" { - ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1465, + ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1466, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39842,9 +39861,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2368 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" + // Pos:2369 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" { - ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1466, + ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1467, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39859,9 +39878,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2369 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" + // Pos:2370 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" { - ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1467, + ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1468, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39876,9 +39895,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2370 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" + // Pos:2371 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" { - ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1468, + ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1469, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39893,9 +39912,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2371 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" + // Pos:2372 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" { - ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1469, + ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1470, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39910,9 +39929,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2372 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" + // Pos:2373 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" { - ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1470, + ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1471, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39927,9 +39946,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2373 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" + // Pos:2374 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" { - ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1471, + ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1472, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39943,9 +39962,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2374 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" + // Pos:2375 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" { - ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1472, + ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1473, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -39960,9 +39979,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2375 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" + // Pos:2376 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" { - ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1473, + ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1474, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -39977,9 +39996,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2376 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" + // Pos:2377 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" { - ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1473, + ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1474, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -39993,9 +40012,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2377 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" + // Pos:2378 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" { - ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1473, + ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1474, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -40009,9 +40028,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2378 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" + // Pos:2379 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" { - ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1474, + ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1475, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40026,9 +40045,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2379 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" + // Pos:2380 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" { - ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1474, + ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1475, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40042,9 +40061,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2380 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" + // Pos:2381 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" { - ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1474, + ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1475, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -40058,9 +40077,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2381 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" + // Pos:2382 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" { - ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1475, + ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1476, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40075,9 +40094,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2382 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" + // Pos:2383 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" { - ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1475, + ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1476, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40091,9 +40110,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2383 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" + // Pos:2384 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" { - ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1475, + ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1476, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -40107,9 +40126,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2384 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" + // Pos:2385 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" { - ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1476, + ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1477, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40124,9 +40143,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2385 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" + // Pos:2386 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" { - ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1476, + ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1477, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40140,9 +40159,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2386 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" + // Pos:2387 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" { - ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1476, + ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1477, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -40156,9 +40175,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2387 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" + // Pos:2388 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" { - ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1477, + ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1478, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40173,9 +40192,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2388 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" + // Pos:2389 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" { - ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1477, + ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1478, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40189,9 +40208,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2389 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" + // Pos:2390 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" { - ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1477, + ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1478, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -40205,9 +40224,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2390 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" + // Pos:2391 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" { - ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1478, + ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1479, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40222,9 +40241,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2391 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" + // Pos:2392 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" { - ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1478, + ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1479, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40238,9 +40257,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2392 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" + // Pos:2393 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" { - ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1478, + ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1479, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -40254,9 +40273,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2393 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" + // Pos:2394 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" { - ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1479, + ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1480, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40272,9 +40291,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2394 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" + // Pos:2395 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" { - ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1479, + ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1480, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40289,9 +40308,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2395 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" + // Pos:2396 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" { - ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1480, + ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1481, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40307,9 +40326,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2396 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" + // Pos:2397 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" { - ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1480, + ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1481, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40324,9 +40343,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2397 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" + // Pos:2398 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" { - ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1481, + ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1482, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40342,9 +40361,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2398 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" + // Pos:2399 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" { - ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1481, + ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1482, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40359,9 +40378,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2399 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" + // Pos:2400 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" { - ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1482, + ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1483, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40377,9 +40396,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2400 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" + // Pos:2401 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" { - ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1482, + ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1483, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40394,9 +40413,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2401 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" + // Pos:2402 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" { - ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1483, + ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1484, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40412,9 +40431,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2402 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" + // Pos:2403 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" { - ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1483, + ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1484, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40429,9 +40448,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2403 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" + // Pos:2404 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" { - ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1484, + ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1485, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -40447,9 +40466,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2404 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" + // Pos:2405 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" { - ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1485, + ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1486, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -40465,9 +40484,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2405 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" + // Pos:2406 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" { - ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1485, + ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1486, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40482,9 +40501,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2406 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" + // Pos:2407 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" { - ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1486, + ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1487, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, @@ -40500,9 +40519,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2407 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" + // Pos:2408 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" { - ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1487, + ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1488, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40518,9 +40537,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2408 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" + // Pos:2409 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" { - ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1487, + ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1488, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40535,9 +40554,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2409 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" + // Pos:2410 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" { - ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1488, + ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1489, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, @@ -40552,9 +40571,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2410 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" + // Pos:2411 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" { - ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1489, + ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1490, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, @@ -40569,9 +40588,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2411 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" + // Pos:2412 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" { - ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1490, + ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1491, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, @@ -40586,9 +40605,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2412 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" + // Pos:2413 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" { - ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1491, + ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1492, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, @@ -40603,9 +40622,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2413 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" + // Pos:2414 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" { - ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1492, + ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1493, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -40620,9 +40639,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2414 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" + // Pos:2415 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" { - ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1493, + ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1494, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40638,9 +40657,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2415 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" + // Pos:2416 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" { - ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1494, + ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1495, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40656,9 +40675,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2416 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" + // Pos:2417 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" { - ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1495, + ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1496, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40674,9 +40693,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2417 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" + // Pos:2418 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" { - ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1495, + ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1496, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40692,9 +40711,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2418 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" + // Pos:2419 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" { - ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1496, + ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1497, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40710,9 +40729,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2419 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" + // Pos:2420 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" { - ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1497, + ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1498, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40728,9 +40747,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2420 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" + // Pos:2421 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" { - ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1498, + ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1499, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40746,9 +40765,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2421 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" + // Pos:2422 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" { - ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1499, + ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1500, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40764,9 +40783,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2422 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" + // Pos:2423 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" { - ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1500, + ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1501, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40782,9 +40801,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2423 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" + // Pos:2424 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" { - ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1501, + ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1502, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40800,9 +40819,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2424 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" + // Pos:2425 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" { - ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1502, + ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40818,9 +40837,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2425 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" + // Pos:2426 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" { - ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1503, + ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1504, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -40836,9 +40855,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2426 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" + // Pos:2427 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" { - ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1504, + ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1505, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40853,9 +40872,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2427 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" + // Pos:2428 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" { - ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1504, + ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1505, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40870,9 +40889,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2428 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" + // Pos:2429 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" { - ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1504, + ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1505, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40887,9 +40906,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2429 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" + // Pos:2430 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" { - ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1505, + ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1506, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40904,9 +40923,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2430 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" + // Pos:2431 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" { - ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1505, + ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1506, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40921,9 +40940,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2431 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" + // Pos:2432 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" { - ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1505, + ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1506, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40938,9 +40957,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2432 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" + // Pos:2433 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" { - ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1506, + ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1507, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40955,9 +40974,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2433 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" + // Pos:2434 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" { - ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1506, + ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1507, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40972,9 +40991,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2434 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" + // Pos:2435 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" { - ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1506, + ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1507, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -40989,9 +41008,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2435 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" + // Pos:2436 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" { - ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1507, + ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1508, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41006,9 +41025,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2436 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" + // Pos:2437 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" { - ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1507, + ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1508, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41023,9 +41042,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2437 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" + // Pos:2438 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" { - ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1507, + ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1508, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41040,9 +41059,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2438 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + // Pos:2439 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" { - ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1508, + ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1509, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41057,9 +41076,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2439 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + // Pos:2440 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" { - ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1508, + ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1509, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41074,9 +41093,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2440 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" + // Pos:2441 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" { - ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1509, + ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1510, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41091,9 +41110,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2441 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" + // Pos:2442 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" { - ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1510, + ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1511, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41108,9 +41127,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2442 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" + // Pos:2443 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" { - ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1511, + ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1512, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41125,9 +41144,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2443 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" + // Pos:2444 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" { - ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1512, + ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1513, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41142,9 +41161,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2444 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" + // Pos:2445 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" { - ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1513, + ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1514, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41159,9 +41178,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2445 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" + // Pos:2446 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" { - ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1513, + ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1514, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41176,9 +41195,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2446 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" + // Pos:2447 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" { - ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1514, + ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1515, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41193,9 +41212,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2447 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" + // Pos:2448 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" { - ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1514, + ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1515, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41210,9 +41229,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2448 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" + // Pos:2449 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" { - ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1515, + ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1516, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41227,9 +41246,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2449 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" + // Pos:2450 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" { - ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1515, + ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1516, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41244,9 +41263,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2450 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" + // Pos:2451 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" { - ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1516, + ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1517, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41261,9 +41280,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2451 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" + // Pos:2452 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" { - ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1516, + ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1517, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41278,9 +41297,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2452 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" + // Pos:2453 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1517, + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1518, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41295,9 +41314,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2453 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" + // Pos:2454 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1517, + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1518, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41312,9 +41331,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2454 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" + // Pos:2455 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1517, + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1518, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41329,9 +41348,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2455 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" + // Pos:2456 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1517, + ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1518, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41346,9 +41365,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2456 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" + // Pos:2457 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" { - ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1518, + ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1519, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41363,9 +41382,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2457 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" + // Pos:2458 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" { - ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1519, + ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1520, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -41382,9 +41401,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2458 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" + // Pos:2459 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" { - ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1520, + ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1521, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -41401,9 +41420,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2459 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" + // Pos:2460 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" { - ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1521, + ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1522, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -41419,9 +41438,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2460 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" + // Pos:2461 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" { - ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1522, + ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1523, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -41437,9 +41456,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2461 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" + // Pos:2462 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" { - ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1523, + ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1524, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -41455,9 +41474,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2462 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" + // Pos:2463 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" { - ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1524, + ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1525, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -41474,9 +41493,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2463 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" + // Pos:2464 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" { - ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1525, + ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1526, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41491,9 +41510,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2464 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" + // Pos:2465 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" { - ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1525, + ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1526, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41508,9 +41527,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2465 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" + // Pos:2466 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" { - ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1526, + ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1527, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, @@ -41525,9 +41544,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2466 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" + // Pos:2467 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" { - ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1527, + ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1528, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -41544,9 +41563,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2467 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" + // Pos:2468 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" { - ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1528, + ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1529, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -41563,9 +41582,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2468 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" + // Pos:2469 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" { - ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1529, + ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1530, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -41581,9 +41600,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2469 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" + // Pos:2470 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" { - ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1530, + ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1531, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -41599,9 +41618,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2470 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" + // Pos:2471 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" { - ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1531, + ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1532, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -41617,9 +41636,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2471 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" + // Pos:2472 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" { - ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1532, + ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1533, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, @@ -41636,9 +41655,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2472 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" + // Pos:2473 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" { - ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1533, + ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1534, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41654,9 +41673,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2473 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" + // Pos:2474 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" { - ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1533, + ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1534, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41671,9 +41690,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2474 Instruction:"VPSHUFBITQMB rK{K},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" + // Pos:2475 Instruction:"VPSHUFBITQMB rK{K},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" { - ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1534, + ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1535, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, @@ -41689,9 +41708,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2475 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" + // Pos:2476 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" { - ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1535, + ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1536, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41707,9 +41726,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2476 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" + // Pos:2477 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" { - ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1535, + ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1536, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41724,9 +41743,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2477 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" + // Pos:2478 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" { - ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1536, + ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1537, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41742,9 +41761,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2478 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" + // Pos:2479 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" { - ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1536, + ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1537, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41759,9 +41778,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2479 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" + // Pos:2480 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" { - ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1537, + ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1538, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41777,9 +41796,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2480 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" + // Pos:2481 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" { - ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1537, + ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1538, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41794,9 +41813,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2481 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" + // Pos:2482 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" { - ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1538, + ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1539, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41811,9 +41830,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2482 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" + // Pos:2483 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" { - ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1539, + ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1540, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41828,9 +41847,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2483 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" + // Pos:2484 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" { - ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1540, + ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1541, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41845,9 +41864,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2484 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" + // Pos:2485 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" { - ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1541, + ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1542, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41863,9 +41882,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2485 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" + // Pos:2486 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" { - ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1541, + ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1542, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41881,9 +41900,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2486 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" + // Pos:2487 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" { - ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1541, + ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1542, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41898,9 +41917,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2487 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" + // Pos:2488 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" { - ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1541, + ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1542, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41915,9 +41934,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2488 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" + // Pos:2489 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" { - ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1542, + ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1543, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -41932,9 +41951,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2489 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" + // Pos:2490 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" { - ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1542, + ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1543, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -41949,9 +41968,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2490 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" + // Pos:2491 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" { - ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1543, + ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1544, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41967,9 +41986,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2491 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" + // Pos:2492 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" { - ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1543, + ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1544, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -41985,9 +42004,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2492 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" + // Pos:2493 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" { - ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1543, + ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1544, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42002,9 +42021,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2493 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" + // Pos:2494 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" { - ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1543, + ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1544, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42019,9 +42038,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2494 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" + // Pos:2495 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" { - ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1544, + ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1545, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42037,9 +42056,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2495 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" + // Pos:2496 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" { - ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1544, + ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1545, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -42054,9 +42073,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2496 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" + // Pos:2497 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" { - ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1545, + ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1546, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42072,9 +42091,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2497 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" + // Pos:2498 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" { - ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1545, + ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1546, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -42089,9 +42108,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2498 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" + // Pos:2499 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" { - ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1546, + ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1547, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42107,9 +42126,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2499 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" + // Pos:2500 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" { - ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1547, + ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1548, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42125,9 +42144,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2500 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" + // Pos:2501 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" { - ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1547, + ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1548, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42143,9 +42162,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2501 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" + // Pos:2502 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" { - ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1547, + ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1548, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42160,9 +42179,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2502 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" + // Pos:2503 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" { - ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1547, + ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1548, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42177,9 +42196,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2503 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" + // Pos:2504 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" { - ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1548, + ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1549, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42195,9 +42214,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2504 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" + // Pos:2505 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" { - ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1548, + ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1549, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42213,9 +42232,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2505 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" + // Pos:2506 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" { - ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1548, + ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1549, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42230,9 +42249,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2506 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" + // Pos:2507 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" { - ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1548, + ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1549, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42247,9 +42266,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2507 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" + // Pos:2508 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" { - ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1549, + ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1550, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42265,9 +42284,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2508 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" + // Pos:2509 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" { - ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1549, + ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1550, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42283,9 +42302,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2509 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" + // Pos:2510 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" { - ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1550, + ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1551, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42301,9 +42320,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2510 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" + // Pos:2511 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" { - ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1550, + ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1551, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -42318,9 +42337,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2511 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" + // Pos:2512 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" { - ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1551, + ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1552, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42336,9 +42355,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2512 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" + // Pos:2513 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" { - ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1552, + ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1553, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42354,9 +42373,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2513 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" + // Pos:2514 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" { - ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1553, + ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1554, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42372,9 +42391,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2514 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" + // Pos:2515 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" { - ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1553, + ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1554, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42390,9 +42409,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2515 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" + // Pos:2516 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" { - ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1553, + ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1554, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42407,9 +42426,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2516 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" + // Pos:2517 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" { - ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1553, + ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1554, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42424,9 +42443,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2517 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" + // Pos:2518 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" { - ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1554, + ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1555, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42442,9 +42461,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2518 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" + // Pos:2519 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" { - ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1554, + ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1555, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42460,9 +42479,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2519 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" + // Pos:2520 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" { - ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1554, + ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1555, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42477,9 +42496,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2520 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" + // Pos:2521 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" { - ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1554, + ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1555, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42494,9 +42513,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2521 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" + // Pos:2522 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" { - ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1555, + ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1556, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42511,9 +42530,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2522 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" + // Pos:2523 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" { - ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1555, + ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1556, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42528,9 +42547,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2523 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" + // Pos:2524 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" { - ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1556, + ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1557, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42546,9 +42565,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2524 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" + // Pos:2525 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" { - ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1556, + ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1557, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42564,9 +42583,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2525 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" + // Pos:2526 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" { - ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1556, + ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1557, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42581,9 +42600,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2526 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" + // Pos:2527 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" { - ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1556, + ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1557, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42598,9 +42617,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2527 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" + // Pos:2528 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" { - ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1557, + ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1558, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42616,9 +42635,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2528 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" + // Pos:2529 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" { - ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1557, + ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1558, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -42633,9 +42652,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2529 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" + // Pos:2530 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" { - ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1558, + ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1559, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42651,9 +42670,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2530 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" + // Pos:2531 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" { - ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1558, + ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1559, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, @@ -42668,9 +42687,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2531 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" + // Pos:2532 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" { - ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1559, + ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1560, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42686,9 +42705,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2532 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" + // Pos:2533 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" { - ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1560, + ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1561, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42704,9 +42723,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2533 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" + // Pos:2534 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" { - ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1560, + ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1561, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42722,9 +42741,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2534 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" + // Pos:2535 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" { - ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1560, + ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1561, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42739,9 +42758,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2535 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" + // Pos:2536 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" { - ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1560, + ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1561, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42756,9 +42775,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2536 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" + // Pos:2537 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" { - ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1561, + ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1562, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42774,9 +42793,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2537 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" + // Pos:2538 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" { - ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1561, + ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1562, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42791,9 +42810,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2538 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" + // Pos:2539 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" { - ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1562, + ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1563, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42809,9 +42828,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2539 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" + // Pos:2540 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" { - ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1562, + ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1563, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42826,9 +42845,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2540 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" + // Pos:2541 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" { - ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1563, + ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1564, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -42844,9 +42863,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2541 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" + // Pos:2542 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" { - ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1563, + ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1564, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42861,9 +42880,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2542 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" + // Pos:2543 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" { - ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1564, + ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1565, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42879,9 +42898,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2543 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" + // Pos:2544 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" { - ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1564, + ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1565, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42896,9 +42915,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2544 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" + // Pos:2545 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" { - ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1565, + ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1566, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42914,9 +42933,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2545 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" + // Pos:2546 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" { - ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1565, + ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1566, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42931,9 +42950,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2546 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" + // Pos:2547 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" { - ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1566, + ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1567, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42949,9 +42968,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2547 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" + // Pos:2548 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" { - ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1566, + ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1567, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -42966,9 +42985,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2548 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" + // Pos:2549 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" { - ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1567, + ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1568, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -42984,9 +43003,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2549 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" + // Pos:2550 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" { - ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1567, + ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1568, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43001,9 +43020,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2550 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" + // Pos:2551 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" { - ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1568, + ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1569, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -43019,9 +43038,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2551 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" + // Pos:2552 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" { - ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1568, + ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1569, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43036,9 +43055,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2552 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" + // Pos:2553 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" { - ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1569, + ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1570, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43055,9 +43074,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2553 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" + // Pos:2554 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" { - ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1570, + ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1571, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43074,9 +43093,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2554 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" + // Pos:2555 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" { - ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1571, + ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1572, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43091,9 +43110,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2555 Instruction:"VPTESTMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" + // Pos:2556 Instruction:"VPTESTMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" { - ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1572, + ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1573, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -43109,9 +43128,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2556 Instruction:"VPTESTMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" + // Pos:2557 Instruction:"VPTESTMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" { - ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1573, + ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1574, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43127,9 +43146,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2557 Instruction:"VPTESTMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" + // Pos:2558 Instruction:"VPTESTMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" { - ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1574, + ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1575, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43145,9 +43164,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2558 Instruction:"VPTESTMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" + // Pos:2559 Instruction:"VPTESTMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" { - ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1575, + ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1576, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -43163,9 +43182,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2559 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" + // Pos:2560 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" { - ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1576, + ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1577, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -43181,9 +43200,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2560 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" + // Pos:2561 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" { - ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1577, + ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1578, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43199,9 +43218,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2561 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" + // Pos:2562 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" { - ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1578, + ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1579, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43217,9 +43236,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2562 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" + // Pos:2563 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" { - ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1579, + ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1580, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -43235,9 +43254,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2563 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" + // Pos:2564 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" { - ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1580, + ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1581, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -43253,9 +43272,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2564 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" + // Pos:2565 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" { - ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1580, + ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1581, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43270,9 +43289,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2565 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" + // Pos:2566 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" { - ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1581, + ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1582, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43288,9 +43307,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2566 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" + // Pos:2567 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" { - ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1581, + ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1582, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43305,9 +43324,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2567 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" + // Pos:2568 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" { - ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1582, + ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1583, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43323,9 +43342,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2568 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" + // Pos:2569 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" { - ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1582, + ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1583, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43340,9 +43359,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2569 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" + // Pos:2570 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" { - ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1583, + ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1584, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -43358,9 +43377,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2570 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" + // Pos:2571 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" { - ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1583, + ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1584, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43375,9 +43394,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2571 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" + // Pos:2572 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" { - ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1584, + ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1585, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -43393,9 +43412,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2572 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" + // Pos:2573 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" { - ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1584, + ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1585, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43410,9 +43429,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2573 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" + // Pos:2574 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" { - ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1585, + ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1586, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43428,9 +43447,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2574 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" + // Pos:2575 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" { - ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1585, + ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1586, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43445,9 +43464,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2575 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" + // Pos:2576 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" { - ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1586, + ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1587, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43463,9 +43482,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2576 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" + // Pos:2577 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" { - ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1586, + ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1587, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43480,9 +43499,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2577 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" + // Pos:2578 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" { - ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1587, + ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1588, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, @@ -43498,9 +43517,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2578 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" + // Pos:2579 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" { - ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1587, + ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1588, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43515,9 +43534,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2579 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" + // Pos:2580 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" { - ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1588, + ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1589, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43532,9 +43551,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2580 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" + // Pos:2581 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" { - ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1589, + ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1590, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43550,9 +43569,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2581 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" + // Pos:2582 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" { - ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1590, + ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1591, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43568,9 +43587,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2582 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" + // Pos:2583 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" { - ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1591, + ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1592, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -43587,9 +43606,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2583 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" + // Pos:2584 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" { - ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1592, + ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1593, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -43606,9 +43625,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2584 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" + // Pos:2585 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" { - ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1593, + ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1594, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -43625,9 +43644,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2585 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" + // Pos:2586 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" { - ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1594, + ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1595, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -43644,9 +43663,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2586 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" + // Pos:2587 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" { - ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1595, + ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1596, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43661,9 +43680,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2587 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" + // Pos:2588 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" { - ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1596, + ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1597, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43678,9 +43697,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2588 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" + // Pos:2589 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" { - ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1597, + ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1598, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43696,9 +43715,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2589 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" + // Pos:2590 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" { - ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1598, + ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1599, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43714,9 +43733,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2590 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" + // Pos:2591 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" { - ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1599, + ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1600, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -43731,9 +43750,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2591 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" + // Pos:2592 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" { - ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1600, + ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1601, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -43748,9 +43767,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2592 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" + // Pos:2593 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" { - ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1601, + ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1602, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -43766,9 +43785,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2593 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" + // Pos:2594 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" { - ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1602, + ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1603, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -43784,9 +43803,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2594 Instruction:"VRCPPH Vn{K}{z},aKq,Wn|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM" + // Pos:2595 Instruction:"VRCPPH Vn{K}{z},aKq,Wn|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM" { - ND_INS_VRCPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1603, + ND_INS_VRCPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1604, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43801,9 +43820,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2595 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" + // Pos:2596 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" { - ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1604, + ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1605, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43817,9 +43836,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2596 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM" + // Pos:2597 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM" { - ND_INS_VRCPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1605, + ND_INS_VRCPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1606, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43835,9 +43854,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2597 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" + // Pos:2598 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" { - ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1606, + ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1607, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -43852,9 +43871,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2598 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" + // Pos:2599 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" { - ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1607, + ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1608, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -43870,9 +43889,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2599 Instruction:"VREDUCEPH Vn{K}{z},aKq,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI" + // Pos:2600 Instruction:"VREDUCEPH Vn{K}{z},aKq,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI" { - ND_INS_VREDUCEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1608, + ND_INS_VREDUCEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1609, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43888,9 +43907,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2600 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" + // Pos:2601 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" { - ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1609, + ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1610, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -43906,9 +43925,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2601 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" + // Pos:2602 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" { - ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1610, + ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1611, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -43925,9 +43944,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2602 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI" + // Pos:2603 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI" { - ND_INS_VREDUCESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1611, + ND_INS_VREDUCESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1612, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43944,9 +43963,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2603 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" + // Pos:2604 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" { - ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1612, + ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1613, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -43963,9 +43982,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2604 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" + // Pos:2605 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" { - ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1613, + ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1614, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -43981,9 +44000,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2605 Instruction:"VRNDSCALEPH Vn{K}{z},aKq,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI" + // Pos:2606 Instruction:"VRNDSCALEPH Vn{K}{z},aKq,Wn|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI" { - ND_INS_VRNDSCALEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1614, + ND_INS_VRNDSCALEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1615, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -43999,9 +44018,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2606 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" + // Pos:2607 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" { - ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1615, + ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1616, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44017,9 +44036,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2607 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" + // Pos:2608 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" { - ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1616, + ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1617, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44036,9 +44055,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2608 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI" + // Pos:2609 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI" { - ND_INS_VRNDSCALESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1617, + ND_INS_VRNDSCALESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1618, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -44055,9 +44074,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2609 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" + // Pos:2610 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" { - ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1618, + ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1619, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44074,9 +44093,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2610 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" + // Pos:2611 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" { - ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1619, + ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1620, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44091,9 +44110,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2611 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" + // Pos:2612 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" { - ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1620, + ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1621, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44108,9 +44127,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2612 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" + // Pos:2613 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" { - ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1621, + ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1622, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44126,9 +44145,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2613 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" + // Pos:2614 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" { - ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1622, + ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1623, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44144,9 +44163,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2614 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" + // Pos:2615 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" { - ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1623, + ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1624, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44161,9 +44180,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2615 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" + // Pos:2616 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" { - ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1624, + ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1625, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44178,9 +44197,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2616 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" + // Pos:2617 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" { - ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1625, + ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1626, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44196,9 +44215,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2617 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" + // Pos:2618 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" { - ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1626, + ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1627, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44214,9 +44233,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2618 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" + // Pos:2619 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" { - ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1627, + ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1628, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -44231,9 +44250,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2619 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" + // Pos:2620 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" { - ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1628, + ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1629, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -44248,9 +44267,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2620 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" + // Pos:2621 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" { - ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1629, + ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1630, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -44266,9 +44285,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2621 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" + // Pos:2622 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" { - ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1630, + ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1631, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, @@ -44284,9 +44303,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2622 Instruction:"VRSQRTPH Vn{K}{z},aKq,Wn|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM" + // Pos:2623 Instruction:"VRSQRTPH Vn{K}{z},aKq,Wn|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM" { - ND_INS_VRSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1631, + ND_INS_VRSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1632, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -44301,9 +44320,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2623 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" + // Pos:2624 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" { - ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1632, + ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1633, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44317,9 +44336,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2624 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM" + // Pos:2625 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM" { - ND_INS_VRSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1633, + ND_INS_VRSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1634, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -44335,9 +44354,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2625 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" + // Pos:2626 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" { - ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1634, + ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1635, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44352,9 +44371,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2626 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" + // Pos:2627 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" { - ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1635, + ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1636, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44370,9 +44389,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2627 Instruction:"VSCALEFPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM" + // Pos:2628 Instruction:"VSCALEFPH Vn{K}{z},aKq,Hn,Wn|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM" { - ND_INS_VSCALEFPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1636, + ND_INS_VSCALEFPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1637, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -44388,9 +44407,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2628 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" + // Pos:2629 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" { - ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1637, + ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1638, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44406,9 +44425,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2629 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" + // Pos:2630 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" { - ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1638, + ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1639, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44424,9 +44443,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2630 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM" + // Pos:2631 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM" { - ND_INS_VSCALEFSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1639, + ND_INS_VSCALEFSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1640, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -44442,9 +44461,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2631 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" + // Pos:2632 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" { - ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1640, + ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1641, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44460,9 +44479,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2632 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" + // Pos:2633 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" { - ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1641, + ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1642, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44477,9 +44496,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2633 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" + // Pos:2634 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" { - ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1642, + ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1643, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44494,9 +44513,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2634 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" + // Pos:2635 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" { - ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1643, + ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1644, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -44510,9 +44529,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2635 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" + // Pos:2636 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" { - ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1644, + ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1645, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -44526,9 +44545,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2636 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" + // Pos:2637 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" { - ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1645, + ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1646, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -44542,9 +44561,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2637 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" + // Pos:2638 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" { - ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1646, + ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1647, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -44558,9 +44577,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2638 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" + // Pos:2639 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" { - ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1647, + ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1648, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -44574,9 +44593,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2639 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" + // Pos:2640 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" { - ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1648, + ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1649, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -44590,9 +44609,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2640 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" + // Pos:2641 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" { - ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1649, + ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1650, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -44606,9 +44625,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2641 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" + // Pos:2642 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" { - ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1650, + ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1651, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, @@ -44622,9 +44641,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2642 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" + // Pos:2643 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" { - ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1651, + ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1652, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44639,9 +44658,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2643 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" + // Pos:2644 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" { - ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1652, + ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1653, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44656,9 +44675,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2644 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" + // Pos:2645 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" { - ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1653, + ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1654, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44675,9 +44694,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2645 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" + // Pos:2646 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" { - ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1654, + ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1655, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44694,9 +44713,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2646 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" + // Pos:2647 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" { - ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1655, + ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1656, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44713,9 +44732,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2647 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" + // Pos:2648 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" { - ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1656, + ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1657, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44732,9 +44751,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2648 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" + // Pos:2649 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" { - ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1657, + ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1658, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44751,9 +44770,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2649 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" + // Pos:2650 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" { - ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1657, + ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1658, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44769,9 +44788,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2650 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" + // Pos:2651 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" { - ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1658, + ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1659, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44788,9 +44807,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2651 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" + // Pos:2652 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" { - ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1658, + ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1659, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44806,9 +44825,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2652 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" + // Pos:2653 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" { - ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1659, + ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1660, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44823,9 +44842,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2653 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" + // Pos:2654 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" { - ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1659, + ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1660, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44839,9 +44858,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2654 Instruction:"VSQRTPH Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM" + // Pos:2655 Instruction:"VSQRTPH Vn{K}{z},aKq,Wn|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM" { - ND_INS_VSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1660, + ND_INS_VSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1661, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -44856,9 +44875,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2655 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" + // Pos:2656 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" { - ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1661, + ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1662, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44873,9 +44892,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2656 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" + // Pos:2657 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" { - ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1661, + ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1662, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44889,9 +44908,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2657 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" + // Pos:2658 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" { - ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1662, + ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1663, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44907,9 +44926,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2658 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" + // Pos:2659 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" { - ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1662, + ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1663, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44924,9 +44943,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2659 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM" + // Pos:2660 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM" { - ND_INS_VSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1663, + ND_INS_VSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1664, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -44942,9 +44961,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2660 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" + // Pos:2661 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" { - ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1664, + ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1665, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -44960,9 +44979,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2661 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" + // Pos:2662 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" { - ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1664, + ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1665, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -44977,9 +44996,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2662 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" + // Pos:2663 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" { - ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1665, + ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1666, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, @@ -44993,9 +45012,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2663 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" + // Pos:2664 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" { - ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1666, + ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1667, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -45011,9 +45030,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2664 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" + // Pos:2665 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" { - ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1666, + ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1667, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45028,9 +45047,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2665 Instruction:"VSUBPH Vn{K}{z},aKq,Hn,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM" + // Pos:2666 Instruction:"VSUBPH Vn{K}{z},aKq,Hn,Wn|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM" { - ND_INS_VSUBPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1667, + ND_INS_VSUBPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1668, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -45046,9 +45065,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2666 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" + // Pos:2667 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" { - ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1668, + ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1669, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -45064,9 +45083,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2667 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" + // Pos:2668 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" { - ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1668, + ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1669, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45081,9 +45100,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2668 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" + // Pos:2669 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" { - ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1669, + ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1670, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -45099,9 +45118,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2669 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" + // Pos:2670 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" { - ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1669, + ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1670, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45116,9 +45135,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2670 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM" + // Pos:2671 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM" { - ND_INS_VSUBSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1670, + ND_INS_VSUBSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1671, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -45134,9 +45153,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2671 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" + // Pos:2672 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" { - ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1671, + ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1672, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -45152,9 +45171,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2672 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" + // Pos:2673 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" { - ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1671, + ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1672, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45169,9 +45188,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2673 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" + // Pos:2674 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" { - ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1672, + ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1673, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45186,9 +45205,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2674 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" + // Pos:2675 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" { - ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1673, + ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1674, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45203,9 +45222,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2675 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" + // Pos:2676 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" { - ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1674, + ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1675, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -45220,9 +45239,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2676 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" + // Pos:2677 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" { - ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1674, + ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1675, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45237,9 +45256,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2677 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM" + // Pos:2678 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM" { - ND_INS_VUCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1675, + ND_INS_VUCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1676, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, @@ -45254,9 +45273,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2678 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" + // Pos:2679 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" { - ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1676, + ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1677, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -45271,9 +45290,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2679 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" + // Pos:2680 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" { - ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1676, + ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1677, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45288,9 +45307,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2680 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" + // Pos:2681 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" { - ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1677, + ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1678, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -45306,9 +45325,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2681 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" + // Pos:2682 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" { - ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1677, + ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1678, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45323,9 +45342,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2682 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" + // Pos:2683 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" { - ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1678, + ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -45341,9 +45360,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2683 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" + // Pos:2684 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" { - ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1678, + ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45358,9 +45377,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2684 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" + // Pos:2685 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" { - ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1679, + ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1680, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -45376,9 +45395,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2685 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" + // Pos:2686 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" { - ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1679, + ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1680, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45393,9 +45412,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2686 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" + // Pos:2687 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" { - ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1680, + ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1681, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, @@ -45411,9 +45430,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2687 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" + // Pos:2688 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" { - ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1680, + ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1681, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45428,9 +45447,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2688 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" + // Pos:2689 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" { - ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1681, + ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1682, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -45446,9 +45465,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2689 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" + // Pos:2690 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" { - ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1681, + ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1682, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45463,9 +45482,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2690 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" + // Pos:2691 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" { - ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1682, + ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1683, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, @@ -45481,9 +45500,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2691 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" + // Pos:2692 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" { - ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1682, + ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1683, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, @@ -45498,9 +45517,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2692 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" + // Pos:2693 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" { - ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1683, + ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1684, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, @@ -45513,9 +45532,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2693 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" + // Pos:2694 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" { - ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1684, + ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1685, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, @@ -45528,9 +45547,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2694 Instruction:"WAIT" Encoding:"0x9B"/"" + // Pos:2695 Instruction:"WAIT" Encoding:"0x9B"/"" { - ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1685, + ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, 0, 0, @@ -45543,9 +45562,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2695 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" + // Pos:2696 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" { - ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1686, + ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1687, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, @@ -45558,9 +45577,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2696 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/"" + // Pos:2697 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/"" { - ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1687, + ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1688, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_WBNOINVD, @@ -45573,9 +45592,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2697 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M" + // Pos:2698 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M" { - ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1688, + ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1689, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, @@ -45589,9 +45608,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2698 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M" + // Pos:2699 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M" { - ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1689, + ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1690, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, @@ -45605,9 +45624,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2699 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" + // Pos:2700 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" { - ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1690, + ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1691, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, ND_CFF_MSR, @@ -45623,9 +45642,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2700 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/"" + // Pos:2701 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/"" { - ND_INS_WRMSRLIST, ND_CAT_SYSTEM, ND_SET_MSRLIST, 1691, + ND_INS_WRMSRLIST, ND_CAT_SYSTEM, ND_SET_MSRLIST, 1692, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_MSRLIST, @@ -45640,9 +45659,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2701 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/"" + // Pos:2702 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/"" { - ND_INS_WRMSRNS, ND_CAT_SYSTEM, ND_SET_WRMSRNS, 1692, + ND_INS_WRMSRNS, ND_CAT_SYSTEM, ND_SET_WRMSRNS, 1693, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WRMSRNS, @@ -45658,9 +45677,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2702 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" + // Pos:2703 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" { - ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1693, + ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1694, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, @@ -45676,9 +45695,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2703 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M" + // Pos:2704 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M" { - ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1694, + ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1695, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45691,23 +45710,7 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2704 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" - { - ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1695, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2705 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" + // Pos:2705 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" { ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1696, 0, @@ -45723,11 +45726,11 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2706 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + // Pos:2706 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" { - ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1697, + ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1697, 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, @@ -45739,7 +45742,7 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2707 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + // Pos:2707 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" { ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1698, 0, @@ -45755,9 +45758,25 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2708 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" + // Pos:2708 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" { - ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1699, + ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1699, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2709 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" + { + ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1700, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, @@ -45772,9 +45791,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2709 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" + // Pos:2710 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" { - ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1700, + ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1701, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45789,9 +45808,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2710 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" + // Pos:2711 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" { - ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1700, + ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1701, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45806,9 +45825,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2711 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" + // Pos:2712 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" { - ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1701, + ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, @@ -45823,9 +45842,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2712 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" + // Pos:2713 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1703, ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45839,9 +45858,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2713 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" + // Pos:2714 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1703, ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45855,9 +45874,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2714 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O" + // Pos:2715 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1703, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -45871,9 +45890,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2715 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O" + // Pos:2716 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1703, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -45887,9 +45906,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2716 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O" + // Pos:2717 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1703, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -45903,9 +45922,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2717 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O" + // Pos:2718 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1703, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -45919,9 +45938,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2718 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O" + // Pos:2719 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1703, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -45935,9 +45954,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2719 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O" + // Pos:2720 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1703, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -45951,9 +45970,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2720 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O" + // Pos:2721 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1703, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -45967,9 +45986,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2721 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O" + // Pos:2722 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O" { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1702, + ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1703, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, @@ -45983,9 +46002,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2722 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/"" + // Pos:2723 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/"" { - ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1703, + ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1704, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -45998,9 +46017,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2723 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/"" + // Pos:2724 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/"" { - ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1704, + ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1705, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46013,9 +46032,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2724 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/"" + // Pos:2725 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/"" { - ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1705, + ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1706, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46028,9 +46047,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2725 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/"" + // Pos:2726 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/"" { - ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1706, + ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1707, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46043,9 +46062,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2726 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/"" + // Pos:2727 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/"" { - ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1707, + ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1708, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46058,9 +46077,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2727 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" + // Pos:2728 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" { - ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1708, + ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1709, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, @@ -46073,9 +46092,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2728 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" + // Pos:2729 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" { - ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1709, + ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1710, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -46091,9 +46110,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2729 Instruction:"XLATB" Encoding:"0xD7"/"" + // Pos:2730 Instruction:"XLATB" Encoding:"0xD7"/"" { - ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1710, + ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, @@ -46107,9 +46126,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2730 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" + // Pos:2731 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1712, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46124,9 +46143,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2731 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" + // Pos:2732 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1712, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46141,9 +46160,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2732 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" + // Pos:2733 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46158,9 +46177,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2733 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" + // Pos:2734 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46175,9 +46194,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2734 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" + // Pos:2735 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -46192,9 +46211,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2735 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" + // Pos:2736 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, @@ -46209,9 +46228,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2736 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" + // Pos:2737 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1712, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46226,9 +46245,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2737 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" + // Pos:2738 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1712, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46243,9 +46262,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2738 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" + // Pos:2739 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1712, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, @@ -46260,9 +46279,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2739 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" + // Pos:2740 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1711, + ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1712, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46277,9 +46296,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2740 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" + // Pos:2741 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" { - ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1712, + ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1713, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, @@ -46293,9 +46312,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2741 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" + // Pos:2742 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" { - ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1713, + ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1714, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, @@ -46309,9 +46328,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2742 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" + // Pos:2743 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" { - ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1714, + ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1715, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, @@ -46324,26 +46343,7 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2743 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" - { - ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1715, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2744 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" + // Pos:2744 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" { ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1716, 0, @@ -46362,12 +46362,12 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2745 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" + // Pos:2745 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" { - ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1717, + ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1717, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, + 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 0, 0, 0, @@ -46381,7 +46381,7 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2746 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" + // Pos:2746 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" { ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1718, 0, @@ -46400,26 +46400,26 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2747 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" + // Pos:2747 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" { - ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1719, + ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1719, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, + 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 0, 0, 0, 0, { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, - // Pos:2748 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" + // Pos:2748 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" { ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1720, 0, @@ -46438,12 +46438,12 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2749 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" + // Pos:2749 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" { - ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1721, + ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1721, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, + 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 0, 0, 0, @@ -46457,7 +46457,7 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2750 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" + // Pos:2750 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" { ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1722, 0, @@ -46476,12 +46476,12 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2751 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" + // Pos:2751 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" { - ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1723, + ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1723, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, + 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, 0, 0, 0, @@ -46495,7 +46495,7 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2752 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" + // Pos:2752 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" { ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1724, 0, @@ -46514,12 +46514,12 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2753 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" + // Pos:2753 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" { - ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1725, + ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1725, 0, ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, + 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 0, 0, 0, @@ -46533,7 +46533,7 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2754 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" + // Pos:2754 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" { ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1726, 0, @@ -46552,9 +46552,28 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2755 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" + // Pos:2755 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" { - ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1727, + ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1727, + 0, + ND_MOD_ANY, + 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2756 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" + { + ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1728, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, @@ -46570,9 +46589,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2756 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/"" + // Pos:2757 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/"" { - ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1728, + ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1729, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46585,9 +46604,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2757 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/"" + // Pos:2758 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/"" { - ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1729, + ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1730, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46600,9 +46619,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2758 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/"" + // Pos:2759 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/"" { - ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1730, + ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1731, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46615,9 +46634,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2759 Instruction:"XSTORE" Encoding:"0xF3 0x0F 0xA7 /0xC0"/"" + // Pos:2760 Instruction:"XSTORE" Encoding:"0xF3 0x0F 0xA7 /0xC0"/"" { - ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1730, + ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1731, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, @@ -46630,9 +46649,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2760 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" + // Pos:2761 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" { - ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1731, + ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1732, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, @@ -46645,9 +46664,9 @@ const ND_INSTRUCTION gInstructions[2762] = }, }, - // Pos:2761 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" + // Pos:2762 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" { - ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1732, + ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1733, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, diff --git a/bddisasm/include/mnemonics.h b/bddisasm/include/mnemonics.h index df99b65..582aacc 100644 --- a/bddisasm/include/mnemonics.h +++ b/bddisasm/include/mnemonics.h @@ -10,7 +10,7 @@ #ifndef MNEMONICS_H #define MNEMONICS_H -const char *gMnemonics[1733] = +const char *gMnemonics[1734] = { "AAA", "AAD", "AADD", "AAM", "AAND", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", @@ -118,101 +118,102 @@ const char *gMnemonics[1733] = "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", "RDGSBASE", "RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", "RDPMC", "RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC", "RDTSCP", "RETF", - "RETN", "RMPADJUST", "RMPUPDATE", "ROL", "ROR", "RORX", "ROUNDPD", - "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSDC", "RSLDT", "RSM", "RSQRTPS", - "RSQRTSS", "RSTORSSP", "RSTS", "SAHF", "SAL", "SALC", "SAR", - "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD", "SCASQ", "SCASW", - "SEAMCALL", "SEAMOPS", "SEAMRET", "SENDUIPI", "SERIALIZE", "SETBE", - "SETC", "SETL", "SETLE", "SETNBE", "SETNC", "SETNL", "SETNLE", - "SETNO", "SETNP", "SETNS", "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY", - "SETZ", "SFENCE", "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", - "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2", "SHL", - "SHLD", "SHLX", "SHR", "SHRD", "SHRX", "SHUFPD", "SHUFPS", "SIDT", - "SKINIT", "SLDT", "SLWPCB", "SMINT", "SMSW", "SPFLT", "SQRTPD", - "SQRTPS", "SQRTSD", "SQRTSS", "STAC", "STC", "STD", "STGI", "STI", - "STMXCSR", "STOSB", "STOSD", "STOSQ", "STOSW", "STR", "STTILECFG", - "STUI", "SUB", "SUBPD", "SUBPS", "SUBSD", "SUBSS", "SVDC", "SVLDT", - "SVTS", "SWAPGS", "SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET", - "T1MSKC", "TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", - "TDPBUUD", "TDPFP16PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDT1", - "TILERELEASE", "TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", - "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", - "UIRET", "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", - "UNPCKLPS", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", - "VADDPD", "VADDPH", "VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD", - "VADDSUBPS", "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", - "VAESIMC", "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", - "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS", "VBCSTNESH2PS", - "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", - "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", - "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", - "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", - "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", "VCMPPD", - "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD", - "VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", - "VCVTDQ2PH", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEEBF162PS", - "VCVTNEEPH2PS", "VCVTNEOBF162PS", "VCVTNEOPH2PS", "VCVTNEPS2BF16", - "VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", - "VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2PD", "VCVTPH2PS", "VCVTPH2PSX", - "VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", "VCVTPH2W", - "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2PHX", "VCVTPS2QQ", - "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PH", "VCVTQQ2PS", - "VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", "VCVTSH2SD", - "VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI", "VCVTSI2SD", "VCVTSI2SH", - "VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH", "VCVTSS2SI", "VCVTSS2USI", - "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPH2DQ", - "VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", "VCVTTPH2UW", "VCVTTPH2W", - "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", "VCVTTSD2SI", - "VCVTTSD2USI", "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2USI", - "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PH", - "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", "VCVTUSI2SS", "VCVTUW2PH", - "VCVTW2PH", "VDBPSADBW", "VDIVPD", "VDIVPH", "VDIVPS", "VDIVSD", - "VDIVSH", "VDIVSS", "VDPBF16PS", "VDPPD", "VDPPS", "VERR", "VERW", - "VEXP2PD", "VEXP2PS", "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128", - "VEXTRACTF32X4", "VEXTRACTF32X8", "VEXTRACTF64X2", "VEXTRACTF64X4", - "VEXTRACTI128", "VEXTRACTI32X4", "VEXTRACTI32X8", "VEXTRACTI64X2", - "VEXTRACTI64X4", "VEXTRACTPS", "VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH", - "VFCMULCSH", "VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", - "VFMADD132PD", "VFMADD132PH", "VFMADD132PS", "VFMADD132SD", "VFMADD132SH", - "VFMADD132SS", "VFMADD213PD", "VFMADD213PH", "VFMADD213PS", "VFMADD213SD", - "VFMADD213SH", "VFMADD213SS", "VFMADD231PD", "VFMADD231PH", "VFMADD231PS", - "VFMADD231SD", "VFMADD231SH", "VFMADD231SS", "VFMADDCPH", "VFMADDCSH", - "VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD", - "VFMADDSUB132PH", "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PH", - "VFMADDSUB213PS", "VFMADDSUB231PD", "VFMADDSUB231PH", "VFMADDSUB231PS", - "VFMADDSUBPD", "VFMADDSUBPS", "VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS", - "VFMSUB132SD", "VFMSUB132SH", "VFMSUB132SS", "VFMSUB213PD", "VFMSUB213PH", - "VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SH", "VFMSUB213SS", "VFMSUB231PD", - "VFMSUB231PH", "VFMSUB231PS", "VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS", - "VFMSUBADD132PD", "VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD", - "VFMSUBADD213PH", "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH", - "VFMSUBADD231PS", "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", - "VFMSUBSD", "VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132PD", - "VFNMADD132PH", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SH", - "VFNMADD132SS", "VFNMADD213PD", "VFNMADD213PH", "VFNMADD213PS", - "VFNMADD213SD", "VFNMADD213SH", "VFNMADD213SS", "VFNMADD231PD", - "VFNMADD231PH", "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SH", - "VFNMADD231SS", "VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", - "VFNMSUB132PD", "VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD", - "VFNMSUB132SH", "VFNMSUB132SS", "VFNMSUB213PD", "VFNMSUB213PH", - "VFNMSUB213PS", "VFNMSUB213SD", "VFNMSUB213SH", "VFNMSUB213SS", - "VFNMSUB231PD", "VFNMSUB231PH", "VFNMSUB231PS", "VFNMSUB231SD", - "VFNMSUB231SH", "VFNMSUB231SS", "VFNMSUBPD", "VFNMSUBPS", "VFNMSUBSD", - "VFNMSUBSS", "VFPCLASSPD", "VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD", - "VFPCLASSSH", "VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD", - "VFRCZSS", "VGATHERDPD", "VGATHERDPS", "VGATHERPF0DPD", "VGATHERPF0DPS", - "VGATHERPF0QPD", "VGATHERPF0QPS", "VGATHERPF1DPD", "VGATHERPF1DPS", - "VGATHERPF1QPD", "VGATHERPF1QPS", "VGATHERQPD", "VGATHERQPS", - "VGETEXPPD", "VGETEXPPH", "VGETEXPPS", "VGETEXPSD", "VGETEXPSH", - "VGETEXPSS", "VGETMANTPD", "VGETMANTPH", "VGETMANTPS", "VGETMANTSD", - "VGETMANTSH", "VGETMANTSS", "VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB", - "VGF2P8MULB", "VHADDPD", "VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128", - "VINSERTF32X4", "VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4", - "VINSERTI128", "VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2", - "VINSERTI64X4", "VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU", - "VMASKMOVPD", "VMASKMOVPS", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD", - "VMAXSH", "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT", - "VMINPD", "VMINPH", "VMINPS", "VMINSD", "VMINSH", "VMINSS", "VMLAUNCH", + "RETN", "RMPADJUST", "RMPQUERY", "RMPUPDATE", "ROL", "ROR", "RORX", + "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSDC", "RSLDT", + "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", "SAHF", "SAL", + "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD", + "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", "SENDUIPI", + "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", "SETNC", + "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", "SETO", + "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", "SHA1MSG1", + "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", + "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", "SHRX", + "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", "SMINT", + "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", "STAC", + "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", "STOSQ", + "STOSW", "STR", "STTILECFG", "STUI", "SUB", "SUBPD", "SUBPS", + "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", "SYSCALL", + "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TDCALL", "TDPBF16PS", + "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TDPFP16PS", "TEST", + "TESTUI", "TILELOADD", "TILELOADDT1", "TILERELEASE", "TILESTORED", + "TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", "UCOMISD", + "UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR", "UMWAIT", + "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "V4FMADDPS", + "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", "VADDPH", + "VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD", "VADDSUBPS", + "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC", + "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", "VANDNPS", + "VANDPD", "VANDPS", "VBCSTNEBF162PS", "VBCSTNESH2PS", "VBLENDMPD", + "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", "VBLENDVPS", + "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", "VBROADCASTF32X8", + "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", "VBROADCASTI32X2", + "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", "VBROADCASTI64X4", + "VBROADCASTSD", "VBROADCASTSS", "VCMPPD", "VCMPPH", "VCMPPS", + "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD", "VCOMISH", "VCOMISS", + "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PH", "VCVTDQ2PS", + "VCVTNE2PS2BF16", "VCVTNEEBF162PS", "VCVTNEEPH2PS", "VCVTNEOBF162PS", + "VCVTNEOPH2PS", "VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS", + "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2PD", + "VCVTPH2PS", "VCVTPH2PSX", "VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", + "VCVTPH2UW", "VCVTPH2W", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", + "VCVTPS2PHX", "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", + "VCVTQQ2PH", "VCVTQQ2PS", "VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS", + "VCVTSD2USI", "VCVTSH2SD", "VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI", + "VCVTSI2SD", "VCVTSI2SH", "VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH", + "VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", + "VCVTTPD2UQQ", "VCVTTPH2DQ", "VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", + "VCVTTPH2UW", "VCVTTPH2W", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", + "VCVTTPS2UQQ", "VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSH2SI", "VCVTTSH2USI", + "VCVTTSS2SI", "VCVTTSS2USI", "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", + "VCVTUQQ2PD", "VCVTUQQ2PH", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", + "VCVTUSI2SS", "VCVTUW2PH", "VCVTW2PH", "VDBPSADBW", "VDIVPD", + "VDIVPH", "VDIVPS", "VDIVSD", "VDIVSH", "VDIVSS", "VDPBF16PS", + "VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD", + "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", + "VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4", + "VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS", + "VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH", "VFCMULCSH", "VFIXUPIMMPD", + "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD", "VFMADD132PH", + "VFMADD132PS", "VFMADD132SD", "VFMADD132SH", "VFMADD132SS", "VFMADD213PD", + "VFMADD213PH", "VFMADD213PS", "VFMADD213SD", "VFMADD213SH", "VFMADD213SS", + "VFMADD231PD", "VFMADD231PH", "VFMADD231PS", "VFMADD231SD", "VFMADD231SH", + "VFMADD231SS", "VFMADDCPH", "VFMADDCSH", "VFMADDPD", "VFMADDPS", + "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD", "VFMADDSUB132PH", "VFMADDSUB132PS", + "VFMADDSUB213PD", "VFMADDSUB213PH", "VFMADDSUB213PS", "VFMADDSUB231PD", + "VFMADDSUB231PH", "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS", + "VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS", "VFMSUB132SD", "VFMSUB132SH", + "VFMSUB132SS", "VFMSUB213PD", "VFMSUB213PH", "VFMSUB213PS", "VFMSUB213SD", + "VFMSUB213SH", "VFMSUB213SS", "VFMSUB231PD", "VFMSUB231PH", "VFMSUB231PS", + "VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS", "VFMSUBADD132PD", + "VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD", "VFMSUBADD213PH", + "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH", "VFMSUBADD231PS", + "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD", + "VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132PD", "VFNMADD132PH", + "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SH", "VFNMADD132SS", + "VFNMADD213PD", "VFNMADD213PH", "VFNMADD213PS", "VFNMADD213SD", + "VFNMADD213SH", "VFNMADD213SS", "VFNMADD231PD", "VFNMADD231PH", + "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SH", "VFNMADD231SS", + "VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", "VFNMSUB132PD", + "VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD", "VFNMSUB132SH", + "VFNMSUB132SS", "VFNMSUB213PD", "VFNMSUB213PH", "VFNMSUB213PS", + "VFNMSUB213SD", "VFNMSUB213SH", "VFNMSUB213SS", "VFNMSUB231PD", + "VFNMSUB231PH", "VFNMSUB231PS", "VFNMSUB231SD", "VFNMSUB231SH", + "VFNMSUB231SS", "VFNMSUBPD", "VFNMSUBPS", "VFNMSUBSD", "VFNMSUBSS", + "VFPCLASSPD", "VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD", "VFPCLASSSH", + "VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD", "VFRCZSS", "VGATHERDPD", + "VGATHERDPS", "VGATHERPF0DPD", "VGATHERPF0DPS", "VGATHERPF0QPD", + "VGATHERPF0QPS", "VGATHERPF1DPD", "VGATHERPF1DPS", "VGATHERPF1QPD", + "VGATHERPF1QPS", "VGATHERQPD", "VGATHERQPS", "VGETEXPPD", "VGETEXPPH", + "VGETEXPPS", "VGETEXPSD", "VGETEXPSH", "VGETEXPSS", "VGETMANTPD", + "VGETMANTPH", "VGETMANTPS", "VGETMANTSD", "VGETMANTSH", "VGETMANTSS", + "VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB", "VGF2P8MULB", "VHADDPD", + "VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128", "VINSERTF32X4", + "VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4", "VINSERTI128", + "VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2", "VINSERTI64X4", + "VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU", "VMASKMOVPD", + "VMASKMOVPS", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD", "VMAXSH", + "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT", "VMINPD", + "VMINPH", "VMINPS", "VMINSD", "VMINSH", "VMINSS", "VMLAUNCH", "VMLOAD", "VMMCALL", "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP", "VMOVDQA", "VMOVDQA32", "VMOVDQA64", "VMOVDQU", "VMOVDQU16", "VMOVDQU32", "VMOVDQU64", "VMOVDQU8", "VMOVHLPS", "VMOVHPD", diff --git a/bddisasm/include/table_evex.h b/bddisasm/include/table_evex.h index d3fd3b6..028a340 100644 --- a/bddisasm/include/table_evex.h +++ b/bddisasm/include/table_evex.h @@ -13,7 +13,7 @@ const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_03_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1396] + (const void *)&gInstructions[1397] }; const ND_TABLE_VEX_W gEvexTable_root_02_9a_03_mem_02_w = @@ -48,13 +48,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9a_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1680] + (const void *)&gInstructions[1681] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1683] + (const void *)&gInstructions[1684] }; const ND_TABLE_VEX_W gEvexTable_root_02_9a_01_w = @@ -80,7 +80,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_03_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1397] + (const void *)&gInstructions[1398] }; const ND_TABLE_VEX_W gEvexTable_root_02_9b_03_mem_w = @@ -104,13 +104,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9b_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1685] + (const void *)&gInstructions[1686] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1688] + (const void *)&gInstructions[1689] }; const ND_TABLE_VEX_W gEvexTable_root_02_9b_01_w = @@ -136,7 +136,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_03_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1398] + (const void *)&gInstructions[1399] }; const ND_TABLE_VEX_W gEvexTable_root_02_aa_03_mem_02_w = @@ -171,13 +171,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_aa_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1690] + (const void *)&gInstructions[1691] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1693] + (const void *)&gInstructions[1694] }; const ND_TABLE_VEX_W gEvexTable_root_02_aa_01_w = @@ -203,7 +203,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_aa_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_03_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1399] + (const void *)&gInstructions[1400] }; const ND_TABLE_VEX_W gEvexTable_root_02_ab_03_mem_w = @@ -227,13 +227,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_ab_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1695] + (const void *)&gInstructions[1696] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1698] + (const void *)&gInstructions[1699] }; const ND_TABLE_VEX_W gEvexTable_root_02_ab_01_w = @@ -259,7 +259,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ab_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_de_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1412] + (const void *)&gInstructions[1413] }; const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp = @@ -276,7 +276,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_df_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1414] + (const void *)&gInstructions[1415] }; const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp = @@ -293,7 +293,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_dc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1416] + (const void *)&gInstructions[1417] }; const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp = @@ -310,7 +310,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_dd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1418] + (const void *)&gInstructions[1419] }; const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp = @@ -327,13 +327,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1434] + (const void *)&gInstructions[1435] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1435] + (const void *)&gInstructions[1436] }; const ND_TABLE_VEX_W gEvexTable_root_02_65_01_w = @@ -359,13 +359,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_65_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1441] + (const void *)&gInstructions[1442] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1452] + (const void *)&gInstructions[1453] }; const ND_TABLE_VEX_W gEvexTable_root_02_19_01_w = @@ -391,13 +391,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_19_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1442] + (const void *)&gInstructions[1443] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1444] + (const void *)&gInstructions[1445] }; const ND_TABLE_VEX_W gEvexTable_root_02_1a_01_mem_w = @@ -432,13 +432,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1443] + (const void *)&gInstructions[1444] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1445] + (const void *)&gInstructions[1446] }; const ND_TABLE_VEX_W gEvexTable_root_02_1b_01_mem_02_w = @@ -484,13 +484,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1447] + (const void *)&gInstructions[1448] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2106] + (const void *)&gInstructions[2107] }; const ND_TABLE_VEX_W gEvexTable_root_02_59_01_w = @@ -516,13 +516,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_59_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1448] + (const void *)&gInstructions[1449] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1450] + (const void *)&gInstructions[1451] }; const ND_TABLE_VEX_W gEvexTable_root_02_5a_01_mem_w = @@ -557,13 +557,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1449] + (const void *)&gInstructions[1450] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1451] + (const void *)&gInstructions[1452] }; const ND_TABLE_VEX_W gEvexTable_root_02_5b_01_mem_02_w = @@ -609,7 +609,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_18_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1454] + (const void *)&gInstructions[1455] }; const ND_TABLE_VEX_W gEvexTable_root_02_18_01_w = @@ -635,13 +635,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_18_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1471] + (const void *)&gInstructions[1472] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1472] + (const void *)&gInstructions[1473] }; const ND_TABLE_VEX_W gEvexTable_root_02_8a_01_w = @@ -667,7 +667,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1479] + (const void *)&gInstructions[1480] }; const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w = @@ -682,7 +682,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1484] + (const void *)&gInstructions[1485] }; const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w = @@ -697,7 +697,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2470] + (const void *)&gInstructions[2471] }; const ND_TABLE_VEX_W gEvexTable_root_02_72_01_w = @@ -723,7 +723,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_72_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1497] + (const void *)&gInstructions[1498] }; const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w = @@ -738,7 +738,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2368] + (const void *)&gInstructions[2369] }; const ND_TABLE_VEX_W gEvexTable_root_02_13_02_w = @@ -764,7 +764,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_13_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1590] + (const void *)&gInstructions[1591] }; const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w = @@ -779,7 +779,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_03_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2046] + (const void *)&gInstructions[2047] }; const ND_TABLE_VEX_W gEvexTable_root_02_52_03_mem_02_w = @@ -814,7 +814,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_52_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2168] + (const void *)&gInstructions[2169] }; const ND_TABLE_VEX_W gEvexTable_root_02_52_01_w = @@ -840,13 +840,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_52_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1595] + (const void *)&gInstructions[1596] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1596] + (const void *)&gInstructions[1597] }; const ND_TABLE_VEX_W gEvexTable_root_02_c8_01_02_w = @@ -883,13 +883,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1597] + (const void *)&gInstructions[1598] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1598] + (const void *)&gInstructions[1599] }; const ND_TABLE_VEX_W gEvexTable_root_02_88_01_w = @@ -915,13 +915,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_88_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1621] + (const void *)&gInstructions[1622] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1624] + (const void *)&gInstructions[1625] }; const ND_TABLE_VEX_W gEvexTable_root_02_98_01_w = @@ -947,13 +947,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_98_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1626] + (const void *)&gInstructions[1627] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1629] + (const void *)&gInstructions[1630] }; const ND_TABLE_VEX_W gEvexTable_root_02_99_01_w = @@ -979,13 +979,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_99_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1631] + (const void *)&gInstructions[1632] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1634] + (const void *)&gInstructions[1635] }; const ND_TABLE_VEX_W gEvexTable_root_02_a8_01_w = @@ -1011,13 +1011,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1636] + (const void *)&gInstructions[1637] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1639] + (const void *)&gInstructions[1640] }; const ND_TABLE_VEX_W gEvexTable_root_02_a9_01_w = @@ -1043,13 +1043,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1641] + (const void *)&gInstructions[1642] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1644] + (const void *)&gInstructions[1645] }; const ND_TABLE_VEX_W gEvexTable_root_02_b8_01_w = @@ -1075,13 +1075,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1646] + (const void *)&gInstructions[1647] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1649] + (const void *)&gInstructions[1650] }; const ND_TABLE_VEX_W gEvexTable_root_02_b9_01_w = @@ -1107,13 +1107,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1661] + (const void *)&gInstructions[1662] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1664] + (const void *)&gInstructions[1665] }; const ND_TABLE_VEX_W gEvexTable_root_02_96_01_w = @@ -1139,13 +1139,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_96_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1666] + (const void *)&gInstructions[1667] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1669] + (const void *)&gInstructions[1670] }; const ND_TABLE_VEX_W gEvexTable_root_02_a6_01_w = @@ -1171,13 +1171,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1671] + (const void *)&gInstructions[1672] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1674] + (const void *)&gInstructions[1675] }; const ND_TABLE_VEX_W gEvexTable_root_02_b6_01_w = @@ -1203,13 +1203,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1700] + (const void *)&gInstructions[1701] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1703] + (const void *)&gInstructions[1704] }; const ND_TABLE_VEX_W gEvexTable_root_02_ba_01_w = @@ -1235,13 +1235,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ba_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1705] + (const void *)&gInstructions[1706] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1708] + (const void *)&gInstructions[1709] }; const ND_TABLE_VEX_W gEvexTable_root_02_bb_01_w = @@ -1267,13 +1267,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1710] + (const void *)&gInstructions[1711] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1713] + (const void *)&gInstructions[1714] }; const ND_TABLE_VEX_W gEvexTable_root_02_97_01_w = @@ -1299,13 +1299,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_97_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1715] + (const void *)&gInstructions[1716] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1718] + (const void *)&gInstructions[1719] }; const ND_TABLE_VEX_W gEvexTable_root_02_a7_01_w = @@ -1331,13 +1331,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1720] + (const void *)&gInstructions[1721] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1723] + (const void *)&gInstructions[1724] }; const ND_TABLE_VEX_W gEvexTable_root_02_b7_01_w = @@ -1363,13 +1363,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1739] + (const void *)&gInstructions[1740] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1742] + (const void *)&gInstructions[1743] }; const ND_TABLE_VEX_W gEvexTable_root_02_9c_01_w = @@ -1395,13 +1395,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1744] + (const void *)&gInstructions[1745] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1747] + (const void *)&gInstructions[1748] }; const ND_TABLE_VEX_W gEvexTable_root_02_9d_01_w = @@ -1427,13 +1427,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1749] + (const void *)&gInstructions[1750] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1752] + (const void *)&gInstructions[1753] }; const ND_TABLE_VEX_W gEvexTable_root_02_ac_01_w = @@ -1459,13 +1459,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ac_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1754] + (const void *)&gInstructions[1755] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1757] + (const void *)&gInstructions[1758] }; const ND_TABLE_VEX_W gEvexTable_root_02_ad_01_w = @@ -1491,13 +1491,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ad_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1759] + (const void *)&gInstructions[1760] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1762] + (const void *)&gInstructions[1763] }; const ND_TABLE_VEX_W gEvexTable_root_02_bc_01_w = @@ -1523,13 +1523,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1764] + (const void *)&gInstructions[1765] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1767] + (const void *)&gInstructions[1768] }; const ND_TABLE_VEX_W gEvexTable_root_02_bd_01_w = @@ -1555,13 +1555,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1777] + (const void *)&gInstructions[1778] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1780] + (const void *)&gInstructions[1781] }; const ND_TABLE_VEX_W gEvexTable_root_02_9e_01_w = @@ -1587,13 +1587,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1782] + (const void *)&gInstructions[1783] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1785] + (const void *)&gInstructions[1786] }; const ND_TABLE_VEX_W gEvexTable_root_02_9f_01_w = @@ -1619,13 +1619,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1787] + (const void *)&gInstructions[1788] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1790] + (const void *)&gInstructions[1791] }; const ND_TABLE_VEX_W gEvexTable_root_02_ae_01_w = @@ -1651,13 +1651,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ae_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1792] + (const void *)&gInstructions[1793] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1795] + (const void *)&gInstructions[1796] }; const ND_TABLE_VEX_W gEvexTable_root_02_af_01_w = @@ -1683,13 +1683,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_af_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1797] + (const void *)&gInstructions[1798] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1800] + (const void *)&gInstructions[1801] }; const ND_TABLE_VEX_W gEvexTable_root_02_be_01_w = @@ -1715,13 +1715,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_be_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1802] + (const void *)&gInstructions[1803] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1805] + (const void *)&gInstructions[1806] }; const ND_TABLE_VEX_W gEvexTable_root_02_bf_01_w = @@ -1747,13 +1747,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bf_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1825] + (const void *)&gInstructions[1826] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1827] + (const void *)&gInstructions[1828] }; const ND_TABLE_VEX_W gEvexTable_root_02_92_01_mem_w = @@ -1788,13 +1788,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_92_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1829] + (const void *)&gInstructions[1830] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1830] + (const void *)&gInstructions[1831] }; const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_01_02_w = @@ -1820,13 +1820,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_01_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1833] + (const void *)&gInstructions[1834] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1834] + (const void *)&gInstructions[1835] }; const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_02_02_w = @@ -1852,13 +1852,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_02_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2634] + (const void *)&gInstructions[2635] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2635] + (const void *)&gInstructions[2636] }; const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_05_02_w = @@ -1884,13 +1884,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_05_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2638] + (const void *)&gInstructions[2639] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2639] + (const void *)&gInstructions[2640] }; const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_06_02_w = @@ -1951,13 +1951,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1831] + (const void *)&gInstructions[1832] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1832] + (const void *)&gInstructions[1833] }; const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_01_02_w = @@ -1983,13 +1983,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_01_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1835] + (const void *)&gInstructions[1836] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1836] + (const void *)&gInstructions[1837] }; const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_02_02_w = @@ -2015,13 +2015,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_02_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2636] + (const void *)&gInstructions[2637] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2637] + (const void *)&gInstructions[2638] }; const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_05_02_w = @@ -2047,13 +2047,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_05_l = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2640] + (const void *)&gInstructions[2641] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2641] + (const void *)&gInstructions[2642] }; const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_06_02_w = @@ -2114,13 +2114,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1837] + (const void *)&gInstructions[1838] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1839] + (const void *)&gInstructions[1840] }; const ND_TABLE_VEX_W gEvexTable_root_02_93_01_mem_w = @@ -2155,13 +2155,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_93_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1841] + (const void *)&gInstructions[1842] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1843] + (const void *)&gInstructions[1844] }; const ND_TABLE_VEX_W gEvexTable_root_02_42_01_w = @@ -2187,13 +2187,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_42_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1844] + (const void *)&gInstructions[1845] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1846] + (const void *)&gInstructions[1847] }; const ND_TABLE_VEX_W gEvexTable_root_02_43_01_w = @@ -2219,7 +2219,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_43_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_cf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1857] + (const void *)&gInstructions[1858] }; const ND_TABLE_VEX_W gEvexTable_root_02_cf_01_w = @@ -2245,7 +2245,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cf_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1970] + (const void *)&gInstructions[1971] }; const ND_TABLE_VEX_W gEvexTable_root_02_2a_01_mem_w = @@ -2269,7 +2269,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2104] + (const void *)&gInstructions[2105] }; const ND_TABLE_VEX_W gEvexTable_root_02_2a_02_reg_w = @@ -2304,13 +2304,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2044] + (const void *)&gInstructions[2045] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2045] + (const void *)&gInstructions[2046] }; const ND_TABLE_VEX_W gEvexTable_root_02_68_03_w = @@ -2336,7 +2336,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_68_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_03_mem_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2047] + (const void *)&gInstructions[2048] }; const ND_TABLE_VEX_W gEvexTable_root_02_53_03_mem_02_w = @@ -2371,7 +2371,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_53_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2170] + (const void *)&gInstructions[2171] }; const ND_TABLE_VEX_W gEvexTable_root_02_53_01_w = @@ -2397,7 +2397,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_53_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2048] + (const void *)&gInstructions[2049] }; const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp = @@ -2414,7 +2414,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2050] + (const void *)&gInstructions[2051] }; const ND_TABLE_VEX_W gEvexTable_root_02_1e_01_w = @@ -2440,7 +2440,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2052] + (const void *)&gInstructions[2053] }; const ND_TABLE_VEX_W gEvexTable_root_02_1f_01_w = @@ -2466,7 +2466,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_1d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2053] + (const void *)&gInstructions[2054] }; const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp = @@ -2483,7 +2483,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2059] + (const void *)&gInstructions[2060] }; const ND_TABLE_VEX_W gEvexTable_root_02_2b_01_w = @@ -2509,13 +2509,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2092] + (const void *)&gInstructions[2093] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2095] + (const void *)&gInstructions[2096] }; const ND_TABLE_VEX_W gEvexTable_root_02_66_01_w = @@ -2541,13 +2541,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_66_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2093] + (const void *)&gInstructions[2094] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2094] + (const void *)&gInstructions[2095] }; const ND_TABLE_VEX_W gEvexTable_root_02_64_01_w = @@ -2573,7 +2573,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_64_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2098] + (const void *)&gInstructions[2099] }; const ND_TABLE_VEX_W gEvexTable_root_02_78_01_w = @@ -2599,7 +2599,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_78_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7a_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2099] + (const void *)&gInstructions[2100] }; const ND_TABLE_VEX_W gEvexTable_root_02_7a_01_reg_w = @@ -2634,7 +2634,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_58_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2101] + (const void *)&gInstructions[2102] }; const ND_TABLE_VEX_W gEvexTable_root_02_58_01_w = @@ -2660,13 +2660,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_58_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2102] + (const void *)&gInstructions[2103] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2107] + (const void *)&gInstructions[2108] }; const ND_TABLE_VEX_W gEvexTable_root_02_7c_01_reg_wi = @@ -2701,7 +2701,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2105] + (const void *)&gInstructions[2106] }; const ND_TABLE_VEX_W gEvexTable_root_02_3a_02_reg_w = @@ -2725,7 +2725,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_3a_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2328] + (const void *)&gInstructions[2329] }; const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp = @@ -2742,7 +2742,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2109] + (const void *)&gInstructions[2110] }; const ND_TABLE_VEX_W gEvexTable_root_02_79_01_w = @@ -2768,7 +2768,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_79_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7b_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2110] + (const void *)&gInstructions[2111] }; const ND_TABLE_VEX_W gEvexTable_root_02_7b_01_reg_w = @@ -2803,7 +2803,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2122] + (const void *)&gInstructions[2123] }; const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w = @@ -2818,13 +2818,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2330] + (const void *)&gInstructions[2331] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2373] + (const void *)&gInstructions[2374] }; const ND_TABLE_VEX_W gEvexTable_root_02_29_02_reg_w = @@ -2859,7 +2859,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_29_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_37_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2132] + (const void *)&gInstructions[2133] }; const ND_TABLE_VEX_W gEvexTable_root_02_37_01_w = @@ -2885,13 +2885,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_37_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2146] + (const void *)&gInstructions[2147] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2149] + (const void *)&gInstructions[2150] }; const ND_TABLE_VEX_W gEvexTable_root_02_63_01_w = @@ -2917,13 +2917,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_63_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2147] + (const void *)&gInstructions[2148] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2148] + (const void *)&gInstructions[2149] }; const ND_TABLE_VEX_W gEvexTable_root_02_8b_01_w = @@ -2949,13 +2949,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2156] + (const void *)&gInstructions[2157] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2157] + (const void *)&gInstructions[2158] }; const ND_TABLE_VEX_W gEvexTable_root_02_c4_01_w = @@ -2981,7 +2981,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_50_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2162] + (const void *)&gInstructions[2163] }; const ND_TABLE_VEX_W gEvexTable_root_02_50_01_w = @@ -3007,7 +3007,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_50_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_51_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2164] + (const void *)&gInstructions[2165] }; const ND_TABLE_VEX_W gEvexTable_root_02_51_01_w = @@ -3033,13 +3033,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_51_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2174] + (const void *)&gInstructions[2175] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2211] + (const void *)&gInstructions[2212] }; const ND_TABLE_VEX_W gEvexTable_root_02_8d_01_w = @@ -3065,13 +3065,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2175] + (const void *)&gInstructions[2176] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2202] + (const void *)&gInstructions[2203] }; const ND_TABLE_VEX_W gEvexTable_root_02_36_01_w = @@ -3097,13 +3097,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_36_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2177] + (const void *)&gInstructions[2178] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2182] + (const void *)&gInstructions[2183] }; const ND_TABLE_VEX_W gEvexTable_root_02_75_01_w = @@ -3129,13 +3129,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_75_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2178] + (const void *)&gInstructions[2179] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2181] + (const void *)&gInstructions[2182] }; const ND_TABLE_VEX_W gEvexTable_root_02_76_01_w = @@ -3161,13 +3161,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_76_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2179] + (const void *)&gInstructions[2180] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2180] + (const void *)&gInstructions[2181] }; const ND_TABLE_VEX_W gEvexTable_root_02_77_01_w = @@ -3193,7 +3193,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_77_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_0d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2187] + (const void *)&gInstructions[2188] }; const ND_TABLE_VEX_W gEvexTable_root_02_0d_01_w = @@ -3219,7 +3219,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_0c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2191] + (const void *)&gInstructions[2192] }; const ND_TABLE_VEX_W gEvexTable_root_02_0c_01_w = @@ -3245,13 +3245,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2195] + (const void *)&gInstructions[2196] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2199] + (const void *)&gInstructions[2200] }; const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w = @@ -3266,13 +3266,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2196] + (const void *)&gInstructions[2197] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2200] + (const void *)&gInstructions[2201] }; const ND_TABLE_VEX_W gEvexTable_root_02_16_01_02_w = @@ -3309,13 +3309,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_16_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2205] + (const void *)&gInstructions[2206] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2210] + (const void *)&gInstructions[2211] }; const ND_TABLE_VEX_W gEvexTable_root_02_7d_01_w = @@ -3341,13 +3341,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2206] + (const void *)&gInstructions[2207] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2209] + (const void *)&gInstructions[2210] }; const ND_TABLE_VEX_W gEvexTable_root_02_7e_01_w = @@ -3373,13 +3373,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2207] + (const void *)&gInstructions[2208] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2208] + (const void *)&gInstructions[2209] }; const ND_TABLE_VEX_W gEvexTable_root_02_7f_01_w = @@ -3405,13 +3405,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2212] + (const void *)&gInstructions[2213] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2215] + (const void *)&gInstructions[2216] }; const ND_TABLE_VEX_W gEvexTable_root_02_62_01_w = @@ -3437,13 +3437,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_62_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2213] + (const void *)&gInstructions[2214] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2214] + (const void *)&gInstructions[2215] }; const ND_TABLE_VEX_W gEvexTable_root_02_89_01_w = @@ -3469,13 +3469,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_89_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2234] + (const void *)&gInstructions[2235] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2236] + (const void *)&gInstructions[2237] }; const ND_TABLE_VEX_W gEvexTable_root_02_90_01_mem_w = @@ -3510,13 +3510,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_90_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2238] + (const void *)&gInstructions[2239] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2240] + (const void *)&gInstructions[2241] }; const ND_TABLE_VEX_W gEvexTable_root_02_91_01_mem_w = @@ -3551,13 +3551,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_91_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2276] + (const void *)&gInstructions[2277] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2277] + (const void *)&gInstructions[2278] }; const ND_TABLE_VEX_W gEvexTable_root_02_44_01_w = @@ -3583,7 +3583,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_44_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b5_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2290] + (const void *)&gInstructions[2291] }; const ND_TABLE_VEX_W gEvexTable_root_02_b5_01_w = @@ -3609,7 +3609,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_b4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2292] + (const void *)&gInstructions[2293] }; const ND_TABLE_VEX_W gEvexTable_root_02_b4_01_w = @@ -3635,7 +3635,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2294] + (const void *)&gInstructions[2295] }; const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp = @@ -3652,7 +3652,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2302] + (const void *)&gInstructions[2303] }; const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp = @@ -3669,13 +3669,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2304] + (const void *)&gInstructions[2305] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2306] + (const void *)&gInstructions[2307] }; const ND_TABLE_VEX_W gEvexTable_root_02_3d_01_w = @@ -3701,13 +3701,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2311] + (const void *)&gInstructions[2312] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2313] + (const void *)&gInstructions[2314] }; const ND_TABLE_VEX_W gEvexTable_root_02_3f_01_w = @@ -3733,7 +3733,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2314] + (const void *)&gInstructions[2315] }; const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp = @@ -3750,19 +3750,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2316] + (const void *)&gInstructions[2317] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2335] + (const void *)&gInstructions[2336] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2336] + (const void *)&gInstructions[2337] }; const ND_TABLE_VEX_W gEvexTable_root_02_38_02_reg_w = @@ -3797,13 +3797,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_38_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2318] + (const void *)&gInstructions[2319] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2320] + (const void *)&gInstructions[2321] }; const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w = @@ -3818,13 +3818,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2331] + (const void *)&gInstructions[2332] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2339] + (const void *)&gInstructions[2340] }; const ND_TABLE_VEX_W gEvexTable_root_02_39_02_reg_w = @@ -3859,13 +3859,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_39_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2325] + (const void *)&gInstructions[2326] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2327] + (const void *)&gInstructions[2328] }; const ND_TABLE_VEX_W gEvexTable_root_02_3b_01_w = @@ -3891,7 +3891,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2332] + (const void *)&gInstructions[2333] }; const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w = @@ -3906,7 +3906,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2375] + (const void *)&gInstructions[2376] }; const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp = @@ -3923,7 +3923,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2333] + (const void *)&gInstructions[2334] }; const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w = @@ -3938,7 +3938,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2387] + (const void *)&gInstructions[2388] }; const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp = @@ -3955,13 +3955,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2334] + (const void *)&gInstructions[2335] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2337] + (const void *)&gInstructions[2338] }; const ND_TABLE_VEX_W gEvexTable_root_02_28_02_reg_w = @@ -3985,7 +3985,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_28_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2393] + (const void *)&gInstructions[2394] }; const ND_TABLE_VEX_W gEvexTable_root_02_28_01_w = @@ -4011,7 +4011,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_28_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2340] + (const void *)&gInstructions[2341] }; const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w = @@ -4026,7 +4026,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2378] + (const void *)&gInstructions[2379] }; const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp = @@ -4043,7 +4043,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2341] + (const void *)&gInstructions[2342] }; const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w = @@ -4058,7 +4058,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2384] + (const void *)&gInstructions[2385] }; const ND_TABLE_VEX_W gEvexTable_root_02_35_01_w = @@ -4084,7 +4084,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_35_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2342] + (const void *)&gInstructions[2343] }; const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w = @@ -4099,7 +4099,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2390] + (const void *)&gInstructions[2391] }; const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp = @@ -4116,7 +4116,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2343] + (const void *)&gInstructions[2344] }; const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w = @@ -4131,7 +4131,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2349] + (const void *)&gInstructions[2350] }; const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp = @@ -4148,7 +4148,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2344] + (const void *)&gInstructions[2345] }; const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w = @@ -4163,7 +4163,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2361] + (const void *)&gInstructions[2362] }; const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp = @@ -4180,7 +4180,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2345] + (const void *)&gInstructions[2346] }; const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w = @@ -4195,7 +4195,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2352] + (const void *)&gInstructions[2353] }; const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp = @@ -4212,7 +4212,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2346] + (const void *)&gInstructions[2347] }; const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w = @@ -4227,7 +4227,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2358] + (const void *)&gInstructions[2359] }; const ND_TABLE_VEX_W gEvexTable_root_02_25_01_w = @@ -4253,7 +4253,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_25_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2347] + (const void *)&gInstructions[2348] }; const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w = @@ -4268,7 +4268,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2364] + (const void *)&gInstructions[2365] }; const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp = @@ -4285,7 +4285,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2348] + (const void *)&gInstructions[2349] }; const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w = @@ -4300,7 +4300,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2355] + (const void *)&gInstructions[2356] }; const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp = @@ -4317,7 +4317,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2367] + (const void *)&gInstructions[2368] }; const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w = @@ -4332,7 +4332,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2512] + (const void *)&gInstructions[2513] }; const ND_TABLE_VEX_W gEvexTable_root_02_11_01_w = @@ -4358,7 +4358,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_11_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2369] + (const void *)&gInstructions[2370] }; const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w = @@ -4373,7 +4373,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2498] + (const void *)&gInstructions[2499] }; const ND_TABLE_VEX_W gEvexTable_root_02_12_01_w = @@ -4399,7 +4399,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_12_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2370] + (const void *)&gInstructions[2371] }; const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w = @@ -4414,13 +4414,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2420] + (const void *)&gInstructions[2421] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2421] + (const void *)&gInstructions[2422] }; const ND_TABLE_VEX_W gEvexTable_root_02_15_01_w = @@ -4446,7 +4446,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_15_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2371] + (const void *)&gInstructions[2372] }; const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w = @@ -4461,13 +4461,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2424] + (const void *)&gInstructions[2425] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2425] + (const void *)&gInstructions[2426] }; const ND_TABLE_VEX_W gEvexTable_root_02_14_01_w = @@ -4493,7 +4493,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_14_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2372] + (const void *)&gInstructions[2373] }; const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w = @@ -4508,7 +4508,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2531] + (const void *)&gInstructions[2532] }; const ND_TABLE_VEX_W gEvexTable_root_02_10_01_w = @@ -4534,7 +4534,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_10_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2374] + (const void *)&gInstructions[2375] }; const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w = @@ -4549,7 +4549,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2381] + (const void *)&gInstructions[2382] }; const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp = @@ -4566,7 +4566,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_0b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2395] + (const void *)&gInstructions[2396] }; const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp = @@ -4583,13 +4583,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2401] + (const void *)&gInstructions[2402] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2403] + (const void *)&gInstructions[2404] }; const ND_TABLE_VEX_W gEvexTable_root_02_40_01_w = @@ -4615,7 +4615,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_40_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_83_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2406] + (const void *)&gInstructions[2407] }; const ND_TABLE_VEX_W gEvexTable_root_02_83_01_w = @@ -4641,13 +4641,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_83_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2409] + (const void *)&gInstructions[2410] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2412] + (const void *)&gInstructions[2413] }; const ND_TABLE_VEX_W gEvexTable_root_02_54_01_w = @@ -4673,13 +4673,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_54_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2410] + (const void *)&gInstructions[2411] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2411] + (const void *)&gInstructions[2412] }; const ND_TABLE_VEX_W gEvexTable_root_02_55_01_w = @@ -4705,13 +4705,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_55_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2440] + (const void *)&gInstructions[2441] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2441] + (const void *)&gInstructions[2442] }; const ND_TABLE_VEX_W gEvexTable_root_02_a0_01_mem_w = @@ -4746,13 +4746,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a0_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2442] + (const void *)&gInstructions[2443] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2443] + (const void *)&gInstructions[2444] }; const ND_TABLE_VEX_W gEvexTable_root_02_a1_01_mem_w = @@ -4787,13 +4787,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a1_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2459] + (const void *)&gInstructions[2460] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2460] + (const void *)&gInstructions[2461] }; const ND_TABLE_VEX_W gEvexTable_root_02_71_01_w = @@ -4819,7 +4819,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_71_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_70_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2461] + (const void *)&gInstructions[2462] }; const ND_TABLE_VEX_W gEvexTable_root_02_70_01_w = @@ -4845,13 +4845,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_70_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2468] + (const void *)&gInstructions[2469] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2469] + (const void *)&gInstructions[2470] }; const ND_TABLE_VEX_W gEvexTable_root_02_73_01_w = @@ -4877,7 +4877,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_73_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2472] + (const void *)&gInstructions[2473] }; const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp = @@ -4894,7 +4894,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_8f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2474] + (const void *)&gInstructions[2475] }; const ND_TABLE_VEX_W gEvexTable_root_02_8f_01_w = @@ -4920,13 +4920,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2494] + (const void *)&gInstructions[2495] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2496] + (const void *)&gInstructions[2497] }; const ND_TABLE_VEX_W gEvexTable_root_02_47_01_w = @@ -4952,13 +4952,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_47_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2509] + (const void *)&gInstructions[2510] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2511] + (const void *)&gInstructions[2512] }; const ND_TABLE_VEX_W gEvexTable_root_02_46_01_w = @@ -4984,13 +4984,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_46_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2527] + (const void *)&gInstructions[2528] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2529] + (const void *)&gInstructions[2530] }; const ND_TABLE_VEX_W gEvexTable_root_02_45_01_w = @@ -5016,13 +5016,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_45_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2555] + (const void *)&gInstructions[2556] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2558] + (const void *)&gInstructions[2559] }; const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w = @@ -5037,13 +5037,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2559] + (const void *)&gInstructions[2560] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2562] + (const void *)&gInstructions[2563] }; const ND_TABLE_VEX_W gEvexTable_root_02_26_02_w = @@ -5069,13 +5069,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_26_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2556] + (const void *)&gInstructions[2557] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2557] + (const void *)&gInstructions[2558] }; const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w = @@ -5090,13 +5090,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2560] + (const void *)&gInstructions[2561] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2561] + (const void *)&gInstructions[2562] }; const ND_TABLE_VEX_W gEvexTable_root_02_27_02_w = @@ -5122,13 +5122,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_27_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2586] + (const void *)&gInstructions[2587] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2587] + (const void *)&gInstructions[2588] }; const ND_TABLE_VEX_W gEvexTable_root_02_4c_01_w = @@ -5154,13 +5154,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2588] + (const void *)&gInstructions[2589] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2589] + (const void *)&gInstructions[2590] }; const ND_TABLE_VEX_W gEvexTable_root_02_4d_01_w = @@ -5186,13 +5186,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2590] + (const void *)&gInstructions[2591] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2591] + (const void *)&gInstructions[2592] }; const ND_TABLE_VEX_W gEvexTable_root_02_ca_01_02_w = @@ -5229,13 +5229,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ca_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2592] + (const void *)&gInstructions[2593] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2593] + (const void *)&gInstructions[2594] }; const ND_TABLE_VEX_W gEvexTable_root_02_cb_01_w = @@ -5261,13 +5261,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2614] + (const void *)&gInstructions[2615] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2615] + (const void *)&gInstructions[2616] }; const ND_TABLE_VEX_W gEvexTable_root_02_4e_01_w = @@ -5293,13 +5293,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2616] + (const void *)&gInstructions[2617] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2617] + (const void *)&gInstructions[2618] }; const ND_TABLE_VEX_W gEvexTable_root_02_4f_01_w = @@ -5325,13 +5325,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2618] + (const void *)&gInstructions[2619] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2619] + (const void *)&gInstructions[2620] }; const ND_TABLE_VEX_W gEvexTable_root_02_cc_01_02_w = @@ -5368,13 +5368,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2620] + (const void *)&gInstructions[2621] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2621] + (const void *)&gInstructions[2622] }; const ND_TABLE_VEX_W gEvexTable_root_02_cd_01_w = @@ -5400,13 +5400,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2626] + (const void *)&gInstructions[2627] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2628] + (const void *)&gInstructions[2629] }; const ND_TABLE_VEX_W gEvexTable_root_02_2c_01_w = @@ -5432,13 +5432,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2629] + (const void *)&gInstructions[2630] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2631] + (const void *)&gInstructions[2632] }; const ND_TABLE_VEX_W gEvexTable_root_02_2d_01_w = @@ -5464,13 +5464,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2632] + (const void *)&gInstructions[2633] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2633] + (const void *)&gInstructions[2634] }; const ND_TABLE_VEX_W gEvexTable_root_02_a2_01_mem_w = @@ -5505,13 +5505,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2642] + (const void *)&gInstructions[2643] }; const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2643] + (const void *)&gInstructions[2644] }; const ND_TABLE_VEX_W gEvexTable_root_02_a3_01_mem_w = @@ -5809,7 +5809,7 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode = const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1400] + (const void *)&gInstructions[1401] }; const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w = @@ -5824,7 +5824,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1403] + (const void *)&gInstructions[1404] }; const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w = @@ -5839,7 +5839,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1405] + (const void *)&gInstructions[1406] }; const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w = @@ -5854,7 +5854,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1408] + (const void *)&gInstructions[1409] }; const ND_TABLE_VEX_W gEvexTable_root_01_58_02_w = @@ -5880,7 +5880,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_58_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1424] + (const void *)&gInstructions[1425] }; const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w = @@ -5895,7 +5895,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1426] + (const void *)&gInstructions[1427] }; const ND_TABLE_VEX_W gEvexTable_root_01_55_00_w = @@ -5921,7 +5921,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_55_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1428] + (const void *)&gInstructions[1429] }; const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w = @@ -5936,7 +5936,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1430] + (const void *)&gInstructions[1431] }; const ND_TABLE_VEX_W gEvexTable_root_01_54_00_w = @@ -5962,7 +5962,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_54_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1456] + (const void *)&gInstructions[1457] }; const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w = @@ -5977,7 +5977,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1459] + (const void *)&gInstructions[1460] }; const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w = @@ -5992,7 +5992,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1461] + (const void *)&gInstructions[1462] }; const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w = @@ -6007,7 +6007,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1464] + (const void *)&gInstructions[1465] }; const ND_TABLE_VEX_W gEvexTable_root_01_c2_02_w = @@ -6033,7 +6033,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1466] + (const void *)&gInstructions[1467] }; const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w = @@ -6048,7 +6048,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1469] + (const void *)&gInstructions[1470] }; const ND_TABLE_VEX_W gEvexTable_root_01_2f_00_w = @@ -6074,13 +6074,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1473] + (const void *)&gInstructions[1474] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1518] + (const void *)&gInstructions[1519] }; const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w = @@ -6095,7 +6095,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1486] + (const void *)&gInstructions[1487] }; const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w = @@ -6110,7 +6110,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1543] + (const void *)&gInstructions[1544] }; const ND_TABLE_VEX_W gEvexTable_root_01_e6_01_w = @@ -6136,13 +6136,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1477] + (const void *)&gInstructions[1478] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1520] + (const void *)&gInstructions[1521] }; const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w = @@ -6157,7 +6157,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1506] + (const void *)&gInstructions[1507] }; const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w = @@ -6172,7 +6172,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1554] + (const void *)&gInstructions[1555] }; const ND_TABLE_VEX_W gEvexTable_root_01_5b_02_w = @@ -6198,7 +6198,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1489] + (const void *)&gInstructions[1490] }; const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w = @@ -6213,7 +6213,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1508] + (const void *)&gInstructions[1509] }; const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w = @@ -6228,7 +6228,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1524] + (const void *)&gInstructions[1525] }; const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w = @@ -6243,7 +6243,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1537] + (const void *)&gInstructions[1538] }; const ND_TABLE_VEX_W gEvexTable_root_01_5a_02_w = @@ -6269,13 +6269,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1492] + (const void *)&gInstructions[1493] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1515] + (const void *)&gInstructions[1516] }; const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w = @@ -6290,13 +6290,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1573] + (const void *)&gInstructions[1574] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1574] + (const void *)&gInstructions[1575] }; const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_wi = @@ -6311,7 +6311,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_wi = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1576] + (const void *)&gInstructions[1577] }; const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp = @@ -6328,13 +6328,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1493] + (const void *)&gInstructions[1494] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1516] + (const void *)&gInstructions[1517] }; const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w = @@ -6349,13 +6349,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1494] + (const void *)&gInstructions[1495] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1517] + (const void *)&gInstructions[1518] }; const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w = @@ -6370,13 +6370,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1526] + (const void *)&gInstructions[1527] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1542] + (const void *)&gInstructions[1543] }; const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp = @@ -6393,13 +6393,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1522] + (const void *)&gInstructions[1523] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1540] + (const void *)&gInstructions[1541] }; const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp = @@ -6416,13 +6416,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1531] + (const void *)&gInstructions[1532] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1532] + (const void *)&gInstructions[1533] }; const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_wi = @@ -6437,7 +6437,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_wi = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1535] + (const void *)&gInstructions[1536] }; const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp = @@ -6454,13 +6454,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1545] + (const void *)&gInstructions[1546] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1556] + (const void *)&gInstructions[1557] }; const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w = @@ -6475,13 +6475,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1567] + (const void *)&gInstructions[1568] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1570] + (const void *)&gInstructions[1571] }; const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w = @@ -6496,13 +6496,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1569] + (const void *)&gInstructions[1570] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1572] + (const void *)&gInstructions[1573] }; const ND_TABLE_VEX_W gEvexTable_root_01_7a_03_w = @@ -6528,13 +6528,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1546] + (const void *)&gInstructions[1547] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1557] + (const void *)&gInstructions[1558] }; const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w = @@ -6549,13 +6549,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1547] + (const void *)&gInstructions[1548] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1558] + (const void *)&gInstructions[1559] }; const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w = @@ -6570,13 +6570,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1561] + (const void *)&gInstructions[1562] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1566] + (const void *)&gInstructions[1567] }; const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp = @@ -6593,13 +6593,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1559] + (const void *)&gInstructions[1560] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1564] + (const void *)&gInstructions[1565] }; const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp = @@ -6616,7 +6616,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1580] + (const void *)&gInstructions[1581] }; const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w = @@ -6631,7 +6631,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1583] + (const void *)&gInstructions[1584] }; const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w = @@ -6646,7 +6646,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1585] + (const void *)&gInstructions[1586] }; const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w = @@ -6661,7 +6661,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1588] + (const void *)&gInstructions[1589] }; const ND_TABLE_VEX_W gEvexTable_root_01_5e_02_w = @@ -6687,7 +6687,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1884] + (const void *)&gInstructions[1885] }; const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w = @@ -6702,7 +6702,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1887] + (const void *)&gInstructions[1888] }; const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w = @@ -6717,7 +6717,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1889] + (const void *)&gInstructions[1890] }; const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w = @@ -6732,7 +6732,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1892] + (const void *)&gInstructions[1893] }; const ND_TABLE_VEX_W gEvexTable_root_01_5f_02_w = @@ -6758,7 +6758,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1899] + (const void *)&gInstructions[1900] }; const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w = @@ -6773,7 +6773,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1902] + (const void *)&gInstructions[1903] }; const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w = @@ -6788,7 +6788,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1904] + (const void *)&gInstructions[1905] }; const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w = @@ -6803,7 +6803,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1907] + (const void *)&gInstructions[1908] }; const ND_TABLE_VEX_W gEvexTable_root_01_5d_02_w = @@ -6829,7 +6829,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1913] + (const void *)&gInstructions[1914] }; const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w = @@ -6844,7 +6844,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1917] + (const void *)&gInstructions[1918] }; const ND_TABLE_VEX_W gEvexTable_root_01_28_00_w = @@ -6870,7 +6870,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_28_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1914] + (const void *)&gInstructions[1915] }; const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w = @@ -6885,7 +6885,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1918] + (const void *)&gInstructions[1919] }; const ND_TABLE_VEX_W gEvexTable_root_01_29_00_w = @@ -6911,13 +6911,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_29_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1921] + (const void *)&gInstructions[1922] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1976] + (const void *)&gInstructions[1977] }; const ND_TABLE_VEX_W gEvexTable_root_01_6e_01_00_wi = @@ -6954,13 +6954,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1922] + (const void *)&gInstructions[1923] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1977] + (const void *)&gInstructions[1978] }; const ND_TABLE_VEX_W gEvexTable_root_01_7e_01_00_wi = @@ -6986,7 +6986,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_7e_01_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_02_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1978] + (const void *)&gInstructions[1979] }; const ND_TABLE_VEX_W gEvexTable_root_01_7e_02_00_w = @@ -7023,7 +7023,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1925] + (const void *)&gInstructions[1926] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w = @@ -7038,7 +7038,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1926] + (const void *)&gInstructions[1927] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w = @@ -7053,7 +7053,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1927] + (const void *)&gInstructions[1928] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_03_02_w = @@ -7079,7 +7079,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_03_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1946] + (const void *)&gInstructions[1947] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_00_reg_00_w = @@ -7105,7 +7105,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_00_reg_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1962] + (const void *)&gInstructions[1963] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_00_mem_00_w = @@ -7140,7 +7140,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_00_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1958] + (const void *)&gInstructions[1959] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_01_mem_00_w = @@ -7175,7 +7175,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1998] + (const void *)&gInstructions[1999] }; const ND_TABLE_VEX_W gEvexTable_root_01_12_02_w = @@ -7201,13 +7201,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_12_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1932] + (const void *)&gInstructions[1933] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1934] + (const void *)&gInstructions[1935] }; const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w = @@ -7222,13 +7222,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1938] + (const void *)&gInstructions[1939] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1944] + (const void *)&gInstructions[1945] }; const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w = @@ -7243,13 +7243,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1940] + (const void *)&gInstructions[1941] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1942] + (const void *)&gInstructions[1943] }; const ND_TABLE_VEX_W gEvexTable_root_01_6f_02_w = @@ -7275,13 +7275,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1933] + (const void *)&gInstructions[1934] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1935] + (const void *)&gInstructions[1936] }; const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w = @@ -7296,13 +7296,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1939] + (const void *)&gInstructions[1940] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1945] + (const void *)&gInstructions[1946] }; const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w = @@ -7317,13 +7317,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1941] + (const void *)&gInstructions[1942] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1943] + (const void *)&gInstructions[1944] }; const ND_TABLE_VEX_W gEvexTable_root_01_7f_02_w = @@ -7349,7 +7349,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1948] + (const void *)&gInstructions[1949] }; const ND_TABLE_VEX_W gEvexTable_root_01_16_01_mem_00_w = @@ -7384,7 +7384,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1952] + (const void *)&gInstructions[1953] }; const ND_TABLE_VEX_W gEvexTable_root_01_16_00_mem_00_w = @@ -7410,7 +7410,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_16_00_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1956] + (const void *)&gInstructions[1957] }; const ND_TABLE_VEX_W gEvexTable_root_01_16_00_reg_00_w = @@ -7445,7 +7445,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_00_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1996] + (const void *)&gInstructions[1997] }; const ND_TABLE_VEX_W gEvexTable_root_01_16_02_w = @@ -7471,7 +7471,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_16_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1949] + (const void *)&gInstructions[1950] }; const ND_TABLE_VEX_W gEvexTable_root_01_17_01_mem_00_w = @@ -7506,7 +7506,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1953] + (const void *)&gInstructions[1954] }; const ND_TABLE_VEX_W gEvexTable_root_01_17_00_mem_00_w = @@ -7552,7 +7552,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_17_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1959] + (const void *)&gInstructions[1960] }; const ND_TABLE_VEX_W gEvexTable_root_01_13_01_mem_00_w = @@ -7587,7 +7587,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_00_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1963] + (const void *)&gInstructions[1964] }; const ND_TABLE_VEX_W gEvexTable_root_01_13_00_mem_00_w = @@ -7633,7 +7633,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_13_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e7_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1968] + (const void *)&gInstructions[1969] }; const ND_TABLE_VEX_W gEvexTable_root_01_e7_01_mem_w = @@ -7668,7 +7668,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1972] + (const void *)&gInstructions[1973] }; const ND_TABLE_VEX_W gEvexTable_root_01_2b_01_mem_w = @@ -7692,7 +7692,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1974] + (const void *)&gInstructions[1975] }; const ND_TABLE_VEX_W gEvexTable_root_01_2b_00_mem_w = @@ -7727,7 +7727,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d6_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1979] + (const void *)&gInstructions[1980] }; const ND_TABLE_VEX_W gEvexTable_root_01_d6_01_00_w = @@ -7764,7 +7764,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1984] + (const void *)&gInstructions[1985] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w = @@ -7779,7 +7779,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1985] + (const void *)&gInstructions[1986] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_03_reg_w = @@ -7803,7 +7803,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2000] + (const void *)&gInstructions[2001] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w = @@ -7818,7 +7818,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2001] + (const void *)&gInstructions[2002] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_02_reg_w = @@ -7842,7 +7842,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2008] + (const void *)&gInstructions[2009] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w = @@ -7857,7 +7857,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2012] + (const void *)&gInstructions[2013] }; const ND_TABLE_VEX_W gEvexTable_root_01_10_00_w = @@ -7883,7 +7883,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_10_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1986] + (const void *)&gInstructions[1987] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w = @@ -7898,7 +7898,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1987] + (const void *)&gInstructions[1988] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_03_reg_w = @@ -7922,7 +7922,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2002] + (const void *)&gInstructions[2003] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w = @@ -7937,7 +7937,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2003] + (const void *)&gInstructions[2004] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_02_reg_w = @@ -7961,7 +7961,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2009] + (const void *)&gInstructions[2010] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w = @@ -7976,7 +7976,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2013] + (const void *)&gInstructions[2014] }; const ND_TABLE_VEX_W gEvexTable_root_01_11_00_w = @@ -8002,7 +8002,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_11_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2027] + (const void *)&gInstructions[2028] }; const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w = @@ -8017,7 +8017,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2030] + (const void *)&gInstructions[2031] }; const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w = @@ -8032,7 +8032,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2032] + (const void *)&gInstructions[2033] }; const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w = @@ -8047,7 +8047,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2035] + (const void *)&gInstructions[2036] }; const ND_TABLE_VEX_W gEvexTable_root_01_59_02_w = @@ -8073,7 +8073,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_59_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2040] + (const void *)&gInstructions[2041] }; const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w = @@ -8088,7 +8088,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2042] + (const void *)&gInstructions[2043] }; const ND_TABLE_VEX_W gEvexTable_root_01_56_00_w = @@ -8114,7 +8114,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_56_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2055] + (const void *)&gInstructions[2056] }; const ND_TABLE_VEX_W gEvexTable_root_01_6b_01_w = @@ -8140,7 +8140,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_63_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2057] + (const void *)&gInstructions[2058] }; const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp = @@ -8157,7 +8157,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_67_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2061] + (const void *)&gInstructions[2062] }; const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp = @@ -8174,7 +8174,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2063] + (const void *)&gInstructions[2064] }; const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp = @@ -8191,7 +8191,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fe_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2065] + (const void *)&gInstructions[2066] }; const ND_TABLE_VEX_W gEvexTable_root_01_fe_01_w = @@ -8217,7 +8217,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fe_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2067] + (const void *)&gInstructions[2068] }; const ND_TABLE_VEX_W gEvexTable_root_01_d4_01_w = @@ -8243,7 +8243,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ec_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2069] + (const void *)&gInstructions[2070] }; const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp = @@ -8260,7 +8260,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ed_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2071] + (const void *)&gInstructions[2072] }; const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp = @@ -8277,7 +8277,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_dc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2073] + (const void *)&gInstructions[2074] }; const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp = @@ -8294,7 +8294,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_dd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2075] + (const void *)&gInstructions[2076] }; const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp = @@ -8311,7 +8311,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2077] + (const void *)&gInstructions[2078] }; const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp = @@ -8328,13 +8328,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2082] + (const void *)&gInstructions[2083] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2086] + (const void *)&gInstructions[2087] }; const ND_TABLE_VEX_W gEvexTable_root_01_db_01_w = @@ -8360,13 +8360,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_db_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2084] + (const void *)&gInstructions[2085] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2085] + (const void *)&gInstructions[2086] }; const ND_TABLE_VEX_W gEvexTable_root_01_df_01_w = @@ -8392,7 +8392,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_df_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2087] + (const void *)&gInstructions[2088] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp = @@ -8409,7 +8409,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2089] + (const void *)&gInstructions[2090] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp = @@ -8426,7 +8426,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_74_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2118] + (const void *)&gInstructions[2119] }; const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp = @@ -8443,7 +8443,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_76_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2120] + (const void *)&gInstructions[2121] }; const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp = @@ -8460,7 +8460,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_75_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2124] + (const void *)&gInstructions[2125] }; const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp = @@ -8477,7 +8477,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_64_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2128] + (const void *)&gInstructions[2129] }; const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp = @@ -8494,7 +8494,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_66_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2130] + (const void *)&gInstructions[2131] }; const ND_TABLE_VEX_W gEvexTable_root_01_66_01_w = @@ -8520,7 +8520,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_66_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_65_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2134] + (const void *)&gInstructions[2135] }; const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp = @@ -8537,7 +8537,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c5_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2228] + (const void *)&gInstructions[2229] }; const ND_TABLE_VEX_L gEvexTable_root_01_c5_01_reg_l = @@ -8574,7 +8574,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2272] + (const void *)&gInstructions[2273] }; const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l = @@ -8591,7 +8591,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2273] + (const void *)&gInstructions[2274] }; const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_reg_l = @@ -8628,7 +8628,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2296] + (const void *)&gInstructions[2297] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp = @@ -8645,7 +8645,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ee_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2307] + (const void *)&gInstructions[2308] }; const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp = @@ -8662,7 +8662,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_de_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2309] + (const void *)&gInstructions[2310] }; const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp = @@ -8679,7 +8679,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ea_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2321] + (const void *)&gInstructions[2322] }; const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp = @@ -8696,7 +8696,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_da_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2323] + (const void *)&gInstructions[2324] }; const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp = @@ -8713,7 +8713,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e4_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2397] + (const void *)&gInstructions[2398] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp = @@ -8730,7 +8730,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2399] + (const void *)&gInstructions[2400] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp = @@ -8747,7 +8747,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2404] + (const void *)&gInstructions[2405] }; const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp = @@ -8764,7 +8764,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2407] + (const void *)&gInstructions[2408] }; const ND_TABLE_VEX_W gEvexTable_root_01_f4_01_w = @@ -8790,13 +8790,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f4_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2414] + (const void *)&gInstructions[2415] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2415] + (const void *)&gInstructions[2416] }; const ND_TABLE_VEX_W gEvexTable_root_01_eb_01_w = @@ -8822,13 +8822,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_eb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2418] + (const void *)&gInstructions[2419] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2419] + (const void *)&gInstructions[2420] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w = @@ -8843,13 +8843,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2422] + (const void *)&gInstructions[2423] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2423] + (const void *)&gInstructions[2424] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w = @@ -8864,7 +8864,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_06_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2484] + (const void *)&gInstructions[2485] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w = @@ -8879,13 +8879,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2503] + (const void *)&gInstructions[2504] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2507] + (const void *)&gInstructions[2508] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w = @@ -8900,7 +8900,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2517] + (const void *)&gInstructions[2518] }; const ND_TABLE_VEX_W gEvexTable_root_01_72_01_02_w = @@ -8941,7 +8941,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_72_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2438] + (const void *)&gInstructions[2439] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp = @@ -8958,7 +8958,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2475] + (const void *)&gInstructions[2476] }; const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w = @@ -8973,13 +8973,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2477] + (const void *)&gInstructions[2478] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2479] + (const void *)&gInstructions[2480] }; const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp = @@ -8996,7 +8996,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f2_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2485] + (const void *)&gInstructions[2486] }; const ND_TABLE_VEX_W gEvexTable_root_01_f2_01_w = @@ -9022,13 +9022,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2488] + (const void *)&gInstructions[2489] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_06_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2490] + (const void *)&gInstructions[2491] }; const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w = @@ -9043,13 +9043,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2521] + (const void *)&gInstructions[2522] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2523] + (const void *)&gInstructions[2524] }; const ND_TABLE_VEX_W gEvexTable_root_01_73_01_02_w = @@ -9090,7 +9090,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_73_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f3_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2491] + (const void *)&gInstructions[2492] }; const ND_TABLE_VEX_W gEvexTable_root_01_f3_01_w = @@ -9116,19 +9116,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f3_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2499] + (const void *)&gInstructions[2500] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2513] + (const void *)&gInstructions[2514] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2532] + (const void *)&gInstructions[2533] }; const ND_TABLE_MODRM_REG gEvexTable_root_01_71_01_modrmreg = @@ -9160,7 +9160,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_71_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2500] + (const void *)&gInstructions[2501] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp = @@ -9177,13 +9177,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2504] + (const void *)&gInstructions[2505] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2508] + (const void *)&gInstructions[2509] }; const ND_TABLE_VEX_W gEvexTable_root_01_e2_01_w = @@ -9209,7 +9209,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2514] + (const void *)&gInstructions[2515] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp = @@ -9226,7 +9226,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d2_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2518] + (const void *)&gInstructions[2519] }; const ND_TABLE_VEX_W gEvexTable_root_01_d2_01_w = @@ -9252,7 +9252,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d3_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2524] + (const void *)&gInstructions[2525] }; const ND_TABLE_VEX_W gEvexTable_root_01_d3_01_w = @@ -9278,7 +9278,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d3_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2533] + (const void *)&gInstructions[2534] }; const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp = @@ -9295,7 +9295,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2536] + (const void *)&gInstructions[2537] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp = @@ -9312,7 +9312,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fa_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2538] + (const void *)&gInstructions[2539] }; const ND_TABLE_VEX_W gEvexTable_root_01_fa_01_w = @@ -9338,7 +9338,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fa_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_fb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2540] + (const void *)&gInstructions[2541] }; const ND_TABLE_VEX_W gEvexTable_root_01_fb_01_w = @@ -9364,7 +9364,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2542] + (const void *)&gInstructions[2543] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp = @@ -9381,7 +9381,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_e9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2544] + (const void *)&gInstructions[2545] }; const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp = @@ -9398,7 +9398,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2546] + (const void *)&gInstructions[2547] }; const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp = @@ -9415,7 +9415,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_d9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2548] + (const void *)&gInstructions[2549] }; const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp = @@ -9432,7 +9432,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_f9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2550] + (const void *)&gInstructions[2551] }; const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp = @@ -9449,7 +9449,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_68_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2563] + (const void *)&gInstructions[2564] }; const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp = @@ -9466,7 +9466,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2565] + (const void *)&gInstructions[2566] }; const ND_TABLE_VEX_W gEvexTable_root_01_6a_01_w = @@ -9492,7 +9492,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2567] + (const void *)&gInstructions[2568] }; const ND_TABLE_VEX_W gEvexTable_root_01_6d_01_w = @@ -9518,7 +9518,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_69_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2569] + (const void *)&gInstructions[2570] }; const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp = @@ -9535,7 +9535,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_60_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2571] + (const void *)&gInstructions[2572] }; const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp = @@ -9552,7 +9552,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_62_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2573] + (const void *)&gInstructions[2574] }; const ND_TABLE_VEX_W gEvexTable_root_01_62_01_w = @@ -9578,7 +9578,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_62_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_6c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2575] + (const void *)&gInstructions[2576] }; const ND_TABLE_VEX_W gEvexTable_root_01_6c_01_w = @@ -9604,7 +9604,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_61_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2577] + (const void *)&gInstructions[2578] }; const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp = @@ -9621,13 +9621,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2580] + (const void *)&gInstructions[2581] }; const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2581] + (const void *)&gInstructions[2582] }; const ND_TABLE_VEX_W gEvexTable_root_01_ef_01_w = @@ -9653,7 +9653,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ef_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2648] + (const void *)&gInstructions[2649] }; const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w = @@ -9668,7 +9668,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2650] + (const void *)&gInstructions[2651] }; const ND_TABLE_VEX_W gEvexTable_root_01_c6_00_w = @@ -9694,7 +9694,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2652] + (const void *)&gInstructions[2653] }; const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w = @@ -9709,7 +9709,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2655] + (const void *)&gInstructions[2656] }; const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w = @@ -9724,7 +9724,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2657] + (const void *)&gInstructions[2658] }; const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w = @@ -9739,7 +9739,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2660] + (const void *)&gInstructions[2661] }; const ND_TABLE_VEX_W gEvexTable_root_01_51_02_w = @@ -9765,7 +9765,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_51_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2663] + (const void *)&gInstructions[2664] }; const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w = @@ -9780,7 +9780,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2666] + (const void *)&gInstructions[2667] }; const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w = @@ -9795,7 +9795,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2668] + (const void *)&gInstructions[2669] }; const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w = @@ -9810,7 +9810,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2671] + (const void *)&gInstructions[2672] }; const ND_TABLE_VEX_W gEvexTable_root_01_5c_02_w = @@ -9836,7 +9836,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2675] + (const void *)&gInstructions[2676] }; const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w = @@ -9851,7 +9851,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2678] + (const void *)&gInstructions[2679] }; const ND_TABLE_VEX_W gEvexTable_root_01_2e_00_w = @@ -9877,7 +9877,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2680] + (const void *)&gInstructions[2681] }; const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w = @@ -9892,7 +9892,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2682] + (const void *)&gInstructions[2683] }; const ND_TABLE_VEX_W gEvexTable_root_01_15_00_w = @@ -9918,7 +9918,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_15_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2684] + (const void *)&gInstructions[2685] }; const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w = @@ -9933,7 +9933,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2686] + (const void *)&gInstructions[2687] }; const ND_TABLE_VEX_W gEvexTable_root_01_14_00_w = @@ -9959,7 +9959,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_14_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2688] + (const void *)&gInstructions[2689] }; const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w = @@ -9974,7 +9974,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2690] + (const void *)&gInstructions[2691] }; const ND_TABLE_VEX_W gEvexTable_root_01_57_00_w = @@ -10263,7 +10263,7 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode = const ND_TABLE_INSTRUCTION gEvexTable_root_05_58_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1402] + (const void *)&gInstructions[1403] }; const ND_TABLE_VEX_W gEvexTable_root_05_58_00_w = @@ -10278,7 +10278,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_58_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_58_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1407] + (const void *)&gInstructions[1408] }; const ND_TABLE_VEX_W gEvexTable_root_05_58_02_w = @@ -10304,7 +10304,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_58_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_2f_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1468] + (const void *)&gInstructions[1469] }; const ND_TABLE_VEX_W gEvexTable_root_05_2f_00_w = @@ -10330,13 +10330,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1476] + (const void *)&gInstructions[1477] }; const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1519] + (const void *)&gInstructions[1520] }; const ND_TABLE_VEX_W gEvexTable_root_05_5b_00_w = @@ -10351,7 +10351,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5b_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1495] + (const void *)&gInstructions[1496] }; const ND_TABLE_VEX_W gEvexTable_root_05_5b_01_w = @@ -10366,7 +10366,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5b_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1548] + (const void *)&gInstructions[1549] }; const ND_TABLE_VEX_W gEvexTable_root_05_5b_02_w = @@ -10392,7 +10392,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1488] + (const void *)&gInstructions[1489] }; const ND_TABLE_VEX_W gEvexTable_root_05_5a_01_w = @@ -10407,7 +10407,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1496] + (const void *)&gInstructions[1497] }; const ND_TABLE_VEX_W gEvexTable_root_05_5a_00_w = @@ -10422,7 +10422,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1521] + (const void *)&gInstructions[1522] }; const ND_TABLE_VEX_W gEvexTable_root_05_5a_03_w = @@ -10437,7 +10437,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1527] + (const void *)&gInstructions[1528] }; const ND_TABLE_VEX_W gEvexTable_root_05_5a_02_w = @@ -10463,7 +10463,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1501] + (const void *)&gInstructions[1502] }; const ND_TABLE_VEX_W gEvexTable_root_05_7b_01_w = @@ -10478,7 +10478,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7b_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7b_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1575] + (const void *)&gInstructions[1576] }; const ND_TABLE_VEX_PP gEvexTable_root_05_7b_pp = @@ -10495,7 +10495,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_79_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1502] + (const void *)&gInstructions[1503] }; const ND_TABLE_VEX_W gEvexTable_root_05_79_00_w = @@ -10510,7 +10510,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_79_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1503] + (const void *)&gInstructions[1504] }; const ND_TABLE_VEX_W gEvexTable_root_05_79_01_w = @@ -10525,7 +10525,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_79_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_79_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1530] + (const void *)&gInstructions[1531] }; const ND_TABLE_VEX_PP gEvexTable_root_05_79_pp = @@ -10542,7 +10542,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_79_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1504] + (const void *)&gInstructions[1505] }; const ND_TABLE_VEX_W gEvexTable_root_05_7d_00_w = @@ -10557,7 +10557,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1505] + (const void *)&gInstructions[1506] }; const ND_TABLE_VEX_W gEvexTable_root_05_7d_01_w = @@ -10572,7 +10572,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1577] + (const void *)&gInstructions[1578] }; const ND_TABLE_VEX_W gEvexTable_root_05_7d_03_w = @@ -10587,7 +10587,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1578] + (const void *)&gInstructions[1579] }; const ND_TABLE_VEX_W gEvexTable_root_05_7d_02_w = @@ -10613,7 +10613,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_1d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1514] + (const void *)&gInstructions[1515] }; const ND_TABLE_VEX_W gEvexTable_root_05_1d_01_w = @@ -10628,7 +10628,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_1d_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_1d_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1539] + (const void *)&gInstructions[1540] }; const ND_TABLE_VEX_W gEvexTable_root_05_1d_00_w = @@ -10654,7 +10654,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_1d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_2d_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1528] + (const void *)&gInstructions[1529] }; const ND_TABLE_VEX_PP gEvexTable_root_05_2d_pp = @@ -10671,7 +10671,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_2a_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1534] + (const void *)&gInstructions[1535] }; const ND_TABLE_VEX_PP gEvexTable_root_05_2a_pp = @@ -10688,7 +10688,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1549] + (const void *)&gInstructions[1550] }; const ND_TABLE_VEX_W gEvexTable_root_05_7a_01_w = @@ -10703,13 +10703,13 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7a_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7a_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1568] + (const void *)&gInstructions[1569] }; const ND_TABLE_INSTRUCTION gEvexTable_root_05_7a_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1571] + (const void *)&gInstructions[1572] }; const ND_TABLE_VEX_W gEvexTable_root_05_7a_03_w = @@ -10735,7 +10735,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_78_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1550] + (const void *)&gInstructions[1551] }; const ND_TABLE_VEX_W gEvexTable_root_05_78_00_w = @@ -10750,7 +10750,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_78_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1551] + (const void *)&gInstructions[1552] }; const ND_TABLE_VEX_W gEvexTable_root_05_78_01_w = @@ -10765,7 +10765,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_78_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_78_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1563] + (const void *)&gInstructions[1564] }; const ND_TABLE_VEX_W gEvexTable_root_05_78_02_wi = @@ -10791,7 +10791,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_78_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7c_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1552] + (const void *)&gInstructions[1553] }; const ND_TABLE_VEX_W gEvexTable_root_05_7c_00_w = @@ -10806,7 +10806,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7c_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1553] + (const void *)&gInstructions[1554] }; const ND_TABLE_VEX_W gEvexTable_root_05_7c_01_w = @@ -10832,7 +10832,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_2c_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1562] + (const void *)&gInstructions[1563] }; const ND_TABLE_VEX_PP gEvexTable_root_05_2c_pp = @@ -10849,7 +10849,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5e_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1582] + (const void *)&gInstructions[1583] }; const ND_TABLE_VEX_W gEvexTable_root_05_5e_00_w = @@ -10864,7 +10864,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5e_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5e_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1587] + (const void *)&gInstructions[1588] }; const ND_TABLE_VEX_W gEvexTable_root_05_5e_02_w = @@ -10890,7 +10890,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5f_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1886] + (const void *)&gInstructions[1887] }; const ND_TABLE_VEX_W gEvexTable_root_05_5f_00_w = @@ -10905,7 +10905,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5f_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5f_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1891] + (const void *)&gInstructions[1892] }; const ND_TABLE_VEX_W gEvexTable_root_05_5f_02_w = @@ -10931,7 +10931,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5d_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1901] + (const void *)&gInstructions[1902] }; const ND_TABLE_VEX_W gEvexTable_root_05_5d_00_w = @@ -10946,7 +10946,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5d_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5d_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1906] + (const void *)&gInstructions[1907] }; const ND_TABLE_VEX_W gEvexTable_root_05_5d_02_w = @@ -10972,7 +10972,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_10_02_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1992] + (const void *)&gInstructions[1993] }; const ND_TABLE_VEX_W gEvexTable_root_05_10_02_mem_w = @@ -10987,7 +10987,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_10_02_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_10_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1993] + (const void *)&gInstructions[1994] }; const ND_TABLE_VEX_W gEvexTable_root_05_10_02_reg_w = @@ -11022,7 +11022,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_10_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_11_02_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1994] + (const void *)&gInstructions[1995] }; const ND_TABLE_VEX_W gEvexTable_root_05_11_02_mem_w = @@ -11037,7 +11037,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_11_02_mem_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_11_02_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1995] + (const void *)&gInstructions[1996] }; const ND_TABLE_VEX_W gEvexTable_root_05_11_02_reg_w = @@ -11072,7 +11072,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_11_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_6e_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2016] + (const void *)&gInstructions[2017] }; const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_mem_l = @@ -11089,7 +11089,7 @@ const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_05_6e_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2017] + (const void *)&gInstructions[2018] }; const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_reg_l = @@ -11126,7 +11126,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_6e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7e_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2018] + (const void *)&gInstructions[2019] }; const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_mem_l = @@ -11143,7 +11143,7 @@ const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_05_7e_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2019] + (const void *)&gInstructions[2020] }; const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_reg_l = @@ -11180,7 +11180,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_59_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2029] + (const void *)&gInstructions[2030] }; const ND_TABLE_VEX_W gEvexTable_root_05_59_00_w = @@ -11195,7 +11195,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_59_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_59_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2034] + (const void *)&gInstructions[2035] }; const ND_TABLE_VEX_W gEvexTable_root_05_59_02_w = @@ -11221,7 +11221,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_59_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_51_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2654] + (const void *)&gInstructions[2655] }; const ND_TABLE_VEX_W gEvexTable_root_05_51_00_w = @@ -11236,7 +11236,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_51_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_51_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2659] + (const void *)&gInstructions[2660] }; const ND_TABLE_VEX_W gEvexTable_root_05_51_02_w = @@ -11262,7 +11262,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_51_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5c_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2665] + (const void *)&gInstructions[2666] }; const ND_TABLE_VEX_W gEvexTable_root_05_5c_00_w = @@ -11277,7 +11277,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5c_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_05_5c_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2670] + (const void *)&gInstructions[2671] }; const ND_TABLE_VEX_W gEvexTable_root_05_5c_02_w = @@ -11303,7 +11303,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_05_2e_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2677] + (const void *)&gInstructions[2678] }; const ND_TABLE_VEX_W gEvexTable_root_05_2e_00_w = @@ -11592,13 +11592,13 @@ const ND_TABLE_OPCODE gEvexTable_root_05_opcode = const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1422] + (const void *)&gInstructions[1423] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1423] + (const void *)&gInstructions[1424] }; const ND_TABLE_VEX_W gEvexTable_root_03_03_01_w = @@ -11624,7 +11624,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_03_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_c2_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1458] + (const void *)&gInstructions[1459] }; const ND_TABLE_VEX_W gEvexTable_root_03_c2_00_w = @@ -11639,7 +11639,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_c2_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_c2_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1463] + (const void *)&gInstructions[1464] }; const ND_TABLE_VEX_W gEvexTable_root_03_c2_02_w = @@ -11665,7 +11665,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_c2_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1511] + (const void *)&gInstructions[1512] }; const ND_TABLE_VEX_W gEvexTable_root_03_1d_01_w = @@ -11691,7 +11691,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_42_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1579] + (const void *)&gInstructions[1580] }; const ND_TABLE_VEX_W gEvexTable_root_03_42_01_w = @@ -11717,13 +11717,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_42_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1600] + (const void *)&gInstructions[1601] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1602] + (const void *)&gInstructions[1603] }; const ND_TABLE_VEX_W gEvexTable_root_03_19_01_w = @@ -11749,13 +11749,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_19_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1601] + (const void *)&gInstructions[1602] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1603] + (const void *)&gInstructions[1604] }; const ND_TABLE_VEX_W gEvexTable_root_03_1b_01_02_w = @@ -11792,13 +11792,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1605] + (const void *)&gInstructions[1606] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1607] + (const void *)&gInstructions[1608] }; const ND_TABLE_VEX_W gEvexTable_root_03_39_01_w = @@ -11824,13 +11824,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_39_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1606] + (const void *)&gInstructions[1607] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1608] + (const void *)&gInstructions[1609] }; const ND_TABLE_VEX_W gEvexTable_root_03_3b_01_02_w = @@ -11867,7 +11867,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1609] + (const void *)&gInstructions[1610] }; const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l = @@ -11884,7 +11884,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1610] + (const void *)&gInstructions[1611] }; const ND_TABLE_VEX_L gEvexTable_root_03_17_01_reg_l = @@ -11921,13 +11921,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_17_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1617] + (const void *)&gInstructions[1618] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1618] + (const void *)&gInstructions[1619] }; const ND_TABLE_VEX_W gEvexTable_root_03_54_01_w = @@ -11953,13 +11953,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_54_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1619] + (const void *)&gInstructions[1620] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1620] + (const void *)&gInstructions[1621] }; const ND_TABLE_VEX_W gEvexTable_root_03_55_01_w = @@ -11985,13 +11985,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_55_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1815] + (const void *)&gInstructions[1816] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1817] + (const void *)&gInstructions[1818] }; const ND_TABLE_VEX_W gEvexTable_root_03_66_01_w = @@ -12006,7 +12006,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_66_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1816] + (const void *)&gInstructions[1817] }; const ND_TABLE_VEX_W gEvexTable_root_03_66_00_w = @@ -12032,13 +12032,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_66_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1818] + (const void *)&gInstructions[1819] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1820] + (const void *)&gInstructions[1821] }; const ND_TABLE_VEX_W gEvexTable_root_03_67_01_w = @@ -12053,7 +12053,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_67_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1819] + (const void *)&gInstructions[1820] }; const ND_TABLE_VEX_W gEvexTable_root_03_67_00_w = @@ -12079,13 +12079,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_67_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1847] + (const void *)&gInstructions[1848] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1849] + (const void *)&gInstructions[1850] }; const ND_TABLE_VEX_W gEvexTable_root_03_26_01_w = @@ -12100,7 +12100,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_26_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1848] + (const void *)&gInstructions[1849] }; const ND_TABLE_VEX_W gEvexTable_root_03_26_00_w = @@ -12126,13 +12126,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_26_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1850] + (const void *)&gInstructions[1851] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1852] + (const void *)&gInstructions[1853] }; const ND_TABLE_VEX_W gEvexTable_root_03_27_01_w = @@ -12147,7 +12147,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_27_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1851] + (const void *)&gInstructions[1852] }; const ND_TABLE_VEX_W gEvexTable_root_03_27_00_w = @@ -12173,7 +12173,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_27_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_cf_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1853] + (const void *)&gInstructions[1854] }; const ND_TABLE_VEX_W gEvexTable_root_03_cf_01_w = @@ -12199,7 +12199,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_cf_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_ce_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1855] + (const void *)&gInstructions[1856] }; const ND_TABLE_VEX_W gEvexTable_root_03_ce_01_w = @@ -12225,13 +12225,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_ce_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1864] + (const void *)&gInstructions[1865] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1866] + (const void *)&gInstructions[1867] }; const ND_TABLE_VEX_W gEvexTable_root_03_18_01_w = @@ -12257,13 +12257,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_18_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1865] + (const void *)&gInstructions[1866] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1867] + (const void *)&gInstructions[1868] }; const ND_TABLE_VEX_W gEvexTable_root_03_1a_01_02_w = @@ -12300,13 +12300,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1869] + (const void *)&gInstructions[1870] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1871] + (const void *)&gInstructions[1872] }; const ND_TABLE_VEX_W gEvexTable_root_03_38_01_w = @@ -12332,13 +12332,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_38_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1870] + (const void *)&gInstructions[1871] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1872] + (const void *)&gInstructions[1873] }; const ND_TABLE_VEX_W gEvexTable_root_03_3a_01_02_w = @@ -12375,7 +12375,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1873] + (const void *)&gInstructions[1874] }; const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l = @@ -12392,7 +12392,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1874] + (const void *)&gInstructions[1875] }; const ND_TABLE_VEX_L gEvexTable_root_03_21_01_reg_l = @@ -12429,7 +12429,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_21_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_0f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2079] + (const void *)&gInstructions[2080] }; const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp = @@ -12446,7 +12446,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_44_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2112] + (const void *)&gInstructions[2113] }; const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp = @@ -12463,13 +12463,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2116] + (const void *)&gInstructions[2117] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2143] + (const void *)&gInstructions[2144] }; const ND_TABLE_VEX_W gEvexTable_root_03_3f_01_w = @@ -12495,13 +12495,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2117] + (const void *)&gInstructions[2118] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2138] + (const void *)&gInstructions[2139] }; const ND_TABLE_VEX_W gEvexTable_root_03_1f_01_w = @@ -12527,13 +12527,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2139] + (const void *)&gInstructions[2140] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2142] + (const void *)&gInstructions[2143] }; const ND_TABLE_VEX_W gEvexTable_root_03_3e_01_w = @@ -12559,13 +12559,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2140] + (const void *)&gInstructions[2141] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2141] + (const void *)&gInstructions[2142] }; const ND_TABLE_VEX_W gEvexTable_root_03_1e_01_w = @@ -12591,7 +12591,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_05_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2188] + (const void *)&gInstructions[2189] }; const ND_TABLE_VEX_W gEvexTable_root_03_05_01_w = @@ -12617,7 +12617,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_05_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_04_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2192] + (const void *)&gInstructions[2193] }; const ND_TABLE_VEX_W gEvexTable_root_03_04_01_w = @@ -12643,7 +12643,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_04_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2197] + (const void *)&gInstructions[2198] }; const ND_TABLE_VEX_W gEvexTable_root_03_01_01_w = @@ -12669,7 +12669,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_01_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_00_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2203] + (const void *)&gInstructions[2204] }; const ND_TABLE_VEX_W gEvexTable_root_03_00_01_w = @@ -12695,7 +12695,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_00_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2216] + (const void *)&gInstructions[2217] }; const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l = @@ -12712,7 +12712,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2217] + (const void *)&gInstructions[2218] }; const ND_TABLE_VEX_L gEvexTable_root_03_14_01_reg_l = @@ -12749,13 +12749,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_14_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2220] + (const void *)&gInstructions[2221] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2224] + (const void *)&gInstructions[2225] }; const ND_TABLE_VEX_W gEvexTable_root_03_16_01_mem_00_wi = @@ -12781,13 +12781,13 @@ const ND_TABLE_VEX_L gEvexTable_root_03_16_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2221] + (const void *)&gInstructions[2222] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2225] + (const void *)&gInstructions[2226] }; const ND_TABLE_VEX_W gEvexTable_root_03_16_01_reg_00_wi = @@ -12833,7 +12833,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_16_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2229] + (const void *)&gInstructions[2230] }; const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l = @@ -12850,7 +12850,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2230] + (const void *)&gInstructions[2231] }; const ND_TABLE_VEX_L gEvexTable_root_03_15_01_reg_l = @@ -12887,7 +12887,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_15_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2264] + (const void *)&gInstructions[2265] }; const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l = @@ -12904,7 +12904,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l = const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2265] + (const void *)&gInstructions[2266] }; const ND_TABLE_VEX_L gEvexTable_root_03_20_01_reg_l = @@ -12941,13 +12941,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_20_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2268] + (const void *)&gInstructions[2269] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2270] + (const void *)&gInstructions[2271] }; const ND_TABLE_VEX_W gEvexTable_root_03_22_01_00_wi = @@ -12984,13 +12984,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_22_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2457] + (const void *)&gInstructions[2458] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2458] + (const void *)&gInstructions[2459] }; const ND_TABLE_VEX_W gEvexTable_root_03_71_01_w = @@ -13016,7 +13016,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_71_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_70_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2462] + (const void *)&gInstructions[2463] }; const ND_TABLE_VEX_W gEvexTable_root_03_70_01_w = @@ -13042,13 +13042,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_70_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2466] + (const void *)&gInstructions[2467] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2467] + (const void *)&gInstructions[2468] }; const ND_TABLE_VEX_W gEvexTable_root_03_73_01_w = @@ -13074,7 +13074,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_73_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_72_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2471] + (const void *)&gInstructions[2472] }; const ND_TABLE_VEX_W gEvexTable_root_03_72_01_w = @@ -13100,13 +13100,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_72_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2552] + (const void *)&gInstructions[2553] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2553] + (const void *)&gInstructions[2554] }; const ND_TABLE_VEX_W gEvexTable_root_03_25_01_w = @@ -13132,13 +13132,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_25_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2582] + (const void *)&gInstructions[2583] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2583] + (const void *)&gInstructions[2584] }; const ND_TABLE_VEX_W gEvexTable_root_03_50_01_w = @@ -13164,13 +13164,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_50_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2584] + (const void *)&gInstructions[2585] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2585] + (const void *)&gInstructions[2586] }; const ND_TABLE_VEX_W gEvexTable_root_03_51_01_w = @@ -13196,13 +13196,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_51_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2598] + (const void *)&gInstructions[2599] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2600] + (const void *)&gInstructions[2601] }; const ND_TABLE_VEX_W gEvexTable_root_03_56_01_w = @@ -13217,7 +13217,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_56_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2599] + (const void *)&gInstructions[2600] }; const ND_TABLE_VEX_W gEvexTable_root_03_56_00_w = @@ -13243,13 +13243,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_56_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2601] + (const void *)&gInstructions[2602] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2603] + (const void *)&gInstructions[2604] }; const ND_TABLE_VEX_W gEvexTable_root_03_57_01_w = @@ -13264,7 +13264,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_57_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2602] + (const void *)&gInstructions[2603] }; const ND_TABLE_VEX_W gEvexTable_root_03_57_00_w = @@ -13290,7 +13290,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_57_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_09_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2604] + (const void *)&gInstructions[2605] }; const ND_TABLE_VEX_W gEvexTable_root_03_09_01_w = @@ -13316,7 +13316,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_09_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2605] + (const void *)&gInstructions[2606] }; const ND_TABLE_VEX_W gEvexTable_root_03_08_00_w = @@ -13331,7 +13331,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_08_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2606] + (const void *)&gInstructions[2607] }; const ND_TABLE_VEX_W gEvexTable_root_03_08_01_w = @@ -13357,7 +13357,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_08_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_0b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2607] + (const void *)&gInstructions[2608] }; const ND_TABLE_VEX_W gEvexTable_root_03_0b_01_w = @@ -13383,7 +13383,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2608] + (const void *)&gInstructions[2609] }; const ND_TABLE_VEX_W gEvexTable_root_03_0a_00_w = @@ -13398,7 +13398,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_0a_00_w = const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2609] + (const void *)&gInstructions[2610] }; const ND_TABLE_VEX_W gEvexTable_root_03_0a_01_w = @@ -13424,13 +13424,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2644] + (const void *)&gInstructions[2645] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2645] + (const void *)&gInstructions[2646] }; const ND_TABLE_VEX_W gEvexTable_root_03_23_01_w = @@ -13456,13 +13456,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_23_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2646] + (const void *)&gInstructions[2647] }; const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2647] + (const void *)&gInstructions[2648] }; const ND_TABLE_VEX_W gEvexTable_root_03_43_01_w = @@ -13751,7 +13751,7 @@ const ND_TABLE_OPCODE gEvexTable_root_03_opcode = const ND_TABLE_INSTRUCTION gEvexTable_root_06_13_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1500] + (const void *)&gInstructions[1501] }; const ND_TABLE_VEX_W gEvexTable_root_06_13_01_w = @@ -13766,7 +13766,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_13_01_w = const ND_TABLE_INSTRUCTION gEvexTable_root_06_13_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1529] + (const void *)&gInstructions[1530] }; const ND_TABLE_VEX_W gEvexTable_root_06_13_00_w = @@ -13792,7 +13792,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_13_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_56_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1613] + (const void *)&gInstructions[1614] }; const ND_TABLE_VEX_W gEvexTable_root_06_56_03_w = @@ -13807,7 +13807,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_56_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_06_56_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1651] + (const void *)&gInstructions[1652] }; const ND_TABLE_VEX_W gEvexTable_root_06_56_02_w = @@ -13833,7 +13833,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_56_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_57_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1614] + (const void *)&gInstructions[1615] }; const ND_TABLE_VEX_W gEvexTable_root_06_57_03_w = @@ -13848,7 +13848,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_57_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_06_57_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1652] + (const void *)&gInstructions[1653] }; const ND_TABLE_VEX_W gEvexTable_root_06_57_02_w = @@ -13874,7 +13874,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_57_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_d6_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1615] + (const void *)&gInstructions[1616] }; const ND_TABLE_VEX_W gEvexTable_root_06_d6_03_w = @@ -13889,7 +13889,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_d6_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_06_d6_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1737] + (const void *)&gInstructions[1738] }; const ND_TABLE_VEX_W gEvexTable_root_06_d6_02_w = @@ -13915,7 +13915,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_d6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_d7_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1616] + (const void *)&gInstructions[1617] }; const ND_TABLE_VEX_W gEvexTable_root_06_d7_03_w = @@ -13930,7 +13930,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_d7_03_w = const ND_TABLE_INSTRUCTION gEvexTable_root_06_d7_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1738] + (const void *)&gInstructions[1739] }; const ND_TABLE_VEX_W gEvexTable_root_06_d7_02_w = @@ -13956,7 +13956,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_d7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_98_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1623] + (const void *)&gInstructions[1624] }; const ND_TABLE_VEX_W gEvexTable_root_06_98_01_w = @@ -13982,7 +13982,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_98_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_99_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1628] + (const void *)&gInstructions[1629] }; const ND_TABLE_VEX_W gEvexTable_root_06_99_01_w = @@ -14008,7 +14008,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_99_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_a8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1633] + (const void *)&gInstructions[1634] }; const ND_TABLE_VEX_W gEvexTable_root_06_a8_01_w = @@ -14034,7 +14034,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_a9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1638] + (const void *)&gInstructions[1639] }; const ND_TABLE_VEX_W gEvexTable_root_06_a9_01_w = @@ -14060,7 +14060,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_b8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1643] + (const void *)&gInstructions[1644] }; const ND_TABLE_VEX_W gEvexTable_root_06_b8_01_w = @@ -14086,7 +14086,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b8_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_b9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1648] + (const void *)&gInstructions[1649] }; const ND_TABLE_VEX_W gEvexTable_root_06_b9_01_w = @@ -14112,7 +14112,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b9_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_96_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1663] + (const void *)&gInstructions[1664] }; const ND_TABLE_VEX_W gEvexTable_root_06_96_01_w = @@ -14138,7 +14138,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_96_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_a6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1668] + (const void *)&gInstructions[1669] }; const ND_TABLE_VEX_W gEvexTable_root_06_a6_01_w = @@ -14164,7 +14164,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_b6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1673] + (const void *)&gInstructions[1674] }; const ND_TABLE_VEX_W gEvexTable_root_06_b6_01_w = @@ -14190,7 +14190,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b6_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_9a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1682] + (const void *)&gInstructions[1683] }; const ND_TABLE_VEX_W gEvexTable_root_06_9a_01_w = @@ -14216,7 +14216,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9a_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_9b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1687] + (const void *)&gInstructions[1688] }; const ND_TABLE_VEX_W gEvexTable_root_06_9b_01_w = @@ -14242,7 +14242,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9b_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_aa_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1692] + (const void *)&gInstructions[1693] }; const ND_TABLE_VEX_W gEvexTable_root_06_aa_01_w = @@ -14268,7 +14268,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_aa_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_ab_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1697] + (const void *)&gInstructions[1698] }; const ND_TABLE_VEX_W gEvexTable_root_06_ab_01_w = @@ -14294,7 +14294,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ab_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_ba_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1702] + (const void *)&gInstructions[1703] }; const ND_TABLE_VEX_W gEvexTable_root_06_ba_01_w = @@ -14320,7 +14320,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ba_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_bb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1707] + (const void *)&gInstructions[1708] }; const ND_TABLE_VEX_W gEvexTable_root_06_bb_01_w = @@ -14346,7 +14346,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bb_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_97_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1712] + (const void *)&gInstructions[1713] }; const ND_TABLE_VEX_W gEvexTable_root_06_97_01_w = @@ -14372,7 +14372,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_97_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_a7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1717] + (const void *)&gInstructions[1718] }; const ND_TABLE_VEX_W gEvexTable_root_06_a7_01_w = @@ -14398,7 +14398,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_b7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1722] + (const void *)&gInstructions[1723] }; const ND_TABLE_VEX_W gEvexTable_root_06_b7_01_w = @@ -14424,7 +14424,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b7_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_9c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1741] + (const void *)&gInstructions[1742] }; const ND_TABLE_VEX_W gEvexTable_root_06_9c_01_w = @@ -14450,7 +14450,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_9d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1746] + (const void *)&gInstructions[1747] }; const ND_TABLE_VEX_W gEvexTable_root_06_9d_01_w = @@ -14476,7 +14476,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_ac_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1751] + (const void *)&gInstructions[1752] }; const ND_TABLE_VEX_W gEvexTable_root_06_ac_01_w = @@ -14502,7 +14502,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ac_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_ad_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1756] + (const void *)&gInstructions[1757] }; const ND_TABLE_VEX_W gEvexTable_root_06_ad_01_w = @@ -14528,7 +14528,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ad_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_bc_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1761] + (const void *)&gInstructions[1762] }; const ND_TABLE_VEX_W gEvexTable_root_06_bc_01_w = @@ -14554,7 +14554,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bc_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_bd_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1766] + (const void *)&gInstructions[1767] }; const ND_TABLE_VEX_W gEvexTable_root_06_bd_01_w = @@ -14580,7 +14580,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bd_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_9e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1779] + (const void *)&gInstructions[1780] }; const ND_TABLE_VEX_W gEvexTable_root_06_9e_01_w = @@ -14606,7 +14606,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_9f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1784] + (const void *)&gInstructions[1785] }; const ND_TABLE_VEX_W gEvexTable_root_06_9f_01_w = @@ -14632,7 +14632,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_ae_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1789] + (const void *)&gInstructions[1790] }; const ND_TABLE_VEX_W gEvexTable_root_06_ae_01_w = @@ -14658,7 +14658,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ae_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_af_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1794] + (const void *)&gInstructions[1795] }; const ND_TABLE_VEX_W gEvexTable_root_06_af_01_w = @@ -14684,7 +14684,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_af_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_be_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1799] + (const void *)&gInstructions[1800] }; const ND_TABLE_VEX_W gEvexTable_root_06_be_01_w = @@ -14710,7 +14710,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_be_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_bf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1804] + (const void *)&gInstructions[1805] }; const ND_TABLE_VEX_W gEvexTable_root_06_bf_01_w = @@ -14736,7 +14736,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bf_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_42_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1842] + (const void *)&gInstructions[1843] }; const ND_TABLE_VEX_W gEvexTable_root_06_42_01_w = @@ -14762,7 +14762,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_42_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_43_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1845] + (const void *)&gInstructions[1846] }; const ND_TABLE_VEX_W gEvexTable_root_06_43_01_w = @@ -14788,7 +14788,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_43_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_4c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2594] + (const void *)&gInstructions[2595] }; const ND_TABLE_VEX_W gEvexTable_root_06_4c_01_w = @@ -14814,7 +14814,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_4d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2596] + (const void *)&gInstructions[2597] }; const ND_TABLE_VEX_W gEvexTable_root_06_4d_01_w = @@ -14840,7 +14840,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4d_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_4e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2622] + (const void *)&gInstructions[2623] }; const ND_TABLE_VEX_W gEvexTable_root_06_4e_01_w = @@ -14866,7 +14866,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4e_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_4f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2624] + (const void *)&gInstructions[2625] }; const ND_TABLE_VEX_W gEvexTable_root_06_4f_01_w = @@ -14892,7 +14892,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4f_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_2c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2627] + (const void *)&gInstructions[2628] }; const ND_TABLE_VEX_W gEvexTable_root_06_2c_01_w = @@ -14918,7 +14918,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_2c_pp = const ND_TABLE_INSTRUCTION gEvexTable_root_06_2d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2630] + (const void *)&gInstructions[2631] }; const ND_TABLE_VEX_W gEvexTable_root_06_2d_01_w = diff --git a/bddisasm/include/table_root.h b/bddisasm/include/table_root.h index b0647d4..a22c237 100644 --- a/bddisasm/include/table_root.h +++ b/bddisasm/include/table_root.h @@ -81,13 +81,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_F3_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2704] + (const void *)&gInstructions[2705] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2705] + (const void *)&gInstructions[2706] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary = @@ -1732,7 +1732,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c9_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1278] + (const void *)&gInstructions[1279] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix = @@ -1749,7 +1749,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_ca_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1279] + (const void *)&gInstructions[1280] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix = @@ -1766,7 +1766,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c8_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1280] + (const void *)&gInstructions[1281] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix = @@ -1783,7 +1783,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cc_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1282] + (const void *)&gInstructions[1283] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix = @@ -1800,7 +1800,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cd_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1283] + (const void *)&gInstructions[1284] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix = @@ -1817,7 +1817,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cb_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1284] + (const void *)&gInstructions[1285] }; const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix = @@ -1834,13 +1834,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2706] + (const void *)&gInstructions[2707] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2707] + (const void *)&gInstructions[2708] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary = @@ -2831,7 +2831,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_22_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_09_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1209] + (const void *)&gInstructions[1210] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix = @@ -2848,7 +2848,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_08_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1210] + (const void *)&gInstructions[1211] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix = @@ -2865,7 +2865,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0b_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1211] + (const void *)&gInstructions[1212] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix = @@ -2882,7 +2882,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0a_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1212] + (const void *)&gInstructions[1213] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix = @@ -2899,7 +2899,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cc_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1281] + (const void *)&gInstructions[1282] }; const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cc_mprefix = @@ -3437,7 +3437,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_None_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1382] + (const void *)&gInstructions[1383] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary = @@ -3631,7 +3631,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_NP_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1254] + (const void *)&gInstructions[1255] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix = @@ -3682,7 +3682,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1255] + (const void *)&gInstructions[1256] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix = @@ -3699,7 +3699,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_05_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1256] + (const void *)&gInstructions[1257] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix = @@ -3716,7 +3716,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_03_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1318] + (const void *)&gInstructions[1319] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix = @@ -3733,7 +3733,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_04_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1359] + (const void *)&gInstructions[1360] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_04_mprefix = @@ -3777,37 +3777,37 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_07_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1306] + (const void *)&gInstructions[1307] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1321] + (const void *)&gInstructions[1322] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1897] + (const void *)&gInstructions[1898] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1898] + (const void *)&gInstructions[1899] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1911] + (const void *)&gInstructions[1912] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1912] + (const void *)&gInstructions[1913] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix = @@ -3824,19 +3824,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1910] + (const void *)&gInstructions[1911] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2025] + (const void *)&gInstructions[2026] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2026] + (const void *)&gInstructions[2027] }; const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm = @@ -3880,7 +3880,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_02_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1235] + (const void *)&gInstructions[1236] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix = @@ -3897,19 +3897,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1258] + (const void *)&gInstructions[1259] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1274] + (const void *)&gInstructions[1275] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2760] + (const void *)&gInstructions[2761] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix = @@ -3926,13 +3926,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1335] + (const void *)&gInstructions[1336] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2702] + (const void *)&gInstructions[2703] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix = @@ -3949,7 +3949,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_05_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1374] + (const void *)&gInstructions[1375] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix = @@ -3966,7 +3966,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_04_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1389] + (const void *)&gInstructions[1390] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix = @@ -3983,7 +3983,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2742] + (const void *)&gInstructions[2743] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix = @@ -4033,7 +4033,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F3_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1195] + (const void *)&gInstructions[1196] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix = @@ -4102,7 +4102,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F2_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1380] + (const void *)&gInstructions[1381] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix = @@ -4116,12 +4116,29 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix = } }; -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_leaf = +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_None_leaf = { ND_ILUT_INSTRUCTION, (const void *)&gInstructions[1180] }; +const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_F3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[1195] +}; + +const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_05_mprefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_05_None_leaf, + /* 01 */ ND_NULL, + /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_05_F3_leaf, + /* 03 */ ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_01_leaf = { ND_ILUT_INSTRUCTION, @@ -4131,7 +4148,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_01_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1353] + (const void *)&gInstructions[1354] }; const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm = @@ -4143,7 +4160,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm = /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_02_mprefix, /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_03_mprefix, /* 04 */ (const void *)&gRootTable_root_0f_01_reg_07_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_01_reg_07_05_leaf, + /* 05 */ (const void *)&gRootTable_root_0f_01_reg_07_05_mprefix, /* 06 */ (const void *)&gRootTable_root_0f_01_reg_07_06_mprefix, /* 07 */ (const void *)&gRootTable_root_0f_01_reg_07_07_mprefix, } @@ -4169,7 +4186,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1896] + (const void *)&gInstructions[1897] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix = @@ -4186,7 +4203,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2727] + (const void *)&gInstructions[2728] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix = @@ -4203,7 +4220,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2728] + (const void *)&gInstructions[2729] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix = @@ -4220,7 +4237,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2755] + (const void *)&gInstructions[2756] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix = @@ -4237,7 +4254,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2761] + (const void *)&gInstructions[2762] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix = @@ -4309,13 +4326,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_F2_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2700] + (const void *)&gInstructions[2701] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2701] + (const void *)&gInstructions[2702] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_06_mprefix = @@ -4332,7 +4349,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1894] + (const void *)&gInstructions[1895] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix = @@ -4349,7 +4366,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1909] + (const void *)&gInstructions[1910] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix = @@ -4366,7 +4383,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2024] + (const void *)&gInstructions[2025] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix = @@ -4383,7 +4400,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2038] + (const void *)&gInstructions[2039] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_04_mprefix = @@ -4421,7 +4438,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_06_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1312] + (const void *)&gInstructions[1313] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg = @@ -4466,7 +4483,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_06_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_05_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1218] + (const void *)&gInstructions[1219] }; const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix = @@ -4483,19 +4500,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1277] + (const void *)&gInstructions[1278] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1305] + (const void *)&gInstructions[1306] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1311] + (const void *)&gInstructions[1312] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_01_mem_modrmreg = @@ -4745,13 +4762,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_66_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2751] + (const void *)&gInstructions[2752] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2752] + (const void *)&gInstructions[2753] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary = @@ -4882,13 +4899,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_F3_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2747] + (const void *)&gInstructions[2748] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2748] + (const void *)&gInstructions[2749] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary = @@ -4920,7 +4937,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_03_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1323] + (const void *)&gInstructions[1324] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix = @@ -4937,13 +4954,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2743] + (const void *)&gInstructions[2744] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2744] + (const void *)&gInstructions[2745] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary = @@ -5040,19 +5057,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_NP_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1381] + (const void *)&gInstructions[1382] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1390] + (const void *)&gInstructions[1391] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1391] + (const void *)&gInstructions[1392] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix = @@ -5150,7 +5167,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_01_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1276] + (const void *)&gInstructions[1277] }; const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix = @@ -5167,7 +5184,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_02_F3_64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2697] + (const void *)&gInstructions[2698] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary = @@ -5199,7 +5216,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_03_F3_64_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2698] + (const void *)&gInstructions[2699] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary = @@ -5431,19 +5448,19 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1895] + (const void *)&gInstructions[1896] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2021] + (const void *)&gInstructions[2022] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2039] + (const void *)&gInstructions[2040] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix = @@ -5460,7 +5477,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_07_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2022] + (const void *)&gInstructions[2023] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix = @@ -5477,13 +5494,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2745] + (const void *)&gInstructions[2746] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2746] + (const void *)&gInstructions[2747] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary = @@ -5515,13 +5532,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2749] + (const void *)&gInstructions[2750] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2750] + (const void *)&gInstructions[2751] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary = @@ -5553,13 +5570,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2753] + (const void *)&gInstructions[2754] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_rexw_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2754] + (const void *)&gInstructions[2755] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary = @@ -5647,7 +5664,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_66_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1257] + (const void *)&gInstructions[1258] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_06_mprefix = @@ -6258,7 +6275,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_F2_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2023] + (const void *)&gInstructions[2024] }; const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix = @@ -6275,7 +6292,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1350] + (const void *)&gInstructions[1351] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_78_cyrix_modrmmod = @@ -6315,7 +6332,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_F2_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2037] + (const void *)&gInstructions[2038] }; const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix = @@ -6332,7 +6349,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_mem_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2037] + (const void *)&gInstructions[2038] }; const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_mem_mprefix = @@ -6358,7 +6375,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_None_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1213] + (const void *)&gInstructions[1214] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_cyrix_modrmmod = @@ -6409,7 +6426,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_cyrix_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2703] + (const void *)&gInstructions[2704] }; const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor = @@ -6451,7 +6468,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1352] + (const void *)&gInstructions[1353] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_7c_cyrix_modrmmod = @@ -6502,7 +6519,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1219] + (const void *)&gInstructions[1220] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_7d_cyrix_modrmmod = @@ -6601,25 +6618,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_03_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1307] + (const void *)&gInstructions[1308] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1332] + (const void *)&gInstructions[1333] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1593] + (const void *)&gInstructions[1594] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1594] + (const void *)&gInstructions[1595] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg = @@ -6675,25 +6692,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_03_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1308] + (const void *)&gInstructions[1309] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1333] + (const void *)&gInstructions[1334] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1593] + (const void *)&gInstructions[1594] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1594] + (const void *)&gInstructions[1595] }; const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg = @@ -7069,7 +7086,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_00_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_01_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2756] + (const void *)&gInstructions[2757] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_01_00_mprefix = @@ -7101,7 +7118,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_01_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_02_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2757] + (const void *)&gInstructions[2758] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_02_00_mprefix = @@ -7375,7 +7392,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_cyrix_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1310] + (const void *)&gInstructions[1311] }; const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor = @@ -10717,7 +10734,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_31_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7b_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1214] + (const void *)&gInstructions[1215] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_7b_cyrix_modrmmod = @@ -10745,19 +10762,19 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7b_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_aa_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1215] + (const void *)&gInstructions[1216] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1216] + (const void *)&gInstructions[1217] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1217] + (const void *)&gInstructions[1218] }; const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix = @@ -10774,133 +10791,133 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1259] + (const void *)&gInstructions[1260] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_92_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1260] + (const void *)&gInstructions[1261] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1261] + (const void *)&gInstructions[1262] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1262] + (const void *)&gInstructions[1263] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1263] + (const void *)&gInstructions[1264] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_93_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1264] + (const void *)&gInstructions[1265] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1265] + (const void *)&gInstructions[1266] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1266] + (const void *)&gInstructions[1267] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_91_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1267] + (const void *)&gInstructions[1268] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1268] + (const void *)&gInstructions[1269] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_99_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1269] + (const void *)&gInstructions[1270] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1270] + (const void *)&gInstructions[1271] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_90_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1271] + (const void *)&gInstructions[1272] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_9a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1272] + (const void *)&gInstructions[1273] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_98_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1273] + (const void *)&gInstructions[1274] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1275] + (const void *)&gInstructions[1276] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1291] + (const void *)&gInstructions[1292] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1292] + (const void *)&gInstructions[1293] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ac_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1300] + (const void *)&gInstructions[1301] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_ad_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1301] + (const void *)&gInstructions[1302] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1303] + (const void *)&gInstructions[1304] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1304] + (const void *)&gInstructions[1305] }; const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix = @@ -10917,25 +10934,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1314] + (const void *)&gInstructions[1315] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1315] + (const void *)&gInstructions[1316] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1316] + (const void *)&gInstructions[1317] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1317] + (const void *)&gInstructions[1318] }; const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix = @@ -10952,25 +10969,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1346] + (const void *)&gInstructions[1347] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1347] + (const void *)&gInstructions[1348] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1348] + (const void *)&gInstructions[1349] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1349] + (const void *)&gInstructions[1350] }; const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix = @@ -10987,7 +11004,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_7a_cyrix_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1351] + (const void *)&gInstructions[1352] }; const ND_TABLE_MODRM_MOD gRootTable_root_0f_7a_cyrix_modrmmod = @@ -11015,37 +11032,37 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7a_vendor = const ND_TABLE_INSTRUCTION gRootTable_root_0f_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1354] + (const void *)&gInstructions[1355] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_34_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1355] + (const void *)&gInstructions[1356] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_35_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1356] + (const void *)&gInstructions[1357] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1357] + (const void *)&gInstructions[1358] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1384] + (const void *)&gInstructions[1385] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1385] + (const void *)&gInstructions[1386] }; const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix = @@ -11062,31 +11079,31 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_ff_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1386] + (const void *)&gInstructions[1387] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_b9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1387] + (const void *)&gInstructions[1388] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1388] + (const void *)&gInstructions[1389] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1392] + (const void *)&gInstructions[1393] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1393] + (const void *)&gInstructions[1394] }; const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix = @@ -11103,13 +11120,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1394] + (const void *)&gInstructions[1395] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1395] + (const void *)&gInstructions[1396] }; const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix = @@ -11126,13 +11143,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix = const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2695] + (const void *)&gInstructions[2696] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_aF3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2696] + (const void *)&gInstructions[2697] }; const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary = @@ -11153,25 +11170,25 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_0f_30_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2699] + (const void *)&gInstructions[2700] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2709] + (const void *)&gInstructions[2710] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2710] + (const void *)&gInstructions[2711] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_02_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2722] + (const void *)&gInstructions[2723] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_02_00_mprefix = @@ -11203,7 +11220,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_02_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_04_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2723] + (const void *)&gInstructions[2724] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_04_00_mprefix = @@ -11235,7 +11252,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_04_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_03_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2724] + (const void *)&gInstructions[2725] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_03_00_mprefix = @@ -11267,7 +11284,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_03_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_01_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2725] + (const void *)&gInstructions[2726] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_01_00_mprefix = @@ -11299,7 +11316,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_01_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_05_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2726] + (const void *)&gInstructions[2727] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_05_00_mprefix = @@ -11331,13 +11348,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_05_modrmrm = const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2758] + (const void *)&gInstructions[2759] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_F3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2759] + (const void *)&gInstructions[2760] }; const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_00_00_mprefix = @@ -11393,13 +11410,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a7_modrmmod = const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_66_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2740] + (const void *)&gInstructions[2741] }; const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_NP_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2741] + (const void *)&gInstructions[2742] }; const ND_TABLE_MPREFIX gRootTable_root_0f_57_mprefix = @@ -11757,19 +11774,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_80_01_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_80_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1242] + (const void *)&gInstructions[1243] }; const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1342] + (const void *)&gInstructions[1343] }; const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2736] + (const void *)&gInstructions[2737] }; const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg = @@ -11820,19 +11837,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_81_01_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_81_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1243] + (const void *)&gInstructions[1244] }; const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1343] + (const void *)&gInstructions[1344] }; const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2737] + (const void *)&gInstructions[2738] }; const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg = @@ -11883,19 +11900,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_82_01_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_82_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1244] + (const void *)&gInstructions[1245] }; const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1344] + (const void *)&gInstructions[1345] }; const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2738] + (const void *)&gInstructions[2739] }; const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg = @@ -11946,19 +11963,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_83_01_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_83_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1245] + (const void *)&gInstructions[1246] }; const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1345] + (const void *)&gInstructions[1346] }; const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2739] + (const void *)&gInstructions[2740] }; const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg = @@ -12582,13 +12599,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_f6_02_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_f6_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1370] + (const void *)&gInstructions[1371] }; const ND_TABLE_INSTRUCTION gRootTable_root_f6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1371] + (const void *)&gInstructions[1372] }; const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg = @@ -12645,13 +12662,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_f7_02_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_f7_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1372] + (const void *)&gInstructions[1373] }; const ND_TABLE_INSTRUCTION gRootTable_root_f7_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1373] + (const void *)&gInstructions[1374] }; const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg = @@ -14813,7 +14830,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_00_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2708] + (const void *)&gInstructions[2709] }; const ND_TABLE_MODRM_RM gRootTable_root_c6_reg_07_modrmrm = @@ -14885,7 +14902,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_00_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_07_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2711] + (const void *)&gInstructions[2712] }; const ND_TABLE_MODRM_RM gRootTable_root_c7_reg_07_modrmrm = @@ -15063,7 +15080,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_90_aF3_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_90_rexb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2714] + (const void *)&gInstructions[2715] }; const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary = @@ -15533,37 +15550,37 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c0_03_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_c0_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1196] + (const void *)&gInstructions[1197] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1202] + (const void *)&gInstructions[1203] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1221] + (const void *)&gInstructions[1222] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1228] + (const void *)&gInstructions[1229] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1285] + (const void *)&gInstructions[1286] }; const ND_TABLE_INSTRUCTION gRootTable_root_c0_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1294] + (const void *)&gInstructions[1295] }; const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg = @@ -15596,37 +15613,37 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c1_03_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_c1_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1197] + (const void *)&gInstructions[1198] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1203] + (const void *)&gInstructions[1204] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1222] + (const void *)&gInstructions[1223] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1229] + (const void *)&gInstructions[1230] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1286] + (const void *)&gInstructions[1287] }; const ND_TABLE_INSTRUCTION gRootTable_root_c1_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1295] + (const void *)&gInstructions[1296] }; const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg = @@ -15659,37 +15676,37 @@ const ND_TABLE_INSTRUCTION gRootTable_root_d0_03_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_d0_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1198] + (const void *)&gInstructions[1199] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1204] + (const void *)&gInstructions[1205] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1223] + (const void *)&gInstructions[1224] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1230] + (const void *)&gInstructions[1231] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1287] + (const void *)&gInstructions[1288] }; const ND_TABLE_INSTRUCTION gRootTable_root_d0_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1296] + (const void *)&gInstructions[1297] }; const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg = @@ -15722,37 +15739,37 @@ const ND_TABLE_INSTRUCTION gRootTable_root_d1_03_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_d1_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1199] + (const void *)&gInstructions[1200] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1205] + (const void *)&gInstructions[1206] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1224] + (const void *)&gInstructions[1225] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1231] + (const void *)&gInstructions[1232] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1288] + (const void *)&gInstructions[1289] }; const ND_TABLE_INSTRUCTION gRootTable_root_d1_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1297] + (const void *)&gInstructions[1298] }; const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg = @@ -15785,37 +15802,37 @@ const ND_TABLE_INSTRUCTION gRootTable_root_d2_03_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_d2_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1200] + (const void *)&gInstructions[1201] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1206] + (const void *)&gInstructions[1207] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1225] + (const void *)&gInstructions[1226] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1232] + (const void *)&gInstructions[1233] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1289] + (const void *)&gInstructions[1290] }; const ND_TABLE_INSTRUCTION gRootTable_root_d2_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1298] + (const void *)&gInstructions[1299] }; const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg = @@ -15848,37 +15865,37 @@ const ND_TABLE_INSTRUCTION gRootTable_root_d3_03_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_d3_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1201] + (const void *)&gInstructions[1202] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1207] + (const void *)&gInstructions[1208] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1226] + (const void *)&gInstructions[1227] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1233] + (const void *)&gInstructions[1234] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1290] + (const void *)&gInstructions[1291] }; const ND_TABLE_INSTRUCTION gRootTable_root_d3_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1299] + (const void *)&gInstructions[1300] }; const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg = @@ -15923,61 +15940,61 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c3_leaf = const ND_TABLE_INSTRUCTION gRootTable_root_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1220] + (const void *)&gInstructions[1221] }; const ND_TABLE_INSTRUCTION gRootTable_root_d6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1227] + (const void *)&gInstructions[1228] }; const ND_TABLE_INSTRUCTION gRootTable_root_18_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1236] + (const void *)&gInstructions[1237] }; const ND_TABLE_INSTRUCTION gRootTable_root_19_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1237] + (const void *)&gInstructions[1238] }; const ND_TABLE_INSTRUCTION gRootTable_root_1a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1238] + (const void *)&gInstructions[1239] }; const ND_TABLE_INSTRUCTION gRootTable_root_1b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1239] + (const void *)&gInstructions[1240] }; const ND_TABLE_INSTRUCTION gRootTable_root_1c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1240] + (const void *)&gInstructions[1241] }; const ND_TABLE_INSTRUCTION gRootTable_root_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1241] + (const void *)&gInstructions[1242] }; const ND_TABLE_INSTRUCTION gRootTable_root_ae_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1246] + (const void *)&gInstructions[1247] }; const ND_TABLE_INSTRUCTION gRootTable_root_ae_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1247] + (const void *)&gInstructions[1248] }; const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary = @@ -15998,13 +16015,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1248] + (const void *)&gInstructions[1249] }; const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1249] + (const void *)&gInstructions[1250] }; const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary = @@ -16025,13 +16042,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1250] + (const void *)&gInstructions[1251] }; const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1251] + (const void *)&gInstructions[1252] }; const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary = @@ -16052,13 +16069,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1252] + (const void *)&gInstructions[1253] }; const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1253] + (const void *)&gInstructions[1254] }; const ND_TABLE_AUXILIARY gRootTable_root_af_ds16_auxiliary = @@ -16092,31 +16109,31 @@ const ND_TABLE_DSIZE gRootTable_root_af_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_f9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1319] + (const void *)&gInstructions[1320] }; const ND_TABLE_INSTRUCTION gRootTable_root_fd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1320] + (const void *)&gInstructions[1321] }; const ND_TABLE_INSTRUCTION gRootTable_root_fb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1322] + (const void *)&gInstructions[1323] }; const ND_TABLE_INSTRUCTION gRootTable_root_aa_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1324] + (const void *)&gInstructions[1325] }; const ND_TABLE_INSTRUCTION gRootTable_root_aa_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1325] + (const void *)&gInstructions[1326] }; const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary = @@ -16137,13 +16154,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1326] + (const void *)&gInstructions[1327] }; const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1327] + (const void *)&gInstructions[1328] }; const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary = @@ -16164,13 +16181,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1328] + (const void *)&gInstructions[1329] }; const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1329] + (const void *)&gInstructions[1330] }; const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary = @@ -16191,13 +16208,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary = const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_None_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1330] + (const void *)&gInstructions[1331] }; const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_rep_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1331] + (const void *)&gInstructions[1332] }; const ND_TABLE_AUXILIARY gRootTable_root_ab_ds16_auxiliary = @@ -16231,163 +16248,163 @@ const ND_TABLE_DSIZE gRootTable_root_ab_dsize = const ND_TABLE_INSTRUCTION gRootTable_root_28_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1336] + (const void *)&gInstructions[1337] }; const ND_TABLE_INSTRUCTION gRootTable_root_29_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1337] + (const void *)&gInstructions[1338] }; const ND_TABLE_INSTRUCTION gRootTable_root_2a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1338] + (const void *)&gInstructions[1339] }; const ND_TABLE_INSTRUCTION gRootTable_root_2b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1339] + (const void *)&gInstructions[1340] }; const ND_TABLE_INSTRUCTION gRootTable_root_2c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1340] + (const void *)&gInstructions[1341] }; const ND_TABLE_INSTRUCTION gRootTable_root_2d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1341] + (const void *)&gInstructions[1342] }; const ND_TABLE_INSTRUCTION gRootTable_root_84_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1366] + (const void *)&gInstructions[1367] }; const ND_TABLE_INSTRUCTION gRootTable_root_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1367] + (const void *)&gInstructions[1368] }; const ND_TABLE_INSTRUCTION gRootTable_root_a8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1368] + (const void *)&gInstructions[1369] }; const ND_TABLE_INSTRUCTION gRootTable_root_a9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1369] + (const void *)&gInstructions[1370] }; const ND_TABLE_INSTRUCTION gRootTable_root_9b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2694] + (const void *)&gInstructions[2695] }; const ND_TABLE_INSTRUCTION gRootTable_root_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2712] + (const void *)&gInstructions[2713] }; const ND_TABLE_INSTRUCTION gRootTable_root_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2713] + (const void *)&gInstructions[2714] }; const ND_TABLE_INSTRUCTION gRootTable_root_91_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2715] + (const void *)&gInstructions[2716] }; const ND_TABLE_INSTRUCTION gRootTable_root_92_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2716] + (const void *)&gInstructions[2717] }; const ND_TABLE_INSTRUCTION gRootTable_root_93_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2717] + (const void *)&gInstructions[2718] }; const ND_TABLE_INSTRUCTION gRootTable_root_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2718] + (const void *)&gInstructions[2719] }; const ND_TABLE_INSTRUCTION gRootTable_root_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2719] + (const void *)&gInstructions[2720] }; const ND_TABLE_INSTRUCTION gRootTable_root_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2720] + (const void *)&gInstructions[2721] }; const ND_TABLE_INSTRUCTION gRootTable_root_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2721] + (const void *)&gInstructions[2722] }; const ND_TABLE_INSTRUCTION gRootTable_root_d7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2729] + (const void *)&gInstructions[2730] }; const ND_TABLE_INSTRUCTION gRootTable_root_30_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2730] + (const void *)&gInstructions[2731] }; const ND_TABLE_INSTRUCTION gRootTable_root_31_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2731] + (const void *)&gInstructions[2732] }; const ND_TABLE_INSTRUCTION gRootTable_root_32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2732] + (const void *)&gInstructions[2733] }; const ND_TABLE_INSTRUCTION gRootTable_root_33_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2733] + (const void *)&gInstructions[2734] }; const ND_TABLE_INSTRUCTION gRootTable_root_34_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2734] + (const void *)&gInstructions[2735] }; const ND_TABLE_INSTRUCTION gRootTable_root_35_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2735] + (const void *)&gInstructions[2736] }; const ND_TABLE_OPCODE gRootTable_root_opcode = diff --git a/bddisasm/include/table_vex.h b/bddisasm/include/table_vex.h index 65d1f85..7fd42da 100644 --- a/bddisasm/include/table_vex.h +++ b/bddisasm/include/table_vex.h @@ -58,7 +58,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_00_l = const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1234] + (const void *)&gInstructions[1235] }; const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l = @@ -75,7 +75,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l = const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1293] + (const void *)&gInstructions[1294] }; const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l = @@ -92,7 +92,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l = const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1302] + (const void *)&gInstructions[1303] }; const ND_TABLE_VEX_L gVexTable_root_02_f7_03_l = @@ -892,7 +892,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_mem_modrmreg = const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_reg_00_00_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1377] + (const void *)&gInstructions[1378] }; const ND_TABLE_VEX_W gVexTable_root_02_49_00_reg_00_00_00_w = @@ -957,7 +957,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_00_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_49_01_mem_00_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1334] + (const void *)&gInstructions[1335] }; const ND_TABLE_VEX_W gVexTable_root_02_49_01_mem_00_00_w = @@ -1007,7 +1007,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_49_03_reg_00_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1379] + (const void *)&gInstructions[1380] }; const ND_TABLE_VEX_W gVexTable_root_02_49_03_reg_00_00_w = @@ -1096,7 +1096,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_02_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1360] + (const void *)&gInstructions[1361] }; const ND_TABLE_VEX_W gVexTable_root_02_5c_02_reg_00_w = @@ -1131,7 +1131,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5c_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_03_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1365] + (const void *)&gInstructions[1366] }; const ND_TABLE_VEX_W gVexTable_root_02_5c_03_reg_00_w = @@ -1177,7 +1177,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_03_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1361] + (const void *)&gInstructions[1362] }; const ND_TABLE_VEX_W gVexTable_root_02_5e_03_reg_00_w = @@ -1212,7 +1212,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_02_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1362] + (const void *)&gInstructions[1363] }; const ND_TABLE_VEX_W gVexTable_root_02_5e_02_reg_00_w = @@ -1247,7 +1247,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1363] + (const void *)&gInstructions[1364] }; const ND_TABLE_VEX_W gVexTable_root_02_5e_01_reg_00_w = @@ -1282,7 +1282,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_00_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1364] + (const void *)&gInstructions[1365] }; const ND_TABLE_VEX_W gVexTable_root_02_5e_00_reg_00_w = @@ -1328,7 +1328,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_03_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1375] + (const void *)&gInstructions[1376] }; const ND_TABLE_VEX_W gVexTable_root_02_4b_03_mem_00_w = @@ -1363,7 +1363,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_01_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1376] + (const void *)&gInstructions[1377] }; const ND_TABLE_VEX_W gVexTable_root_02_4b_01_mem_00_w = @@ -1398,7 +1398,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_02_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1378] + (const void *)&gInstructions[1379] }; const ND_TABLE_VEX_W gVexTable_root_02_4b_02_mem_00_w = @@ -1444,7 +1444,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_4b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_de_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1413] + (const void *)&gInstructions[1414] }; const ND_TABLE_VEX_PP gVexTable_root_02_de_pp = @@ -1461,7 +1461,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_de_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_df_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1415] + (const void *)&gInstructions[1416] }; const ND_TABLE_VEX_PP gVexTable_root_02_df_pp = @@ -1478,7 +1478,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_df_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_dc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1417] + (const void *)&gInstructions[1418] }; const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp = @@ -1495,7 +1495,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_dd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1419] + (const void *)&gInstructions[1420] }; const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp = @@ -1512,7 +1512,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_db_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1420] + (const void *)&gInstructions[1421] }; const ND_TABLE_VEX_L gVexTable_root_02_db_01_l = @@ -1540,7 +1540,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_db_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b1_02_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1432] + (const void *)&gInstructions[1433] }; const ND_TABLE_VEX_W gVexTable_root_02_b1_02_mem_w = @@ -1564,7 +1564,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_b1_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_b1_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1433] + (const void *)&gInstructions[1434] }; const ND_TABLE_VEX_W gVexTable_root_02_b1_01_mem_w = @@ -1599,7 +1599,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b1_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_1a_01_mem_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1440] + (const void *)&gInstructions[1441] }; const ND_TABLE_VEX_W gVexTable_root_02_1a_01_mem_01_w = @@ -1645,7 +1645,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_5a_01_mem_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1446] + (const void *)&gInstructions[1447] }; const ND_TABLE_VEX_W gVexTable_root_02_5a_01_mem_01_w = @@ -1691,7 +1691,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_19_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1453] + (const void *)&gInstructions[1454] }; const ND_TABLE_VEX_W gVexTable_root_02_19_01_w = @@ -1717,7 +1717,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_19_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_18_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1455] + (const void *)&gInstructions[1456] }; const ND_TABLE_VEX_W gVexTable_root_02_18_01_w = @@ -1743,7 +1743,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_18_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_02_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1480] + (const void *)&gInstructions[1481] }; const ND_TABLE_VEX_W gVexTable_root_02_b0_02_mem_w = @@ -1767,7 +1767,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1481] + (const void *)&gInstructions[1482] }; const ND_TABLE_VEX_W gVexTable_root_02_b0_01_mem_w = @@ -1791,7 +1791,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_03_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1482] + (const void *)&gInstructions[1483] }; const ND_TABLE_VEX_W gVexTable_root_02_b0_03_mem_w = @@ -1815,7 +1815,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1483] + (const void *)&gInstructions[1484] }; const ND_TABLE_VEX_W gVexTable_root_02_b0_00_mem_w = @@ -1850,7 +1850,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_72_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1485] + (const void *)&gInstructions[1486] }; const ND_TABLE_VEX_W gVexTable_root_02_72_02_w = @@ -1876,7 +1876,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_72_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1498] + (const void *)&gInstructions[1499] }; const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w = @@ -1891,7 +1891,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w = const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1499] + (const void *)&gInstructions[1500] }; const ND_TABLE_VEX_W gVexTable_root_02_13_01_01_w = @@ -1928,13 +1928,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_13_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1622] + (const void *)&gInstructions[1623] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1625] + (const void *)&gInstructions[1626] }; const ND_TABLE_VEX_W gVexTable_root_02_98_01_w = @@ -1960,13 +1960,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_98_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1627] + (const void *)&gInstructions[1628] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1630] + (const void *)&gInstructions[1631] }; const ND_TABLE_VEX_W gVexTable_root_02_99_01_w = @@ -1992,13 +1992,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_99_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1632] + (const void *)&gInstructions[1633] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1635] + (const void *)&gInstructions[1636] }; const ND_TABLE_VEX_W gVexTable_root_02_a8_01_w = @@ -2024,13 +2024,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1637] + (const void *)&gInstructions[1638] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1640] + (const void *)&gInstructions[1641] }; const ND_TABLE_VEX_W gVexTable_root_02_a9_01_w = @@ -2056,13 +2056,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1642] + (const void *)&gInstructions[1643] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1645] + (const void *)&gInstructions[1646] }; const ND_TABLE_VEX_W gVexTable_root_02_b8_01_w = @@ -2088,13 +2088,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1647] + (const void *)&gInstructions[1648] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1650] + (const void *)&gInstructions[1651] }; const ND_TABLE_VEX_W gVexTable_root_02_b9_01_w = @@ -2120,13 +2120,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1662] + (const void *)&gInstructions[1663] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1665] + (const void *)&gInstructions[1666] }; const ND_TABLE_VEX_W gVexTable_root_02_96_01_w = @@ -2152,13 +2152,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_96_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1667] + (const void *)&gInstructions[1668] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1670] + (const void *)&gInstructions[1671] }; const ND_TABLE_VEX_W gVexTable_root_02_a6_01_w = @@ -2184,13 +2184,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1672] + (const void *)&gInstructions[1673] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1675] + (const void *)&gInstructions[1676] }; const ND_TABLE_VEX_W gVexTable_root_02_b6_01_w = @@ -2216,13 +2216,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1681] + (const void *)&gInstructions[1682] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1684] + (const void *)&gInstructions[1685] }; const ND_TABLE_VEX_W gVexTable_root_02_9a_01_w = @@ -2248,13 +2248,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1686] + (const void *)&gInstructions[1687] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1689] + (const void *)&gInstructions[1690] }; const ND_TABLE_VEX_W gVexTable_root_02_9b_01_w = @@ -2280,13 +2280,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1691] + (const void *)&gInstructions[1692] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1694] + (const void *)&gInstructions[1695] }; const ND_TABLE_VEX_W gVexTable_root_02_aa_01_w = @@ -2312,13 +2312,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_aa_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1696] + (const void *)&gInstructions[1697] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1699] + (const void *)&gInstructions[1700] }; const ND_TABLE_VEX_W gVexTable_root_02_ab_01_w = @@ -2344,13 +2344,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ab_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1701] + (const void *)&gInstructions[1702] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1704] + (const void *)&gInstructions[1705] }; const ND_TABLE_VEX_W gVexTable_root_02_ba_01_w = @@ -2376,13 +2376,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ba_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1706] + (const void *)&gInstructions[1707] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1709] + (const void *)&gInstructions[1710] }; const ND_TABLE_VEX_W gVexTable_root_02_bb_01_w = @@ -2408,13 +2408,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bb_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1711] + (const void *)&gInstructions[1712] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1714] + (const void *)&gInstructions[1715] }; const ND_TABLE_VEX_W gVexTable_root_02_97_01_w = @@ -2440,13 +2440,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_97_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1716] + (const void *)&gInstructions[1717] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1719] + (const void *)&gInstructions[1720] }; const ND_TABLE_VEX_W gVexTable_root_02_a7_01_w = @@ -2472,13 +2472,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1721] + (const void *)&gInstructions[1722] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1724] + (const void *)&gInstructions[1725] }; const ND_TABLE_VEX_W gVexTable_root_02_b7_01_w = @@ -2504,13 +2504,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1740] + (const void *)&gInstructions[1741] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1743] + (const void *)&gInstructions[1744] }; const ND_TABLE_VEX_W gVexTable_root_02_9c_01_w = @@ -2536,13 +2536,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1745] + (const void *)&gInstructions[1746] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1748] + (const void *)&gInstructions[1749] }; const ND_TABLE_VEX_W gVexTable_root_02_9d_01_w = @@ -2568,13 +2568,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1750] + (const void *)&gInstructions[1751] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1753] + (const void *)&gInstructions[1754] }; const ND_TABLE_VEX_W gVexTable_root_02_ac_01_w = @@ -2600,13 +2600,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ac_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1755] + (const void *)&gInstructions[1756] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1758] + (const void *)&gInstructions[1759] }; const ND_TABLE_VEX_W gVexTable_root_02_ad_01_w = @@ -2632,13 +2632,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ad_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1760] + (const void *)&gInstructions[1761] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1763] + (const void *)&gInstructions[1764] }; const ND_TABLE_VEX_W gVexTable_root_02_bc_01_w = @@ -2664,13 +2664,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bc_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1765] + (const void *)&gInstructions[1766] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1768] + (const void *)&gInstructions[1769] }; const ND_TABLE_VEX_W gVexTable_root_02_bd_01_w = @@ -2696,13 +2696,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bd_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1778] + (const void *)&gInstructions[1779] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1781] + (const void *)&gInstructions[1782] }; const ND_TABLE_VEX_W gVexTable_root_02_9e_01_w = @@ -2728,13 +2728,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1783] + (const void *)&gInstructions[1784] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1786] + (const void *)&gInstructions[1787] }; const ND_TABLE_VEX_W gVexTable_root_02_9f_01_w = @@ -2760,13 +2760,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1788] + (const void *)&gInstructions[1789] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1791] + (const void *)&gInstructions[1792] }; const ND_TABLE_VEX_W gVexTable_root_02_ae_01_w = @@ -2792,13 +2792,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ae_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1793] + (const void *)&gInstructions[1794] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1796] + (const void *)&gInstructions[1797] }; const ND_TABLE_VEX_W gVexTable_root_02_af_01_w = @@ -2824,13 +2824,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_af_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1798] + (const void *)&gInstructions[1799] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1801] + (const void *)&gInstructions[1802] }; const ND_TABLE_VEX_W gVexTable_root_02_be_01_w = @@ -2856,13 +2856,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_be_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1803] + (const void *)&gInstructions[1804] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1806] + (const void *)&gInstructions[1807] }; const ND_TABLE_VEX_W gVexTable_root_02_bf_01_w = @@ -2888,13 +2888,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bf_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1826] + (const void *)&gInstructions[1827] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1828] + (const void *)&gInstructions[1829] }; const ND_TABLE_VEX_W gVexTable_root_02_92_01_mem_w = @@ -2929,13 +2929,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_92_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1838] + (const void *)&gInstructions[1839] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1840] + (const void *)&gInstructions[1841] }; const ND_TABLE_VEX_W gVexTable_root_02_93_01_mem_w = @@ -2970,7 +2970,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_93_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_cf_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1858] + (const void *)&gInstructions[1859] }; const ND_TABLE_VEX_W gVexTable_root_02_cf_01_w = @@ -2996,7 +2996,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_cf_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2d_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1880] + (const void *)&gInstructions[1881] }; const ND_TABLE_VEX_W gVexTable_root_02_2d_01_mem_w = @@ -3031,7 +3031,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2f_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1881] + (const void *)&gInstructions[1882] }; const ND_TABLE_VEX_W gVexTable_root_02_2f_01_mem_w = @@ -3066,7 +3066,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2c_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1882] + (const void *)&gInstructions[1883] }; const ND_TABLE_VEX_W gVexTable_root_02_2c_01_mem_w = @@ -3101,7 +3101,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2e_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1883] + (const void *)&gInstructions[1884] }; const ND_TABLE_VEX_W gVexTable_root_02_2e_01_mem_w = @@ -3136,7 +3136,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2a_01_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1971] + (const void *)&gInstructions[1972] }; const ND_TABLE_MODRM_MOD gVexTable_root_02_2a_01_modrmmod = @@ -3162,7 +3162,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_1c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2049] + (const void *)&gInstructions[2050] }; const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp = @@ -3179,7 +3179,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_1e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2051] + (const void *)&gInstructions[2052] }; const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp = @@ -3196,7 +3196,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_1d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2054] + (const void *)&gInstructions[2055] }; const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp = @@ -3213,7 +3213,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_2b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2060] + (const void *)&gInstructions[2061] }; const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp = @@ -3230,7 +3230,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2100] + (const void *)&gInstructions[2101] }; const ND_TABLE_VEX_W gVexTable_root_02_78_01_w = @@ -3256,7 +3256,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_78_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_58_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2103] + (const void *)&gInstructions[2104] }; const ND_TABLE_VEX_W gVexTable_root_02_58_01_w = @@ -3282,7 +3282,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_58_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_59_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2108] + (const void *)&gInstructions[2109] }; const ND_TABLE_VEX_W gVexTable_root_02_59_01_w = @@ -3308,7 +3308,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_59_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2111] + (const void *)&gInstructions[2112] }; const ND_TABLE_VEX_W gVexTable_root_02_79_01_w = @@ -3334,7 +3334,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_79_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_29_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2123] + (const void *)&gInstructions[2124] }; const ND_TABLE_VEX_PP gVexTable_root_02_29_pp = @@ -3351,7 +3351,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_29_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_37_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2133] + (const void *)&gInstructions[2134] }; const ND_TABLE_VEX_PP gVexTable_root_02_37_pp = @@ -3368,7 +3368,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_37_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_50_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2158] + (const void *)&gInstructions[2159] }; const ND_TABLE_VEX_W gVexTable_root_02_50_03_w = @@ -3383,7 +3383,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_50_03_w = const ND_TABLE_INSTRUCTION gVexTable_root_02_50_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2160] + (const void *)&gInstructions[2161] }; const ND_TABLE_VEX_W gVexTable_root_02_50_02_w = @@ -3398,7 +3398,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_50_02_w = const ND_TABLE_INSTRUCTION gVexTable_root_02_50_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2163] + (const void *)&gInstructions[2164] }; const ND_TABLE_VEX_W gVexTable_root_02_50_01_w = @@ -3413,7 +3413,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_50_01_w = const ND_TABLE_INSTRUCTION gVexTable_root_02_50_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2166] + (const void *)&gInstructions[2167] }; const ND_TABLE_VEX_W gVexTable_root_02_50_00_w = @@ -3439,7 +3439,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_50_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_51_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2159] + (const void *)&gInstructions[2160] }; const ND_TABLE_VEX_W gVexTable_root_02_51_03_w = @@ -3454,7 +3454,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_51_03_w = const ND_TABLE_INSTRUCTION gVexTable_root_02_51_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2161] + (const void *)&gInstructions[2162] }; const ND_TABLE_VEX_W gVexTable_root_02_51_02_w = @@ -3469,7 +3469,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_51_02_w = const ND_TABLE_INSTRUCTION gVexTable_root_02_51_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2165] + (const void *)&gInstructions[2166] }; const ND_TABLE_VEX_W gVexTable_root_02_51_01_w = @@ -3484,7 +3484,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_51_01_w = const ND_TABLE_INSTRUCTION gVexTable_root_02_51_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2167] + (const void *)&gInstructions[2168] }; const ND_TABLE_VEX_W gVexTable_root_02_51_00_w = @@ -3510,7 +3510,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_51_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_52_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2169] + (const void *)&gInstructions[2170] }; const ND_TABLE_VEX_W gVexTable_root_02_52_01_w = @@ -3536,7 +3536,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_52_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_53_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2171] + (const void *)&gInstructions[2172] }; const ND_TABLE_VEX_W gVexTable_root_02_53_01_w = @@ -3562,7 +3562,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_53_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_36_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2176] + (const void *)&gInstructions[2177] }; const ND_TABLE_VEX_W gVexTable_root_02_36_01_01_w = @@ -3599,7 +3599,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_36_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2189] + (const void *)&gInstructions[2190] }; const ND_TABLE_VEX_W gVexTable_root_02_0d_01_w = @@ -3625,7 +3625,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2193] + (const void *)&gInstructions[2194] }; const ND_TABLE_VEX_W gVexTable_root_02_0c_01_w = @@ -3651,7 +3651,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_16_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2201] + (const void *)&gInstructions[2202] }; const ND_TABLE_VEX_W gVexTable_root_02_16_01_01_w = @@ -3688,13 +3688,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_16_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2235] + (const void *)&gInstructions[2236] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2237] + (const void *)&gInstructions[2238] }; const ND_TABLE_VEX_W gVexTable_root_02_90_01_mem_w = @@ -3729,13 +3729,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_90_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2239] + (const void *)&gInstructions[2240] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2241] + (const void *)&gInstructions[2242] }; const ND_TABLE_VEX_W gVexTable_root_02_91_01_mem_w = @@ -3770,7 +3770,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_91_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2245] + (const void *)&gInstructions[2246] }; const ND_TABLE_VEX_PP gVexTable_root_02_02_pp = @@ -3787,7 +3787,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_02_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2247] + (const void *)&gInstructions[2248] }; const ND_TABLE_VEX_PP gVexTable_root_02_03_pp = @@ -3804,7 +3804,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_03_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2254] + (const void *)&gInstructions[2255] }; const ND_TABLE_VEX_PP gVexTable_root_02_01_pp = @@ -3821,7 +3821,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_01_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_41_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2257] + (const void *)&gInstructions[2258] }; const ND_TABLE_VEX_L gVexTable_root_02_41_01_l = @@ -3849,7 +3849,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_41_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_06_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2259] + (const void *)&gInstructions[2260] }; const ND_TABLE_VEX_PP gVexTable_root_02_06_pp = @@ -3866,7 +3866,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_06_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_07_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2261] + (const void *)&gInstructions[2262] }; const ND_TABLE_VEX_PP gVexTable_root_02_07_pp = @@ -3883,7 +3883,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_07_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_05_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2262] + (const void *)&gInstructions[2263] }; const ND_TABLE_VEX_PP gVexTable_root_02_05_pp = @@ -3900,7 +3900,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_05_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b5_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2291] + (const void *)&gInstructions[2292] }; const ND_TABLE_VEX_W gVexTable_root_02_b5_01_w = @@ -3926,7 +3926,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_b4_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2293] + (const void *)&gInstructions[2294] }; const ND_TABLE_VEX_W gVexTable_root_02_b4_01_w = @@ -3952,7 +3952,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_04_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2295] + (const void *)&gInstructions[2296] }; const ND_TABLE_VEX_PP gVexTable_root_02_04_pp = @@ -3969,13 +3969,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_04_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2298] + (const void *)&gInstructions[2299] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2300] + (const void *)&gInstructions[2301] }; const ND_TABLE_VEX_W gVexTable_root_02_8c_01_mem_w = @@ -4010,13 +4010,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2299] + (const void *)&gInstructions[2300] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2301] + (const void *)&gInstructions[2302] }; const ND_TABLE_VEX_W gVexTable_root_02_8e_01_mem_w = @@ -4051,7 +4051,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2303] + (const void *)&gInstructions[2304] }; const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp = @@ -4068,7 +4068,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2305] + (const void *)&gInstructions[2306] }; const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp = @@ -4085,7 +4085,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2312] + (const void *)&gInstructions[2313] }; const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp = @@ -4102,7 +4102,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2315] + (const void *)&gInstructions[2316] }; const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp = @@ -4119,7 +4119,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_38_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2317] + (const void *)&gInstructions[2318] }; const ND_TABLE_VEX_PP gVexTable_root_02_38_pp = @@ -4136,7 +4136,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_38_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_39_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2319] + (const void *)&gInstructions[2320] }; const ND_TABLE_VEX_PP gVexTable_root_02_39_pp = @@ -4153,7 +4153,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_39_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2326] + (const void *)&gInstructions[2327] }; const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp = @@ -4170,7 +4170,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_3a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2329] + (const void *)&gInstructions[2330] }; const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp = @@ -4187,13 +4187,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2350] + (const void *)&gInstructions[2351] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2351] + (const void *)&gInstructions[2352] }; const ND_TABLE_VEX_L gVexTable_root_02_21_01_l = @@ -4221,13 +4221,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_21_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2353] + (const void *)&gInstructions[2354] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2354] + (const void *)&gInstructions[2355] }; const ND_TABLE_VEX_L gVexTable_root_02_22_01_l = @@ -4255,13 +4255,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_22_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2356] + (const void *)&gInstructions[2357] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2357] + (const void *)&gInstructions[2358] }; const ND_TABLE_VEX_L gVexTable_root_02_20_01_l = @@ -4289,13 +4289,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_20_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2359] + (const void *)&gInstructions[2360] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2360] + (const void *)&gInstructions[2361] }; const ND_TABLE_VEX_L gVexTable_root_02_25_01_l = @@ -4323,13 +4323,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_25_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2362] + (const void *)&gInstructions[2363] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2363] + (const void *)&gInstructions[2364] }; const ND_TABLE_VEX_L gVexTable_root_02_23_01_l = @@ -4357,13 +4357,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_23_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2365] + (const void *)&gInstructions[2366] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2366] + (const void *)&gInstructions[2367] }; const ND_TABLE_VEX_L gVexTable_root_02_24_01_l = @@ -4391,13 +4391,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_24_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2376] + (const void *)&gInstructions[2377] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2377] + (const void *)&gInstructions[2378] }; const ND_TABLE_VEX_L gVexTable_root_02_31_01_l = @@ -4425,13 +4425,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_31_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2379] + (const void *)&gInstructions[2380] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2380] + (const void *)&gInstructions[2381] }; const ND_TABLE_VEX_L gVexTable_root_02_32_01_l = @@ -4459,13 +4459,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_32_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2382] + (const void *)&gInstructions[2383] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2383] + (const void *)&gInstructions[2384] }; const ND_TABLE_VEX_L gVexTable_root_02_30_01_l = @@ -4493,13 +4493,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_30_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2385] + (const void *)&gInstructions[2386] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2386] + (const void *)&gInstructions[2387] }; const ND_TABLE_VEX_L gVexTable_root_02_35_01_l = @@ -4527,13 +4527,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_35_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2388] + (const void *)&gInstructions[2389] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2389] + (const void *)&gInstructions[2390] }; const ND_TABLE_VEX_L gVexTable_root_02_33_01_l = @@ -4561,13 +4561,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_33_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2391] + (const void *)&gInstructions[2392] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2392] + (const void *)&gInstructions[2393] }; const ND_TABLE_VEX_L gVexTable_root_02_34_01_l = @@ -4595,7 +4595,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_34_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_28_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2394] + (const void *)&gInstructions[2395] }; const ND_TABLE_VEX_PP gVexTable_root_02_28_pp = @@ -4612,7 +4612,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_28_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2396] + (const void *)&gInstructions[2397] }; const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp = @@ -4629,7 +4629,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_40_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2402] + (const void *)&gInstructions[2403] }; const ND_TABLE_VEX_PP gVexTable_root_02_40_pp = @@ -4646,7 +4646,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_40_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2473] + (const void *)&gInstructions[2474] }; const ND_TABLE_VEX_PP gVexTable_root_02_00_pp = @@ -4663,7 +4663,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_00_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_08_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2481] + (const void *)&gInstructions[2482] }; const ND_TABLE_VEX_PP gVexTable_root_02_08_pp = @@ -4680,7 +4680,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_08_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2482] + (const void *)&gInstructions[2483] }; const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp = @@ -4697,7 +4697,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_09_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2483] + (const void *)&gInstructions[2484] }; const ND_TABLE_VEX_PP gVexTable_root_02_09_pp = @@ -4714,13 +4714,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_09_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2495] + (const void *)&gInstructions[2496] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2497] + (const void *)&gInstructions[2498] }; const ND_TABLE_VEX_W gVexTable_root_02_47_01_w = @@ -4746,7 +4746,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_47_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_46_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2510] + (const void *)&gInstructions[2511] }; const ND_TABLE_VEX_W gVexTable_root_02_46_01_w = @@ -4772,13 +4772,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_46_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2528] + (const void *)&gInstructions[2529] }; const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2530] + (const void *)&gInstructions[2531] }; const ND_TABLE_VEX_W gVexTable_root_02_45_01_w = @@ -4804,7 +4804,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_45_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_17_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2554] + (const void *)&gInstructions[2555] }; const ND_TABLE_VEX_PP gVexTable_root_02_17_pp = @@ -4821,7 +4821,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_17_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2673] + (const void *)&gInstructions[2674] }; const ND_TABLE_VEX_W gVexTable_root_02_0f_01_w = @@ -4847,7 +4847,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_02_0e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2674] + (const void *)&gInstructions[2675] }; const ND_TABLE_VEX_W gVexTable_root_02_0e_01_w = @@ -5157,7 +5157,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_mem_modrmreg = const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1313] + (const void *)&gInstructions[1314] }; const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_reg_modrmreg = @@ -5238,13 +5238,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1878] + (const void *)&gInstructions[1879] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2662] + (const void *)&gInstructions[2663] }; const ND_TABLE_MODRM_REG gVexTable_root_01_ae_00_mem_modrmreg = @@ -6795,25 +6795,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_47_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_58_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1401] + (const void *)&gInstructions[1402] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_58_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1404] + (const void *)&gInstructions[1405] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_58_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1406] + (const void *)&gInstructions[1407] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_58_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1409] + (const void *)&gInstructions[1410] }; const ND_TABLE_VEX_PP gVexTable_root_01_58_pp = @@ -6830,13 +6830,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_58_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1410] + (const void *)&gInstructions[1411] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1411] + (const void *)&gInstructions[1412] }; const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp = @@ -6853,13 +6853,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_55_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1425] + (const void *)&gInstructions[1426] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_55_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1427] + (const void *)&gInstructions[1428] }; const ND_TABLE_VEX_PP gVexTable_root_01_55_pp = @@ -6876,13 +6876,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_55_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_54_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1429] + (const void *)&gInstructions[1430] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_54_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1431] + (const void *)&gInstructions[1432] }; const ND_TABLE_VEX_PP gVexTable_root_01_54_pp = @@ -6899,25 +6899,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_54_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1457] + (const void *)&gInstructions[1458] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1460] + (const void *)&gInstructions[1461] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1462] + (const void *)&gInstructions[1463] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1465] + (const void *)&gInstructions[1466] }; const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp = @@ -6934,13 +6934,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1467] + (const void *)&gInstructions[1468] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1470] + (const void *)&gInstructions[1471] }; const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp = @@ -6957,13 +6957,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1474] + (const void *)&gInstructions[1475] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1475] + (const void *)&gInstructions[1476] }; const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l = @@ -6980,13 +6980,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1487] + (const void *)&gInstructions[1488] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1544] + (const void *)&gInstructions[1545] }; const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp = @@ -7003,19 +7003,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1478] + (const void *)&gInstructions[1479] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1507] + (const void *)&gInstructions[1508] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1555] + (const void *)&gInstructions[1556] }; const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp = @@ -7032,13 +7032,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1490] + (const void *)&gInstructions[1491] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1491] + (const void *)&gInstructions[1492] }; const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l = @@ -7055,13 +7055,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1509] + (const void *)&gInstructions[1510] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1510] + (const void *)&gInstructions[1511] }; const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l = @@ -7078,13 +7078,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1525] + (const void *)&gInstructions[1526] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1538] + (const void *)&gInstructions[1539] }; const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp = @@ -7101,13 +7101,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1523] + (const void *)&gInstructions[1524] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1541] + (const void *)&gInstructions[1542] }; const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp = @@ -7124,13 +7124,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1533] + (const void *)&gInstructions[1534] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1536] + (const void *)&gInstructions[1537] }; const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp = @@ -7147,13 +7147,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1560] + (const void *)&gInstructions[1561] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1565] + (const void *)&gInstructions[1566] }; const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp = @@ -7170,25 +7170,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1581] + (const void *)&gInstructions[1582] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1584] + (const void *)&gInstructions[1585] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1586] + (const void *)&gInstructions[1587] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1589] + (const void *)&gInstructions[1590] }; const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp = @@ -7205,13 +7205,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1859] + (const void *)&gInstructions[1860] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1860] + (const void *)&gInstructions[1861] }; const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp = @@ -7228,13 +7228,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1861] + (const void *)&gInstructions[1862] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1862] + (const void *)&gInstructions[1863] }; const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp = @@ -7251,7 +7251,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f0_03_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1877] + (const void *)&gInstructions[1878] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_f0_03_modrmmod = @@ -7277,7 +7277,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f7_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1879] + (const void *)&gInstructions[1880] }; const ND_TABLE_VEX_L gVexTable_root_01_f7_01_reg_l = @@ -7314,25 +7314,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1885] + (const void *)&gInstructions[1886] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1888] + (const void *)&gInstructions[1889] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1890] + (const void *)&gInstructions[1891] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1893] + (const void *)&gInstructions[1894] }; const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp = @@ -7349,25 +7349,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1900] + (const void *)&gInstructions[1901] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1903] + (const void *)&gInstructions[1904] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1905] + (const void *)&gInstructions[1906] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1908] + (const void *)&gInstructions[1909] }; const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp = @@ -7384,13 +7384,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_28_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1915] + (const void *)&gInstructions[1916] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_28_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1919] + (const void *)&gInstructions[1920] }; const ND_TABLE_VEX_PP gVexTable_root_01_28_pp = @@ -7407,13 +7407,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_28_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_29_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1916] + (const void *)&gInstructions[1917] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_29_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1920] + (const void *)&gInstructions[1921] }; const ND_TABLE_VEX_PP gVexTable_root_01_29_pp = @@ -7430,13 +7430,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_29_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1923] + (const void *)&gInstructions[1924] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1980] + (const void *)&gInstructions[1981] }; const ND_TABLE_VEX_W gVexTable_root_01_6e_01_00_wi = @@ -7473,13 +7473,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1924] + (const void *)&gInstructions[1925] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1981] + (const void *)&gInstructions[1982] }; const ND_TABLE_VEX_W gVexTable_root_01_7e_01_00_wi = @@ -7505,7 +7505,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_7e_01_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_02_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1982] + (const void *)&gInstructions[1983] }; const ND_TABLE_VEX_L gVexTable_root_01_7e_02_l = @@ -7533,13 +7533,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1928] + (const void *)&gInstructions[1929] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1929] + (const void *)&gInstructions[1930] }; const ND_TABLE_VEX_L gVexTable_root_01_12_03_l = @@ -7556,7 +7556,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_03_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1947] + (const void *)&gInstructions[1948] }; const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l = @@ -7573,7 +7573,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1964] + (const void *)&gInstructions[1965] }; const ND_TABLE_VEX_L gVexTable_root_01_12_00_mem_l = @@ -7599,7 +7599,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_00_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1960] + (const void *)&gInstructions[1961] }; const ND_TABLE_VEX_L gVexTable_root_01_12_01_mem_l = @@ -7625,7 +7625,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_12_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1999] + (const void *)&gInstructions[2000] }; const ND_TABLE_VEX_PP gVexTable_root_01_12_pp = @@ -7642,13 +7642,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_12_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1930] + (const void *)&gInstructions[1931] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1936] + (const void *)&gInstructions[1937] }; const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp = @@ -7665,13 +7665,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1931] + (const void *)&gInstructions[1932] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1937] + (const void *)&gInstructions[1938] }; const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp = @@ -7688,7 +7688,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_16_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1950] + (const void *)&gInstructions[1951] }; const ND_TABLE_VEX_L gVexTable_root_01_16_01_mem_l = @@ -7714,7 +7714,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1954] + (const void *)&gInstructions[1955] }; const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l = @@ -7731,7 +7731,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1957] + (const void *)&gInstructions[1958] }; const ND_TABLE_VEX_L gVexTable_root_01_16_00_reg_l = @@ -7757,7 +7757,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_00_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_16_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1997] + (const void *)&gInstructions[1998] }; const ND_TABLE_VEX_PP gVexTable_root_01_16_pp = @@ -7774,7 +7774,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_16_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_17_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1951] + (const void *)&gInstructions[1952] }; const ND_TABLE_VEX_L gVexTable_root_01_17_01_mem_l = @@ -7800,7 +7800,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_17_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_17_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1955] + (const void *)&gInstructions[1956] }; const ND_TABLE_VEX_L gVexTable_root_01_17_00_mem_l = @@ -7837,7 +7837,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_17_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_13_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1961] + (const void *)&gInstructions[1962] }; const ND_TABLE_VEX_L gVexTable_root_01_13_01_mem_l = @@ -7863,7 +7863,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_13_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_13_00_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1965] + (const void *)&gInstructions[1966] }; const ND_TABLE_VEX_L gVexTable_root_01_13_00_mem_l = @@ -7900,7 +7900,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_13_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_50_01_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1966] + (const void *)&gInstructions[1967] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod = @@ -7915,7 +7915,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_50_00_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1967] + (const void *)&gInstructions[1968] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_50_00_modrmmod = @@ -7941,7 +7941,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_50_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e7_01_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1969] + (const void *)&gInstructions[1970] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_e7_01_modrmmod = @@ -7967,7 +7967,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_01_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1973] + (const void *)&gInstructions[1974] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod = @@ -7982,7 +7982,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_00_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1975] + (const void *)&gInstructions[1976] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_00_modrmmod = @@ -8008,7 +8008,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d6_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1983] + (const void *)&gInstructions[1984] }; const ND_TABLE_VEX_L gVexTable_root_01_d6_01_l = @@ -8036,13 +8036,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1988] + (const void *)&gInstructions[1989] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1989] + (const void *)&gInstructions[1990] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod = @@ -8057,13 +8057,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2004] + (const void *)&gInstructions[2005] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2005] + (const void *)&gInstructions[2006] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod = @@ -8078,13 +8078,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_10_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2010] + (const void *)&gInstructions[2011] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_10_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2014] + (const void *)&gInstructions[2015] }; const ND_TABLE_VEX_PP gVexTable_root_01_10_pp = @@ -8101,13 +8101,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_10_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1990] + (const void *)&gInstructions[1991] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1991] + (const void *)&gInstructions[1992] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod = @@ -8122,13 +8122,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2006] + (const void *)&gInstructions[2007] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_mem_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2007] + (const void *)&gInstructions[2008] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod = @@ -8143,13 +8143,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod = const ND_TABLE_INSTRUCTION gVexTable_root_01_11_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2011] + (const void *)&gInstructions[2012] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_11_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2015] + (const void *)&gInstructions[2016] }; const ND_TABLE_VEX_PP gVexTable_root_01_11_pp = @@ -8166,25 +8166,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_11_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_59_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2028] + (const void *)&gInstructions[2029] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_59_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2031] + (const void *)&gInstructions[2032] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_59_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2033] + (const void *)&gInstructions[2034] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_59_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2036] + (const void *)&gInstructions[2037] }; const ND_TABLE_VEX_PP gVexTable_root_01_59_pp = @@ -8201,13 +8201,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_59_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_56_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2041] + (const void *)&gInstructions[2042] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_56_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2043] + (const void *)&gInstructions[2044] }; const ND_TABLE_VEX_PP gVexTable_root_01_56_pp = @@ -8224,7 +8224,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_56_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2056] + (const void *)&gInstructions[2057] }; const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp = @@ -8241,7 +8241,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_63_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2058] + (const void *)&gInstructions[2059] }; const ND_TABLE_VEX_PP gVexTable_root_01_63_pp = @@ -8258,7 +8258,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_63_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_67_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2062] + (const void *)&gInstructions[2063] }; const ND_TABLE_VEX_PP gVexTable_root_01_67_pp = @@ -8275,7 +8275,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_67_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2064] + (const void *)&gInstructions[2065] }; const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp = @@ -8292,7 +8292,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fe_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2066] + (const void *)&gInstructions[2067] }; const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp = @@ -8309,7 +8309,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d4_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2068] + (const void *)&gInstructions[2069] }; const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp = @@ -8326,7 +8326,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ec_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2070] + (const void *)&gInstructions[2071] }; const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp = @@ -8343,7 +8343,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ed_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2072] + (const void *)&gInstructions[2073] }; const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp = @@ -8360,7 +8360,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_dc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2074] + (const void *)&gInstructions[2075] }; const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp = @@ -8377,7 +8377,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_dd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2076] + (const void *)&gInstructions[2077] }; const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp = @@ -8394,7 +8394,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fd_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2078] + (const void *)&gInstructions[2079] }; const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp = @@ -8411,7 +8411,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_db_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2081] + (const void *)&gInstructions[2082] }; const ND_TABLE_VEX_PP gVexTable_root_01_db_pp = @@ -8428,7 +8428,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_db_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_df_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2083] + (const void *)&gInstructions[2084] }; const ND_TABLE_VEX_PP gVexTable_root_01_df_pp = @@ -8445,7 +8445,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_df_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e0_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2088] + (const void *)&gInstructions[2089] }; const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp = @@ -8462,7 +8462,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2090] + (const void *)&gInstructions[2091] }; const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp = @@ -8479,7 +8479,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_74_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2119] + (const void *)&gInstructions[2120] }; const ND_TABLE_VEX_PP gVexTable_root_01_74_pp = @@ -8496,7 +8496,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_74_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_76_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2121] + (const void *)&gInstructions[2122] }; const ND_TABLE_VEX_PP gVexTable_root_01_76_pp = @@ -8513,7 +8513,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_76_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_75_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2125] + (const void *)&gInstructions[2126] }; const ND_TABLE_VEX_PP gVexTable_root_01_75_pp = @@ -8530,7 +8530,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_75_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_64_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2129] + (const void *)&gInstructions[2130] }; const ND_TABLE_VEX_PP gVexTable_root_01_64_pp = @@ -8547,7 +8547,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_64_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_66_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2131] + (const void *)&gInstructions[2132] }; const ND_TABLE_VEX_PP gVexTable_root_01_66_pp = @@ -8564,7 +8564,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_66_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_65_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2135] + (const void *)&gInstructions[2136] }; const ND_TABLE_VEX_PP gVexTable_root_01_65_pp = @@ -8581,7 +8581,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_65_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_c5_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2231] + (const void *)&gInstructions[2232] }; const ND_TABLE_VEX_L gVexTable_root_01_c5_01_reg_l = @@ -8618,7 +8618,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2274] + (const void *)&gInstructions[2275] }; const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l = @@ -8635,7 +8635,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2275] + (const void *)&gInstructions[2276] }; const ND_TABLE_VEX_L gVexTable_root_01_c4_01_reg_l = @@ -8672,7 +8672,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2297] + (const void *)&gInstructions[2298] }; const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp = @@ -8689,7 +8689,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ee_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2308] + (const void *)&gInstructions[2309] }; const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp = @@ -8706,7 +8706,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_de_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2310] + (const void *)&gInstructions[2311] }; const ND_TABLE_VEX_PP gVexTable_root_01_de_pp = @@ -8723,7 +8723,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_de_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ea_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2322] + (const void *)&gInstructions[2323] }; const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp = @@ -8740,7 +8740,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_da_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2324] + (const void *)&gInstructions[2325] }; const ND_TABLE_VEX_PP gVexTable_root_01_da_pp = @@ -8757,7 +8757,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_da_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d7_01_reg_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2338] + (const void *)&gInstructions[2339] }; const ND_TABLE_MODRM_MOD gVexTable_root_01_d7_01_modrmmod = @@ -8783,7 +8783,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d7_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e4_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2398] + (const void *)&gInstructions[2399] }; const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp = @@ -8800,7 +8800,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2400] + (const void *)&gInstructions[2401] }; const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp = @@ -8817,7 +8817,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d5_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2405] + (const void *)&gInstructions[2406] }; const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp = @@ -8834,7 +8834,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f4_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2408] + (const void *)&gInstructions[2409] }; const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp = @@ -8851,7 +8851,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_eb_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2413] + (const void *)&gInstructions[2414] }; const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp = @@ -8868,7 +8868,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2439] + (const void *)&gInstructions[2440] }; const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp = @@ -8885,19 +8885,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_70_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2476] + (const void *)&gInstructions[2477] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_70_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2478] + (const void *)&gInstructions[2479] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_70_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2480] + (const void *)&gInstructions[2481] }; const ND_TABLE_VEX_PP gVexTable_root_01_70_pp = @@ -8914,19 +8914,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_70_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2486] + (const void *)&gInstructions[2487] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2505] + (const void *)&gInstructions[2506] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2519] + (const void *)&gInstructions[2520] }; const ND_TABLE_MODRM_REG gVexTable_root_01_72_01_reg_modrmreg = @@ -8967,7 +8967,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_72_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2487] + (const void *)&gInstructions[2488] }; const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp = @@ -8984,25 +8984,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2489] + (const void *)&gInstructions[2490] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2492] + (const void *)&gInstructions[2493] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2522] + (const void *)&gInstructions[2523] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2525] + (const void *)&gInstructions[2526] }; const ND_TABLE_MODRM_REG gVexTable_root_01_73_01_reg_modrmreg = @@ -9043,7 +9043,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_73_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2493] + (const void *)&gInstructions[2494] }; const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp = @@ -9060,19 +9060,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2501] + (const void *)&gInstructions[2502] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2515] + (const void *)&gInstructions[2516] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2534] + (const void *)&gInstructions[2535] }; const ND_TABLE_MODRM_REG gVexTable_root_01_71_01_reg_modrmreg = @@ -9113,7 +9113,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_71_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2502] + (const void *)&gInstructions[2503] }; const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp = @@ -9130,7 +9130,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2506] + (const void *)&gInstructions[2507] }; const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp = @@ -9147,7 +9147,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2516] + (const void *)&gInstructions[2517] }; const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp = @@ -9164,7 +9164,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2520] + (const void *)&gInstructions[2521] }; const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp = @@ -9181,7 +9181,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2526] + (const void *)&gInstructions[2527] }; const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp = @@ -9198,7 +9198,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d1_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2535] + (const void *)&gInstructions[2536] }; const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp = @@ -9215,7 +9215,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2537] + (const void *)&gInstructions[2538] }; const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp = @@ -9232,7 +9232,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fa_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2539] + (const void *)&gInstructions[2540] }; const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp = @@ -9249,7 +9249,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_fb_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2541] + (const void *)&gInstructions[2542] }; const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp = @@ -9266,7 +9266,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2543] + (const void *)&gInstructions[2544] }; const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp = @@ -9283,7 +9283,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_e9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2545] + (const void *)&gInstructions[2546] }; const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp = @@ -9300,7 +9300,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d8_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2547] + (const void *)&gInstructions[2548] }; const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp = @@ -9317,7 +9317,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_d9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2549] + (const void *)&gInstructions[2550] }; const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp = @@ -9334,7 +9334,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_f9_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2551] + (const void *)&gInstructions[2552] }; const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp = @@ -9351,7 +9351,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_68_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2564] + (const void *)&gInstructions[2565] }; const ND_TABLE_VEX_PP gVexTable_root_01_68_pp = @@ -9368,7 +9368,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_68_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2566] + (const void *)&gInstructions[2567] }; const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp = @@ -9385,7 +9385,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2568] + (const void *)&gInstructions[2569] }; const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp = @@ -9402,7 +9402,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_69_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2570] + (const void *)&gInstructions[2571] }; const ND_TABLE_VEX_PP gVexTable_root_01_69_pp = @@ -9419,7 +9419,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_69_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_60_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2572] + (const void *)&gInstructions[2573] }; const ND_TABLE_VEX_PP gVexTable_root_01_60_pp = @@ -9436,7 +9436,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_60_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_62_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2574] + (const void *)&gInstructions[2575] }; const ND_TABLE_VEX_PP gVexTable_root_01_62_pp = @@ -9453,7 +9453,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_62_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_6c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2576] + (const void *)&gInstructions[2577] }; const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp = @@ -9470,7 +9470,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_61_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2578] + (const void *)&gInstructions[2579] }; const ND_TABLE_VEX_PP gVexTable_root_01_61_pp = @@ -9487,7 +9487,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_61_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_ef_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2579] + (const void *)&gInstructions[2580] }; const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp = @@ -9504,13 +9504,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_53_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2595] + (const void *)&gInstructions[2596] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_53_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2597] + (const void *)&gInstructions[2598] }; const ND_TABLE_VEX_PP gVexTable_root_01_53_pp = @@ -9527,13 +9527,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_53_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_52_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2623] + (const void *)&gInstructions[2624] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_52_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2625] + (const void *)&gInstructions[2626] }; const ND_TABLE_VEX_PP gVexTable_root_01_52_pp = @@ -9550,13 +9550,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_52_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2649] + (const void *)&gInstructions[2650] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2651] + (const void *)&gInstructions[2652] }; const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp = @@ -9573,25 +9573,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_51_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2653] + (const void *)&gInstructions[2654] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_51_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2656] + (const void *)&gInstructions[2657] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_51_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2658] + (const void *)&gInstructions[2659] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_51_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2661] + (const void *)&gInstructions[2662] }; const ND_TABLE_VEX_PP gVexTable_root_01_51_pp = @@ -9608,25 +9608,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_51_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2664] + (const void *)&gInstructions[2665] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2667] + (const void *)&gInstructions[2668] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2669] + (const void *)&gInstructions[2670] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2672] + (const void *)&gInstructions[2673] }; const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp = @@ -9643,13 +9643,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2676] + (const void *)&gInstructions[2677] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2679] + (const void *)&gInstructions[2680] }; const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp = @@ -9666,13 +9666,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_15_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2681] + (const void *)&gInstructions[2682] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_15_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2683] + (const void *)&gInstructions[2684] }; const ND_TABLE_VEX_PP gVexTable_root_01_15_pp = @@ -9689,13 +9689,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_15_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_14_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2685] + (const void *)&gInstructions[2686] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_14_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2687] + (const void *)&gInstructions[2688] }; const ND_TABLE_VEX_PP gVexTable_root_01_14_pp = @@ -9712,13 +9712,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_14_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_57_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2689] + (const void *)&gInstructions[2690] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_57_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2691] + (const void *)&gInstructions[2692] }; const ND_TABLE_VEX_PP gVexTable_root_01_57_pp = @@ -9735,13 +9735,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_57_pp = const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2692] + (const void *)&gInstructions[2693] }; const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2693] + (const void *)&gInstructions[2694] }; const ND_TABLE_VEX_L gVexTable_root_01_77_00_l = @@ -10240,7 +10240,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_31_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_f0_03_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1208] + (const void *)&gInstructions[1209] }; const ND_TABLE_VEX_L gVexTable_root_03_f0_03_l = @@ -10268,7 +10268,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_f0_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_df_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1421] + (const void *)&gInstructions[1422] }; const ND_TABLE_VEX_L gVexTable_root_03_df_01_l = @@ -10296,7 +10296,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_df_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0d_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1436] + (const void *)&gInstructions[1437] }; const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp = @@ -10313,7 +10313,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0c_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1437] + (const void *)&gInstructions[1438] }; const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp = @@ -10330,7 +10330,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_4b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1438] + (const void *)&gInstructions[1439] }; const ND_TABLE_VEX_W gVexTable_root_03_4b_01_w = @@ -10356,7 +10356,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_4a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1439] + (const void *)&gInstructions[1440] }; const ND_TABLE_VEX_W gVexTable_root_03_4a_01_w = @@ -10382,7 +10382,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1512] + (const void *)&gInstructions[1513] }; const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w = @@ -10397,7 +10397,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w = const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1513] + (const void *)&gInstructions[1514] }; const ND_TABLE_VEX_W gVexTable_root_03_1d_01_01_w = @@ -10434,7 +10434,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_1d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_41_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1591] + (const void *)&gInstructions[1592] }; const ND_TABLE_VEX_L gVexTable_root_03_41_01_l = @@ -10462,7 +10462,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_41_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_40_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1592] + (const void *)&gInstructions[1593] }; const ND_TABLE_VEX_PP gVexTable_root_03_40_pp = @@ -10479,7 +10479,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_40_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_19_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1599] + (const void *)&gInstructions[1600] }; const ND_TABLE_VEX_W gVexTable_root_03_19_01_01_w = @@ -10516,7 +10516,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_19_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_39_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1604] + (const void *)&gInstructions[1605] }; const ND_TABLE_VEX_W gVexTable_root_03_39_01_01_w = @@ -10553,7 +10553,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_39_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1611] + (const void *)&gInstructions[1612] }; const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l = @@ -10570,7 +10570,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1612] + (const void *)&gInstructions[1613] }; const ND_TABLE_VEX_L gVexTable_root_03_17_01_reg_l = @@ -10607,13 +10607,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_17_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1653] + (const void *)&gInstructions[1654] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1654] + (const void *)&gInstructions[1655] }; const ND_TABLE_VEX_W gVexTable_root_03_69_01_w = @@ -10639,13 +10639,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_69_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1655] + (const void *)&gInstructions[1656] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1656] + (const void *)&gInstructions[1657] }; const ND_TABLE_VEX_W gVexTable_root_03_68_01_w = @@ -10671,13 +10671,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_68_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1657] + (const void *)&gInstructions[1658] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1658] + (const void *)&gInstructions[1659] }; const ND_TABLE_VEX_W gVexTable_root_03_6b_01_w = @@ -10703,13 +10703,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1659] + (const void *)&gInstructions[1660] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1660] + (const void *)&gInstructions[1661] }; const ND_TABLE_VEX_W gVexTable_root_03_6a_01_w = @@ -10735,13 +10735,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1676] + (const void *)&gInstructions[1677] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1677] + (const void *)&gInstructions[1678] }; const ND_TABLE_VEX_W gVexTable_root_03_5d_01_w = @@ -10767,13 +10767,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1678] + (const void *)&gInstructions[1679] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1679] + (const void *)&gInstructions[1680] }; const ND_TABLE_VEX_W gVexTable_root_03_5c_01_w = @@ -10799,13 +10799,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1725] + (const void *)&gInstructions[1726] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1726] + (const void *)&gInstructions[1727] }; const ND_TABLE_VEX_W gVexTable_root_03_5f_01_w = @@ -10831,13 +10831,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1727] + (const void *)&gInstructions[1728] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1728] + (const void *)&gInstructions[1729] }; const ND_TABLE_VEX_W gVexTable_root_03_5e_01_w = @@ -10863,13 +10863,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1729] + (const void *)&gInstructions[1730] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1730] + (const void *)&gInstructions[1731] }; const ND_TABLE_VEX_W gVexTable_root_03_6d_01_w = @@ -10895,13 +10895,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1731] + (const void *)&gInstructions[1732] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1732] + (const void *)&gInstructions[1733] }; const ND_TABLE_VEX_W gVexTable_root_03_6c_01_w = @@ -10927,13 +10927,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1733] + (const void *)&gInstructions[1734] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1734] + (const void *)&gInstructions[1735] }; const ND_TABLE_VEX_W gVexTable_root_03_6f_01_w = @@ -10959,13 +10959,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1735] + (const void *)&gInstructions[1736] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1736] + (const void *)&gInstructions[1737] }; const ND_TABLE_VEX_W gVexTable_root_03_6e_01_w = @@ -10991,13 +10991,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1769] + (const void *)&gInstructions[1770] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1770] + (const void *)&gInstructions[1771] }; const ND_TABLE_VEX_W gVexTable_root_03_79_01_w = @@ -11023,13 +11023,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_79_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1771] + (const void *)&gInstructions[1772] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1772] + (const void *)&gInstructions[1773] }; const ND_TABLE_VEX_W gVexTable_root_03_78_01_w = @@ -11055,13 +11055,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_78_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1773] + (const void *)&gInstructions[1774] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1774] + (const void *)&gInstructions[1775] }; const ND_TABLE_VEX_W gVexTable_root_03_7b_01_w = @@ -11087,13 +11087,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1775] + (const void *)&gInstructions[1776] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1776] + (const void *)&gInstructions[1777] }; const ND_TABLE_VEX_W gVexTable_root_03_7a_01_w = @@ -11119,13 +11119,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7a_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1807] + (const void *)&gInstructions[1808] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1808] + (const void *)&gInstructions[1809] }; const ND_TABLE_VEX_W gVexTable_root_03_7d_01_w = @@ -11151,13 +11151,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7d_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1809] + (const void *)&gInstructions[1810] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1810] + (const void *)&gInstructions[1811] }; const ND_TABLE_VEX_W gVexTable_root_03_7c_01_w = @@ -11183,13 +11183,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1811] + (const void *)&gInstructions[1812] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1812] + (const void *)&gInstructions[1813] }; const ND_TABLE_VEX_W gVexTable_root_03_7f_01_w = @@ -11215,13 +11215,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1813] + (const void *)&gInstructions[1814] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1814] + (const void *)&gInstructions[1815] }; const ND_TABLE_VEX_W gVexTable_root_03_7e_01_w = @@ -11247,7 +11247,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_cf_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1854] + (const void *)&gInstructions[1855] }; const ND_TABLE_VEX_W gVexTable_root_03_cf_01_w = @@ -11273,7 +11273,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_cf_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_ce_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1856] + (const void *)&gInstructions[1857] }; const ND_TABLE_VEX_W gVexTable_root_03_ce_01_w = @@ -11299,7 +11299,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_ce_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_18_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1863] + (const void *)&gInstructions[1864] }; const ND_TABLE_VEX_W gVexTable_root_03_18_01_01_w = @@ -11336,7 +11336,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_18_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_38_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1868] + (const void *)&gInstructions[1869] }; const ND_TABLE_VEX_W gVexTable_root_03_38_01_01_w = @@ -11373,7 +11373,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_38_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1875] + (const void *)&gInstructions[1876] }; const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l = @@ -11390,7 +11390,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1876] + (const void *)&gInstructions[1877] }; const ND_TABLE_VEX_L gVexTable_root_03_21_01_reg_l = @@ -11427,7 +11427,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_21_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_42_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2020] + (const void *)&gInstructions[2021] }; const ND_TABLE_VEX_PP gVexTable_root_03_42_pp = @@ -11444,7 +11444,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_42_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0f_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2080] + (const void *)&gInstructions[2081] }; const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp = @@ -11461,7 +11461,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_02_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2091] + (const void *)&gInstructions[2092] }; const ND_TABLE_VEX_W gVexTable_root_03_02_01_w = @@ -11487,7 +11487,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_02_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_4c_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2096] + (const void *)&gInstructions[2097] }; const ND_TABLE_VEX_W gVexTable_root_03_4c_01_w = @@ -11513,7 +11513,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4c_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0e_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2097] + (const void *)&gInstructions[2098] }; const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp = @@ -11530,7 +11530,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_44_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2113] + (const void *)&gInstructions[2114] }; const ND_TABLE_VEX_PP gVexTable_root_03_44_pp = @@ -11547,7 +11547,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_44_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_61_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2126] + (const void *)&gInstructions[2127] }; const ND_TABLE_VEX_L gVexTable_root_03_61_01_l = @@ -11575,7 +11575,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_61_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_60_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2127] + (const void *)&gInstructions[2128] }; const ND_TABLE_VEX_L gVexTable_root_03_60_01_l = @@ -11603,7 +11603,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_60_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_63_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2136] + (const void *)&gInstructions[2137] }; const ND_TABLE_VEX_L gVexTable_root_03_63_01_l = @@ -11631,7 +11631,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_63_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_62_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2137] + (const void *)&gInstructions[2138] }; const ND_TABLE_VEX_L gVexTable_root_03_62_01_l = @@ -11659,7 +11659,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_62_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_06_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2172] + (const void *)&gInstructions[2173] }; const ND_TABLE_VEX_W gVexTable_root_03_06_01_01_w = @@ -11696,7 +11696,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_06_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_46_01_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2173] + (const void *)&gInstructions[2174] }; const ND_TABLE_VEX_W gVexTable_root_03_46_01_01_w = @@ -11733,13 +11733,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_46_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2183] + (const void *)&gInstructions[2184] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2184] + (const void *)&gInstructions[2185] }; const ND_TABLE_VEX_W gVexTable_root_03_49_01_w = @@ -11765,13 +11765,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_49_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2185] + (const void *)&gInstructions[2186] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2186] + (const void *)&gInstructions[2187] }; const ND_TABLE_VEX_W gVexTable_root_03_48_01_w = @@ -11797,7 +11797,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_48_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_05_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2190] + (const void *)&gInstructions[2191] }; const ND_TABLE_VEX_W gVexTable_root_03_05_01_w = @@ -11823,7 +11823,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_05_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_04_01_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2194] + (const void *)&gInstructions[2195] }; const ND_TABLE_VEX_W gVexTable_root_03_04_01_w = @@ -11849,7 +11849,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_04_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_01_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2198] + (const void *)&gInstructions[2199] }; const ND_TABLE_VEX_W gVexTable_root_03_01_01_01_w = @@ -11886,7 +11886,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_01_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_00_01_01_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2204] + (const void *)&gInstructions[2205] }; const ND_TABLE_VEX_W gVexTable_root_03_00_01_01_w = @@ -11923,7 +11923,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_00_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2218] + (const void *)&gInstructions[2219] }; const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l = @@ -11940,7 +11940,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2219] + (const void *)&gInstructions[2220] }; const ND_TABLE_VEX_L gVexTable_root_03_14_01_reg_l = @@ -11977,13 +11977,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_14_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_mem_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2222] + (const void *)&gInstructions[2223] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_mem_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2226] + (const void *)&gInstructions[2227] }; const ND_TABLE_VEX_W gVexTable_root_03_16_01_mem_00_wi = @@ -12009,13 +12009,13 @@ const ND_TABLE_VEX_L gVexTable_root_03_16_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_reg_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2223] + (const void *)&gInstructions[2224] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_reg_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2227] + (const void *)&gInstructions[2228] }; const ND_TABLE_VEX_W gVexTable_root_03_16_01_reg_00_wi = @@ -12061,7 +12061,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_16_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2232] + (const void *)&gInstructions[2233] }; const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l = @@ -12078,7 +12078,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2233] + (const void *)&gInstructions[2234] }; const ND_TABLE_VEX_L gVexTable_root_03_15_01_reg_l = @@ -12115,7 +12115,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_15_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_mem_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2266] + (const void *)&gInstructions[2267] }; const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l = @@ -12132,7 +12132,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l = const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_reg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2267] + (const void *)&gInstructions[2268] }; const ND_TABLE_VEX_L gVexTable_root_03_20_01_reg_l = @@ -12169,13 +12169,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_20_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2269] + (const void *)&gInstructions[2270] }; const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2271] + (const void *)&gInstructions[2272] }; const ND_TABLE_VEX_W gVexTable_root_03_22_01_00_wi = @@ -12212,7 +12212,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_22_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_09_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2610] + (const void *)&gInstructions[2611] }; const ND_TABLE_VEX_PP gVexTable_root_03_09_pp = @@ -12229,7 +12229,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_09_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_08_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2611] + (const void *)&gInstructions[2612] }; const ND_TABLE_VEX_PP gVexTable_root_03_08_pp = @@ -12246,7 +12246,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_08_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2612] + (const void *)&gInstructions[2613] }; const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp = @@ -12263,7 +12263,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp = const ND_TABLE_INSTRUCTION gVexTable_root_03_0a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2613] + (const void *)&gInstructions[2614] }; const ND_TABLE_VEX_PP gVexTable_root_03_0a_pp = diff --git a/bddisasm/include/table_xop.h b/bddisasm/include/table_xop.h index 7f6f0ca..2686762 100644 --- a/bddisasm/include/table_xop.h +++ b/bddisasm/include/table_xop.h @@ -339,13 +339,13 @@ const ND_TABLE_INSTRUCTION gXopTable_root_09_01_06_leaf = const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1358] + (const void *)&gInstructions[1359] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1383] + (const void *)&gInstructions[1384] }; const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg = @@ -399,7 +399,7 @@ const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_00_leaf = const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1309] + (const void *)&gInstructions[1310] }; const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg = @@ -429,127 +429,127 @@ const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod = const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1821] + (const void *)&gInstructions[1822] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1822] + (const void *)&gInstructions[1823] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1823] + (const void *)&gInstructions[1824] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1824] + (const void *)&gInstructions[1825] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2242] + (const void *)&gInstructions[2243] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2243] + (const void *)&gInstructions[2244] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2244] + (const void *)&gInstructions[2245] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2246] + (const void *)&gInstructions[2247] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2248] + (const void *)&gInstructions[2249] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2249] + (const void *)&gInstructions[2250] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2250] + (const void *)&gInstructions[2251] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2251] + (const void *)&gInstructions[2252] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2252] + (const void *)&gInstructions[2253] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2253] + (const void *)&gInstructions[2254] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2255] + (const void *)&gInstructions[2256] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2256] + (const void *)&gInstructions[2257] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2258] + (const void *)&gInstructions[2259] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2260] + (const void *)&gInstructions[2261] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2263] + (const void *)&gInstructions[2264] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2427] + (const void *)&gInstructions[2428] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2428] + (const void *)&gInstructions[2429] }; const ND_TABLE_VEX_W gXopTable_root_09_90_w = @@ -564,13 +564,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_90_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2430] + (const void *)&gInstructions[2431] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2431] + (const void *)&gInstructions[2432] }; const ND_TABLE_VEX_W gXopTable_root_09_92_w = @@ -585,13 +585,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_92_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2433] + (const void *)&gInstructions[2434] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2434] + (const void *)&gInstructions[2435] }; const ND_TABLE_VEX_W gXopTable_root_09_93_w = @@ -606,13 +606,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_93_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2436] + (const void *)&gInstructions[2437] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2437] + (const void *)&gInstructions[2438] }; const ND_TABLE_VEX_W gXopTable_root_09_91_w = @@ -627,13 +627,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_91_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2444] + (const void *)&gInstructions[2445] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2445] + (const void *)&gInstructions[2446] }; const ND_TABLE_VEX_W gXopTable_root_09_98_w = @@ -648,13 +648,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_98_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2446] + (const void *)&gInstructions[2447] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2447] + (const void *)&gInstructions[2448] }; const ND_TABLE_VEX_W gXopTable_root_09_9a_w = @@ -669,13 +669,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9a_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2448] + (const void *)&gInstructions[2449] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2449] + (const void *)&gInstructions[2450] }; const ND_TABLE_VEX_W gXopTable_root_09_9b_w = @@ -690,13 +690,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9b_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2450] + (const void *)&gInstructions[2451] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2451] + (const void *)&gInstructions[2452] }; const ND_TABLE_VEX_W gXopTable_root_09_99_w = @@ -711,13 +711,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_99_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2452] + (const void *)&gInstructions[2453] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2453] + (const void *)&gInstructions[2454] }; const ND_TABLE_VEX_W gXopTable_root_09_94_w = @@ -732,13 +732,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_94_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2454] + (const void *)&gInstructions[2455] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2465] + (const void *)&gInstructions[2466] }; const ND_TABLE_VEX_W gXopTable_root_09_95_w = @@ -753,13 +753,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_95_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2455] + (const void *)&gInstructions[2456] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2456] + (const void *)&gInstructions[2457] }; const ND_TABLE_VEX_W gXopTable_root_09_96_w = @@ -774,13 +774,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_96_w = const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2463] + (const void *)&gInstructions[2464] }; const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2464] + (const void *)&gInstructions[2465] }; const ND_TABLE_VEX_W gXopTable_root_09_97_w = @@ -1058,13 +1058,13 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode = const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2114] + (const void *)&gInstructions[2115] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2115] + (const void *)&gInstructions[2116] }; const ND_TABLE_VEX_W gXopTable_root_08_a2_w = @@ -1079,133 +1079,133 @@ const ND_TABLE_VEX_W gXopTable_root_08_a2_w = const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2144] + (const void *)&gInstructions[2145] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2145] + (const void *)&gInstructions[2146] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2150] + (const void *)&gInstructions[2151] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2151] + (const void *)&gInstructions[2152] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2152] + (const void *)&gInstructions[2153] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2153] + (const void *)&gInstructions[2154] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2154] + (const void *)&gInstructions[2155] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2155] + (const void *)&gInstructions[2156] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2278] + (const void *)&gInstructions[2279] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2279] + (const void *)&gInstructions[2280] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2280] + (const void *)&gInstructions[2281] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2281] + (const void *)&gInstructions[2282] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2282] + (const void *)&gInstructions[2283] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2283] + (const void *)&gInstructions[2284] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2284] + (const void *)&gInstructions[2285] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2285] + (const void *)&gInstructions[2286] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2286] + (const void *)&gInstructions[2287] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2287] + (const void *)&gInstructions[2288] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2288] + (const void *)&gInstructions[2289] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2289] + (const void *)&gInstructions[2290] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2416] + (const void *)&gInstructions[2417] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2417] + (const void *)&gInstructions[2418] }; const ND_TABLE_VEX_W gXopTable_root_08_a3_w = @@ -1220,25 +1220,25 @@ const ND_TABLE_VEX_W gXopTable_root_08_a3_w = const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2426] + (const void *)&gInstructions[2427] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2429] + (const void *)&gInstructions[2430] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2432] + (const void *)&gInstructions[2433] }; const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2435] + (const void *)&gInstructions[2436] }; const ND_TABLE_OPCODE gXopTable_root_08_opcode = diff --git a/bddisasm_test/x86/basic/snp_64.asm b/bddisasm_test/x86/basic/snp_64.asm index e2608e0..867cbf8 100644 --- a/bddisasm_test/x86/basic/snp_64.asm +++ b/bddisasm_test/x86/basic/snp_64.asm @@ -3,4 +3,5 @@ rmpadjust rmpupdate psmash - pvalidate \ No newline at end of file + pvalidate + rmpquery \ No newline at end of file diff --git a/bddisasm_test/x86/basic/snp_64.result b/bddisasm_test/x86/basic/snp_64.result index 49e5461..0c70f66 100644 --- a/bddisasm_test/x86/basic/snp_64.result +++ b/bddisasm_test/x86/basic/snp_64.result @@ -78,3 +78,25 @@ Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 +0000000000000010 f30f01fd RMPQUERY + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: SNP, Ins cat: SYSTEM, CET tracked: no + CPUID leaf: 0x8000001f, reg: eax, bit: 6 + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S, + Segment: 3, Base: 0, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + diff --git a/bddisasm_test/x86/basic/snp_64.test b/bddisasm_test/x86/basic/snp_64.test index a23eb11..14eefd5 100644 --- a/bddisasm_test/x86/basic/snp_64.test +++ b/bddisasm_test/x86/basic/snp_64.test @@ -1 +1 @@ -óþòþóÿòÿ \ No newline at end of file +óþòþóÿòÿóý \ No newline at end of file diff --git a/bindings/pybddisasm/setup.py b/bindings/pybddisasm/setup.py index b5d9333..5b59434 100644 --- a/bindings/pybddisasm/setup.py +++ b/bindings/pybddisasm/setup.py @@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution from codecs import open VERSION = (0, 1, 3) -LIBRARY_VERSION = (1, 35, 0) +LIBRARY_VERSION = (1, 36, 0) LIBRARY_INSTRUX_SIZE = 856 packages = ['pybddisasm'] diff --git a/disasmtool_lix/dumpers.cpp b/disasmtool_lix/dumpers.cpp index b0a95e0..44cf66b 100644 --- a/disasmtool_lix/dumpers.cpp +++ b/disasmtool_lix/dumpers.cpp @@ -1585,6 +1585,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls) case ND_INS_VPDPBUUDS: return "vpdpbuuds"; case ND_INS_WRMSRLIST: return "wrmsrlist"; case ND_INS_WRMSRNS: return "wrmsrns"; + case ND_INS_RMPQUERY: return "rmpquery"; default: return "unhandled!"; } diff --git a/inc/constants.h b/inc/constants.h index 7f853fe..9e70a96 100644 --- a/inc/constants.h +++ b/inc/constants.h @@ -640,6 +640,7 @@ typedef enum _ND_INS_CLASS ND_INS_RETF, ND_INS_RETN, ND_INS_RMPADJUST, + ND_INS_RMPQUERY, ND_INS_RMPUPDATE, ND_INS_ROL, ND_INS_ROR, diff --git a/inc/cpuidflags.h b/inc/cpuidflags.h index b4028e9..5e0f34b 100644 --- a/inc/cpuidflags.h +++ b/inc/cpuidflags.h @@ -128,5 +128,6 @@ #define ND_CFF_RDPRU ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 4) #define ND_CFF_MCOMMIT ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 8) #define ND_CFF_SNP ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 4) +#define ND_CFF_RMPQUERY ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 6) #endif // CPUID_FLAGS_H diff --git a/inc/version.h b/inc/version.h index 3506e46..df59fbd 100644 --- a/inc/version.h +++ b/inc/version.h @@ -6,7 +6,7 @@ #define DISASM_VER_H #define DISASM_VERSION_MAJOR 1 -#define DISASM_VERSION_MINOR 35 +#define DISASM_VERSION_MINOR 36 #define DISASM_VERSION_REVISION 0 // bdshemu depends on bddisasm. It cannot be used without it. diff --git a/isagenerator/instructions/cpuid.dat b/isagenerator/instructions/cpuid.dat index 7c6a456..92014d4 100644 --- a/isagenerator/instructions/cpuid.dat +++ b/isagenerator/instructions/cpuid.dat @@ -135,3 +135,4 @@ MCOMMIT : 0x80000008, 0xFFFFFFFF, EBX, 8 SNP : 0x8000001F, 0xFFFFFFFF, EAX, 4 +RMPQUERY : 0x8000001F, 0xFFFFFFFF, EAX, 6 diff --git a/isagenerator/instructions/table_0F.dat b/isagenerator/instructions/table_0F.dat index 7b798ea..60285ae 100644 --- a/isagenerator/instructions/table_0F.dat +++ b/isagenerator/instructions/table_0F.dat @@ -76,6 +76,7 @@ MCOMMIT nil Fv [ 0xF3 0x0F 0x01 /0 MWAITX nil EAX,ECX,EBX [ NP 0x0F 0x01 /0xFB] s:MWAITT, t:SYSTEM, w:R|R|R, m:KERNEL|NOV86 CLZERO nil rAX [ 0x0F 0x01 /0xFC] s:CLZERO, t:MISC, w:R RDPRU nil EAX,EDX,ECX,Fv [ 0x0F 0x01 /0xFD] s:RDPRU, t:MISC, w:W|W|R|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 +RMPQUERY nil pAXb,EAX,RCX,RDX,Fv [ 0xF3 0x0F 0x01 /0xFD] s:SNP, t:SYSTEM, w:R|RW|W|RW|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL, i:RMPQUERY INVLPGB nil rAX,ECX,EDX [ 0x0F 0x01 /0xFE] s:INVLPGB, t:SYSTEM, w:R|R|R, m:NOREAL|KERNEL RMPADJUST nil pAXb,EAX,RCX,RDX,Fv [ 0xF3 0x0F 0x01 /0xFE] s:SNP, t:SYSTEM, w:R|RW|R|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL RMPUPDATE nil RAX,pCXdq,Fv [ 0xF2 0x0F 0x01 /0xFE] s:SNP, t:SYSTEM, w:RW|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL