- Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvementspull/52/head v1.33.0
parent
5b8b67c596
commit
76d92e73c2
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@ -0,0 +1,46 @@
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bits 64
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; srcdest == src1, src1 == src2 or srcdest == src2 => #UD.
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db 0xc4, 0xe2, 0x78, 0x5e, 0xC0 ; TDPBUUD tmm0, tmm0, tmm0
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x78, 0x5e, 0xC1 ; TDPBUUD tmm0, tmm1, tmm0
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x78, 0x5e, 0xC8 ; TDPBUUD tmm1, tmm0, tmm0
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x70, 0x5e, 0xC0 ; TDPBUUD tmm0, tmm0, tmm1
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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; tileload or tilestore without SIB => #UD.
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db 0xc4, 0xe2, 0x79, 0x4b, 0x00 ; TILELOADDT1 tmm0, [rax]
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x7b, 0x4b, 0x00, ; TILELOADD tmm0, [rax]
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x7a, 0x4b, 0x00 ; TILESTORED tmm0, [rax+rax]
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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; using vex.vvvv != 0b1111 => #UD
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db 0xc4, 0xe2, 0x70, 0x49, 0x00 ; LDTILECFG zmmword ptr [rax]
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x71, 0x49, 0x00 ; STTILECFG zmmword ptr [rax]
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x71, 0x4b, 0x04, 0x00 ; TILELOADDT1 tmm0, [rax+rax]
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x73, 0x4b, 0x04, 0x00 ; TILELOADD tmm0, [rax+rax]
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x72, 0x4b, 0x04, 0x00 ; TILESTORED tmm0, [rax+rax]
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x71, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILELOADDT1 tmm0, [rax+rax+0]
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x73, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILELOADD tmm0, [rax+rax+0]
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x72, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILESTORED tmm0, [rax+rax+0]
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x70, 0x49, 0xC0 ; TILERELEASE
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x73, 0x49, 0xC0 ; TILEZERO tmm0
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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db 0xc4, 0xe2, 0x73, 0x49, 0xf8 ; TILEZERO tmm7
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db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
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@ -0,0 +1,18 @@
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0000000000000000 c4 db 0xc4 (0x80000043)
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0000000000000010 c4 db 0xc4 (0x80000043)
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0000000000000020 c4 db 0xc4 (0x80000043)
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0000000000000030 c4 db 0xc4 (0x80000043)
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0000000000000040 c4 db 0xc4 (0x80000042)
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0000000000000050 c4 db 0xc4 (0x80000042)
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0000000000000060 c4 db 0xc4 (0x80000042)
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0000000000000070 c4 db 0xc4 (0x80000032)
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0000000000000080 c4 db 0xc4 (0x80000032)
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0000000000000090 c4 db 0xc4 (0x80000032)
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00000000000000A0 c4 db 0xc4 (0x80000032)
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00000000000000B0 c4 db 0xc4 (0x80000032)
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00000000000000C0 c4 db 0xc4 (0x80000032)
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00000000000000D0 c4 db 0xc4 (0x80000032)
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00000000000000E0 c4 db 0xc4 (0x80000032)
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00000000000000F0 c4 db 0xc4 (0x80000032)
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0000000000000100 c4 db 0xc4 (0x80000032)
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0000000000000110 c4 db 0xc4 (0x80000032)
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@ -0,0 +1,3 @@
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bits 64
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vpgatherqq xmm2, [rbx+xmm2*8+0x1000], xmm13
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@ -0,0 +1 @@
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0000000000000000 c4 db 0xc4 (0x80000031)
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@ -0,0 +1,3 @@
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bits 64
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vpgatherqq xmm2, [rbx+xmm7*8+0x1000], xmm2
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@ -0,0 +1 @@
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0000000000000000 c4 db 0xc4 (0x80000031)
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@ -0,0 +1,3 @@
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bits 64
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vpgatherqq xmm2, [rbx+xmm7*8+0x1000], xmm7
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@ -0,0 +1 @@
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0000000000000000 c4 db 0xc4 (0x80000031)
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@ -0,0 +1,110 @@
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0000000000000000 62f1fd086ec9 VMOVD xmm1, ecx
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DSIZE: 32, ASIZE: 32, VLEN: 128
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ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no
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CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
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EVEX Tuple Type: Tuple 1 Scalar
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Exception class: EVEX, exception type: E9NF
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Valid modes
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R0: yes, R1: yes, R2: yes, R3: yes
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Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
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SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
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VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
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Valid prefixes
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REP: no, REPcc: no, LOCK: no
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HLE: no, XACQUIRE only: no, XRELEASE only: no
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BND: no, BHINT: no, DNT: no
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Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
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Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
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0000000000000006 62f1fd087ec9 VMOVD ecx, xmm1
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DSIZE: 32, ASIZE: 32, VLEN: 128
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ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no
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CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
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EVEX Tuple Type: Tuple 1 Scalar
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Exception class: EVEX, exception type: E9NF
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Valid modes
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R0: yes, R1: yes, R2: yes, R3: yes
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Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
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SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
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VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
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Valid prefixes
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REP: no, REPcc: no, LOCK: no
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HLE: no, XACQUIRE only: no, XRELEASE only: no
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BND: no, BHINT: no, DNT: no
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Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
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Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
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000000000000000C 62f17f482ac9 VCVTSI2SD xmm1, xmm0, ecx
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DSIZE: 32, ASIZE: 32, VLEN: 512
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ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
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CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
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EVEX Tuple Type: Tuple 1 Scalar
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Exception class: EVEX, exception type: E10NF
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Valid modes
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R0: yes, R1: yes, R2: yes, R3: yes
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Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
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SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
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VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
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Valid prefixes
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REP: no, REPcc: no, LOCK: no
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HLE: no, XACQUIRE only: no, XRELEASE only: no
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BND: no, BHINT: no, DNT: no
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Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
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Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
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Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
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0000000000000012 62f1ff482ac9 VCVTSI2SD xmm1, xmm0, ecx
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DSIZE: 32, ASIZE: 32, VLEN: 512
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ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
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CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
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EVEX Tuple Type: Tuple 1 Scalar
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Exception class: EVEX, exception type: E10NF
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Valid modes
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R0: yes, R1: yes, R2: yes, R3: yes
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Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
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SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
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VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
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Valid prefixes
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REP: no, REPcc: no, LOCK: no
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HLE: no, XACQUIRE only: no, XRELEASE only: no
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BND: no, BHINT: no, DNT: no
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Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
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Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
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Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
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0000000000000018 62f17f482dc9 VCVTSD2SI ecx, xmm1
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DSIZE: 32, ASIZE: 32, VLEN: 512
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ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
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CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
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EVEX Tuple Type: Tuple 1 Fixes
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Exception class: EVEX, exception type: E3
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Valid modes
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R0: yes, R1: yes, R2: yes, R3: yes
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Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
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SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
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VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
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Valid prefixes
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REP: no, REPcc: no, LOCK: no
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HLE: no, XACQUIRE only: no, XRELEASE only: no
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BND: no, BHINT: no, DNT: no
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Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
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Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
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000000000000001E 62f1ff482dc9 VCVTSD2SI ecx, xmm1
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DSIZE: 32, ASIZE: 32, VLEN: 512
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ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
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CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
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EVEX Tuple Type: Tuple 1 Fixes
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Exception class: EVEX, exception type: E3
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Valid modes
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R0: yes, R1: yes, R2: yes, R3: yes
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Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
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SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
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VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
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Valid prefixes
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REP: no, REPcc: no, LOCK: no
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HLE: no, XACQUIRE only: no, XRELEASE only: no
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BND: no, BHINT: no, DNT: no
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Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
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Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
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@ -0,0 +1,110 @@
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0000000000000000 62f1fd086ec9 VMOVQ xmm1, rcx
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DSIZE: 64, ASIZE: 64, VLEN: 128
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ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no
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CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
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EVEX Tuple Type: Tuple 1 Scalar
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Exception class: EVEX, exception type: E9NF
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Valid modes
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R0: yes, R1: yes, R2: yes, R3: yes
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Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
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SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
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VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
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Valid prefixes
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REP: no, REPcc: no, LOCK: no
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HLE: no, XACQUIRE only: no, XRELEASE only: no
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BND: no, BHINT: no, DNT: no
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Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
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Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
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0000000000000006 62f1fd087ec9 VMOVQ rcx, xmm1
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DSIZE: 64, ASIZE: 64, VLEN: 128
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ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no
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CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
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EVEX Tuple Type: Tuple 1 Scalar
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Exception class: EVEX, exception type: E9NF
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Valid modes
|
||||||
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R0: yes, R1: yes, R2: yes, R3: yes
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|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
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SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
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VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
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Valid prefixes
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REP: no, REPcc: no, LOCK: no
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HLE: no, XACQUIRE only: no, XRELEASE only: no
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BND: no, BHINT: no, DNT: no
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||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
|
||||||
|
|
||||||
|
000000000000000C 62f17f482ac9 VCVTSI2SD xmm1, xmm0, ecx
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||||
|
ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
|
||||||
|
EVEX Tuple Type: Tuple 1 Scalar
|
||||||
|
Exception class: EVEX, exception type: E10NF
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000012 62f1ff482ac9 VCVTSI2SD xmm1, xmm0, rcx
|
||||||
|
DSIZE: 64, ASIZE: 64, VLEN: 512
|
||||||
|
ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
|
||||||
|
EVEX Tuple Type: Tuple 1 Scalar
|
||||||
|
Exception class: EVEX, exception type: E3
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000018 62f17f482dc9 VCVTSD2SI ecx, xmm1
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||||
|
ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
|
||||||
|
EVEX Tuple Type: Tuple 1 Fixes
|
||||||
|
Exception class: EVEX, exception type: E3
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
|
||||||
|
|
||||||
|
000000000000001E 62f1ff482dc9 VCVTSD2SI rcx, xmm1
|
||||||
|
DSIZE: 64, ASIZE: 64, VLEN: 512
|
||||||
|
ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
|
||||||
|
EVEX Tuple Type: Tuple 1 Fixes
|
||||||
|
Exception class: EVEX, exception type: E3
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
|
||||||
|
|
@ -0,0 +1,19 @@
|
|||||||
|
bits 32
|
||||||
|
|
||||||
|
db 0x0F, 0x01, 0xF8 ; SWAPGS
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x0F, 0x05 ; SYSCALL
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x0F, 0x07 ; SYSRET
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0xF3, 0x0F, 0xAE, 0xC0 ; RDFSBASE eax
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0xF3, 0x0F, 0xAE, 0xC8 ; RDGSBASE eax
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0xF3, 0x0F, 0xAE, 0xD0 ; WRFSBASE eax
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0xF3, 0x0F, 0xAE, 0xD8 ; WRGSBASE eax
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,55 @@
|
|||||||
|
0000000000000000 0f db 0x0f (0x80000009)
|
||||||
|
0000000000000010 0f05 SYSCALL
|
||||||
|
DSIZE: 32, ASIZE: 32, VLEN: -
|
||||||
|
ISA Set: AMD, Ins cat: SYSCALL, CET tracked: no
|
||||||
|
CPUID leaf: 0x80000001, reg: ecx, bit: 11
|
||||||
|
FLAGS access
|
||||||
|
Entire register
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 0xc0000081, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 0xc0000082, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 0xc0000084, RegCount: 1
|
||||||
|
Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1
|
||||||
|
Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
|
||||||
|
Operand: 5, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1
|
||||||
|
Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1
|
||||||
|
Operand: 7, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1
|
||||||
|
Operand: 8, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
|
||||||
|
Operand: 9, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: SSP, RegSize: 4, RegId: 0, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000020 0f07 SYSRET
|
||||||
|
DSIZE: 32, ASIZE: 32, VLEN: -
|
||||||
|
ISA Set: AMD, Ins cat: SYSRET, CET tracked: no
|
||||||
|
CPUID leaf: 0x80000001, reg: ecx, bit: 11
|
||||||
|
FLAGS access
|
||||||
|
Entire register
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: no, R2: no, R3: no
|
||||||
|
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 0xc0000081, RegCount: 1
|
||||||
|
Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
|
||||||
|
Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1
|
||||||
|
Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1
|
||||||
|
Operand: 5, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1
|
||||||
|
Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
|
||||||
|
Operand: 7, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: SSP, RegSize: 4, RegId: 0, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000030 f3 db 0xf3 (0x80000002)
|
||||||
|
0000000000000040 f3 db 0xf3 (0x80000002)
|
||||||
|
0000000000000050 f3 db 0xf3 (0x80000002)
|
||||||
|
0000000000000060 f3 db 0xf3 (0x80000002)
|
@ -0,0 +1,36 @@
|
|||||||
|
bits 64
|
||||||
|
|
||||||
|
db 0x06 ; PUSH es
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x07 ; POP es
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x0E ; PUSH cs
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x16 ; PUSH ss
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x17 ; POP ss
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x1E ; PUSH ds
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x1F ; POP ds
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x27 ; DAA
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x2F ; DAS
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x37 ; AAA
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x3F ; AAS
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0xD4, 0x90 ; AAM
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0xD5, 0x90 ; AAD
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x60 ; PUSHA
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x61 ; POPA
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0x9A, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 ; CALL far
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
db 0xEA, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 ; JMP far
|
||||||
|
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
@ -0,0 +1,17 @@
|
|||||||
|
0000000000000000 06 db 0x06 (0x80000009)
|
||||||
|
0000000000000010 07 db 0x07 (0x80000009)
|
||||||
|
0000000000000020 0e db 0x0e (0x80000009)
|
||||||
|
0000000000000030 16 db 0x16 (0x80000009)
|
||||||
|
0000000000000040 17 db 0x17 (0x80000009)
|
||||||
|
0000000000000050 1e db 0x1e (0x80000009)
|
||||||
|
0000000000000060 1f db 0x1f (0x80000009)
|
||||||
|
0000000000000070 27 db 0x27 (0x80000009)
|
||||||
|
0000000000000080 2f db 0x2f (0x80000009)
|
||||||
|
0000000000000090 37 db 0x37 (0x80000009)
|
||||||
|
00000000000000A0 3f db 0x3f (0x80000009)
|
||||||
|
00000000000000B0 d4 db 0xd4 (0x80000009)
|
||||||
|
00000000000000C0 d5 db 0xd5 (0x80000009)
|
||||||
|
00000000000000D0 60 db 0x60 (0x80000009)
|
||||||
|
00000000000000E0 61 db 0x61 (0x80000009)
|
||||||
|
00000000000000F0 9a db 0x9a (0x80000009)
|
||||||
|
0000000000000100 ea db 0xea (0x80000009)
|
@ -0,0 +1,67 @@
|
|||||||
|
bits 64
|
||||||
|
|
||||||
|
; EVEX.b (broadcast) enabled for an instruction which does not support broadcast (mod: mem)
|
||||||
|
db 0x62, 0xf1, 0x7d, 0x18, 0xc4, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.b (ER/SAE) enabled for an instruction which does not support ER/SAE (mod: reg)
|
||||||
|
db 0x62, 0xf1, 0x7d, 0x18, 0xc4, 0xd2, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.aaa != 0 for an instruction which does not support masking
|
||||||
|
db 0x62, 0xf1, 0x7d, 0x0b, 0xc4, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.aaa != 0 for an instruction which does not support masking
|
||||||
|
db 0x62, 0xf1, 0x7d, 0x0b, 0xc4, 0xd2, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.z enabled for an instruction which does not support zeroing
|
||||||
|
db 0x62, 0xf1, 0x7d, 0x88, 0xc4, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.z enabled for an instruction which does not support zeroing
|
||||||
|
db 0x62, 0xf1, 0x7d, 0x88, 0xc4, 0xd2, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.aaa == 0 for an instruction which has mandatory masking
|
||||||
|
db 0x62, 0xf2, 0xfd, 0x08, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.aaa == 0 for an instruction which has mandatory masking
|
||||||
|
db 0x62, 0xf2, 0xfd, 0x28, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.aaa == 0 for an instruction which has mandatory masking
|
||||||
|
db 0x62, 0xf2, 0xfd, 0x48, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.b (broadcast) enabled for an instruction which does not support broadcast (mod: mem)
|
||||||
|
db 0x62, 0xf2, 0xfd, 0x19, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.b (broadcast) enabled for an instruction which does not support broadcast (mod: mem)
|
||||||
|
db 0x62, 0xf2, 0xfd, 0x39, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.b (broadcast) enabled for an instruction which does not support broadcast (mod: mem)
|
||||||
|
db 0x62, 0xf2, 0xfd, 0x59, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.z enabled for an instruction which does not support zeroing
|
||||||
|
db 0x62, 0xf2, 0xfd, 0x89, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.z enabled for an instruction which does not support zeroing
|
||||||
|
db 0x62, 0xf2, 0xfd, 0xa9, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.z enabled for an instruction which does not support zeroing
|
||||||
|
db 0x62, 0xf2, 0xfd, 0xc9, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; Destination reg equal to the first source operand for instruction which must have dst != sources
|
||||||
|
db 0x62, 0xf6, 0x7f, 0x49, 0x56, 0xdb, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; Destination reg equal to the second source operand for instruction which must have dst != sources
|
||||||
|
db 0x62, 0xf6, 0x67, 0x49, 0x56, 0xdf, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.VVVV != 0 for instruction that does not use EVEX.VVVV
|
||||||
|
db 0x62, 0xf1, 0x64, 0xa9, 0x11, 0xdf, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.V' set for an instruction which does not use it
|
||||||
|
db 0x62, 0xf1, 0x7c, 0xa1, 0x11, 0xdf, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.z set for memory operand
|
||||||
|
db 0x62, 0xf1, 0x7c, 0xa9, 0x11, 0x1f, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.z set but EVEX.aaa == 0
|
||||||
|
db 0x62, 0xf3, 0x7d, 0xa8, 0x19, 0xc9, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
||||||
|
|
||||||
|
; EVEX.z set but EVEX.aaa == 0
|
||||||
|
db 0x62, 0xf3, 0xfd, 0xa8, 0x0b, 0xc9, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
|
@ -0,0 +1,22 @@
|
|||||||
|
0000000000000000 62 db 0x62 (0x80000039)
|
||||||
|
0000000000000010 62 db 0x62 (0x80000035)
|
||||||
|
0000000000000020 62 db 0x62 (0x80000033)
|
||||||
|
0000000000000030 62 db 0x62 (0x80000033)
|
||||||
|
0000000000000040 62 db 0x62 (0x80000036)
|
||||||
|
0000000000000050 62 db 0x62 (0x80000036)
|
||||||
|
0000000000000060 62 db 0x62 (0x80000034)
|
||||||
|
0000000000000070 62 db 0x62 (0x80000034)
|
||||||
|
0000000000000080 62 db 0x62 (0x80000034)
|
||||||
|
0000000000000090 62 db 0x62 (0x80000039)
|
||||||
|
00000000000000A0 62 db 0x62 (0x80000039)
|
||||||
|
00000000000000B0 62 db 0x62 (0x80000039)
|
||||||
|
00000000000000C0 62 db 0x62 (0x80000036)
|
||||||
|
00000000000000D0 62 db 0x62 (0x80000036)
|
||||||
|
00000000000000E0 62 db 0x62 (0x80000036)
|
||||||
|
00000000000000F0 62 db 0x62 (0x80000044)
|
||||||
|
0000000000000100 62 db 0x62 (0x80000044)
|
||||||
|
0000000000000110 62 db 0x62 (0x80000032)
|
||||||
|
0000000000000120 62 db 0x62 (0x80000040)
|
||||||
|
0000000000000130 62 db 0x62 (0x80000037)
|
||||||
|
0000000000000140 62 db 0x62 (0x80000038)
|
||||||
|
0000000000000150 62 db 0x62 (0x80000038)
|
@ -0,0 +1,65 @@
|
|||||||
|
# Mnemonic Explicit Operands Implicit Encoding Flags, Prefixes, Set, Category, Class, RW map, Additional ops
|
||||||
|
#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||||
|
# 0x10 - 0x1F
|
||||||
|
VMOVSH Vdq{K}{z},Wsh nil [evex m:5 p:2 l:i w:0 0x10 /r:mem] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E5, w:W|R|R
|
||||||
|
VMOVSH Vdq{K}{z},Hdq,Wsh nil [evex m:5 p:2 l:i w:0 0x10 /r:reg] s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R
|
||||||
|
VMOVSH Wsh{K},Vdq nil [evex m:5 p:2 l:i w:0 0x11 /r:mem] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E5, w:W|R|R
|
||||||
|
VMOVSH Wsh{K}{z},Hdq,Vdq nil [evex m:5 p:2 l:i w:0 0x11 /r:reg] s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R
|
||||||
|
VCVTPS2PHX Vh{K}{z},Wn|B32{er} nil [evex m:5 p:1 l:x w:0 0x1D /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VCVTSS2SH Vdq{K}{z},Hdq,Wss{er} nil [evex m:5 p:0 l:i w:0 0x1D /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R
|
||||||
|
|
||||||
|
# 0x20 - 0x2F
|
||||||
|
VCVTSI2SH Vdq,Hdq,Ey nil [evex m:5 p:2 l:i w:x 0x2A /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64
|
||||||
|
VCVTTSH2SI Gy,Wsh{sae} nil [evex m:5 p:2 l:i w:x 0x2C /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
|
||||||
|
VCVTSH2SI Gy,Wsh{er} nil [evex m:5 p:2 l:i w:x 0x2D /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
|
||||||
|
VUCOMISH Vdq,Wsh{sae} Fv [evex m:5 p:0 l:i w:0 0x2E /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0
|
||||||
|
VCOMISH Vdq,Wsh{sae} Fv [evex m:5 p:0 l:i w:0 0x2F /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0
|
||||||
|
|
||||||
|
# 0x50 - 0x5F
|
||||||
|
VSQRTPH Vn{K}{z},Wn|B16{er} nil [evex m:5 p:0 l:x w:0 0x51 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VSQRTSH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:5 p:2 l:i w:0 0x51 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||||
|
VADDPH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:5 p:0 l:x w:0 0x58 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||||
|
VADDSH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:5 p:2 l:i w:0 0x58 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||||
|
VMULPH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:5 p:0 l:x w:0 0x59 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||||
|
VMULSH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:5 p:2 l:i w:0 0x59 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||||
|
VCVTPH2PD Vn{K}{z},Wf|B16{sae} nil [evex m:5 p:0 l:x w:0 0x5A /r] s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
|
||||||
|
VCVTPD2PH Vdq{K}{z},Wn|B64{er} nil [evex m:5 p:1 l:x w:1 0x5A /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VCVTSH2SD Vdq{K}{z},Hdq,Wsh{sae} nil [evex m:5 p:2 l:i w:0 0x5A /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||||
|
VCVTSD2SH Vdq{K}{z},Hdq,Wsd{er} nil [evex m:5 p:3 l:i w:1 0x5A /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R
|
||||||
|
VCVTDQ2PH Vh{K}{z},Wn|B32{er} nil [evex m:5 p:0 l:x w:0 0x5B /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VCVTQQ2PH Vdq{K}{z},Wn|B64{er} nil [evex m:5 p:0 l:x w:1 0x5B /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VCVTPH2DQ Vn{K}{z},Wh|B16{er} nil [evex m:5 p:1 l:x w:0 0x5B /r] s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
|
||||||
|
VCVTTPH2DQ Vn{K}{z},Wh|B16{sae} nil [evex m:5 p:2 l:x w:0 0x5B /r] s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
|
||||||
|
VSUBPH Vn{K}{z},Hn,Wn|B16{sae} nil [evex m:5 p:0 l:x w:0 0x5C /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||||
|
VSUBSH Vdq{K}{z},Hdq,Wsh{sae} nil [evex m:5 p:2 l:i w:0 0x5C /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||||
|
VMINPH Vn{K}{z},Hn,Wn|B16{sae} nil [evex m:5 p:0 l:x w:0 0x5D /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||||
|
VMINSH Vdq{K}{z},Hdq,Wsh{sae} nil [evex m:5 p:2 l:i w:0 0x5D /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||||
|
VDIVPH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:5 p:0 l:x w:0 0x5E /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||||
|
VDIVSH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:5 p:2 l:i w:0 0x5E /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||||
|
VMAXPH Vn{K}{z},Hn,Wn|B16{sae} nil [evex m:5 p:0 l:x w:0 0x5F /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||||
|
VMAXSH Vdq{K}{z},Hdq,Wsh{sae} nil [evex m:5 p:2 l:i w:0 0x5F /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||||
|
|
||||||
|
# 0x60 - 0x6F
|
||||||
|
VMOVW Vdq,Mw nil [evex m:5 p:1 l:0 w:i 0x6E /r:mem] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
|
||||||
|
VMOVW Vdq,Rd nil [evex m:5 p:1 l:0 w:i 0x6E /r:reg] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
|
||||||
|
|
||||||
|
# 0x70 - 0x7F
|
||||||
|
VCVTTPH2UDQ Vn{K}{z},Wh|B16{sae} nil [evex m:5 p:0 l:x w:0 0x78 /r] s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
|
||||||
|
VCVTTPH2UQQ Vn{K}{z},Wf|B16{sae} nil [evex m:5 p:1 l:x w:0 0x78 /r] s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
|
||||||
|
VCVTTSH2USI Gy,Wsh{sae} nil [evex m:5 p:2 l:i w:0 0x78 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
|
||||||
|
VCVTPH2UDQ Vn{K}{z},Wh|B16{er} nil [evex m:5 p:0 l:x w:0 0x79 /r] s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
|
||||||
|
VCVTPH2UQQ Vn{K}{z},Wf|B16{er} nil [evex m:5 p:1 l:x w:0 0x79 /r] s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
|
||||||
|
VCVTSH2USI Gy,Wsh{er} nil [evex m:5 p:2 l:i w:x 0x79 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
|
||||||
|
VCVTUDQ2PH Vh{K}{z},Wn|B32{er} nil [evex m:5 p:3 l:x w:0 0x7A /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VCVTUQQ2PH Vf{K}{z},Wn|B64{er} nil [evex m:5 p:3 l:x w:1 0x7A /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VCVTTPH2QQ Vn{K}{z},Wf|B16{sae} nil [evex m:5 p:1 l:x w:0 0x7A /r] s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
|
||||||
|
VCVTPH2QQ Vn{K}{z},Wf|B16{er} nil [evex m:5 p:1 l:x w:0 0x7B /r] s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
|
||||||
|
VCVTUSI2SH Vdq,Hdq,Ey{er} nil [evex m:5 p:2 l:i w:x 0x7B /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64
|
||||||
|
VCVTTPH2UW Vn{K}{z},Wn|B16{sae} nil [evex m:5 p:0 l:x w:0 0x7C /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VCVTTPH2W Vn{K}{z},Wn|B16{sae} nil [evex m:5 p:1 l:x w:0 0x7C /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VCVTPH2UW Vn{K}{z},Wn|B16{er} nil [evex m:5 p:0 l:x w:0 0x7D /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VCVTPH2W Vn{K}{z},Wn|B16{er} nil [evex m:5 p:1 l:x w:0 0x7D /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VCVTW2PH Vn{K}{z},Wn|B16{er} nil [evex m:5 p:2 l:x w:0 0x7D /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VCVTUW2PH Vn{K}{z},Wn|B16{er} nil [evex m:5 p:3 l:x w:0 0x7D /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VMOVW Mw,Vdq nil [evex m:5 p:1 l:0 w:i 0x7E /r:mem] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
|
||||||
|
VMOVW Rd,Vdq nil [evex m:5 p:1 l:0 w:i 0x7E /r:reg] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
|
@ -0,0 +1,65 @@
|
|||||||
|
# Mnemonic Explicit Operands Implicit Encoding Flags, Prefixes, Set, Category, Class, RW map, Additional ops
|
||||||
|
#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||||
|
# 0x10 - 0x1F
|
||||||
|
VCVTSH2SS Vdq{K}{z},Hdq,Wsh{sae} nil [evex m:6 p:0 l:i w:0 0x13 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||||
|
VCVTPH2PSX Vn{K}{z},Wh|B16{sae} nil [evex m:6 p:1 l:x w:0 0x13 /r] s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
|
||||||
|
|
||||||
|
# 0x20 - 0x2F
|
||||||
|
VSCALEFPH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x2C /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||||
|
VSCALEFSH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0x2D /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
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||||||
|
# 0x40 - 0x4F
|
||||||
|
VGETEXPPH Vn{K}{z},Wn|B16{sae} nil [evex m:6 p:1 l:x w:0 0x42 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||||
|
VGETEXPSH Vdq{K}{z},Hdq,Wsh{sae} nil [evex m:6 p:1 l:i w:0 0x43 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||||
|
VRCPPH Vn{K}{z},Wn|B16 nil [evex m:6 p:1 l:x w:0 0x4C /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R
|
||||||
|
VRCPSH Vdq{K}{z},Hdq,Wsh nil [evex m:6 p:1 l:i w:0 0x4D /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
|
||||||
|
VRSQRTPH Vn{K}{z},Wn|B16 nil [evex m:6 p:1 l:x w:0 0x4E /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R
|
||||||
|
VRSQRTSH Vdq{K}{z},Hdq,Wsh nil [evex m:6 p:1 l:i w:0 0x4F /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
|
||||||
|
|
||||||
|
# 0x50 - 0x5F
|
||||||
|
VFMADDCPH Vn{K}{z},Hn,Wn|B32{er} nil [evex m:6 p:2 l:x w:0 0x56 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R
|
||||||
|
VFCMADDCPH Vn{K}{z},Hn,Wn|B32{er} nil [evex m:6 p:3 l:x w:0 0x56 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R
|
||||||
|
VFMADDCSH Vdq{K}{z},Hdq,Wd{er} nil [evex m:6 p:2 l:i w:0 0x57 /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R
|
||||||
|
VFCMADDCSH Vdq{K}{z},Hdq,Wd{er} nil [evex m:6 p:3 l:i w:0 0x57 /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R
|
||||||
|
|
||||||
|
# 0x90 - 0x9F
|
||||||
|
VFMADDSUB132PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x96 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFMSUBADD132PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x97 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFMADD132PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x98 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFMADD132SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0x99 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||||
|
VFMSUB132PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x9A /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFMSUB132SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0x9B /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||||
|
VFNMADD132PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x9C /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFNMADD132SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0x9D /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||||
|
VFNMSUB132PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x9E /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFNMSUB132SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0x9F /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||||
|
|
||||||
|
# 0xA0 - 0xAF
|
||||||
|
VFMADDSUB213PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xA6 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFMSUBADD213PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xA7 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFMADD213PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xA8 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFMADD213SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xA9 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||||
|
VFMSUB213PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xAA /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFMSUB213SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xAB /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||||
|
VFNMADD213PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xAC /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFNMADD213SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xAD /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||||
|
VFNMSUB213PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xAE /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFNMSUB213SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xAF /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||||
|
|
||||||
|
# 0xB0 - 0xBF
|
||||||
|
VFMADDSUB231PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xB6 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFMSUBADD231PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xB7 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFMADD231PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xB8 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFMADD231SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xB9 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||||
|
VFMSUB231PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xBA /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFMSUB231SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xBB /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||||
|
VFNMADD231PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xBC /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFNMADD231SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xBD /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||||
|
VFNMSUB231PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xBE /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||||
|
VFNMSUB231SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xBF /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||||
|
|
||||||
|
# 0xD0 - 0xD7
|
||||||
|
VFMULCPH Vn{K}{z},Hn,Wn|B32{er} nil [evex m:6 p:2 l:x w:0 0xD6 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R
|
||||||
|
VFCMULCPH Vn{K}{z},Hn,Wn|B32{er} nil [evex m:6 p:3 l:x w:0 0xD6 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R
|
||||||
|
VFMULCSH Vdq{K}{z},Hdq,Wd{er} nil [evex m:6 p:2 l:i w:0 0xD7 /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R
|
||||||
|
VFCMULCSH Vdq{K}{z},Hdq,Wd{er} nil [evex m:6 p:3 l:i w:0 0xD7 /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R
|
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Reference in new issue