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Make sure upper 32 bit of a CMOV destination register is cleared to 0 even if the condition is not satisfied

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This commit is contained in:
BITDEFENDER\vlutas 2022-07-16 12:21:46 +03:00
parent 1805a9edec
commit 6dda2c122c
4 changed files with 10 additions and 3 deletions
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9
bdshemu/bdshemu.c
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@ -1882,11 +1882,18 @@ ShemuEmulate(
break;
case ND_INS_CMOVcc:
GET_OP(Context, 0, &dst);
GET_OP(Context, 1, &src);
if (ShemuEvalCondition(Context, Context->Instruction.Condition))
{
GET_OP(Context, 1, &src);
SET_OP(Context, 0, &src);
}
else
{
// Write back the same value that was already present in destination. This has the side-effect of
// clearing the upper 32 bit in the 64 bit destination register while in long mode.
SET_OP(Context, 0, &dst);
}
break;
case ND_INS_SETcc:

BIN
bdshemu_test/bdshemu_test.zip
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2
bindings/pybddisasm/setup.py
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@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution
from codecs import open
VERSION = (0, 1, 3)
LIBRARY_VERSION = (1, 34, 15)
LIBRARY_VERSION = (1, 34, 16)
LIBRARY_INSTRUX_SIZE = 856
packages = ['pybddisasm']

2
inc/version.h
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@ -7,6 +7,6 @@
#define DISASM_VERSION_MAJOR 1
#define DISASM_VERSION_MINOR 34
#define DISASM_VERSION_REVISION 15
#define DISASM_VERSION_REVISION 16
#endif // DISASM_VER_H