Make sure upper 32 bit of a CMOV destination register is cleared to 0 even if the condition is not satisfied

pull/78/head
BITDEFENDER\vlutas 2 years ago
parent 1805a9edec
commit 6dda2c122c

@ -1882,11 +1882,18 @@ ShemuEmulate(
break; break;
case ND_INS_CMOVcc: case ND_INS_CMOVcc:
GET_OP(Context, 0, &dst);
GET_OP(Context, 1, &src);
if (ShemuEvalCondition(Context, Context->Instruction.Condition)) if (ShemuEvalCondition(Context, Context->Instruction.Condition))
{ {
GET_OP(Context, 1, &src);
SET_OP(Context, 0, &src); SET_OP(Context, 0, &src);
} }
else
{
// Write back the same value that was already present in destination. This has the side-effect of
// clearing the upper 32 bit in the 64 bit destination register while in long mode.
SET_OP(Context, 0, &dst);
}
break; break;
case ND_INS_SETcc: case ND_INS_SETcc:

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@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution
from codecs import open from codecs import open
VERSION = (0, 1, 3) VERSION = (0, 1, 3)
LIBRARY_VERSION = (1, 34, 15) LIBRARY_VERSION = (1, 34, 16)
LIBRARY_INSTRUX_SIZE = 856 LIBRARY_INSTRUX_SIZE = 856
packages = ['pybddisasm'] packages = ['pybddisasm']

@ -7,6 +7,6 @@
#define DISASM_VERSION_MAJOR 1 #define DISASM_VERSION_MAJOR 1
#define DISASM_VERSION_MINOR 34 #define DISASM_VERSION_MINOR 34
#define DISASM_VERSION_REVISION 15 #define DISASM_VERSION_REVISION 16
#endif // DISASM_VER_H #endif // DISASM_VER_H

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