From 698ba367a105d9c0db637f29a6b7dedc92ca4ec4 Mon Sep 17 00:00:00 2001 From: Andrei Vlad LUTAS Date: Tue, 21 Jul 2020 11:19:18 +0300 Subject: [PATCH] Initial commit. --- .gitignore | 65 + .vsconfig | 21 + Makefile | 22 + README.md | 50 +- bddisasm.sln | 87 + bddisasm/Makefile | 123 + bddisasm/bddisasm.c | 5050 + bddisasm/bddisasm.vcproj | 474 + bddisasm/bddisasm.vcxproj | 458 + bddisasm/bddisasm.vcxproj.filters | 81 + bddisasm/crt.c | 44 + bddisasm/include/instructions.h | 35360 ++ bddisasm/include/mnemonics.h | 282 + bddisasm/include/nd_crt.h | 90 + bddisasm/include/prefixes.h | 34 + bddisasm/include/table_evex.h | 12254 + bddisasm/include/table_root.h | 15555 + bddisasm/include/table_vex.h | 11644 + bddisasm/include/table_xop.h | 1541 + bddisasm/include/tabledefs.h | 480 + bddisasm_test/README.md | 12 + bddisasm_test/amx/amx1_64 | Bin 0 -> 98 bytes bddisasm_test/amx/amx1_64.asm | 23 + bddisasm_test/amx/amx1_64.result | 263 + bddisasm_test/avx/avx2_64 | Bin 0 -> 2198 bytes bddisasm_test/avx/avx2_64.asm | 302 + bddisasm_test/avx/avx2_64.result | 5540 + bddisasm_test/avx/avx2gather_64 | Bin 0 -> 100 bytes bddisasm_test/avx/avx2gather_64.asm | 12 + bddisasm_test/avx/avx2gather_64.result | 180 + bddisasm_test/avx/avx_64 | Bin 0 -> 15667 bytes bddisasm_test/avx/avx_64.asm | 2200 + bddisasm_test/avx/avx_64.result | 40788 +++ bddisasm_test/avx/f16c_64 | 4 + bddisasm_test/avx/f16c_64.asm | 11 + bddisasm_test/avx/f16c_64.result | 136 + bddisasm_test/avx/fma4_64 | 1 + bddisasm_test/avx/fma4_64.asm | 133 + bddisasm_test/avx/fma4_64.result | 2240 + bddisasm_test/avx/fma_64 | 1 + bddisasm_test/avx/fma_64.asm | 198 + bddisasm_test/avx/fma_64.result | 3360 + bddisasm_test/avx512/avx512bitalg_64 | 1 + bddisasm_test/avx512/avx512bitalg_64.asm | 122 + bddisasm_test/avx512/avx512bitalg_64.result | 2358 + bddisasm_test/avx512/avx512bw_64 | Bin 0 -> 24734 bytes bddisasm_test/avx512/avx512bw_64.asm | 3492 + bddisasm_test/avx512/avx512bw_64.result | 71037 ++++ bddisasm_test/avx512/avx512cd_64 | 1 + bddisasm_test/avx512/avx512cd_64.asm | 248 + bddisasm_test/avx512/avx512cd_64.result | 4902 + bddisasm_test/avx512/avx512dq_64 | Bin 0 -> 13518 bytes bddisasm_test/avx512/avx512dq_64.asm | 1926 + bddisasm_test/avx512/avx512dq_64.result | 39404 ++ bddisasm_test/avx512/avx512er_64 | 1 + bddisasm_test/avx512/avx512er_64.asm | 226 + bddisasm_test/avx512/avx512er_64.result | 4504 + bddisasm_test/avx512/avx512f_64 | Bin 0 -> 94145 bytes bddisasm_test/avx512/avx512f_64.asm | 13534 + bddisasm_test/avx512/avx512f_64.result | 277669 +++++++++++++++ bddisasm_test/avx512/avx512fma_64 | 1 + bddisasm_test/avx512/avx512fma_64.asm | 122 + bddisasm_test/avx512/avx512fma_64.result | 2520 + bddisasm_test/avx512/avx512pf_64 | Bin 0 -> 176 bytes bddisasm_test/avx512/avx512pf_64.asm | 18 + bddisasm_test/avx512/avx512pf_64.result | 320 + bddisasm_test/avx512/avx512vbmi_64 | 1 + bddisasm_test/avx512/avx512vbmi_64.asm | 926 + bddisasm_test/avx512/avx512vbmi_64.result | 23586 ++ bddisasm_test/avx512/avx512vnni_64 | 1 + bddisasm_test/avx512/avx512vnni_64.asm | 242 + bddisasm_test/avx512/avx512vnni_64.result | 5040 + bddisasm_test/basic/address_16 | Bin 0 -> 71 bytes bddisasm_test/basic/address_16.asm | 31 + bddisasm_test/basic/address_16.result | 255 + bddisasm_test/basic/address_32 | Bin 0 -> 73 bytes bddisasm_test/basic/address_32.asm | 32 + bddisasm_test/basic/address_32.result | 255 + bddisasm_test/basic/address_64 | Bin 0 -> 195 bytes bddisasm_test/basic/address_64.asm | 81 + bddisasm_test/basic/address_64.result | 525 + bddisasm_test/basic/aes_64 | 5 + bddisasm_test/basic/aes_64.asm | 57 + bddisasm_test/basic/aes_64.result | 696 + bddisasm_test/basic/basic1_64 | Bin 0 -> 1600 bytes bddisasm_test/basic/basic1_64.asm | 562 + bddisasm_test/basic/basic1_64.result | 9088 + bddisasm_test/basic/basic2_64 | 7 + bddisasm_test/basic/basic2_64.asm | 171 + bddisasm_test/basic/basic2_64.result | 2604 + bddisasm_test/basic/bmi_64 | 4 + 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inc/bddisasm.h | 1454 + inc/bdshemu/bdshemu.h | 279 + inc/constants.h | 1687 + inc/cpuidflags.h | 107 + inc/disasmstatus.h | 57 + inc/disasmtypes.h | 20 + inc/registers.h | 148 + inc/version.h | 12 + isagenerator/Makefile | 4 + isagenerator/README.md | 184 + isagenerator/disasmlib.py | 1349 + isagenerator/generate_tables.py | 1262 + isagenerator/instructions/cpuid.dat | 112 + isagenerator/instructions/flags.dat | 95 + isagenerator/instructions/modes.dat | 78 + isagenerator/instructions/prefixes.dat | 35 + isagenerator/instructions/table_0F.dat | 668 + isagenerator/instructions/table_0F_38.dat | 128 + isagenerator/instructions/table_0F_3A.dat | 68 + isagenerator/instructions/table_3dnow.dat | 28 + isagenerator/instructions/table_base.dat | 445 + isagenerator/instructions/table_evex1.dat | 254 + isagenerator/instructions/table_evex2.dat | 343 + isagenerator/instructions/table_evex3.dat | 120 + isagenerator/instructions/table_fpu.dat | 175 + isagenerator/instructions/table_vex1.dat | 306 + isagenerator/instructions/table_vex2.dat | 212 + isagenerator/instructions/table_vex3.dat | 125 + isagenerator/instructions/table_xop.dat | 193 + isagenerator/isagenerator.vcxproj | 166 + isagenerator/isagenerator.vcxproj.filters | 84 + pydis/README.md | 21 + pydis/_pydis/_pydis.c | 1131 + pydis/_pydis/pydis.c | 34 + pydis/_pydis/pydis.h | 20 + pydis/pydis/__init__.py | 7 + pydis/pydis/__main__.py | 11 + pydis/pydis/__version__.py | 9 + pydis/pydis/app.py | 15 + pydis/pydis/core.py | 52 + pydis/pydis/disasm.py | 71 + pydis/pydis/helpers.py | 156 + pydis/setup.py | 53 + 448 files changed, 686845 insertions(+), 15 deletions(-) create mode 100644 .gitignore create mode 100644 .vsconfig create mode 100644 Makefile create mode 100644 bddisasm.sln create mode 100644 bddisasm/Makefile create mode 100644 bddisasm/bddisasm.c create mode 100644 bddisasm/bddisasm.vcproj create mode 100644 bddisasm/bddisasm.vcxproj create mode 100644 bddisasm/bddisasm.vcxproj.filters create mode 100644 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bdshemu_test/basic/test_64_branch1.result create mode 100644 bdshemu_test/basic/test_64_branch2 create mode 100644 bdshemu_test/basic/test_64_branch2.asm create mode 100644 bdshemu_test/basic/test_64_branch2.result create mode 100644 bdshemu_test/basic/test_64_branch3 create mode 100644 bdshemu_test/basic/test_64_branch3.asm create mode 100644 bdshemu_test/basic/test_64_branch3.result create mode 100644 bdshemu_test/basic/test_64_branch4 create mode 100644 bdshemu_test/basic/test_64_branch4.asm create mode 100644 bdshemu_test/basic/test_64_branch4.result create mode 100644 bdshemu_test/basic/test_64_div create mode 100644 bdshemu_test/basic/test_64_div.asm create mode 100644 bdshemu_test/basic/test_64_div.result create mode 100644 bdshemu_test/basic/test_64_eicar create mode 100644 bdshemu_test/basic/test_64_eicar.asm create mode 100644 bdshemu_test/basic/test_64_eicar.result create mode 100644 bdshemu_test/basic/test_64_flags create mode 100644 bdshemu_test/basic/test_64_flags.asm create mode 100644 bdshemu_test/basic/test_64_flags.result create mode 100644 bdshemu_test/basic/test_64_loadrip01 create mode 100644 bdshemu_test/basic/test_64_loadrip01.asm create mode 100644 bdshemu_test/basic/test_64_loadrip01.result create mode 100644 bdshemu_test/basic/test_64_loadrip02 create mode 100644 bdshemu_test/basic/test_64_loadrip02.asm create mode 100644 bdshemu_test/basic/test_64_loadrip02.result create mode 100644 bdshemu_test/basic/test_64_loadrip03 create mode 100644 bdshemu_test/basic/test_64_loadrip03.asm create mode 100644 bdshemu_test/basic/test_64_loadrip03.result create mode 100644 bdshemu_test/basic/test_64_moffset create mode 100644 bdshemu_test/basic/test_64_moffset.asm create mode 100644 bdshemu_test/basic/test_64_moffset.result create mode 100644 bdshemu_test/basic/test_64_mov create mode 100644 bdshemu_test/basic/test_64_mov.asm create mode 100644 bdshemu_test/basic/test_64_mov.result create mode 100644 bdshemu_test/basic/test_64_nopsled01 create mode 100644 bdshemu_test/basic/test_64_nopsled01.asm create mode 100644 bdshemu_test/basic/test_64_nopsled01.result create mode 100644 bdshemu_test/basic/test_64_nopsled02 create mode 100644 bdshemu_test/basic/test_64_nopsled02.asm create mode 100644 bdshemu_test/basic/test_64_nopsled02.result create mode 100644 bdshemu_test/basic/test_64_nopsled03 create mode 100644 bdshemu_test/basic/test_64_nopsled03.asm create mode 100644 bdshemu_test/basic/test_64_nopsled03.result create mode 100644 bdshemu_test/basic/test_64_selfwrite01 create mode 100644 bdshemu_test/basic/test_64_selfwrite01.asm create mode 100644 bdshemu_test/basic/test_64_selfwrite01.result create mode 100644 bdshemu_test/basic/test_64_selfwrite02 create mode 100644 bdshemu_test/basic/test_64_selfwrite02.asm create mode 100644 bdshemu_test/basic/test_64_selfwrite02.result create mode 100644 bdshemu_test/basic/test_64_selfwrite03 create mode 100644 bdshemu_test/basic/test_64_selfwrite03.asm create mode 100644 bdshemu_test/basic/test_64_selfwrite03.result create mode 100644 bdshemu_test/basic/test_64_string create mode 100644 bdshemu_test/basic/test_64_string.asm create mode 100644 bdshemu_test/basic/test_64_string.result create mode 100644 bdshemu_test/basic/test_64_sys01 create mode 100644 bdshemu_test/basic/test_64_sys01.asm create mode 100644 bdshemu_test/basic/test_64_sys01.result create mode 100644 bdshemu_test/basic/test_64_sys02 create mode 100644 bdshemu_test/basic/test_64_sys02.asm create mode 100644 bdshemu_test/basic/test_64_sys02.result create mode 100644 bdshemu_test/basic/test_64_sys03 create mode 100644 bdshemu_test/basic/test_64_sys03.asm create mode 100644 bdshemu_test/basic/test_64_sys03.result create mode 100644 bdshemu_test/test_all.py create mode 100644 disasmtool/disasmtool.c create mode 100644 disasmtool/disasmtool.vcxproj create mode 100644 disasmtool/disasmtool.vcxproj.filters create mode 100644 disasmtool_lix/CMakeLists.txt create mode 100644 disasmtool_lix/Makefile create mode 100644 disasmtool_lix/disasm.hpp create mode 100644 disasmtool_lix/disasmtool.cpp create mode 100644 disasmtool_lix/dumpers.cpp create mode 100644 disasmtool_lix/external/argparse.h create mode 100644 disasmtool_lix/rapidjson.cpp create mode 100644 docs/Makefile create mode 100644 docs/make.bat create mode 100644 docs/source/conf.py create mode 100644 docs/source/index.rst create mode 100644 inc/bddisasm.h create mode 100644 inc/bdshemu/bdshemu.h create mode 100644 inc/constants.h create mode 100644 inc/cpuidflags.h create mode 100644 inc/disasmstatus.h create mode 100644 inc/disasmtypes.h create mode 100644 inc/registers.h create mode 100644 inc/version.h create mode 100644 isagenerator/Makefile create mode 100644 isagenerator/README.md create mode 100644 isagenerator/disasmlib.py create mode 100644 isagenerator/generate_tables.py create mode 100644 isagenerator/instructions/cpuid.dat create mode 100644 isagenerator/instructions/flags.dat create mode 100644 isagenerator/instructions/modes.dat create mode 100644 isagenerator/instructions/prefixes.dat create mode 100644 isagenerator/instructions/table_0F.dat create mode 100644 isagenerator/instructions/table_0F_38.dat create mode 100644 isagenerator/instructions/table_0F_3A.dat create mode 100644 isagenerator/instructions/table_3dnow.dat create mode 100644 isagenerator/instructions/table_base.dat create mode 100644 isagenerator/instructions/table_evex1.dat create mode 100644 isagenerator/instructions/table_evex2.dat create mode 100644 isagenerator/instructions/table_evex3.dat create mode 100644 isagenerator/instructions/table_fpu.dat create mode 100644 isagenerator/instructions/table_vex1.dat create mode 100644 isagenerator/instructions/table_vex2.dat create mode 100644 isagenerator/instructions/table_vex3.dat create mode 100644 isagenerator/instructions/table_xop.dat create mode 100644 isagenerator/isagenerator.vcxproj create mode 100644 isagenerator/isagenerator.vcxproj.filters create mode 100644 pydis/README.md create mode 100644 pydis/_pydis/_pydis.c create mode 100644 pydis/_pydis/pydis.c create mode 100644 pydis/_pydis/pydis.h create mode 100644 pydis/pydis/__init__.py create mode 100644 pydis/pydis/__main__.py create mode 100644 pydis/pydis/__version__.py create mode 100644 pydis/pydis/app.py create mode 100644 pydis/pydis/core.py create mode 100644 pydis/pydis/disasm.py create mode 100644 pydis/pydis/helpers.py create mode 100644 pydis/setup.py diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..587ccdd --- /dev/null +++ b/.gitignore @@ -0,0 +1,65 @@ +syntax: glob +# Object files +*.o +*.obj + +# Libraries +*.lib +*.a + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.sys + +#VS/WDK project files +*.ilk +*.pdb +*.user +*.mac +*.res +*.log +build*_*_*.xml +*.suo +*.sdf +*.opensdf +*.tlog +*.ipch +vc*.idb +/bin/ +/_intdir/ +*.aps +*.vcxprojResolveAssemblyReference.cache +*.manifest +*.unsuccessfulbuild +UpgradeLog*.XML +_UpgradeReport_Files/* +*.sbr + +#other files +*.pyc +.*.swp +*.pyd +pydis/pydis.egg-info/ +pydis/build/ +pydis/dist/ +.vs/ + +disasmtool_lix/build +.dir-locals.el +.ccls-cache/ +compile_commands.json +.gdb_history +pydis/.eggs +bdshemu_fuzz/out +bdshemu_fuzz/shfuzz +bdshemu_fuzz/out-32 +bdshemu_fuzz/out-64 +docs/build diff --git a/.vsconfig b/.vsconfig new file mode 100644 index 0000000..d5d7d24 --- /dev/null +++ b/.vsconfig @@ -0,0 +1,21 @@ +{ + "version": "1.0", + "components": [ + "Microsoft.VisualStudio.Component.CoreEditor", + "Microsoft.VisualStudio.Workload.CoreEditor", + "Microsoft.VisualStudio.Component.Roslyn.Compiler", + "Microsoft.Component.MSBuild", + "Microsoft.VisualStudio.Component.TextTemplating", + "Microsoft.VisualStudio.Component.IntelliCode", + "Microsoft.VisualStudio.Component.VC.CoreIde", + "Microsoft.VisualStudio.Component.VC.Tools.x86.x64", + "Microsoft.VisualStudio.Component.Windows10SDK.18362", + "Microsoft.VisualStudio.Component.VC.Redist.14.Latest", + "Microsoft.VisualStudio.ComponentGroup.NativeDesktop.Core", + "Microsoft.VisualStudio.ComponentGroup.WebToolsExtensions.CMake", + "Microsoft.VisualStudio.Component.VC.CMake.Project", + "Microsoft.VisualStudio.Component.VC.ATL", + "Microsoft.VisualStudio.Workload.NativeDesktop", + "Microsoft.VisualStudio.Component.VC.Runtimes.x86.x64.Spectre" + ] +} \ No newline at end of file diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..c575013 --- /dev/null +++ b/Makefile @@ -0,0 +1,22 @@ +.PHONY: all bddisasm bdshemu + +all: bddisasm bdshemu + +bddisasm: + @$(MAKE) --no-print-directory -C bddisasm + @$(MAKE) --no-print-directory RELEASE=y -C bddisasm + +bdshemu: + @$(MAKE) --no-print-directory -C bdshemu + @$(MAKE) --no-print-directory RELEASE=y -C bdshemu + +clean: + @$(MAKE) --no-print-directory -C bddisasm clean + @$(MAKE) --no-print-directory RELEASE=y -C bddisasm clean + @$(MAKE) --no-print-directory -C bdshemu clean + @$(MAKE) --no-print-directory RELEASE=y -C bdshemu clean + +install: + @$(MAKE) --no-print-directory RELEASE=y -C bddisasm install + @$(MAKE) --no-print-directory RELEASE=y -C bdshemu install + \ No newline at end of file diff --git a/README.md b/README.md index 8483244..1b3ed01 100644 --- a/README.md +++ b/README.md @@ -1,30 +1,30 @@ # The Bitdefender disassembler -The Bitdefender disassembler is a lightweight, x86/x64 only instruction decoder. It is easy to integrate, easy to work with, it has no external dependencies, it is thread-safe, it allocates no memory at all, it works in virtually any environment (we use it inside user, kernel, hypervisor, on both Windows and Linux environments), and it provides lots of info regarding the decoded instructions, such as: operands (both explicit and implicit), access mode for each operand, CPUID feature flag, flags access, etc. +The Bitdefender disassembler (bddisasm) is a lightweight, x86/x64 only instruction decoder. It is easy to integrate, easy to work with, it has no external dependencies, it is thread-safe, it allocates no memory at all, it works in virtually any environment (we use it inside user, kernel, hypervisor, on both Windows and Linux environments), and it provides lots of info regarding the decoded instructions, such as: operands (both explicit and implicit), access mode for each operand, CPUID feature flag, flags access, etc. More examples and info about the project can be found on the official documentation: [Bitdefender disassembler](http://bddisasm.readthedocs.io) ## Projects -1. disasm - this is the main disassembler project. In order to use the Bitdefender disassembler, all you have to do is build this project, and link with the output library. The only headers you need are located inside the inc folder. +1. bddisasm - this is the main disassembler project. In order to use the Bitdefender disassembler, all you have to do is build this project, and link with the output library. The only headers you need are located inside the `inc` folder. -2. shemu - this project makes use of the main disasm lib in order to build a simple, lightweight, fast, instructions emulator, designated to target shellcodes. This project is also integrated inside the disasmtool, so you can -emulate raw binary files, and see their output. Note that this simple emulator supports basic x86/x64 instructions, and does not support emulating any kind of API call. +2. bdshemu - this project makes use of the main bddisasm lib in order to build a simple, lightweight, fast, instructions emulator, designated to target shellcodes. This project is also integrated inside the disasmtool, so you can +emulate raw binary files, and see their output. Note that this simple emulator supports basic x86/x64 instructions, and does not support emulating any kind of API call. In addition, the only supported memory accesses are inside the shellcode itself, and on the emulated stack. -3. isagenerator - this project contains the instruction definitions and the scripts required to generate the disassembly tables. If you wish to add support for a new instruction, this is the place. This project will automatically generate several header files (instructions.h, mnemonics.h, constants.h, table_\*.h), so please make sure you don't manually edit any of these files. +3. isagenerator - this project contains the instruction definitions and the scripts required to generate the disassembly tables. If you wish to add support for a new instruction, this is the place. This project will automatically generate several header files (instructions.h, mnemonics.h, constants.h, table_\*.h), so please make sure you don't manually edit any of these files. You will need Python 3 to run the generation scripts. -4. disasmtool - this project is a command line disassembler tool, used mainly as an example of how to integrate the disasm lib. +4. disasmtool - this project is a command line disassembler tool, used mainly as an example of how to integrate the bddisasm and bdshemu libraries. 5. disasmtool_lix - like disasmtool, but for Linux. -6. pydis - this is the Python binding for the disasm project. +6. pydis - this is the Python binding for the bddisasm project. You will need Python 3 for this. ## Objectives The main objectives of this disassembler are: 1. Lighetweight - it's written in C, with no external dependencies, no memory allocated, and thread safe by design. -2. Fast - less than 300 CPU clocks on a Intel Core i7-8650U per decoded instruction. -3. Resilient - tested against internal fuzzers and the famous [mishegos](https://github.com/trailofbits/mishegos) tool -4. Easy to work with - just include the main header file, disasm.h, link with the disasmlib library, and call the NdDecode API! +2. Fast - less than 300 CPU clocks on an Intel Core i7-8650U per decoded instruction (more than 7M instructions per second). +3. Resilient - tested against internal fuzzers and the famous [mishegos](https://github.com/trailofbits/mishegos) tool. +4. Easy to work with - just include the main header file, bddisasm.h, link with the bddisasm library, and call the NdDecode API! 5. Complete - support every x86 instruction to date, and provide as much information as possible. ## Build @@ -35,13 +35,14 @@ In order to build the projects on Windows you need: * [Visual Studio 2019](https://visualstudio.microsoft.com/vs/) with the Desktop development with C++ workload. * [Windows SDK 10.0.18362.0](https://developer.microsoft.com/en-us/windows/downloads/windows-10-sdk/). +* [Python 3.7 or newer](https://www.python.org/downloads/release/python-373/) When you first open the solution Visual Studio should prompt you to install any missing components. -This should be enough to build disasm, disasmtool and shemu for the Debug and Release configurations. +This should be enough to build bddisasm, disasmtool and bdshemu for the Debug and Release configurations. For the DebugKernel and ReleaseKernel configurations, [WDK 1903](https://go.microsoft.com/fwlink/?linkid=2085767) is needed, alongside the Windows Driver Kit Visual Studio extension (the WDK installer should take care of this). -For isagenerator, python is needed. +For isagenerator, Python 3 is needed. Building any of the projects is done directly from Visual Studio. @@ -60,16 +61,35 @@ For disasmtool_lix you also need: * cmake 3.12 or newer * [RapidJSON](https://github.com/Tencent/rapidjson/) -In order to build disasm and shemu run `make` in the root of the repository. The results will be placed in the bin directory. +In order to build bddisasm and bdshemu run `make` in the root of the repository. The results will be placed in the bin directory. In order to build disasmtool_lix go to the disasmtool_lix directory and run `make`. The results will be in the bin directory in the disasmtool_lix/build directory. ## Example -Working with disasm is very easy. Decoding and printing the disassembly of an instruction is quick & simple: +Working with bddisasm is very easy. Decoding and printing the disassembly of an instruction is quick & simple: ```c -#include "disasm.h" +#include +#include "bddisasm/disasmtypes.h" +#include "bddisasm/bddisasm.h" + +int nd_vsnprintf_s( + char *buffer, + size_t sizeOfBuffer, + size_t count, + const char *format, + va_list argptr + ) +{ + return vsnprintf(buffer, sizeOfBuffer, format, argptr); +} + +void* nd_memset(void *s, int c, size_t n) +{ + return memset(s, c, n); +} + int main() { diff --git a/bddisasm.sln b/bddisasm.sln new file mode 100644 index 0000000..e716baa --- /dev/null +++ b/bddisasm.sln @@ -0,0 +1,87 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio Version 16 +VisualStudioVersion = 16.0.29519.87 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "disasmtool", "disasmtool\disasmtool.vcxproj", "{94F1B65D-3305-4CCB-9DF1-50B56900D867}" + ProjectSection(ProjectDependencies) = postProject + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA} = {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "bddisasm", "bddisasm\bddisasm.vcxproj", "{3653AA19-048B-410E-B5C4-FF78E1D84C12}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "bdshemu", "bdshemu\bdshemu.vcxproj", "{3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}" + ProjectSection(ProjectDependencies) = postProject + {3653AA19-048B-410E-B5C4-FF78E1D84C12} = {3653AA19-048B-410E-B5C4-FF78E1D84C12} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "isagenerator", "isagenerator\isagenerator.vcxproj", "{0E9D2957-34FA-40EE-B4B2-0D008D2FE317}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Debug|x64 = Debug|x64 + DebugKernel|Win32 = DebugKernel|Win32 + DebugKernel|x64 = DebugKernel|x64 + Release|Win32 = Release|Win32 + Release|x64 = Release|x64 + ReleaseKernel|Win32 = ReleaseKernel|Win32 + ReleaseKernel|x64 = ReleaseKernel|x64 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.Debug|Win32.ActiveCfg = Debug|Win32 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.Debug|x64.ActiveCfg = Debug|x64 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.DebugKernel|Win32.ActiveCfg = Debug|Win32 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.DebugKernel|x64.ActiveCfg = Debug|x64 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.Release|Win32.ActiveCfg = Release|Win32 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.Release|x64.ActiveCfg = Release|x64 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.ReleaseKernel|Win32.ActiveCfg = Release|Win32 + {94F1B65D-3305-4CCB-9DF1-50B56900D867}.ReleaseKernel|x64.ActiveCfg = Release|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Debug|Win32.ActiveCfg = Debug|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Debug|Win32.Build.0 = Debug|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Debug|x64.ActiveCfg = Debug|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Debug|x64.Build.0 = Debug|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.DebugKernel|Win32.ActiveCfg = DebugKernel|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.DebugKernel|Win32.Build.0 = DebugKernel|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.DebugKernel|x64.ActiveCfg = DebugKernel|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.DebugKernel|x64.Build.0 = DebugKernel|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Release|Win32.ActiveCfg = Release|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Release|Win32.Build.0 = Release|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Release|x64.ActiveCfg = Release|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.Release|x64.Build.0 = Release|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.ReleaseKernel|Win32.ActiveCfg = ReleaseKernel|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.ReleaseKernel|Win32.Build.0 = ReleaseKernel|Win32 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.ReleaseKernel|x64.ActiveCfg = ReleaseKernel|x64 + {3653AA19-048B-410E-B5C4-FF78E1D84C12}.ReleaseKernel|x64.Build.0 = ReleaseKernel|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Debug|Win32.ActiveCfg = Debug|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Debug|Win32.Build.0 = Debug|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Debug|x64.ActiveCfg = Debug|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Debug|x64.Build.0 = Debug|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.DebugKernel|Win32.ActiveCfg = DebugKernel|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.DebugKernel|Win32.Build.0 = DebugKernel|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.DebugKernel|x64.ActiveCfg = DebugKernel|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.DebugKernel|x64.Build.0 = DebugKernel|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Release|Win32.ActiveCfg = Release|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Release|Win32.Build.0 = Release|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Release|x64.ActiveCfg = Release|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.Release|x64.Build.0 = Release|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.ReleaseKernel|Win32.ActiveCfg = ReleaseKernel|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.ReleaseKernel|Win32.Build.0 = ReleaseKernel|Win32 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.ReleaseKernel|x64.ActiveCfg = ReleaseKernel|x64 + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA}.ReleaseKernel|x64.Build.0 = ReleaseKernel|x64 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.Debug|Win32.ActiveCfg = Debug|Win32 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.Debug|x64.ActiveCfg = Debug|x64 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.DebugKernel|Win32.ActiveCfg = Debug|Win32 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.DebugKernel|x64.ActiveCfg = Debug|x64 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.Release|Win32.ActiveCfg = Release|Win32 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.Release|x64.ActiveCfg = Release|x64 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.ReleaseKernel|Win32.ActiveCfg = Release|Win32 + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317}.ReleaseKernel|x64.ActiveCfg = Release|x64 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection + GlobalSection(ExtensibilityGlobals) = postSolution + SolutionGuid = {E950FA16-07C1-4613-8328-906BC10C7C02} + EndGlobalSection +EndGlobal diff --git a/bddisasm/Makefile b/bddisasm/Makefile new file mode 100644 index 0000000..cbfd9d4 --- /dev/null +++ b/bddisasm/Makefile @@ -0,0 +1,123 @@ +.PHONY: clean + +SRC_FILES := crt.c bddisasm.c + +OBJECTS := $(SRC_FILES:.c=.o) + +INCLUDES := -Iinclude -I../inc + +ifeq ($(PLATFORM),) + PLATFORM := x64 +endif + +ifeq ($(RELEASE),y) + CONFIGURATION := Release +else + CONFIGURATION := Debug +endif + +ifeq ($(PREFIX),) + PREFIX := /usr/local +endif + +DEFINES := -D_LIB -DAMD64 + +INT_DIR := ../_intdir/bddisasm/$(PLATFORM)/$(CONFIGURATION) + +DEP_DIR := $(INT_DIR)/.d + +OUT_DIR := ../bin/$(PLATFORM)/$(CONFIGURATION) + +OBJECTS_PATH := $(addprefix $(INT_DIR)/, $(OBJECTS)) + +LIB_NAME := libbddisasm.a + +WARNINGS_ENABLE := -Wall -Wextra -Wshadow -Wstrict-overflow \ + -Wframe-larger-than=3072 -Wstack-usage=3072 + +WARNINGS_DISABLE := -Wno-missing-field-initializers \ + -Wno-missing-braces \ + -Wno-unused-function \ + -Wno-unused-variable \ + -Wno-unknown-pragmas \ + -Wno-format \ + -Wno-multichar + +# Some warnings are compiler-specific, some version-specific +ifeq (,$(findstring clang,$(CC))) + CC_VERSION_MAJOR = $(shell $(CC) -dumpversion | cut -d '.' -f1) + CC_VERSION_GT_4 = $(shell [ $(CC_VERSION_MAJOR) -gt 4 ] && echo true) + CC_VERSION_GT_5 = $(shell [ $(CC_VERSION_MAJOR) -gt 5 ] && echo true) + + ifeq (true,$(CC_VERSION_GT_4)) + WARNINGS_DISABLE += -Wno-incompatible-pointer-types + endif + + ifeq (true,$(CC_VERSION_GT_5)) + WARNINGS_ENABLE += -Wshift-overflow=2 \ + -Wnull-dereference \ + -Wduplicated-cond + endif +else + WARNINGS_DISABLE += -Wno-typedef-redefinition \ + -Wno-missing-braces \ + -Wno-incompatible-pointer-types \ + -Wno-missing-field-initializers +endif + +DEPFLAGS = -MT $@ -MMD -MP -MF $(DEP_DIR)/$*.Td + +CFLAGS = -pipe -c -std=c11 -fpic -fno-strict-aliasing \ + -D_REENTRANT -fstack-protector -ffunction-sections -fdata-sections \ + $(WARNINGS_ENABLE) $(WARNINGS_DISABLE) $(DEFINES) $(INCLUDES) + +ifeq ($(RELEASE),y) + CFLAGS += -Ofast -g3 -DNDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=1 +else + CFLAGS += -O0 -g3 -D_DEBUG -DDEBUG +endif + +all: $(LIB_NAME) + +# Here it will link the objects created below in the final .a +$(LIB_NAME): $(OBJECTS_PATH) + @mkdir -p $(OUT_DIR) + @ar rcs $(OUT_DIR)/$(LIB_NAME) $(OBJECTS_PATH) + @echo Disasm library in $(OUT_DIR)/$(LIB_NAME) + +# We need to mkdir inside the rule, so each subfolder gets created, +# and avoiding conflicts: +# ./linux/example.c => $(INT_DIR)/linux/example.o +# ./example.c => $(INT_DIR)/example.o +$(INT_DIR)/%.o: %.c $(DEP_DIR)/%.d + @mkdir -p $(dir $@) + @mkdir -p $(dir $(DEP_DIR)/$<) >/dev/null + @echo $< + @$(CC) $(DEPFLAGS) $(CFLAGS) -c $< -o $@ + @mv -f $(DEP_DIR)/$*.Td $(DEP_DIR)/$*.d + +# So 'make' won't fail if the dependecy file doesn't exist +$(DEP_DIR)/%.d: ; + +# Don't delete the dependecy files +.PRECIOUS: $(DEP_DIR)/%.d + +# Include all the dependecy files (this will trigger a rebuild if a header is changed) +-include $(patsubst %,$(DEP_DIR)/%.d,$(basename $(SRC_FILES))) + +clean_lib_file: + @rm $(OUT_DIR)/$(LIB_NAME) 2>/dev/null ||: + +clean_int_dir: + @rm -r $(INT_DIR) 2>/dev/null ||: + +clean_dep_dir: + @rm -r $(DEP_DIR) 2>/dev/null ||: + +clean: clean_lib_file clean_int_dir clean_dep_dir + +install: all + install -d $(DESTDIR)$(PREFIX)/lib/ + install -m 644 $(OUT_DIR)/$(LIB_NAME) $(DESTDIR)$(PREFIX)/lib/ + install -d $(DESTDIR)$(PREFIX)/include/bddisasm + cp -r ../inc/* $(DESTDIR)$(PREFIX)/include/bddisasm/ \ No newline at end of file diff --git a/bddisasm/bddisasm.c b/bddisasm/bddisasm.c new file mode 100644 index 0000000..34f0f31 --- /dev/null +++ b/bddisasm/bddisasm.c @@ -0,0 +1,5050 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#include "include/nd_crt.h" +#include "../inc/bddisasm.h" + +// The table definitions. +#include "include/tabledefs.h" + +// Handy macros. +#define RET_EQ(x, y, z) if ((x) == (y)) { return (z); } +#define RET_GE(x, y, z) if ((x) >= (y)) { return (z); } +#define RET_GT(x, y, z) if ((x) > (y)) { return (z); } + + +static const char *gReg8Bit[] = +{ + "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", +}; + +static const char *gReg8Bit64[] = +{ + "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", + "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", +}; + +static const char *gReg16Bit[] = +{ + "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", + "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w", +}; + +static const char *gReg32Bit[] = +{ + "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", + "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", +}; + +static const char *gReg64Bit[] = +{ + "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" +}; + +static const char *gRegFpu[] = +{ + "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", +}; + +static const char *gRegMmx[] = +{ + "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", +}; + +static const char *gRegControl[] = +{ + "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", + "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15", +}; + +static const char *gRegDebug[] = +{ + "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", + "dr8", "dr9", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15", +}; + +static const char *gRegTest[] = +{ + "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", + "tr8", "tr9", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15", +}; + +static const char *gRegXmm[] = +{ + "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", + "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", + "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", + "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", +}; + +static const char *gRegYmm[] = +{ + "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", + "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", + "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", + "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31" +}; + +static const char *gRegZmm[] = +{ + "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", + "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", + "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", + "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", +}; + +static const char *gRegSeg[] = +{ + "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7", +}; + +static const char *gRegBound[] = +{ + "bnd0", "bnd1", "bnd2", "bnd3", +}; + +static const char *gRegMask[] = +{ + "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", +}; + +static const char *gRegTile[] = +{ + "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", +}; + +static const char *gConditionCodes[] = +{ + "EQ", "LT", "LE", "UNORD", "NEQ", "NLT", "NLE", "ORD", + "EQ_UQ", "NGE", "NGT", "false", "NEQ_OQ", "GE", "GT", "TRUE", + "EQ_OS", "LT_OQ", "LE_OQ", "UNORD_S", "NEQ_US", "NLT_UQ", "NLE_UQ", "ORD_S", + "EQ_US", "NGE_UQ", "NGT_UQ", "FALSE_OS", "NEQ_OS", "GE_OQ", "GT_OQ", "TRUE_US", +}; + +static const char *gEmbeddedRounding[] = +{ + "rn", "rd", "ru", "rz", +}; + +static const uint16_t gOperandMap[] = +{ + ND_OPE_D, // ND_OPT_A + ND_OPE_V, // ND_OPT_B + ND_OPE_R, // ND_OPT_C + ND_OPE_R, // ND_OPT_D + ND_OPE_M, // ND_OPT_E + ND_OPE_S, // ND_OPT_F + ND_OPE_R, // ND_OPT_G + ND_OPE_V, // ND_OPT_H + ND_OPE_I, // ND_OPT_I + ND_OPE_D, // ND_OPT_J + ND_OPE_S, // ND_OPT_K + ND_OPE_L, // ND_OPT_L + ND_OPE_M, // ND_OPT_M + ND_OPE_M, // ND_OPT_N + ND_OPE_D, // ND_OPT_O + ND_OPE_R, // ND_OPT_P + ND_OPE_M, // ND_OPT_Q + ND_OPE_M, // ND_OPT_R + ND_OPE_R, // ND_OPT_S + ND_OPE_R, // ND_OPT_T + ND_OPE_M, // ND_OPT_U + ND_OPE_R, // ND_OPT_V + ND_OPE_M, // ND_OPT_W + ND_OPE_S, // ND_OPT_X + ND_OPE_S, // ND_OPT_Y + ND_OPE_O, // ND_OPT_Z + ND_OPE_R, // ND_OPT_rB + ND_OPE_M, // ND_OPT_mB + ND_OPE_R, // ND_OPT_rK + ND_OPE_V, // ND_OPT_vK + ND_OPE_M, // ND_OPT_mK + ND_OPE_A, // ND_OPT_aK + ND_OPE_R, // ND_OPT_mR + ND_OPE_M, // ND_OPT_mM + ND_OPE_R, // ND_OPT_rT + ND_OPE_M, // ND_OPT_mT + ND_OPE_V, // ND_OPT_vT + ND_OPE_1, // ND_OPT_1 + + ND_OPE_S, // ND_OPT_RIP + ND_OPE_S, // ND_OPT_MXCSR + ND_OPE_S, // ND_OPT_PKRU + ND_OPE_S, // ND_OPT_SSP + + ND_OPE_S, // ND_OPT_GPR_AH + ND_OPE_S, // ND_OPT_GPR_rAX + ND_OPE_S, // ND_OPT_GPR_rCX + ND_OPE_S, // ND_OPT_GPR_rDX + ND_OPE_S, // ND_OPT_GPR_rBX + ND_OPE_S, // ND_OPT_GPR_rSP + ND_OPE_S, // ND_OPT_GPR_rBP + ND_OPE_S, // ND_OPT_GPR_rSI + ND_OPE_S, // ND_OPT_GPR_rDI + ND_OPE_S, // ND_OPT_GPR_rR11 + + ND_OPE_S, // ND_OPT_SEG_CS + ND_OPE_S, // ND_OPT_SEG_SS + ND_OPE_S, // ND_OPT_SEG_DS + ND_OPE_S, // ND_OPT_SEG_ES + ND_OPE_S, // ND_OPT_SEG_FS + ND_OPE_S, // ND_OPT_SEG_GS + + ND_OPE_S, // ND_OPT_FPU_ST0 + ND_OPE_M, // ND_OPT_FPU_STX + + ND_OPE_S, // ND_OPT_SSE_XMM0 + + ND_OPE_S, // ND_OPT_MEM_rBX_AL (as used by XLAT) + ND_OPE_S, // ND_OPT_MEM_rDI (as used by masked moves) + ND_OPE_S, // ND_OPT_MEM_SHS + + ND_OPE_S, // ND_OPT_CR_0 + ND_OPE_S, // ND_OPT_IDTR + ND_OPE_S, // ND_OPT_GDTR + ND_OPE_S, // ND_OPT_LDTR + ND_OPE_S, // ND_OPT_TR + + ND_OPE_S, // ND_OPT_X87_CONTROL + ND_OPE_S, // ND_OPT_X87_TAG + ND_OPE_S, // ND_OPT_X87_STATUS + + ND_OPE_E, // ND_OPT_MSR + ND_OPE_E, // ND_OPT_XCR + ND_OPE_S, // ND_OPT_MSR_TSC + ND_OPE_S, // ND_OPT_MSR_TSCAUX + ND_OPE_S, // ND_OPT_MSR_SEIP + ND_OPE_S, // ND_OPT_MSR_SESP + ND_OPE_S, // ND_OPT_MSR_SCS + ND_OPE_S, // ND_OPT_MSR_STAR + ND_OPE_S, // ND_OPT_MSR_LSTAR + ND_OPE_S, // ND_OPT_MSR_FMASK + ND_OPE_S, // ND_OPT_MSR_FSBASE + ND_OPE_S, // ND_OPT_MSR_GSBASE + ND_OPE_S, // ND_OPT_MSR_KGSBASE + ND_OPE_S, // ND_OPT_XCR_0 + ND_OPE_S, // ND_OPT_REG_BANK + ND_OPE_S, // Unused. +}; + + +static const uint8_t gDispsizemap16[4][8] = +{ + { 0, 0, 0, 0, 0, 0, 2, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1 }, + { 2, 2, 2, 2, 2, 2, 2, 2 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, +}; + +static const uint8_t gDispsizemap[4][8] = +{ + { 0, 0, 0, 0, 0, 4, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1 }, + { 4, 4, 4, 4, 4, 4, 4, 4 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, +}; + + +// +// NdGetVersion +// +void +NdGetVersion( + uint32_t *Major, + uint32_t *Minor, + uint32_t *Revision, + char **BuildDate, + char **BuildTime + ) +{ + if (NULL != Major) + { + *Major = DISASM_VERSION_MAJOR; + } + + if (NULL != Minor) + { + *Minor = DISASM_VERSION_MINOR; + } + + if (NULL != Revision) + { + *Revision = DISASM_VERSION_REVISION; + } + + if (NULL != BuildDate) + { + *BuildDate = __DATE__; + } + + if (NULL != BuildTime) + { + *BuildTime = __TIME__; + } +} + +#ifndef KERNEL_MODE +// +// NdSprintf +// +static NDSTATUS +NdSprintf( + char *Destination, + size_t DestinationSize, + const char *Formatstring, + ... + ) +// +// Wrapper on vsnprintf. +// +{ + int res; + va_list args; + + if (NULL == Destination) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (NULL == Formatstring) + { + return ND_STATUS_INVALID_PARAMETER; + } + + nd_memzero(Destination, DestinationSize); + + va_start(args, Formatstring); + + // _vsnprintf is used instead of the more secure _vsnprintf_s because the mini-Petru supports just + // the unsecured version, and we depend on it. + res = nd_vsnprintf_s(Destination, DestinationSize, DestinationSize - 1, Formatstring, args); + + va_end(args); + + if ((res < 0) || ((size_t)res >= DestinationSize - 1)) + { + return ND_STATUS_BUFFER_OVERFLOW; + } + + return ND_STATUS_SUCCESS; +} +#else +#define NdSprintf(Destination, DestinationSize, Formatstring, ...) RtlStringCbPrintfA(Destination, \ + DestinationSize, \ + Formatstring, \ + __VA_ARGS__); +#endif + + +// +// NdFetchData +// +static uint64_t +NdFetchData( + const uint8_t *Buffer, + uint8_t Size + ) +{ + return (4 == Size) ? ND_FETCH_32(Buffer) : + (1 == Size) ? ND_FETCH_8(Buffer) : + (8 == Size) ? ND_FETCH_64(Buffer) : + (2 == Size) ? ND_FETCH_16(Buffer) : + 0; +} + + +// +// NdFetchXop +// +static NDSTATUS +NdFetchXop( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // Offset points to the 0x8F XOP prefix. + // One more byte has to follow, the modrm or the second XOP byte. + RET_GT((size_t)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL); + + if (((Code[Offset + 1] & 0x1F) >= 8)) + { + // XOP found, make sure the third byte is here. + RET_GT((size_t)Offset + 3, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // Make sure we don't have any other prefix. + if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || Instrux->HasRepRepzXrelease || Instrux->HasRex) + { + return ND_STATUS_XOP_WITH_PREFIX; + } + + // Fill in XOP info. + Instrux->HasXop = true; + Instrux->EncMode = ND_ENCM_XOP; + Instrux->Xop.Xop[0] = Code[Offset]; + Instrux->Xop.Xop[1] = Code[Offset + 1]; + Instrux->Xop.Xop[2] = Code[Offset + 2]; + + Instrux->Exs.w = Instrux->Xop.w; + Instrux->Exs.r = ~Instrux->Xop.r; + Instrux->Exs.x = ~Instrux->Xop.x; + Instrux->Exs.b = ~Instrux->Xop.b; + Instrux->Exs.l = Instrux->Xop.l; + Instrux->Exs.v = ~Instrux->Xop.v; + Instrux->Exs.m = Instrux->Xop.m; + Instrux->Exs.p = Instrux->Xop.p; + + // if we are in non 64 bit mode, we must make sure that none of the extended registers are being addressed. + if (Instrux->DefCode != ND_CODE_64) + { + // Xop.R and Xop.X must be 1 (inverted). + if ((Instrux->Exs.r | Instrux->Exs.x) == 1) + { + return ND_STATUS_INVALID_ENCODING_IN_MODE; + } + + // Xop.V must be less than 8. + if ((Instrux->Exs.v & 0x8) == 0x8) + { + return ND_STATUS_INVALID_ENCODING_IN_MODE; + } + + // Xop.B is ignored, so we force it to 0. + Instrux->Exs.b = 0; + } + + // Update Instrux length & offset, and make sure we don't exceed 15 bytes. + Instrux->Length += 3; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchVex2 +// +static NDSTATUS +NdFetchVex2( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // One more byte has to follow, the modrm or the second VEX byte. + RET_GT((size_t)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // VEX is available only in 32 & 64 bit mode. + if ((ND_CODE_64 == Instrux->DefCode) || ((Code[Offset + 1] & 0xC0) == 0xC0)) + { + // Make sure we don't have any other prefix. + if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || + Instrux->HasRepRepzXrelease || Instrux->HasRex || Instrux->HasLock) + { + return ND_STATUS_VEX_WITH_PREFIX; + } + + // Fill in VEX2 info. + Instrux->VexMode = ND_VEXM_2B; + Instrux->HasVex = true; + Instrux->EncMode = ND_ENCM_VEX; + Instrux->Vex2.Vex[0] = Code[Offset]; + Instrux->Vex2.Vex[1] = Code[Offset + 1]; + + Instrux->Exs.m = 1; // For VEX2 instructions, always use the second table. + Instrux->Exs.r = ~Instrux->Vex2.r; + Instrux->Exs.v = ~Instrux->Vex2.v; + Instrux->Exs.l = Instrux->Vex2.l; + Instrux->Exs.p = Instrux->Vex2.p; + + // Update Instrux length & offset, and make sure we don't exceed 15 bytes. + Instrux->Length += 2; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchVex3 +// +static NDSTATUS +NdFetchVex3( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // One more byte has to follow, the modrm or the second VEX byte. + RET_GT((size_t)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // VEX is available only in 32 & 64 bit mode. + if ((ND_CODE_64 == Instrux->DefCode) || ((Code[Offset + 1] & 0xC0) == 0xC0)) + { + // VEX found, make sure the third byte is here. + RET_GT((size_t)Offset + 3, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // Make sure we don't have any other prefix. + if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || + Instrux->HasRepRepzXrelease || Instrux->HasRex || Instrux->HasLock) + { + return ND_STATUS_VEX_WITH_PREFIX; + } + + // Fill in XOP info. + Instrux->VexMode = ND_VEXM_3B; + Instrux->HasVex = true; + Instrux->EncMode = ND_ENCM_VEX; + Instrux->Vex3.Vex[0] = Code[Offset]; + Instrux->Vex3.Vex[1] = Code[Offset + 1]; + Instrux->Vex3.Vex[2] = Code[Offset + 2]; + + Instrux->Exs.r = ~Instrux->Vex3.r; + Instrux->Exs.x = ~Instrux->Vex3.x; + Instrux->Exs.b = ~Instrux->Vex3.b; + Instrux->Exs.m = Instrux->Vex3.m; + Instrux->Exs.w = Instrux->Vex3.w; + Instrux->Exs.v = ~Instrux->Vex3.v; + Instrux->Exs.l = Instrux->Vex3.l; + Instrux->Exs.p = Instrux->Vex3.p; + + // Do validations in case of VEX outside 64 bits. + if (Instrux->DefCode != ND_CODE_64) + { + // Vex.R and Vex.X have been tested by the initial if. + + // Vex.vvvv must be less than 8. + if ((Instrux->Exs.v & 0x8) == 0x8) + { + return ND_STATUS_INVALID_ENCODING_IN_MODE; + } + + // Vex.B is ignored, so we force it to 0. + Instrux->Exs.b = 0; + } + + // Update Instrux length & offset, and make sure we don't exceed 15 bytes. + Instrux->Length += 3; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchEvex +// +static NDSTATUS +NdFetchEvex( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // One more byte has to follow, the modrm or the second VEX byte. + RET_GT((size_t)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL); + + if ((ND_CODE_64 != Instrux->DefCode) && ((Code[Offset + 1] & 0xC0) != 0xC0)) + { + // BOUND instruction in non-64 bit mode, not EVEX. + return ND_STATUS_SUCCESS; + } + + // EVEX found, make sure all the bytes are present. At least 4 bytes in total must be present. + RET_GT((size_t)Offset + 4, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // This is EVEX. + Instrux->HasEvex = true; + Instrux->EncMode = ND_ENCM_EVEX; + Instrux->Evex.Evex[0] = Code[Offset + 0]; + Instrux->Evex.Evex[1] = Code[Offset + 1]; + Instrux->Evex.Evex[2] = Code[Offset + 2]; + Instrux->Evex.Evex[3] = Code[Offset + 3]; + + // Legacy prefixes are not accepted with EVEX. + if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || Instrux->HasRepRepzXrelease || Instrux->HasRex) + { + return ND_STATUS_EVEX_WITH_PREFIX; + } + + // Do the opcode independent checks. Opcode dependent checks are done when decoding each + if (Instrux->Evex.zero != 0 || Instrux->Evex.one != 1 || Instrux->Evex.m == 0) + { + return ND_STATUS_INVALID_ENCODING; + } + + // Fill in the generic extension bits + Instrux->Exs.r = ~Instrux->Evex.r; + Instrux->Exs.x = ~Instrux->Evex.x; + Instrux->Exs.b = ~Instrux->Evex.b; + Instrux->Exs.rp = ~Instrux->Evex.rp; + Instrux->Exs.m = Instrux->Evex.m; + Instrux->Exs.w = Instrux->Evex.w; + Instrux->Exs.v = ~Instrux->Evex.v; + Instrux->Exs.vp = ~Instrux->Evex.vp; + Instrux->Exs.p = Instrux->Evex.p; + Instrux->Exs.z = Instrux->Evex.z; + Instrux->Exs.l = Instrux->Evex.l; + Instrux->Exs.bm = Instrux->Evex.bm; + Instrux->Exs.k = Instrux->Evex.a; + + // Do EVEX validations outside 64 bits mode. + if (ND_CODE_64 != Instrux->DefCode) + { + // Evex.R and Evex.X must be 1. If they're not, we have BOUND instruction. This is checkked in the + // first if. Note that they are inverted inside the Evex prefix. + Instrux->Exs.r = 0; + Instrux->Exs.x = 0; + + // Evex.B is ignored, so we force it to 0. + Instrux->Exs.b = 0; + + // Evex.R' is ignored, so we force it to 0. + Instrux->Exs.rp = 0; + + // High bit inside Evex.VVVV is ignored, so we force it to 0. + Instrux->Exs.v &= 0x7; + + // Evex.V' is ignored. + Instrux->Exs.vp = 0; + } + + // Update Instrux length & offset, and make sure we don't exceed 15 bytes. + Instrux->Length += 4; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchPrefixes +// +static NDSTATUS +NdFetchPrefixes( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + NDSTATUS status; + bool morePrefixes; + uint8_t prefix; + + morePrefixes = true; + + while (morePrefixes) + { + morePrefixes = false; + + RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + + prefix = Code[Offset]; + + // Speedup: if the current byte is not a prefix of any kind, leave now. This will be the case most of the times. + if (ND_PREF_CODE_NONE == gPrefixesMap[prefix]) + { + status = ND_STATUS_SUCCESS; + goto done_prefixes; + } + + if (ND_PREF_CODE_STANDARD == gPrefixesMap[prefix]) + { + switch (prefix) + { + case ND_PREFIX_G0_LOCK: + Instrux->HasLock = true; + morePrefixes = true; + break; + case ND_PREFIX_G1_REPE_REPZ: + Instrux->Rep = ND_PREFIX_G1_REPE_REPZ; + Instrux->HasRepRepzXrelease = true; + morePrefixes = true; + break; + case ND_PREFIX_G1_REPNE_REPNZ: + Instrux->Rep = ND_PREFIX_G1_REPNE_REPNZ; + Instrux->HasRepnzXacquireBnd = true; + morePrefixes = true; + break; + case ND_PREFIX_G2_SEG_CS: + case ND_PREFIX_G2_SEG_SS: + case ND_PREFIX_G2_SEG_DS: + case ND_PREFIX_G2_SEG_ES: + case ND_PREFIX_G2_SEG_FS: + case ND_PREFIX_G2_SEG_GS: + if (ND_CODE_64 == Instrux->DefCode) + { + // Do not overwrite FS/GS with ES/CS/DS/SS in 64 bit mode. In 64 bit mode, only FS/GS overrides + // are considered. + if (prefix == ND_PREFIX_G2_SEG_FS || prefix == ND_PREFIX_G2_SEG_GS) + { + Instrux->Seg = prefix; + Instrux->HasSeg = true; + } + } + else + { + Instrux->Seg = prefix; + Instrux->HasSeg = true; + } + if (prefix == ND_PREFIX_G2_BR_TAKEN || prefix == ND_PREFIX_G2_BR_NOT_TAKEN) + { + Instrux->Bhint = prefix; + Instrux->HasSeg = true; + } + morePrefixes = true; + break; + case ND_PREFIX_G3_OPERAND_SIZE: + Instrux->HasOpSize = true; + morePrefixes = true; + break; + case ND_PREFIX_G4_ADDR_SIZE: + Instrux->HasAddrSize = true; + morePrefixes = true; + break; + default: + break; + } + } + + // REX must precede the opcode byte. However, if one or more other prefixes are present, the instruction + // will still decode & execute properly, but REX will be ignored. + if (morePrefixes && Instrux->HasRex) + { + Instrux->HasRex = false; + Instrux->Rex.Rex = 0; + Instrux->Exs.w = 0; + Instrux->Exs.r = 0; + Instrux->Exs.x = 0; + Instrux->Exs.b = 0; + } + + // Check for REX. + if ((ND_CODE_64 == Instrux->DefCode) && (ND_PREF_CODE_REX == gPrefixesMap[prefix])) + { + Instrux->HasRex = true; + Instrux->Rex.Rex = prefix; + Instrux->Exs.w = Instrux->Rex.w; + Instrux->Exs.r = Instrux->Rex.r; + Instrux->Exs.x = Instrux->Rex.x; + Instrux->Exs.b = Instrux->Rex.b; + morePrefixes = true; + } + + // We have found prefixes, update the instruction length and the current offset. + if (morePrefixes) + { + Instrux->Length++, Offset++; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + } + } + + // We must have at least one more free byte after the prefixes, which will be either the opcode, either + // XOP/VEX/EVEX/MVEX prefix. + RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // Try to match a XOP/VEX/EVEX/MVEX prefix. + if (ND_PREF_CODE_EX == gPrefixesMap[Code[Offset]]) + { + // Check for XOP + if (Code[Offset] == ND_PREFIX_XOP) + { + status = NdFetchXop(Instrux, Code, Offset, Size); + if (!ND_SUCCESS(status)) + { + return status; + } + } + else if (Code[Offset] == ND_PREFIX_VEX_2B) + { + status = NdFetchVex2(Instrux, Code, Offset, Size); + if (!ND_SUCCESS(status)) + { + return status; + } + } + else if (Code[Offset] == ND_PREFIX_VEX_3B) + { + status = NdFetchVex3(Instrux, Code, Offset, Size); + if (!ND_SUCCESS(status)) + { + return status; + } + } + else if (Code[Offset] == ND_PREFIX_EVEX) + { + status = NdFetchEvex(Instrux, Code, Offset, Size); + if (!ND_SUCCESS(status)) + { + return status; + } + } + else + { + return ND_STATUS_INVALID_INSTRUX; + } + } + else + { + Instrux->EncMode = ND_ENCM_LEGACY; + } + +done_prefixes: + // The total length of the instruction is the total length of the prefixes right now. + Instrux->PrefLength = Instrux->OpOffset = Instrux->Length; + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchOpcode +// +static NDSTATUS +NdFetchOpcode( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // At least one byte must be available, for the fetched opcode. + RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + + Instrux->OpCodeBytes[Instrux->OpLength++] = Code[Offset]; + + Instrux->Length++; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchModrm +// +static NDSTATUS +NdFetchModrm( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // At least one byte must be available, for the modrm byte. + RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // If we get called, we assume we have ModRM. + Instrux->HasModRm = true; + + // Fetch the ModRM byte & update the offset and the instruction length. + Instrux->ModRm.ModRm = Code[Offset]; + Instrux->ModRmOffset = Offset; + + Instrux->Length++, Offset++; + + // Make sure we don't exceed the maximum instruction length. + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchModrmAndSib +// +static NDSTATUS +NdFetchModrmAndSib( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +{ + // At least one byte must be available, for the modrm byte. + RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // If we get called, we assume we have ModRM. + Instrux->HasModRm = true; + + // Fetch the ModRM byte & update the offset and the instruction length. + Instrux->ModRm.ModRm = Code[Offset]; + Instrux->ModRmOffset = Offset; + + Instrux->Length++, Offset++; + + // Make sure we don't exceed the maximum instruction length. + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + // If needed, fetch the SIB. + if ((Instrux->ModRm.rm == REG_RSP) && (Instrux->ModRm.mod != 3) && (Instrux->AddrMode != ND_ADDR_16)) + { + // At least one more byte must be available, for the sib. + RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // SIB present. + Instrux->HasSib = true; + + Instrux->Sib.Sib = Code[Offset]; + Instrux->Length++; + + // Make sure we don't exceed the maximum instruction length. + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchDisplacement +// +static NDSTATUS +NdFetchDisplacement( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size + ) +// +// Will decode the displacement from the instruction. Will fill in extracted information in Instrux, +// and will update the instruction length. +// +{ + uint8_t displSize; + + displSize = 0; + + if (ND_ADDR_16 == Instrux->AddrMode) + { + displSize = gDispsizemap16[Instrux->ModRm.mod][Instrux->ModRm.rm]; + } + else + { + displSize = gDispsizemap[Instrux->ModRm.mod][Instrux->HasSib ? Instrux->Sib.base : Instrux->ModRm.rm]; + } + + if (0 != displSize) + { + static const uint32_t signMask[4] = { 0x80, 0x8000, 0, 0x80000000 }; + + // Make sure enough buffer space is available. + RET_GT((size_t)Offset + displSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // If we get here, we have displacement. + Instrux->HasDisp = true; + + Instrux->Displacement = (uint32_t)NdFetchData(Code + Offset, displSize); + Instrux->SignDisp = (Instrux->Displacement & signMask[displSize - 1]) ? true : false; + + // Fill in displacement info. + Instrux->DispLength = displSize; + Instrux->DispOffset = Offset; + Instrux->Length += displSize; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchAddress +// +static NDSTATUS +NdFetchAddress( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint8_t AddressSize + ) +{ + //. Make sure the + RET_GT((size_t)Offset + AddressSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + Instrux->HasAddr = true; + Instrux->AddrLength = AddressSize; + Instrux->AddrOffset = Offset; + + Instrux->Address.Ip = (uint32_t)NdFetchData(Code + Offset, Instrux->AddrLength - 2); + Instrux->Address.Cs = (uint16_t)NdFetchData(Code + Offset + Instrux->AddrLength - 2, 2); + + Instrux->Length += Instrux->AddrLength; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchImmediate +// +static NDSTATUS +NdFetchImmediate( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint8_t ImmediateSize + ) +{ + uint64_t imm; + + RET_GT((size_t)Offset + ImmediateSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + imm = NdFetchData(Code + Offset, ImmediateSize); + + if (Instrux->HasImm2) + { + Instrux->HasImm3 = true; + Instrux->Imm3Length = ImmediateSize; + Instrux->Imm3Offset = Offset; + Instrux->Immediate3 = (uint8_t)imm; + } + else if (Instrux->HasImm1) + { + Instrux->HasImm2 = true; + Instrux->Imm2Length = ImmediateSize; + Instrux->Imm2Offset = Offset; + Instrux->Immediate2 = (uint8_t)imm; + } + else + { + Instrux->HasImm1 = true; + Instrux->Imm1Length = ImmediateSize; + Instrux->Imm1Offset = Offset; + Instrux->Immediate1 = imm; + } + + Instrux->Length += ImmediateSize; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchRelativeOffset +// +static NDSTATUS +NdFetchRelativeOffset( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint8_t RelOffsetSize + ) +{ + // Make sure we don't outrun the buffer. + RET_GT((size_t)Offset + RelOffsetSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + Instrux->HasRelOffs = true; + Instrux->RelOffsLength = RelOffsetSize; + Instrux->RelOffsOffset = Offset; + + Instrux->RelativeOffset = (uint32_t)NdFetchData(Code + Offset, RelOffsetSize); + + Instrux->Length += RelOffsetSize; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchMoffset +// +static NDSTATUS +NdFetchMoffset( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint8_t MoffsetSize + ) +{ + RET_GT((size_t)Offset + MoffsetSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + Instrux->HasMoffset = true; + Instrux->MoffsetLength = MoffsetSize; + Instrux->MoffsetOffset = Offset; + + Instrux->Moffset = NdFetchData(Code + Offset, MoffsetSize); + + Instrux->Length += MoffsetSize; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdFetchSseImmediate +// +static NDSTATUS +NdFetchSseImmediate( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint8_t SseImmSize + ) +{ + RET_GT((size_t)Offset + SseImmSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + Instrux->HasSseImm = true; + Instrux->SseImmOffset = Offset; + Instrux->SseImmediate = *(Code + Offset); + + Instrux->Length += SseImmSize; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdGetSegOverride +// +static uint8_t +NdGetSegOverride( + INSTRUX *Instrux, + uint8_t DefaultSeg + ) +{ + // In 64 bit mode, the segment override is ignored, except for FS and GS. + if ((Instrux->DefCode == ND_CODE_64) && + (Instrux->Seg != ND_PREFIX_G2_SEG_FS) && + (Instrux->Seg != ND_PREFIX_G2_SEG_GS)) + { + return DefaultSeg; + } + + switch (Instrux->Seg) + { + case ND_PREFIX_G2_SEG_CS: + return REG_CS; + case ND_PREFIX_G2_SEG_DS: + return REG_DS; + case ND_PREFIX_G2_SEG_ES: + return REG_ES; + case ND_PREFIX_G2_SEG_SS: + return REG_SS; + case ND_PREFIX_G2_SEG_FS: + return REG_FS; + case ND_PREFIX_G2_SEG_GS: + return REG_GS; + default: + return DefaultSeg; + } +} + + +// +// NdGetCompDispSize +// +static uint8_t +NdGetCompDispSize( + const INSTRUX *Instrux, + uint32_t MemSize + ) +{ + static const uint8_t fvszLut[2][2][4] = + { + { { 16, 32, 64, 0 }, { 4, 4, 4, 0 }, }, + { { 16, 32, 64, 0 }, { 8, 8, 8, 0 }, }, + }; + + static const uint8_t hvszLut[2][4] = { { 8, 16, 32, 0 }, { 4, 4, 4, 0 }, }; + static const uint8_t dupszLut[4] = { 8, 32, 64, 0 }; + static const uint8_t fvmszLut[4] = { 16, 32, 64, 0 }; + static const uint8_t hvmszLut[4] = { 8, 16, 32, 0 }; + static const uint8_t qvmszLut[4] = { 4, 8, 16, 0 }; + static const uint8_t ovmszLut[4] = { 2, 4, 8, 0 }; + + switch (Instrux->TupleType) + { + case ND_TUPLE_FV: + return fvszLut[Instrux->Exs.w][Instrux->Exs.bm][Instrux->Exs.l]; + case ND_TUPLE_HV: + return hvszLut[Instrux->Exs.bm][Instrux->Exs.l]; + case ND_TUPLE_DUP: + return dupszLut[Instrux->Exs.l]; + case ND_TUPLE_FVM: + return fvmszLut[Instrux->Exs.l]; + case ND_TUPLE_HVM: + return hvmszLut[Instrux->Exs.l]; + case ND_TUPLE_QVM: + return qvmszLut[Instrux->Exs.l]; + case ND_TUPLE_OVM: + return ovmszLut[Instrux->Exs.l]; + case ND_TUPLE_M128: + return 16; + case ND_TUPLE_T1S8: + return 1; + case ND_TUPLE_T1S16: + return 2; + case ND_TUPLE_T1S: + return Instrux->Exs.w ? 8 : 4; + case ND_TUPLE_T1F: + return (uint8_t)MemSize; + case ND_TUPLE_T2: + return Instrux->Exs.w ? 16 : 8; + case ND_TUPLE_T4: + return Instrux->Exs.w ? 32 : 16; + case ND_TUPLE_T8: + return 32; + case ND_TUPLE_T1_4X: + return 16; + default: + // Default - we assume byte granularity for memory accesses, therefore, no scaling will be done. + return 1; + } +} + + +// +// NdParseOperand +// +static NDSTATUS +NdParseOperand( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint32_t Index, + uint64_t Specifier + ) +{ + NDSTATUS status; + PND_OPERAND operand; + uint8_t opt, ops, opf, opd, opb; + ND_REG_SIZE vsibRegSize; + uint8_t vsibIndexSize, vsibIndexCount; + ND_OPERAND_SIZE size, bcstSize; + bool width; + + // pre-init + status = ND_STATUS_SUCCESS; + vsibRegSize = 0; + vsibIndexSize = vsibIndexCount = 0; + size = bcstSize = 0; + + // Get actual width. + width = Instrux->Exs.w && !(Instrux->Attributes & ND_FLAG_WIG); + + // Get operand components. + opt = ND_OP_TYPE(Specifier); + ops = ND_OP_SIZE(Specifier); + opf = ND_OP_FLAGS(Specifier); + opd = ND_OP_DECORATORS(Specifier); + opb = ND_OP_BLOCK(Specifier); + + // Get a pointer to our op. + operand = &Instrux->Operands[Index]; + + // Fill in the flags. + operand->Flags.Flags = opf & 0xF; + + // Store operand access modes. + operand->Access.Access = opf >> 4; + + + // + // Fill in operand size. + // + switch (ops) + { + case ND_OPS_asz: + // Size given by the address mode. + size = 2 << Instrux->AddrMode; + break; + + case ND_OPS_ssz: + // Size given by the stack mode. + size = 2 << Instrux->DefStack; + break; + + case ND_OPS_0: + // No memory access. 0 operand size. + size = 0; + break; + + case ND_OPS_b: + // Byte, regardless of operand-size attribute. + size = ND_SIZE_8BIT; + break; + + case ND_OPS_w: + // Word, regardless of operand-size attribute. + size = ND_SIZE_16BIT; + break; + + case ND_OPS_d: + // Dword, regardless of operand-size attribute. + size = ND_SIZE_32BIT; + break; + + case ND_OPS_q: + // Qword, regardless of operand-size attribute. + size = ND_SIZE_64BIT; + break; + + case ND_OPS_dq: + // Double-Qword, regardless of operand-size attribute. + size = ND_SIZE_128BIT; + break; + + case ND_OPS_qq: + // Quad-Quadword (256-bits), regardless of operand-size attribute. + size = ND_SIZE_256BIT; + break; + + case ND_OPS_oq: + // Octo-Quadword (512-bits), regardless of operand-size attribute. + size = ND_SIZE_512BIT; + break; + + case ND_OPS_fa: + // 80 bits packed BCD. + size = ND_SIZE_80BIT; + break; + + case ND_OPS_fw: + // 16 bits real number. + size = ND_SIZE_16BIT; + break; + + case ND_OPS_fd: + // 32 bit real number. + size = ND_SIZE_32BIT; + break; + + case ND_OPS_fq: + // 64 bit real number. + size = ND_SIZE_64BIT; + break; + + case ND_OPS_ft: + // 80 bit real number. + size = ND_SIZE_80BIT; + break; + + case ND_OPS_fe: + // 14 bytes or 28 bytes FPU environment. + size = (Instrux->EfOpMode == ND_OPSZ_16) ? ND_SIZE_112BIT : ND_SIZE_224BIT; + break; + + case ND_OPS_fs: + // 94 bytes or 108 bytes FPU state. + size = (Instrux->EfOpMode == ND_OPSZ_16) ? ND_SIZE_752BIT : ND_SIZE_864BIT; + break; + + case ND_OPS_rx: + // 512 bytes extended state. + size = ND_SIZE_4096BIT; + break; + + case ND_OPS_cl: + // The size of one cache line. + size = ND_SIZE_CACHE_LINE; + break; + + case ND_OPS_v: + // Word, doubleword or quadword (in 64-bit mode), depending on operand-size attribute. + { + static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + + size = szLut[Instrux->EfOpMode]; + } + break; + + case ND_OPS_y: + // Doubleword or quadword (in 64-bit mode), depending on operand-size attribute. + { + static const uint8_t szLut[3] = { ND_SIZE_32BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + + size = szLut[Instrux->EfOpMode]; + } + break; + + case ND_OPS_yf: + // Always uint64_t in 64 bit mode and uint32_t in 16/32 bit mode. + { + static const uint8_t szLut[3] = { ND_SIZE_32BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + + size = szLut[Instrux->DefCode]; + } + break; + + case ND_OPS_z: + // Word for 16-bit operand-size or double word for 32 or 64-bit operand-size. + { + static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_32BIT }; + + size = szLut[Instrux->EfOpMode]; + } + break; + + case ND_OPS_a: + // Two one-word operands in memory or two double-word operands in memory, + // depending on operand-size attribute (used only by the BOUND instruction). + { + static const uint8_t szLut[3] = { ND_SIZE_16BIT * 2, ND_SIZE_32BIT * 2, 0 }; + + if (Instrux->DefCode > ND_CODE_32) + { + return ND_STATUS_INVALID_INSTRUX; + } + + size = szLut[Instrux->EfOpMode]; + } + break; + + case ND_OPS_c: + // Byte or word, depending on operand-size attribute. + switch (Instrux->DefCode) + { + case ND_CODE_16: + size = Instrux->HasOpSize ? ND_SIZE_16BIT : ND_SIZE_8BIT; + break; + case ND_CODE_32: + size = Instrux->HasOpSize ? ND_SIZE_16BIT : ND_SIZE_32BIT; + break; + case ND_CODE_64: + size = ND_SIZE_64BIT; + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + break; + + case ND_OPS_p: + // 32-bit, 48-bit, or 80-bit pointer, depending on operand-size attribute. + { + static const uint8_t szLut[3] = { ND_SIZE_32BIT, ND_SIZE_48BIT, ND_SIZE_80BIT }; + + size = szLut[Instrux->EfOpMode]; + } + break; + + case ND_OPS_s: + // 6-byte or 10-byte pseudo-descriptor. + { + static const uint8_t szLut[3] = { ND_SIZE_48BIT, ND_SIZE_48BIT, ND_SIZE_80BIT }; + + size = szLut[Instrux->DefCode]; + } + break; + + case ND_OPS_l: + // 64 bit in 16 or 32 bit mode, 128 bit in long mode. Used by BNDMOV instruction. + { + static const uint8_t szLut[3] = { ND_SIZE_64BIT, ND_SIZE_64BIT, ND_SIZE_128BIT }; + + size = szLut[Instrux->DefCode]; + } + break; + + case ND_OPS_x: + // dq, qq or oq based on the operand-size attribute. + { + static const uint8_t szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT }; + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_n: + // 128, 256 or 512 bit, depending on vector length. + { + static const uint8_t szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT }; + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_u: + // 256 or 512 bit, depending on vector length. + { + static const uint8_t szLut[3] = { 0, ND_SIZE_256BIT, ND_SIZE_512BIT }; + + if (ND_VECM_128 == Instrux->EfVecMode) + { + return ND_STATUS_INVALID_INSTRUX; + } + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_e: + // eighth = word or dword or qword + { + static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_f: + // fourth = dword or qword or oword + { + static const uint8_t szLut[3] = { ND_SIZE_32BIT, ND_SIZE_64BIT, ND_SIZE_128BIT }; + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_h: + // half = qword or oword or yword + { + static const uint8_t szLut[3] = { ND_SIZE_64BIT, ND_SIZE_128BIT, ND_SIZE_256BIT }; + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_pd: + case ND_OPS_ps: + // packed double or packed single precision values. + { + static const uint8_t szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT }; + + size = szLut[Instrux->EfVecMode]; + } + break; + + case ND_OPS_ss: + // Scalar single. + size = ND_SIZE_32BIT; + break; + + case ND_OPS_sd: + // Scalar double. + size = ND_SIZE_64BIT; + break; + + case ND_OPS_mib: + // MIB addressing, used by MPX instructions. + size = 0; + break; + + case ND_OPS_vm32x: + case ND_OPS_vm32y: + case ND_OPS_vm32z: + // 32 bit indexes from XMM, YMM or ZMM register. + vsibIndexSize = ND_SIZE_32BIT; + vsibIndexCount = (Instrux->Exs.l == 0) ? 4 : ((Instrux->Exs.l == 1) ? 8 : 16); + vsibRegSize = (ops == ND_OPS_vm32x) ? ND_SIZE_128BIT : + (ops == ND_OPS_vm32y) ? ND_SIZE_256BIT : + ND_SIZE_512BIT; + size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT); + break; + + case ND_OPS_vm32h: + // 32 bit indexes from XMM or YMM. + vsibIndexSize = ND_SIZE_32BIT; + vsibIndexCount = (Instrux->Exs.l == 0) ? 2 : ((Instrux->Exs.l == 1) ? 4 : 8); + vsibRegSize = (Instrux->Exs.l == 0) ? ND_SIZE_128BIT : + (Instrux->Exs.l == 1) ? ND_SIZE_128BIT : + ND_SIZE_256BIT; + size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT); + break; + + case ND_OPS_vm32n: + // 32 bit indexes from XMM, YMM or ZMM register. + vsibIndexSize = ND_SIZE_32BIT; + vsibIndexCount = (Instrux->Exs.l == 0) ? 4 : ((Instrux->Exs.l == 1) ? 8 : 16); + vsibRegSize = (Instrux->Exs.l == 0) ? ND_SIZE_128BIT : + (Instrux->Exs.l == 1) ? ND_SIZE_256BIT : + ND_SIZE_512BIT; + size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT); + break; + + case ND_OPS_vm64x: + case ND_OPS_vm64y: + case ND_OPS_vm64z: + // 64 bit indexes from XMM, YMM or ZMM register. + vsibIndexSize = ND_SIZE_64BIT; + vsibIndexCount = (Instrux->Exs.l == 0) ? 2 : ((Instrux->Exs.l == 1) ? 4 : 8); + vsibRegSize = (ops == ND_OPS_vm64x) ? ND_SIZE_128BIT : + (ops == ND_OPS_vm64y) ? ND_SIZE_256BIT : + ND_SIZE_512BIT; + size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT); + break; + + case ND_OPS_vm64h: + // 64 bit indexes from XMM or YMM. + vsibIndexSize = ND_SIZE_64BIT; + vsibIndexCount = (Instrux->Exs.l == 0) ? 1 : ((Instrux->Exs.l == 1) ? 2 : 4); + vsibRegSize = (Instrux->Exs.l == 0) ? ND_SIZE_128BIT : + (Instrux->Exs.l == 1) ? ND_SIZE_128BIT : + ND_SIZE_256BIT; + size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT); + break; + + case ND_OPS_vm64n: + // 64 bit indexes from XMM, YMM or ZMM register. + vsibIndexSize = ND_SIZE_64BIT; + vsibIndexCount = (Instrux->Exs.l == 0) ? 2 : ((Instrux->Exs.l == 1) ? 4 : 8); + vsibRegSize = (Instrux->Exs.l == 0) ? ND_SIZE_128BIT : + (Instrux->Exs.l == 1) ? ND_SIZE_256BIT : + ND_SIZE_512BIT; + size = vsibIndexCount * (width ? ND_SIZE_64BIT : ND_SIZE_32BIT); + break; + + case ND_OPS_v2: + case ND_OPS_v3: + case ND_OPS_v4: + case ND_OPS_v8: + // Multiple words accessed. + { + static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + uint8_t scale = 1; + + scale = (ops == ND_OPS_v2) ? 2 : ((ops == ND_OPS_v3) ? 3 : ((ops == ND_OPS_v4) ? 4 : 8)); + + size = scale * szLut[Instrux->EfOpMode]; + } + break; + + case ND_OPS_t: + // Tile register. The actual size depends on how the TILECFG register has been programmed, but it can be + // up to 1K in size. + size = ND_SIZE_1KB; + break; + + case ND_OPS_unknown: + size = ND_SIZE_UNKNOWN; + break; + + default: + return ND_STATUS_INVALID_INSTRUX; + } + + // Store operand info. + operand->Size = operand->RawSize = bcstSize = size; + + // + // Fill in the operand type. + // + switch (opt) + { + case ND_OPT_CONST_1: + // operand is an implicit constant (used by shift/rotate instruction). + operand->Type = ND_OP_CONST; + operand->Info.Constant.Const = 1; + break; + + case ND_OPT_RIP: + // The operand is the instruction pointer. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_RIP; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = 0; + Instrux->RipAccess |= operand->Access.Access; + break; + + case ND_OPT_GPR_rAX: + // Operator is the accumulator. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RAX; + break; + + case ND_OPT_GPR_AH: + // Operator is the accumulator. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = ND_SIZE_8BIT; + operand->Info.Register.Reg = REG_AH; + operand->Info.Register.IsHigh8 = true; + break; + + case ND_OPT_GPR_rCX: + // Operator is the counter register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RCX; + break; + + case ND_OPT_GPR_rDX: + // Operator is rDX. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RDX; + break; + + case ND_OPT_GPR_rBX: + // Operator is BX. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RBX; + break; + + case ND_OPT_GPR_rBP: + // Operand is rBP. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RBP; + break; + + case ND_OPT_GPR_rSP: + // Operand is rSP. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RSP; + break; + + case ND_OPT_GPR_rSI: + // Operand is rSI. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RSI; + break; + + case ND_OPT_GPR_rDI: + // Operand is rDI. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_RDI; + break; + + case ND_OPT_GPR_rR11: + // Operand is R11. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_R11; + break; + + case ND_OPT_SEG_CS: + // Operand is the CS register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_CS; + break; + + case ND_OPT_SEG_SS: + // Operand is the SS register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_SS; + break; + + case ND_OPT_SEG_DS: + // Operand is the DS register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_DS; + break; + + case ND_OPT_SEG_ES: + // Operand is the ES register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_ES; + break; + + case ND_OPT_SEG_FS: + // Operand is the FS register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_FS; + break; + + case ND_OPT_SEG_GS: + // Operand is the GS register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_GS; + break; + + case ND_OPT_FPU_ST0: + // Operand is the ST(0) register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_FPU; + operand->Info.Register.Size = ND_SIZE_80BIT; + operand->Info.Register.Reg = 0; + break; + + case ND_OPT_FPU_STX: + // Operand is the ST(i) register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_FPU; + operand->Info.Register.Size = ND_SIZE_80BIT; + operand->Info.Register.Reg = Instrux->ModRm.rm; + break; + + case ND_OPT_SSE_XMM0: + // Operand is the XMM0 register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = ND_SIZE_128BIT; + operand->Info.Register.Reg = 0; + break; + + // Special operands. These are always implicit, and can't be encoded inside the instruction. + case ND_OPT_CR_0: + // The operand is implicit and is control register 0. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_CR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_CR0; + break; + + case ND_OPT_SYS_GDTR: + // The operand is implicit and is the global descriptor table register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_GDTR; + break; + + case ND_OPT_SYS_IDTR: + // The operand is implicit and is the interrupt descriptor table register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_IDTR; + break; + + case ND_OPT_SYS_LDTR: + // The operand is implicit and is the local descriptor table register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_LDTR; + break; + + case ND_OPT_SYS_TR: + // The operand is implicit and is the task register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = REG_TR; + break; + + case ND_OPT_X87_CONTROL: + // The operand is implicit and is the x87 control word. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = ND_SIZE_16BIT; + operand->Info.Register.Reg = REG_X87_CONTROL; + break; + + case ND_OPT_X87_TAG: + // The operand is implicit and is the x87 tag word. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = ND_SIZE_16BIT; + operand->Info.Register.Reg = REG_X87_TAG; + break; + + case ND_OPT_X87_STATUS: + // The operand is implicit and is the x87 status word. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SYS; + operand->Info.Register.Size = ND_SIZE_16BIT; + operand->Info.Register.Reg = REG_X87_STATUS; + break; + + case ND_OPT_MXCSR: + // The operand is implicit and is the MXCSR. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MXCSR; + operand->Info.Register.Size = ND_SIZE_32BIT; + operand->Info.Register.Reg = 0; + break; + + case ND_OPT_PKRU: + // The operand is the PKRU register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_PKRU; + operand->Info.Register.Size = ND_SIZE_32BIT; + operand->Info.Register.Reg = 0; + break; + + case ND_OPT_SSP: + // The operand is the SSP register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSP; + operand->Info.Register.Size = (Instrux->OpMode == ND_OPSZ_64) ? ND_SIZE_64BIT : ND_SIZE_32BIT; + operand->Info.Register.Reg = 0; + break; + + case ND_OPT_MSR: + // The operand is implicit and is a MSR (usually selected by the ECX register). + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = 0xFFFFFFFF; + break; + + case ND_OPT_MSR_TSC: + // The operand is implicit and is the IA32_TSC. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_TSC; + break; + + case ND_OPT_MSR_TSCAUX: + // The operand is implicit and is the IA32_TSCAUX. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_TSC_AUX; + break; + + case ND_OPT_MSR_SCS: + // The operand is implicit and is the IA32_SYSENTER_CS. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_SYSENTER_CS; + break; + + case ND_OPT_MSR_SESP: + // The operand is implicit and is the IA32_SYSENTER_ESP. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_SYSENTER_ESP; + break; + + case ND_OPT_MSR_SEIP: + // The operand is implicit and is the IA32_SYSENTER_EIP. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_SYSENTER_EIP; + break; + + case ND_OPT_MSR_STAR: + // The operand is implicit and is the IA32_STAR. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_STAR; + break; + + case ND_OPT_MSR_LSTAR: + // The operand is implicit and is the IA32_STAR. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_LSTAR; + break; + + case ND_OPT_MSR_FMASK: + // The operand is implicit and is the IA32_FMASK. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_FMASK; + break; + + case ND_OPT_MSR_FSBASE: + // The operand is implicit and is the IA32_FS_BASE MSR. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_FS_BASE; + break; + + case ND_OPT_MSR_GSBASE: + // The operand is implicit and is the IA32_GS_BASE MSR. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_GS_BASE; + break; + + case ND_OPT_MSR_KGSBASE: + // The operand is implicit and is the IA32_KERNEL_GS_BASE MSR. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = REG_IA32_GS_BASE; + break; + + case ND_OPT_XCR: + // The operand is implicit and is an extended control register (usually selected by ECX register). + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_XCR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = 0xFF; + break; + + case ND_OPT_XCR_0: + // The operand is implicit and is XCR0. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_XCR; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = 0; + break; + + case ND_OPT_REG_BANK: + // Multiple registers are accessed. + if ((Instrux->Instruction == ND_INS_PUSHA) || (Instrux->Instruction == ND_INS_POPA)) + { + operand->Type = ND_OP_REG; + operand->Size = operand->RawSize = Instrux->WordLength; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = Instrux->WordLength; + operand->Info.Register.Reg = REG_EAX; + operand->Info.Register.Count = 8; + operand->Info.Register.IsBlock = true; + } + else + { + operand->Type = ND_OP_BANK; + } + break; + + case ND_OPT_A: + // Fetch the address. NOTE: The size can't be larger than 8 bytes. + status = NdFetchAddress(Instrux, Code, Offset, Size, (uint8_t)size); + if (!ND_SUCCESS(status)) + { + return status; + } + + // Fill in operand info. + operand->Type = ND_OP_ADDR; + operand->Info.Address.BaseSeg = Instrux->Address.Cs; + operand->Info.Address.Offset = Instrux->Address.Ip; + + Offset = Instrux->Length; + break; + + case ND_OPT_B: + // General purpose register encoded in VEX.vvvv field. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + + // EVEX.V' must be 0, if a GPR is encoded using EVEX encoding. + if (Instrux->Exs.vp != 0) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + operand->Info.Register.Reg = (uint8_t)Instrux->Exs.v; + break; + + case ND_OPT_C: + // Control register, encoded in modrm.reg. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_CR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + // On some AMD processors, the presence of the LOCK prefix before MOV to/from control registers allows accessing + // higher 8 control registers. + if ((ND_CODE_64 != Instrux->DefCode) && (Instrux->HasLock)) + { + operand->Info.Register.Reg |= 0x8; + } + + // Only CR0, CR2, CR3, CR4 & CR8 valid. + if (operand->Info.Register.Reg != 0 && + operand->Info.Register.Reg != 2 && + operand->Info.Register.Reg != 3 && + operand->Info.Register.Reg != 4 && + operand->Info.Register.Reg != 8) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + break; + + case ND_OPT_D: + // Debug register, encoded in modrm.reg. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_DR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + + // Only DR0-DR7 valid. + if (operand->Info.Register.Reg >= 8) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + break; + + case ND_OPT_T: + // Test register, encoded in modrm.reg. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_TR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + + // Only TR0-TR7 valid, only on 486. + if (operand->Info.Register.Reg >= 8) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + break; + + case ND_OPT_S: + // Segment register, encoded in modrm.reg. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SEG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = Instrux->ModRm.reg; + + // Only ES, CS, SS, DS, FS, GS valid. + if (operand->Info.Register.Reg >= 6) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + // If CS is loaded - #UD. + if ((operand->Info.Register.Reg == REG_CS) && operand->Access.Write) + { + return ND_STATUS_CS_LOAD; + } + + break; + + case ND_OPT_E: + // General purpose register or memory, encoded in modrm.rm. + if (Instrux->ModRm.mod == 3) + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && + (operand->Info.Register.Reg >= 4) && + (ND_ENCM_LEGACY == Instrux->EncMode) && + !Instrux->HasRex; + } + else + { + goto memory; + } + break; + + case ND_OPT_F: + // The flags register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_FLG; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = 0; + Instrux->FlagsAccess.RegAccess |= operand->Access.Access; + break; + + case ND_OPT_K: + // The operand is the stack. + { + static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.IsStack = true; + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = REG_RSP; + operand->Info.Memory.BaseSize = szLut[Instrux->DefStack]; + operand->Info.Memory.HasSeg = true; + operand->Info.Memory.Seg = REG_SS; + Instrux->StackWords = (uint8_t)(operand->Size / Instrux->WordLength); + Instrux->StackAccess |= operand->Access.Access; + } + break; + + case ND_OPT_G: + // General purpose register encoded in modrm.reg. + if (Instrux->Exs.rp == 1) + { + return ND_STATUS_INVALID_ENCODING; + } + + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + + // EVEX.R' must be 0 if a GPR is encoded. + if (Instrux->Exs.rp != 0) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && + (operand->Info.Register.Reg >= 4) && + (ND_ENCM_LEGACY == Instrux->EncMode) && + !Instrux->HasRex; + break; + + case ND_OPT_R: + // General purpose register encoded in modrm.rm. + if ((Instrux->ModRm.mod == 3) || (0 != (Instrux->Attributes & ND_FLAG_MFR))) + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && + (operand->Info.Register.Reg >= 4) && + (ND_ENCM_LEGACY == Instrux->EncMode) && + !Instrux->HasRex; + } + else + { + return ND_STATUS_INVALID_ENCODING; + } + break; + + case ND_OPT_I: + // Immediate, encoded in instructon bytes. + { + uint64_t imm; + + // Fetch the immediate. NOTE: The size won't exceed 8 bytes. + status = NdFetchImmediate(Instrux, Code, Offset, Size, (uint8_t)size); + if (!ND_SUCCESS(status)) + { + return status; + } + + // Get the last immediate. + if (Instrux->HasImm3) + { + imm = Instrux->Immediate3; + } + else if (Instrux->HasImm2) + { + imm = Instrux->Immediate2; + } + else + { + imm = Instrux->Immediate1; + } + + operand->Type = ND_OP_IMM; + + if (operand->Flags.SignExtendedDws) + { + static const uint8_t wszLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + + // Get the default word size: the immediate is sign extended to the default word size. + operand->Size = wszLut[Instrux->EfOpMode]; + + operand->Info.Immediate.Imm = ND_SIGN_EX(size, imm); + } + else if (operand->Flags.SignExtendedOp1) + { + // The immediate is sign extended to the size of the first operand. + operand->Size = Instrux->Operands[0].Size; + + operand->Info.Immediate.Imm = ND_SIGN_EX(size, imm); + } + else + { + operand->Info.Immediate.Imm = imm; + } + + Offset = Instrux->Length; + } + break; + + case ND_OPT_J: + // Fetch the relative offset. NOTE: The size of the relative can't exceed 4 bytes. + status = NdFetchRelativeOffset(Instrux, Code, Offset, Size, (uint8_t)size); + if (!ND_SUCCESS(status)) + { + return status; + } + + // The instruction is RIP relative. + Instrux->IsRipRelative = true; + + operand->Type = ND_OP_OFFS; + // The relative offset is forced to the default word length. Care must be taken with the 32 bit + // branches that have 0x66 prefix (in 32 bit mode)! + operand->Size = Instrux->WordLength; + operand->Info.RelativeOffset.Rel = ND_SIGN_EX(size, Instrux->RelativeOffset); + + Offset = Instrux->Length; + + break; + + case ND_OPT_N: + // The R/M field of the ModR/M byte selects a packed-quadword, MMX technology register. + if (Instrux->ModRm.mod != 3) + { + return ND_STATUS_INVALID_ENCODING; + } + + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MMX; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = Instrux->ModRm.rm; + break; + + case ND_OPT_P: + // The reg field of the ModR/M byte selects a packed quadword MMX technology register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MMX; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = Instrux->ModRm.reg; + break; + + case ND_OPT_Q: + // A ModR/M byte follows the opcode and specifies the operand. The operand is either an MMX technology + // register or a memory address. If it is a memory address, the address is computed from a segment register + // and any of the following values: a base register, an index register, a scaling factor, and a displacement + if (Instrux->ModRm.mod == 3) + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MMX; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = Instrux->ModRm.rm; + } + else + { + goto memory; + } + break; + + case ND_OPT_O: + // Absolute address, encoded in instruction bytes. + { + // NOTE: The moffset len can't exceed 8 bytes. + status = NdFetchMoffset(Instrux, Code, Offset, Size, 2 << Instrux->AddrMode); + if (!ND_SUCCESS(status)) + { + return status; + } + + // operand info. + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasDisp = true; + operand->Info.Memory.IsDirect = true; + operand->Info.Memory.DispSize = Instrux->MoffsetLength; + operand->Info.Memory.Disp = Instrux->Moffset; + operand->Info.Memory.HasSeg = true; + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS); + + Offset = Instrux->Length; + } + break; + + case ND_OPT_M: + // Modrm based memory addressing. + if (Instrux->ModRm.mod == 3) + { + return ND_STATUS_INVALID_ENCODING; + } + +memory: + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasSeg = true; + + if (ND_ADDR_16 == Instrux->AddrMode) + { + // 16 bit addressing, make sure the instruction supports this. + if (!!(Instrux->Attributes & ND_FLAG_NOA16)) + { + return ND_STATUS_16_BIT_ADDRESSING_NOT_SUPPORTED; + } + + switch (Instrux->ModRm.rm) + { + case 0: + // [bx + si] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.HasIndex = true; + operand->Info.Memory.Scale = 1; + operand->Info.Memory.Base = REG_BX; + operand->Info.Memory.Index = REG_SI; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.IndexSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_DS; + break; + case 1: + // [bx + di] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.HasIndex = true; + operand->Info.Memory.Scale = 1; + operand->Info.Memory.Base = REG_BX; + operand->Info.Memory.Index = REG_DI; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.IndexSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_DS; + break; + case 2: + // [bp + si] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.HasIndex = true; + operand->Info.Memory.Scale = 1; + operand->Info.Memory.Base = REG_BP; + operand->Info.Memory.Index = REG_SI; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.IndexSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_SS; + break; + case 3: + // [bp + di] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.HasIndex = true; + operand->Info.Memory.Scale = 1; + operand->Info.Memory.Base = REG_BP; + operand->Info.Memory.Index = REG_DI; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.IndexSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_SS; + break; + case 4: + // [si] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = REG_SI; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_DS; + break; + case 5: + // [di] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = REG_DI; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_DS; + break; + case 6: + // [bp] + if (Instrux->ModRm.mod != 0) + { + // If mod is not zero, than we have "[bp + displacement]". + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = REG_BP; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_SS; + } + else + { + // If mod is zero, than we only have a displacement that is used to directly address mem. + operand->Info.Memory.Seg = REG_DS; + } + break; + case 7: + // [bx] + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = REG_BX; + operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + operand->Info.Memory.Seg = REG_DS; + break; + } + + // Store the displacement. + operand->Info.Memory.HasDisp = !!Instrux->HasDisp; + operand->Info.Memory.DispSize = Instrux->DispLength; + operand->Info.Memory.Disp = ND_SIGN_EX(Instrux->DispLength, Instrux->Displacement); + } + else + { + uint8_t defsize = (Instrux->AddrMode == ND_ADDR_32 ? ND_SIZE_32BIT : ND_SIZE_64BIT); + + // Implicit segment is DS. + operand->Info.Memory.Seg = REG_DS; + + if (Instrux->HasSib) + { + // Check for base. + if ((Instrux->ModRm.mod == 0) && (Instrux->Sib.base == REG_RBP)) + { + // Mod is mem without displacement and base reg is RBP -> no base reg used. + // Note that this addressing mode is not RIP relative. + } + else + { + operand->Info.Memory.HasBase = true; + operand->Info.Memory.BaseSize = defsize; + operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.b << 3) | Instrux->Sib.base); + + if ((operand->Info.Memory.Base == REG_RSP) || (operand->Info.Memory.Base == REG_RBP)) + { + operand->Info.Memory.Seg = REG_SS; + } + } + + // Check for index. + if ((((Instrux->Exs.x << 3) | Instrux->Sib.index) != REG_RSP) || ND_HAS_VSIB(Instrux)) + { + // Index * Scale is present. + operand->Info.Memory.HasIndex = true; + operand->Info.Memory.IndexSize = defsize; + operand->Info.Memory.Index = (uint8_t)((Instrux->Exs.x << 3) | Instrux->Sib.index); + + if (ND_HAS_VSIB(Instrux)) + { + operand->Info.Memory.IndexSize = vsibRegSize; + operand->Info.Memory.Index |= Instrux->Exs.vp << 4; + } + + operand->Info.Memory.Scale = 1 << Instrux->Sib.scale; + } + } + else + { + if ((Instrux->ModRm.mod == 0) && (Instrux->ModRm.rm == REG_RBP)) + { + // Some instructions (example: MPX) don't support RIP relative addressing. + if (!!(Instrux->Attributes & ND_FLAG_NO_RIP_REL)) + { + return ND_STATUS_RIP_REL_ADDRESSING_NOT_SUPPORTED; + } + + // + // RIP relative addressing addresses a memory region relative to the current RIP; However, + // the current RIP, when executing the current instruction, is already updated and points + // to the next instruction, therefore, we must add the instruction length also to the final + // address. Note that RIP relative addressing is used even if the instruction uses 32 bit + // addressing, as long as we're in long mode. + // + operand->Info.Memory.IsRipRel = Instrux->IsRipRelative = (Instrux->DefCode == ND_CODE_64); + } + else + { + operand->Info.Memory.HasBase = true; + operand->Info.Memory.BaseSize = defsize; + operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + + if ((operand->Info.Memory.Base == REG_RSP) || (operand->Info.Memory.Base == REG_RBP)) + { + operand->Info.Memory.Seg = REG_SS; + } + } + } + + operand->Info.Memory.HasDisp = Instrux->HasDisp; + operand->Info.Memory.DispSize = Instrux->DispLength; + operand->Info.Memory.Disp = ND_SIGN_EX(Instrux->DispLength, Instrux->Displacement); + } + + // Get the segment. Note that in long mode, segment prefixes are ignored, except for FS and GS. + if (Instrux->HasSeg) + { + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, operand->Info.Memory.Seg); + } + + // Handle VSIB addressing. + if (ND_HAS_VSIB(Instrux)) + { + // VSIB requires SIB. + if (!Instrux->HasSib) + { + return ND_STATUS_VSIB_WITHOUT_SIB; + } + + operand->Info.Memory.IsVsib = true; + + operand->Info.Memory.Vsib.IndexSize = vsibIndexSize; + operand->Info.Memory.Vsib.ElemCount = vsibIndexCount; + operand->Info.Memory.Vsib.ElemSize = (uint8_t)(size / vsibIndexCount); + } + + // Handle sibmem addressing, as used by Intel AMX instructions. + if (ND_HAS_SIBMEM(Instrux)) + { + // sibmem requires SIB to be present. + if (!Instrux->HasSib) + { + return ND_STATUS_INVALID_ENCODING; + } + + operand->Info.Memory.IsSibMem = true; + } + + if (Instrux->HasEvex) + { + // Handle compressed displacement, if any. Note that most EVEX instructions with 8 bit displacement + // use compressed displacement addressing. + if ((Instrux->HasDisp) && (ND_SIZE_8BIT == Instrux->DispLength)) + { + Instrux->HasCompDisp = true; + + operand->Info.Memory.HasCompDisp = true; + operand->Info.Memory.CompDispSize = NdGetCompDispSize(Instrux, operand->Size); + } + + // If we have broadcast, the operand size is fixed to either 32 bit, either 64 bit, depending on bcast size. + // Therefore, we will override the rawSize with either 32 or 64 bits. Note that bcstSize will save the total + // size of the access, and it will be used to compute the number of broadcasted elements: bcstSize / rawSize. + if ((Instrux->Exs.bm) && (opd & (ND_OPD_B32 | ND_OPD_B64))) + { + Instrux->HasBroadcast = true; + operand->Info.Memory.HasBroadcast = true; + + if (opd & ND_OPD_B32) + { + size = ND_SIZE_32BIT; + } + else if (opd & ND_OPD_B64) + { + size = ND_SIZE_64BIT; + } + else + { + size = width ? ND_SIZE_64BIT : ND_SIZE_32BIT; + } + + // Override operand size. + operand->Size = operand->RawSize = size; + } + } + + // MIB, if any. Used by some MPX instructions. + operand->Info.Memory.IsMib = ND_HAS_MIB(Instrux); + + // Bitbase, if any. Used by BT* instructions when the first op is mem and the second one reg. + operand->Info.Memory.IsBitbase = ND_HAS_BITBASE(Instrux); + + // AG, if this is the case. + if (ND_HAS_AG(Instrux)) + { + operand->Info.Memory.IsAG = true; + + // Address generation instructions ignore the segment prefixes. Examples are LEA and MPX instructions. + operand->Info.Memory.HasSeg = false; + operand->Info.Memory.Seg = 0; + } + + // Shadow Stack Access, if this is the case. + operand->Info.Memory.IsShadowStack = ND_HAS_SHS(Instrux); + + break; + + + case ND_OPT_H: + // Vector register, encoded in VEX/EVEX.vvvv. + if (ND_ENCM_LEGACY == Instrux->EncMode) + { + return ND_STATUS_HINT_OPERAND_NOT_USED; + } + else + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.vp << 4) | Instrux->Exs.v); + } + break; + + case ND_OPT_L: + // Vector register, encoded in immediate. + status = NdFetchSseImmediate(Instrux, Code, Offset, Size, 1); + if (!ND_SUCCESS(status)) + { + return status; + } + + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); + operand->Info.Register.Reg = ((Instrux->SseImmediate >> 4) & 0xF) | ((Instrux->SseImmediate & 8) << 1); + + Offset = Instrux->Length; + break; + + case ND_OPT_U: + // Vector register encoded in modrm.rm. + if (Instrux->ModRm.mod != 3) + { + return ND_STATUS_INVALID_ENCODING; + } + + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + if (Instrux->HasEvex || Instrux->HasMvex) + { + operand->Info.Register.Reg |= Instrux->Exs.x << 4; + } + break; + + case ND_OPT_V: + // Vector register encoded in modrm.reg. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + if (Instrux->HasEvex || Instrux->HasMvex) + { + operand->Info.Register.Reg |= Instrux->Exs.rp << 4; + } + break; + + case ND_OPT_W: + // Vector register or memory encoded in modrm.rm. + if (Instrux->ModRm.mod == 3) + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + if (Instrux->HasEvex || Instrux->HasMvex) + { + operand->Info.Register.Reg |= Instrux->Exs.x << 4; + } + } + else + { + goto memory; + } + break; + + case ND_OPT_X: + case ND_OPT_Y: + case ND_OPT_MEM_rDI: + // RSI/RDI based addressing, as used by string instructions. + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasBase = true; + operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; + operand->Info.Memory.HasSeg = true; + operand->Info.Memory.Base = (uint8_t)(((opt == ND_OPT_X) ? REG_RSI : REG_RDI)); + operand->Info.Memory.IsString = (ND_OPT_X == opt || ND_OPT_Y == opt); + // DS:rSI supports segment overriding. ES:rDI does not. + if (opt == ND_OPT_Y) + { + operand->Info.Memory.Seg = REG_ES; + } + else + { + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS); + } + break; + + case ND_OPT_MEM_rBX_AL: + // [rBX + AL], used by XLAT. + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasBase = true; + operand->Info.Memory.HasIndex = true; + operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; + operand->Info.Memory.IndexSize = ND_SIZE_8BIT; // Always 1 Byte. + operand->Info.Memory.Base = REG_RBX; // Always rBX. + operand->Info.Memory.Index = REG_AL; // Always AL. + operand->Info.Memory.Scale = 1; // Always 1. + operand->Info.Memory.HasSeg = true; + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS); + break; + + case ND_OPT_MEM_SHS: + // Shadow stack. + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.IsShadowStack = true; + break; + + case ND_OPT_Z: + // A GPR Register is selected by the low 3 bits inside the opcode. REX.B can be used to extend it. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | (Instrux->PrimaryOpCode & 0x7)); + operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && + (operand->Info.Register.Reg >= 4) && + (ND_ENCM_LEGACY == Instrux->EncMode) && + !Instrux->HasRex; + break; + + case ND_OPT_rB: + // reg inside modrm selects a BND register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_BND; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + if (operand->Info.Register.Reg >= 4) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + break; + + case ND_OPT_mB: + // rm inside modrm selects either a BND register, either memory. + if (Instrux->ModRm.mod == 3) + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_BND; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + if (operand->Info.Register.Reg >= 4) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + } + else + { + goto memory; + } + break; + + case ND_OPT_rK: + // reg inside modrm selects a mask register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSK; + + // Opcode dependent #UD, R and R' must be zero (1 actually, but they're inverted). + if ((Instrux->Exs.r != 0) || (Instrux->Exs.rp != 0)) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = (uint8_t)(Instrux->ModRm.reg); + + break; + + case ND_OPT_vK: + // vex.vvvv selects a mask register. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSK; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = (uint8_t)Instrux->Exs.v; + if (operand->Info.Register.Reg >= 8) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + break; + + case ND_OPT_mK: + // rm inside modrm selects either a mask register, either memory. + if (Instrux->ModRm.mod == 3) + { + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSK; + operand->Info.Register.Size = ND_SIZE_64BIT; + // X and B are ignored when Msk registers are being addressed. + operand->Info.Register.Reg = Instrux->ModRm.rm; + } + else + { + goto memory; + } + break; + + case ND_OPT_aK: + // aaa inside evex selects either a mask register, which is used for masking a destination operand. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_MSK; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = Instrux->Exs.k; + break; + + case ND_OPT_rM: + // Sigh. reg field inside mod r/m encodes memory. This encoding is used by MOVDIR64b and ENQCMD instructions. + // When the ModR/M.reg field is used to select a memory operand, the following apply: + // - The ES segment register is used as a base + // - The ES segment register cannot be overridden + // - The size of the base register is selected by the address size, not the operand size. + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; + operand->Info.Memory.HasSeg = true; + operand->Info.Memory.Seg = REG_ES; + break; + + case ND_OPT_mM: + // Sigh. rm field inside mod r/m encodes memory, even if mod is 3. + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasBase = true; + operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.m << 3) | Instrux->ModRm.rm); + operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; + operand->Info.Memory.HasSeg = true; + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS); + break; + + case ND_OPT_rT: + // Tile register encoded in ModR/M.reg field. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_TILE; + operand->Info.Register.Size = size; + operand->Info.Register.Reg = Instrux->ModRm.reg; + + // #UD if a tile register > 7 is encoded. + if (Instrux->Exs.r != 0) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + break; + + case ND_OPT_mT: + // Tile register encoded in ModR/M.rm field. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_TILE; + operand->Info.Register.Size = size; + operand->Info.Register.Reg = Instrux->ModRm.rm; + + // #UD if a tile register > 7 is encoded. + if (Instrux->Exs.b != 0) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + break; + + case ND_OPT_vT: + // Tile register encoded in vex.vvvv field. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_TILE; + operand->Info.Register.Size = size; + operand->Info.Register.Reg = Instrux->Exs.v; + + // #UD if a tile register > 7 is encoded. + if (operand->Info.Register.Reg > 7) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + break; + + default: + return ND_STATUS_INVALID_INSTRUX; + } + + // Handle block addressing - used by AVX512_4FMAPS and AVX512_4VNNIW instructions. Also used by VP2INTERSECTD/Q + // instructions. Also note that in block addressing, the base of the block is masked using the size of the block; + // for example, for a block size of 1, the first register must be even; For a block size of 4, the first register + // must be divisible by 4. + if (operand->Type == ND_OP_REG) + { + if (opb != 0) + { + operand->Info.Register.Count = opb; + operand->Info.Register.Reg &= ~(opb - 1); + operand->Info.Register.IsBlock = true; + } + else + { + operand->Info.Register.Count = 1; + } + } + + // Store the operand encoding inside the bitmap. + Instrux->OperandsEncodingMap |= (1 << gOperandMap[opt]); + + operand->Encoding = (ND_OPERAND_ENCODING)gOperandMap[opt]; + + // Handle decorators. + if (0 != opd) + { + // Check for mask register. Mask if present only if the operand supports masking and if the + // mask register is not k0 (which implies "no masking"). + if ((opd & ND_OPD_MASK) && (Instrux->Exs.k != 0)) + { + operand->Decorator.HasMask = true; + operand->Decorator.Mask.Msk = (uint8_t)Instrux->Exs.k; + Instrux->HasMask = true; + } + + // Check for zeroing. The operand must support zeroing and the z bit inside vex3 must be set. Note that + // zeroing is allowed only for register destinations, and NOT for memory. + if ((opd & ND_OPD_Z) && (Instrux->Exs.z) && (operand->Type != ND_OP_MEM)) + { + operand->Decorator.HasZero = true; + Instrux->HasZero = true; + } + + // Check for broadcast again. We've already filled the broadcast size before parsing the op size. + if (((opd & ND_OPD_B32) || (opd & ND_OPD_B64)) && (Instrux->Exs.bm) && (Instrux->ModRm.mod != 3)) + { + operand->Decorator.HasBroadcast = true; + operand->Decorator.Broadcast.Size = (uint8_t)operand->Size; + operand->Decorator.Broadcast.Count = (uint8_t)(bcstSize / operand->Size); + } + + if (opd & ND_OPD_SAE) + { + operand->Decorator.HasSae = Instrux->HasSae; + } + + if (opd & ND_OPD_ER) + { + operand->Decorator.HasEr = Instrux->HasEr; + } + } + + return status; +} + + +// +// NdFindInstruction +// +static NDSTATUS +NdFindInstruction( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t Offset, + size_t Size, + uint8_t Vendor, + ND_INSTRUCTION **InsDef + ) +{ + NDSTATUS status; + const ND_TABLE *pTable; + ND_INSTRUCTION *pIns; + bool stop, redf2, redf3; + uint32_t nextOpcode, nextIndex; + + UNREFERENCED_PARAMETER(Offset); + + // pre-init + status = ND_STATUS_SUCCESS; + pIns = NULL; + stop = false; + nextOpcode = 0; + redf2 = redf3 = false; + + switch (Instrux->EncMode) + { + case ND_ENCM_LEGACY: + pTable = (const ND_TABLE *)gRootTable; + break; + case ND_ENCM_XOP: + pTable = (const ND_TABLE *)gXopTable; + break; + case ND_ENCM_VEX: + pTable = (const ND_TABLE *)gVexTable; + break; + case ND_ENCM_EVEX: + pTable = (const ND_TABLE *)gEvexTable; + break; + default: + pTable = (const ND_TABLE *)NULL; + break; + } + + while ((!stop) && (NULL != pTable)) + { + switch (pTable->Type) + { + case ND_ILUT_INSTRUCTION: + // We've found the leaf entry, which is an instruction - we can leave. + pIns = (ND_INSTRUCTION *)(((ND_TABLE_INSTRUCTION *)pTable)->Instruction); + stop = true; + break; + + case ND_ILUT_OPCODE: + // We need an opcode to keep going. + status = NdFetchOpcode(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + pTable = (const ND_TABLE *)pTable->Table[Instrux->OpCodeBytes[nextOpcode++]]; + break; + + case ND_ILUT_OPCODE_3DNOW: + // We need an opcode to select the next table, but the opcode is AFTER the modrm/sib/displacement. + if (!Instrux->HasModRm) + { + // Fetch modrm + status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + + // Fetch displacement. + status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + } + + // Fetch the opcode, which is after the modrm and displacement. + status = NdFetchOpcode(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + + pTable = (const ND_TABLE *)pTable->Table[Instrux->OpCodeBytes[nextOpcode++]]; + break; + + case ND_ILUT_MODRM_MOD: + // We need modrm.mod to select the next table. + if (!Instrux->HasModRm) + { + // Fetch modrm + status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + + // Fetch displacement. + status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + } + + // Next index is either 0 (mem) or 1 (reg) + pTable = (const ND_TABLE *)pTable->Table[Instrux->ModRm.mod == 3 ? 1 : 0]; + break; + + case ND_ILUT_MODRM_REG: + // We need modrm.reg to select the next table. + if (!Instrux->HasModRm) + { + // Fetch modrm + status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + + // Fetch displacement. + status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + } + + // Next index is the reg. + pTable = (const ND_TABLE *)pTable->Table[Instrux->ModRm.reg]; + break; + + case ND_ILUT_MODRM_RM: + // We need modrm.rm to select the next table. + if (!Instrux->HasModRm) + { + // Fetch modrm + status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + + // Fetch displacement. + status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + } + + // Next index is the rm. + pTable = (const ND_TABLE *)pTable->Table[Instrux->ModRm.rm]; + break; + + case ND_ILUT_MAN_PREFIX: + // We have mandatory prefixes. + if ((Instrux->Rep == 0xF2) && !redf2) + { + // We can only redirect once through one mandatory prefix, otherwise we may + // enter an infinite loop (see CRC32 Gw Eb -> 0x66 0xF2 0x0F ...) + redf2 = true; + nextIndex = ND_ILUT_INDEX_MAN_PREF_F2; + Instrux->HasMandatoryF2 = true; + } + else if ((Instrux->Rep == 0xF3) && !redf3) + { + redf3 = true; + nextIndex = ND_ILUT_INDEX_MAN_PREF_F3; + Instrux->HasMandatoryF3 = true; + } + else if (Instrux->HasOpSize) + { + nextIndex = ND_ILUT_INDEX_MAN_PREF_66; + Instrux->HasMandatory66 = true; + } + else + { + nextIndex = ND_ILUT_INDEX_MAN_PREF_NONE; + } + pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + break; + + case ND_ILUT_MODE: + { + static const uint8_t indexes[3] = + { + ND_ILUT_INDEX_MODE_16, ND_ILUT_INDEX_MODE_32, ND_ILUT_INDEX_MODE_64 + }; + + nextIndex = ND_ILUT_INDEX_MODE_NONE; + + if (NULL != pTable->Table[indexes[Instrux->DefCode]]) + { + nextIndex = indexes[Instrux->DefCode]; + } + + pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + } + break; + + case ND_ILUT_DSIZE: + { + static const uint8_t indexes[3] = + { + ND_ILUT_INDEX_DSIZE_16, ND_ILUT_INDEX_DSIZE_32, ND_ILUT_INDEX_DSIZE_64 + }; + + nextIndex = ND_ILUT_INDEX_DSIZE_NONE; + + if (NULL != pTable->Table[indexes[Instrux->OpMode]]) + { + nextIndex = indexes[Instrux->OpMode]; + } + + // Handle default/forced redirections in 64 bit mode. + if (ND_CODE_64 == Instrux->DefCode) + { + if ((NULL != pTable->Table[4]) && (!Instrux->HasOpSize || Instrux->Exs.w)) + { + nextIndex = 4; + } + else if (NULL != pTable->Table[5]) + { + nextIndex = 5; + } + } + + pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + } + break; + + case ND_ILUT_ASIZE: + { + static const uint8_t indexes[3] = {ND_ILUT_INDEX_ASIZE_16, ND_ILUT_INDEX_ASIZE_32, ND_ILUT_INDEX_ASIZE_64}; + + nextIndex = ND_ILUT_INDEX_ASIZE_NONE; + + if (NULL != pTable->Table[indexes[Instrux->AddrMode]]) + { + nextIndex = indexes[Instrux->AddrMode]; + } + + pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + } + break; + + case ND_ILUT_AUXILIARY: + // Auxiliary redirection. Default to table[0] if nothing matches. + if (Instrux->HasRex && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_REX])) + { + nextIndex = ND_ILUT_INDEX_AUX_REX; + } + else if (Instrux->HasRex && Instrux->Rex.w && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXW])) + { + nextIndex = ND_ILUT_INDEX_AUX_REXW; + } + else if ((Instrux->DefCode == ND_CODE_64) && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_O64])) + { + nextIndex = ND_ILUT_INDEX_AUX_O64; + } + else if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_F3])) + { + nextIndex = ND_ILUT_INDEX_AUX_F3; + } + else if ((Instrux->Rep != 0) && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_REP])) + { + nextIndex = ND_ILUT_INDEX_AUX_REP; + } + else + { + nextIndex = ND_ILUT_INDEX_AUX_NONE; + } + pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + break; + + case ND_ILUT_VENDOR: + // Vendor redirection. Go to the vendor specific entry. + if (NULL != pTable->Table[Vendor]) + { + pTable = (const ND_TABLE *)pTable->Table[Vendor]; + } + else + { + pTable = (const ND_TABLE *)pTable->Table[ND_VEND_ANY]; + } + break; + + case ND_ILUT_VEX_MMMMM: + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.m]; + break; + + case ND_ILUT_VEX_PP: + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.p]; + break; + + case ND_ILUT_VEX_L: + if (Instrux->HasEvex && Instrux->Exs.bm) + { + // We have evex; we need to fetch the modrm now, because we have to make sure we don't have SAE or ER; + // if we do have SAE or ER, we have to check the modrm byte and see if it is a reg-reg form (mod = 3), + // in which case L'L is forced to the maximum vector length of the instruction. We know for sure that + // all EVEX instructions have modrm. + if (!Instrux->HasModRm) + { + // Fetch modrm + status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + + // Fetch displacement. + status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + stop = true; + break; + } + } + + if (3 == Instrux->ModRm.mod) + { + // We use the maximum vector length of the instruction. If the instruction does not support + // SAE or ER, a #UD would be generated. We check for this later. + if (NULL != pTable->Table[2]) + { + pTable = (const ND_TABLE *)pTable->Table[2]; + } + else if (NULL != pTable->Table[1]) + { + pTable = (const ND_TABLE *)pTable->Table[1]; + } + else + { + pTable = (const ND_TABLE *)pTable->Table[0]; + } + } + else + { + // Mod is mem, we simply use L'L for indexing, as no SAE or ER can be present. + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.l]; + } + } + else + { + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.l]; + } + break; + + case ND_ILUT_VEX_W: + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.w]; + break; + + default: + status = ND_STATUS_INTERNAL_ERROR; + stop = true; + break; + } + } + + if (!ND_SUCCESS(status)) + { + goto cleanup_and_exit; + } + + if (NULL != pIns) + { + // Bingo! Valid instruction found for the encoding. If Modrm is needed and we didn't fetch it - do it now. + if ((pIns->Attributes & ND_FLAG_MODRM) && (!Instrux->HasModRm)) + { + if (0 == (pIns->Attributes & ND_FLAG_MFR)) + { + // Fetch Mod R/M and SIB. + status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + goto cleanup_and_exit; + } + + // Fetch displacement. + status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + goto cleanup_and_exit; + } + } + else + { + // Handle special MOV with control and debug registers - the mod is always forced to register. SIB + // and displacement is ignored. + status = NdFetchModrm(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + goto cleanup_and_exit; + } + } + } + + // Store primary opcode. + Instrux->PrimaryOpCode = Instrux->OpCodeBytes[Instrux->OpLength - 1]; + + Instrux->MainOpOffset = ND_IS_3DNOW(Instrux) ? + Instrux->Length - 1 : Instrux->OpOffset + Instrux->OpLength - 1; + + // Make sure the instruction is valid in the given mode. + if ((ND_CODE_64 == Instrux->DefCode) && (pIns->Attributes & ND_FLAG_I64)) + { + status = ND_STATUS_INVALID_ENCODING_IN_MODE; + } + + if ((ND_CODE_64 != Instrux->DefCode) && (pIns->Attributes & ND_FLAG_O64)) + { + status = ND_STATUS_INVALID_ENCODING_IN_MODE; + } + } + else + { + status = ND_STATUS_INVALID_ENCODING; + } + +cleanup_and_exit: + *InsDef = pIns; + + return status; +} + + + +// +// NdGetVectorLength +// +static __forceinline NDSTATUS +NdGetVectorLength( + INSTRUX *Instrux + ) +{ + if (Instrux->HasEvex && Instrux->Exs.bm && (Instrux->ModRm.mod == 3) && + (ND_ER_SUPPORT(Instrux) || ND_SAE_SUPPORT(Instrux))) + { + // Embedded rounding present, force the vector length to 512. + if ((Instrux->TupleType == ND_TUPLE_T1S) || (Instrux->TupleType == ND_TUPLE_T1F)) + { + Instrux->VecMode = Instrux->EfVecMode = ND_VECM_128; + } + else + { + Instrux->VecMode = Instrux->EfVecMode = ND_VECM_512; + } + + return ND_STATUS_SUCCESS; + } + + // Decode VEX vector length. Also take into consideration the "ignore L" flag. + switch (Instrux->Exs.l) + { + case 0: + Instrux->VecMode = ND_VECM_128; + Instrux->EfVecMode = ND_VECM_128; + break; + case 1: + Instrux->VecMode = ND_VECM_256; + Instrux->EfVecMode = (Instrux->Attributes & ND_FLAG_LIG) ? ND_VECM_128 : ND_VECM_256; + break; + case 2: + Instrux->VecMode = ND_VECM_512; + Instrux->EfVecMode = (Instrux->Attributes & ND_FLAG_LIG) ? ND_VECM_128 : ND_VECM_512; + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdGetAddrAndOpMode +// +static __forceinline NDSTATUS +NdGetAddrAndOpMode( + INSTRUX *Instrux + ) +{ + // Fill in addressing mode & default op size. + switch (Instrux->DefCode) + { + case ND_CODE_16: + Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_32 : ND_ADDR_16; + Instrux->OpMode = Instrux->HasOpSize ? ND_OPSZ_32 : ND_OPSZ_16; + break; + case ND_CODE_32: + Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_16 : ND_ADDR_32; + Instrux->OpMode = Instrux->HasOpSize ? ND_OPSZ_16 : ND_OPSZ_32; + break; + case ND_CODE_64: + Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_32 : ND_ADDR_64; + Instrux->OpMode = Instrux->Exs.w ? ND_OPSZ_64 : (Instrux->HasOpSize ? ND_OPSZ_16 : ND_OPSZ_32); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdGetEffectiveOpMode +// +static __forceinline NDSTATUS +NdGetEffectiveOpMode( + INSTRUX *Instrux + ) +{ + static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + bool width, f64, d64, has66; + + // Extract the flags. + width = (0 != Instrux->Exs.w) && !(Instrux->Attributes & ND_FLAG_WIG); + // In 64 bit mode, the operand is forced to 64 bit. Size-changing prefixes are ignored. + f64 = 0 != (Instrux->Attributes & ND_FLAG_F64); + // In 64 bit mode, the operand defaults to 64 bit No 32 bit form of the instruction exists. + d64 = 0 != (Instrux->Attributes & ND_FLAG_D64); + // Check if 0x66 is indeed interpreted as a size changing prefix. Note that if 0x66 is a mandatory prefix, + // then it won't be interpreted as a size changing prefix. However, there is an exception: MOVBE and CRC32 + // have mandatory 0xF2, and 0x66 is in fact a size changing prefix. + has66 = Instrux->HasOpSize && (!Instrux->HasMandatory66 || (Instrux->Attributes & ND_FLAG_S66)); + + // Fill in the effective operand size. + switch (Instrux->DefCode) + { + case ND_CODE_16: + Instrux->EfOpMode = has66 ? ND_OPSZ_32 : ND_OPSZ_16; + break; + case ND_CODE_32: + Instrux->EfOpMode = has66 ? ND_OPSZ_16 : ND_OPSZ_32; + break; + case ND_CODE_64: + Instrux->EfOpMode = (width || f64 || (d64 && !has66)) ? ND_OPSZ_64 : (has66 ? ND_OPSZ_16 : ND_OPSZ_32); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + + // Fill in the default word length. It can't be more than 8 bytes. + Instrux->WordLength = szLut[Instrux->EfOpMode]; + + return ND_STATUS_SUCCESS; +} + + +// +// NdValidateInstruction +// +static __forceinline NDSTATUS +NdValidateInstruction( + INSTRUX *Instrux + ) +{ + // If LOCK is present, make sure that the instruction 1. supports LOCKing and 2. the destination is memory. + // A special case are MOV to/from CRs, on AMD, in 16/32 bit mode. + if (Instrux->HasLock && (0 == (Instrux->Attributes & ND_FLAG_LOCK_SPECIAL) || (ND_CODE_64 == Instrux->DefCode)) && + (!ND_LOCK_SUPPORT(Instrux) || (Instrux->Operands[0].Type != ND_OP_MEM))) + { + return ND_STATUS_BAD_LOCK_PREFIX; + } + + // Some instructions (example: PTWRITE) do not accept the 0x66 prefix. + if (Instrux->HasOpSize && (0 != (Instrux->Attributes & ND_FLAG_NO66))) + { + return ND_STATUS_66_NOT_ACCEPTED; + } + + // 16 bit addressing is checked when decoding the memory operand (if present). + // RIP-relative addressing is checked when decoding the memory operand (if present). + // Register validity is checked when decoding the said register. + // Memory/register encoding for instructions which don't support it is checked when decoding the operand. + + // VEX/EVEX validations. + if (ND_ENCM_LEGACY != Instrux->EncMode) + { + // Instructions that don't use VEX/XOP vvvv field must set it to 1111b/0, otherwise a #UD will be generated. + if ((0 == (Instrux->OperandsEncodingMap & (1 << ND_OPE_V))) && (0 != Instrux->Exs.v)) + { + return ND_STATUS_VEX_VVVV_MUST_BE_ZERO; + } + + // Some instructions don't support 128 bit vectors. + if ((ND_VECM_128 == Instrux->EfVecMode) && (0 != (Instrux->Attributes & ND_FLAG_NOL0))) + { + return ND_STATUS_INVALID_ENCODING; + } + + // VSIB instructions have a restriction: the same vector register can't be used by more than one operand. + if (ND_HAS_VSIB(Instrux)) + { + uint8_t usedVects[32] = { 0 }; + + for (uint32_t i = 0; i < Instrux->OperandsCount; i++) + { + if (Instrux->Operands[i].Type == ND_OP_REG && Instrux->Operands[i].Info.Register.Type == ND_REG_SSE) + { + if (++usedVects[Instrux->Operands[i].Info.Register.Reg] > 1) + { + return ND_STATUS_INVALID_VSIB_REGS; + } + } + else if (Instrux->Operands[i].Type == ND_OP_MEM) + { + if (++usedVects[Instrux->Operands[i].Info.Memory.Index] > 1) + { + return ND_STATUS_INVALID_VSIB_REGS; + } + } + } + } + + // Handle AMX exception class. + if (Instrux->ExceptionClass == ND_EXC_AMX) + { + if (Instrux->ExceptionType == ND_EXT_AMX_E4) + { + // #UD if srcdest == src1, srcdest == src2 or src1 == src2. All three operands are tile regs. + if (Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[1].Info.Register.Reg || + Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg || + Instrux->Operands[1].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + } + else + { + // #UD if vex.vvvv is not 0 (0b1111 negated) for all other exception classes, as they do not use it. + if (Instrux->Exs.v != 0) + { + return ND_STATUS_VEX_VVVV_MUST_BE_ZERO; + } + } + } + + if (Instrux->HasEvex) + { + // Instructions that don't support masking must have EVEX.aaa = 0. + if (!ND_MASK_SUPPORT(Instrux) && (0 != Instrux->Exs.k)) + { + return ND_STATUS_MASK_NOT_SUPPORTED; + } + + // Some instructions have mandatory masking, and using k0 as a mask triggers #UD. + if ((Instrux->Attributes & ND_FLAG_MMASK) && (0 == Instrux->Exs.k)) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + + // EVEX.z must be 0 if: + // - zeroing is not supported by the instruction. + // - zeroing is supported, but the destination is memory. + // If zeroing is supported and the mask is 0, then zeroing is ignored. + if (0 != Instrux->Exs.z) + { + if (!ND_ZERO_SUPPORT(Instrux)) + { + return ND_STATUS_ZEROING_NOT_SUPPORTED; + } + + if (Instrux->Operands[0].Type == ND_OP_MEM) + { + return ND_STATUS_ZEROING_ON_MEMORY; + } + } + + // EVEX.b must be 0 if SAE/ER is not used. + if (Instrux->Exs.bm && (Instrux->ModRm.mod == 3) && !ND_SAE_SUPPORT(Instrux) && !ND_ER_SUPPORT(Instrux)) + { + return ND_STATUS_ER_SAE_NOT_SUPPORTED; + } + + // EVEX.b must be 0 if broadcast is not supported. + if (Instrux->Exs.bm && (Instrux->ModRm.mod != 3) && !ND_BROADCAST_SUPPORT(Instrux)) + { + return ND_STATUS_BROADCAST_NOT_SUPPORTED; + } + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdDecodeEx2 +// +NDSTATUS +NdDecodeEx2( + INSTRUX *Instrux, + const uint8_t *Code, + size_t Size, + uint8_t DefCode, + uint8_t DefData, + uint8_t DefStack, + uint8_t Vendor + ) +{ + NDSTATUS status; + PND_INSTRUCTION pIns; + uint32_t opIndex; + + // pre-init + status = ND_STATUS_SUCCESS; + pIns = NULL; + opIndex = 0; + + // validate + if (NULL == Instrux) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (NULL == Code) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (Size == 0) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (ND_CODE_64 < DefCode) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (ND_DATA_64 < DefData) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (ND_VEND_CYRIX < Vendor) + { + return ND_STATUS_INVALID_PARAMETER; + } + + // Initialize with zero. + nd_memzero(Instrux, sizeof(INSTRUX)); + + Instrux->DefCode = DefCode; + Instrux->DefData = DefData; + Instrux->DefStack = DefStack; + + // Fetch prefixes. We peek at the first byte, if that's not a prefix, there's no need to call the main decoder. + if (ND_PREF_CODE_NONE != gPrefixesMap[Code[0]]) + { + status = NdFetchPrefixes(Instrux, Code, 0, Size); + if (!ND_SUCCESS(status)) + { + return status; + } + } + + // Get addressing mode & operand size. + status = NdGetAddrAndOpMode(Instrux); + if (!ND_SUCCESS(status)) + { + return status; + } + + // Start iterating the tables, in order to extract the instruction entry. + status = NdFindInstruction(Instrux, Code, Instrux->Length, Size, Vendor, &pIns); + if (!ND_SUCCESS(status)) + { + return status; + } + + // Instruction found, copy information inside the Instrux. + Instrux->Attributes = pIns->Attributes; + Instrux->Instruction = Instrux->Iclass = (ND_INS_CLASS)pIns->Instruction; + Instrux->Category = (ND_INS_CATEGORY)pIns->Category; + Instrux->IsaSet = (ND_INS_SET)pIns->IsaSet; + Instrux->FlagsAccess.Undefined.Raw = pIns->SetFlags & pIns->ClearedFlags; + Instrux->FlagsAccess.Tested.Raw = pIns->TestedFlags; + Instrux->FlagsAccess.Modified.Raw = pIns->ModifiedFlags; + Instrux->FlagsAccess.Set.Raw = pIns->SetFlags ^ Instrux->FlagsAccess.Undefined.Raw; + Instrux->FlagsAccess.Cleared.Raw = pIns->ClearedFlags ^ Instrux->FlagsAccess.Undefined.Raw; + Instrux->CpuidFlag.Flag = pIns->CpuidFlag; + Instrux->ValidModes.Raw = pIns->ValidModes; + Instrux->ValidPrefixes.Raw = pIns->ValidPrefixes; + Instrux->ValidDecorators.Raw = pIns->ValidDecorators; + *((uint8_t*)&Instrux->FpuFlagsAccess) = pIns->FpuFlags; + // Valid for EVEX, VEX and SSE instructions only. A value of 0 means it's not used. + Instrux->ExceptionClass = pIns->ExcClass; + Instrux->ExceptionType = pIns->ExcType; + // Used only by EVEX instructions. + Instrux->TupleType = pIns->TupleType; + + // Copy the mnemonic, up until the NULL terminator. + for (size_t i = 0; i < sizeof(Instrux->Mnemonic); i++) + { + Instrux->Mnemonic[i] = gMnemonics[pIns->Mnemonic][i]; + if (Instrux->Mnemonic[i] == 0) + { + break; + } + } + + // Get effective operand mode. + status = NdGetEffectiveOpMode(Instrux); + if (!ND_SUCCESS(status)) + { + return status; + } + + if (ND_HAS_VECTOR(Instrux)) + { + // Get vector length. + status = NdGetVectorLength(Instrux); + if (!ND_SUCCESS(status)) + { + return status; + } + } + + // Handle condition byte, if present. + if (ND_HAS_SSE_CONDITION(Instrux)) + { + Instrux->SseCondition = Instrux->Immediate1 & 0x1F; + } + + // Handle predicate, if present. + if (ND_HAS_CONDITION(Instrux)) + { + Instrux->Condition = Instrux->Predicate = Instrux->PrimaryOpCode & 0xF; + } + + if (0 != pIns->ValidDecorators) + { + // Check for suppress all exceptions. + if ((Instrux->ValidDecorators.Sae) && (Instrux->Exs.bm) && (Instrux->ModRm.mod == 3)) + { + Instrux->HasSae = true; + } + + // Check for embedded rounding. This is available only in reg-reg encodings. Also, if embedded + // rounding is used, the vector length is forced to 512 bit, as the + if ((Instrux->ValidDecorators.Er) && (Instrux->Exs.bm) && (Instrux->ModRm.mod == 3)) + { + Instrux->HasEr = true; + Instrux->HasSae = true; + Instrux->RoundingMode = (uint8_t)Instrux->Exs.l; + } + } + + Instrux->ExpOperandsCount = ND_EXP_OPS_CNT(pIns->OpsCount); + Instrux->OperandsCount = Instrux->ExpOperandsCount + ND_IMP_OPS_CNT(pIns->OpsCount); + + // And now decode each operand. + for (opIndex = 0; opIndex < Instrux->OperandsCount; ++opIndex) + { + status = NdParseOperand(Instrux, Code, Instrux->Length, Size, opIndex, pIns->Operands[opIndex]); + if (!ND_SUCCESS(status)) + { + return status; + } + } + + // Check if the instruction is XACQUIRE or XRELEASE enabled. + if ((Instrux->Rep != 0) && (Instrux->HasLock || (!!Instrux->ValidPrefixes.HleNoLock)) && + (Instrux->Operands[0].Type == ND_OP_MEM)) + { + if ((ND_XACQUIRE_SUPPORT(Instrux) || ND_HLE_SUPPORT(Instrux)) && (Instrux->Rep == ND_PREFIX_G1_XACQUIRE)) + { + Instrux->IsXacquireEnabled = true; + } + else if ((ND_XRELEASE_SUPPORT(Instrux) || ND_HLE_SUPPORT(Instrux)) && (Instrux->Rep == ND_PREFIX_G1_XRELEASE)) + { + Instrux->IsXreleaseEnabled = true; + } + } + + // Check if the instruction is REPed. + Instrux->IsRepeated = ((Instrux->Rep != 0) && (ND_REP_SUPPORT(Instrux) || ND_REPC_SUPPORT(Instrux))); + + // Check if the instruction is CET tracked. The do not track prefix (0x3E) works only for indirect near JMP and CALL + // via register. It is always enabled for indirect far JMP and CALL or near indirect JMP and CALL via memoery. + Instrux->IsCetTracked = ND_HAS_CETT(Instrux) && ((!ND_DNT_SUPPORT(Instrux)) || + (Instrux->Seg != ND_PREFIX_G2_NO_TRACK) || + (Instrux->HasModRm && (Instrux->ModRm.mod != 3))); + + // Do instruction validations. These checks are made in order to filter out encodings that would normally + // be invalid and would generate #UD. + status = NdValidateInstruction(Instrux); + if (!ND_SUCCESS(status)) + { + return status; + } + + // Copy the instruction bytes. + for (opIndex = 0; opIndex < Instrux->Length; opIndex++) + { + Instrux->InstructionBytes[opIndex] = Code[opIndex]; + } + + // All done! Instruction successfully decoded! + return ND_STATUS_SUCCESS; +} + + +// +// NdDecodeEx +// +NDSTATUS +NdDecodeEx( + INSTRUX *Instrux, + const uint8_t *Code, + size_t Size, + uint8_t DefCode, + uint8_t DefData + ) +{ + return NdDecodeEx2(Instrux, Code, Size, DefCode, DefData, DefCode, ND_VEND_ANY); +} + + +// +// NdDecode +// +NDSTATUS +NdDecode( + INSTRUX *Instrux, + const uint8_t *Code, + uint8_t DefCode, + uint8_t DefData + ) +{ + return NdDecodeEx2(Instrux, Code, ND_MAX_INSTRUCTION_LENGTH, DefCode, DefData, DefCode, ND_VEND_ANY); +} + + +// +// NdToText +// +NDSTATUS +NdToText( + const INSTRUX *Instrux, + uint64_t Rip, + uint32_t BufferSize, + char *Buffer + ) +{ + NDSTATUS status; + char *res, temp[64]; + uint32_t opIndex, opsStored; + const ND_OPERAND *pOp; + bool alignmentStored; + + // pre-init + status = ND_STATUS_SUCCESS; + res = NULL; + opIndex = 0; + opsStored = 0; + pOp = NULL; + alignmentStored = false; + + // Validate args. + if (NULL == Instrux) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (NULL == Buffer) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (BufferSize < ND_MIN_BUF_SIZE) + { + return ND_STATUS_INVALID_PARAMETER; + } + + // init the text. + nd_memzero(Buffer, BufferSize); + nd_memzero(temp, sizeof(temp)); + + // First, store the prefixes. + if (Instrux->Rep != 0) + { + // Check for REPZ/REPNZ support, and store prefixes. + if (ND_REPC_SUPPORT(Instrux)) + { + if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ) + { + res = nd_strcat_s(Buffer, BufferSize, "REPZ "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + else if (Instrux->Rep == ND_PREFIX_G1_REPNE_REPNZ) + { + res = nd_strcat_s(Buffer, BufferSize, "REPNZ "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + // Check for REP support and store prefixes. + if (ND_REP_SUPPORT(Instrux)) + { + if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ) + { + res = nd_strcat_s(Buffer, BufferSize, "REP "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + else if (Instrux->Rep == ND_PREFIX_G1_REPNE_REPNZ) + { + res = nd_strcat_s(Buffer, BufferSize, "REPNZ "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + if (Instrux->IsXreleaseEnabled) + { + res = nd_strcat_s(Buffer, BufferSize, "XRELEASE "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + else if (Instrux->IsXacquireEnabled) + { + res = nd_strcat_s(Buffer, BufferSize, "XACQUIRE "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + if (Instrux->HasLock) + { + if (ND_LOCK_SUPPORT(Instrux)) + { + res = nd_strcat_s(Buffer, BufferSize, "LOCK "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + if (Instrux->Rep == ND_PREFIX_G1_BND) + { + if (ND_BND_SUPPORT(Instrux)) + { + res = nd_strcat_s(Buffer, BufferSize, "BND "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + if (Instrux->HasSeg && ND_BHINT_SUPPORT(Instrux)) + { + switch (Instrux->Bhint) + { + case ND_PREFIX_G2_BR_TAKEN: + res = nd_strcat_s(Buffer, BufferSize, "BHT "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + + case ND_PREFIX_G2_BR_NOT_TAKEN: + res = nd_strcat_s(Buffer, BufferSize, "BHNT "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + + case ND_PREFIX_G2_BR_ALT: + res = nd_strcat_s(Buffer, BufferSize, "BHALT "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + + default: + break; + } + } + + if (Instrux->HasSeg && ND_DNT_SUPPORT(Instrux)) + { + if (!Instrux->IsCetTracked) + { + res = nd_strcat_s(Buffer, BufferSize, "DNT "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + // Store the mnemonic. + res = nd_strcat_s(Buffer, BufferSize, Instrux->Mnemonic); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + + // Store condition code, if any. + if (ND_HAS_SSE_CONDITION(Instrux)) + { + res = nd_strcat_s(Buffer, BufferSize, gConditionCodes[Instrux->SseCondition]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // If there are no explicit operands, we can leave. + if (0 == Instrux->ExpOperandsCount) + { + return ND_STATUS_SUCCESS; + } + + // Now the operands. + for (opIndex = 0; opIndex < Instrux->OperandsCount; opIndex++) + { + status = ND_STATUS_SUCCESS; + + pOp = &Instrux->Operands[opIndex]; + + if (pOp->Type == ND_OP_NOT_PRESENT) + { + break; + } + + if (pOp->Flags.IsDefault) + { + continue; + } + + // If this is a mask operand that has been used as masking for a previous operand, than we + // can safely skip it. We check this by seeing where is the operand encoded. If it's encoded + // in the evex.aaa field, than it is a conventional mask. + if ((pOp->Encoding == ND_OPE_A) && (pOp->Type == ND_OP_REG) && + (pOp->Info.Register.Type == ND_REG_MSK) && (opIndex > 0)) + { + continue; + } + + // Store alignment. + if (!alignmentStored) + { + size_t idx = 0; + + while ((idx < BufferSize) && (Buffer[idx])) + { + idx++; + } + + while ((idx < 9) && (idx + 1 < BufferSize)) + { + Buffer[idx++] = 0x20; + } + + if (idx + 1 < BufferSize) + { + Buffer[idx++] = 0x20; + } + + Buffer[idx] = 0; + + alignmentStored = true; + } + + // Store the comma, if this isn't the first operand. + if (opsStored > 0) + { + res = nd_strcat_s(Buffer, BufferSize, ", "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + opsStored++; + + switch (pOp->Type) + { + case ND_OP_REG: + switch (pOp->Info.Register.Type) + { + case ND_REG_GPR: + { + if (pOp->Info.Register.Reg >= ND_MAX_GPR_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + // General purpose register. + switch (pOp->Info.Register.Size) + { + case ND_SIZE_8BIT: + // 8 bit register. + if ((Instrux->EncMode != ND_ENCM_LEGACY) || Instrux->HasRex) + { + res = nd_strcat_s(Buffer, BufferSize, gReg8Bit64[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + else + { + res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_SIZE_16BIT: + // 16 bit register. + res = nd_strcat_s(Buffer, BufferSize, gReg16Bit[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + + case ND_SIZE_32BIT: + // 32 bit register. + res = nd_strcat_s(Buffer, BufferSize, gReg32Bit[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + + case ND_SIZE_64BIT: + // 64 bit register. + res = nd_strcat_s(Buffer, BufferSize, gReg64Bit[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + + default: + return ND_STATUS_INVALID_INSTRUX; + } + } + break; + + case ND_REG_SEG: + { + if (pOp->Info.Register.Reg >= ND_MAX_SEG_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegSeg[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_FPU: + { + if (pOp->Info.Register.Reg >= ND_MAX_FPU_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegFpu[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_MMX: + { + if (pOp->Info.Register.Reg >= ND_MAX_MMX_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegMmx[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_SSE: + { + if (pOp->Info.Register.Reg >= ND_MAX_SSE_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + switch (pOp->Info.Register.Size) + { + case ND_SIZE_128BIT: + res = nd_strcat_s(Buffer, BufferSize, gRegXmm[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_256BIT: + res = nd_strcat_s(Buffer, BufferSize, gRegYmm[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_512BIT: + res = nd_strcat_s(Buffer, BufferSize, gRegZmm[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + } + break; + + case ND_REG_CR: + { + if (pOp->Info.Register.Reg >= ND_MAX_CR_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegControl[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_DR: + { + if (pOp->Info.Register.Reg >= ND_MAX_DR_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegDebug[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_TR: + { + if (pOp->Info.Register.Reg >= ND_MAX_TR_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegTest[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_BND: + { + // Sanity check. + if (pOp->Info.Register.Reg >= ND_MAX_BND_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegBound[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_MSK: + { + // Sanity check. + if (pOp->Info.Register.Reg >= ND_MAX_MSK_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegMask[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_REG_TILE: + { + // Sanity check. + if (pOp->Info.Register.Reg >= ND_MAX_TILE_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, gRegTile[pOp->Info.Register.Reg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + default: + break; + } + + if (pOp->Info.Register.Count > 1) + { + status = NdSprintf(temp, sizeof(temp), "+%d", pOp->Info.Register.Count - 1); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + break; + + case ND_OP_BANK: + // Nothing to show. + break; + + case ND_OP_CONST: + { + // Implicit constant + status = NdSprintf(temp, sizeof(temp), "%d", pOp->Info.Constant.Const); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_OP_IMM: + { + switch (pOp->RawSize) + { + case 1: + status = NdSprintf(temp, sizeof(temp), "0x%02x", (uint8_t)pOp->Info.Immediate.Imm); + break; + case 2: + status = NdSprintf(temp, sizeof(temp), "0x%04x", (uint16_t)pOp->Info.Immediate.Imm); + break; + case 4: + status = NdSprintf(temp, sizeof(temp), "0x%08x", (uint32_t)pOp->Info.Immediate.Imm); + break; + case 8: + status = NdSprintf(temp, sizeof(temp), "0x%016llx", (uint64_t)pOp->Info.Immediate.Imm); + break; + } + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_OP_OFFS: + { + uint64_t dest = Rip + Instrux->Length + pOp->Info.RelativeOffset.Rel; + + // Truncate to the actual word length. + switch (Instrux->WordLength) + { + case 2: + dest &= 0xFFFF; + break; + case 4: + dest &= 0xFFFFFFFF; + break; + default: + break; + } + + status = NdSprintf(temp, sizeof(temp), "0x%llx", dest); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_OP_ADDR: + { + switch (Instrux->AddrLength) + { + case 4: + status = NdSprintf(temp, sizeof(temp), "0x%04x:0x%04x", + pOp->Info.Address.BaseSeg, (uint16_t)pOp->Info.Address.Offset); + break; + case 6: + status = NdSprintf(temp, sizeof(temp), "0x%04x:0x%08x", + pOp->Info.Address.BaseSeg, (uint32_t)pOp->Info.Address.Offset); + break; + case 10: + status = NdSprintf(temp, sizeof(temp), "0x%04x:0x%016llx", + pOp->Info.Address.BaseSeg, (uint64_t)pOp->Info.Address.Offset); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_OP_MEM: + { + // Prepend the size. + switch (pOp->Size) + { + case 1: + res = nd_strcat_s(Buffer, BufferSize, "byte ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 2: + res = nd_strcat_s(Buffer, BufferSize, "word ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 4: + res = nd_strcat_s(Buffer, BufferSize, "dword ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 6: + res = nd_strcat_s(Buffer, BufferSize, "fword ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 8: + res = nd_strcat_s(Buffer, BufferSize, "qword ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 10: + res = nd_strcat_s(Buffer, BufferSize, "tbyte ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 16: + res = nd_strcat_s(Buffer, BufferSize, "xmmword ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 32: + res = nd_strcat_s(Buffer, BufferSize, "ymmword ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case 64: + res = nd_strcat_s(Buffer, BufferSize, "zmmword ptr "); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + default: + break; + } + + // Perpend the segment, only if it is overridden via a prefix. + if (pOp->Info.Memory.HasSeg && Instrux->HasSeg) + { + if (pOp->Info.Memory.Seg >= ND_MAX_SEG_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + if ((ND_CODE_64 != Instrux->DefCode) || (REG_FS == pOp->Info.Memory.Seg) || + (REG_GS == pOp->Info.Memory.Seg)) + { + res = nd_strcat_s(Buffer, BufferSize, gRegSeg[pOp->Info.Memory.Seg]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + + res = nd_strcat_s(Buffer, BufferSize, ":"); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + // Prepend the "[" + res = nd_strcat_s(Buffer, BufferSize, "["); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + + // Base, if any. + if (pOp->Info.Memory.HasBase) + { + if (pOp->Info.Memory.Base >= ND_MAX_GPR_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + switch (pOp->Info.Memory.BaseSize) + { + case ND_SIZE_8BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Memory.Base]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_16BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg16Bit[pOp->Info.Memory.Base]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_32BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg32Bit[pOp->Info.Memory.Base]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_64BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg64Bit[pOp->Info.Memory.Base]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + } + + // Index, if any. Special treatment for VSIB addressing. Also, perpend a "+" if base is present. + if (pOp->Info.Memory.HasIndex) + { + if (pOp->Info.Memory.Index >= (pOp->Info.Memory.IsVsib ? ND_MAX_SSE_REGS : ND_MAX_GPR_REGS)) + { + return ND_STATUS_INVALID_INSTRUX; + } + + if (pOp->Info.Memory.HasBase) + { + res = nd_strcat_s(Buffer, BufferSize, "+"); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + switch (pOp->Info.Memory.IndexSize) + { + case ND_SIZE_8BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_16BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg16Bit[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_32BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg32Bit[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_64BIT: + res = nd_strcat_s(Buffer, BufferSize, gReg64Bit[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_128BIT: + res = nd_strcat_s(Buffer, BufferSize, gRegXmm[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_256BIT: + res = nd_strcat_s(Buffer, BufferSize, gRegYmm[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + case ND_SIZE_512BIT: + res = nd_strcat_s(Buffer, BufferSize, gRegZmm[pOp->Info.Memory.Index]); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + + // If index is present, scale is also present. + if (pOp->Info.Memory.Scale != 1 && !pOp->Info.Memory.IsMib) + { + status = NdSprintf(temp, sizeof(temp), "*%d", pOp->Info.Memory.Scale); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + // Handle displacement. + if (pOp->Info.Memory.HasDisp) + { + uint64_t normDisp, disp; + + disp = pOp->Info.Memory.Disp; + + // If this is direct addressing (O operand) or we don't have base or index, than we don't normalize + // the displacement, since it is used as a direct offset. Note that the second condition also + // includes the RIP-relative case. + if (pOp->Info.Memory.IsDirect || !(pOp->Info.Memory.HasBase || pOp->Info.Memory.HasIndex)) + { + normDisp = disp; + } + else + { + switch (pOp->Info.Memory.DispSize) + { + case 1: + normDisp = ((disp & 0x80) ? ~((uint8_t)disp) + 1UL : disp) & 0xFF; + break; + case 2: + normDisp = ((disp & 0x8000) ? ~((uint16_t)disp) + 1UL : disp) & 0xFFFF; + break; + case 4: + normDisp = ((disp & 0x80000000) ? ~((uint32_t)disp) + 1 : disp) & 0xFFFFFFFF; + break; + default: + normDisp = disp; + break; + } + + // Handle compressed displacement. It is fine to cast the normDisp to uint32_t, as the + // compressed displacement only works with uint8_t displacements. Also, in this phase, + // the normDisp is converted to a positive quantity, so no sign-extension is needed. + if (pOp->Info.Memory.HasCompDisp) + { + normDisp = (uint32_t)normDisp * pOp->Info.Memory.CompDispSize; + } + } + + + // Now displacement. + if (pOp->Info.Memory.HasBase || pOp->Info.Memory.HasIndex) + { + res = nd_strcat_s(Buffer, BufferSize, Instrux->SignDisp ? "-" : "+"); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + if (pOp->Info.Memory.IsRipRel) + { + status = NdSprintf(temp, sizeof(temp), "rel 0x%llx", disp + Rip + Instrux->Length); + } + else + { + uint8_t trimSize; + + trimSize = (Instrux->AddrMode == ND_ADDR_16) ? 2 : ((Instrux->AddrMode == ND_ADDR_32) ? 4 : 8); + + // Truncate the displacement size to the size of the address length. + normDisp = ND_TRIM(trimSize, normDisp); + + status = NdSprintf(temp, sizeof(temp), "0x%llx", normDisp); + } + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // And the ending "]" + res = nd_strcat_s(Buffer, BufferSize, "]"); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + default: + return ND_STATUS_INVALID_INSTRUX; + } + + // Handle memory broadcast. + if (pOp->Decorator.HasBroadcast) + { + status = NdSprintf(temp, sizeof(temp), "{1to%d}", pOp->Decorator.Broadcast.Count); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // Handle masking. + if (pOp->Decorator.HasMask) + { + if (pOp->Decorator.Mask.Msk >= ND_MAX_MSK_REGS) + { + return ND_STATUS_INVALID_INSTRUX; + } + + status = NdSprintf(temp, sizeof(temp), "{%s}", gRegMask[pOp->Decorator.Mask.Msk]); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // Handle zeroing. Note that zeroing without masking is ignored. + if (pOp->Decorator.HasZero && pOp->Decorator.HasMask) + { + res = nd_strcat_s(Buffer, BufferSize, "{z}"); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // Append Suppress All Exceptions decorator. + if (pOp->Decorator.HasSae && !pOp->Decorator.HasEr) + { + // ER implies SAE, so if we have ER, we will list that. + res = nd_strcat_s(Buffer, BufferSize, ", {sae}"); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // Append Embedded Rounding decorator. + if (pOp->Decorator.HasEr) + { + if (Instrux->RoundingMode >= 4) + { + return ND_STATUS_INVALID_INSTRUX; + } + + status = NdSprintf(temp, sizeof(temp), ", {%s-sae}", gEmbeddedRounding[Instrux->RoundingMode]); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdIsInstruxRipRelative +// +bool +NdIsInstruxRipRelative( + const INSTRUX *Instrux + ) +// +// Provided for backwards compatibility with existing code that uses disasm 1.0 +// +{ + if (NULL == Instrux) + { + return false; + } + else + { + return Instrux->IsRipRelative; + } +} + + +// +// NdGetFullAccessMap +// +NDSTATUS +NdGetFullAccessMap( + const INSTRUX *Instrux, + ND_ACCESS_MAP *AccessMap + ) +{ + uint32_t i; + const ND_OPERAND *pOp; + + // pre-init + i = 0; + pOp = NULL; + + // validate + if (NULL == Instrux) + { + return ND_STATUS_INVALID_PARAMETER; + } + + if (NULL == AccessMap) + { + return ND_STATUS_INVALID_PARAMETER; + } + + for (i = 0; i < Instrux->OperandsCount; i++) + { + pOp = &Instrux->Operands[i]; + + if (ND_OP_MEM == pOp->Type) + { + if (pOp->Info.Memory.IsStack) + { + AccessMap->StackAccess |= pOp->Access.Access; + AccessMap->GprAccess[REG_RSP] |= ND_ACCESS_READ|ND_ACCESS_WRITE; + AccessMap->SegAccess[REG_SS] |= ND_ACCESS_READ; + } + else + { + AccessMap->MemAccess |= pOp->Access.Access; + + if (pOp->Info.Memory.HasSeg) + { + AccessMap->SegAccess[pOp->Info.Memory.Seg] |= ND_ACCESS_READ; + } + + if (pOp->Info.Memory.HasBase) + { + AccessMap->GprAccess[pOp->Info.Memory.Base] |= ND_ACCESS_READ; + } + + if (pOp->Info.Memory.HasIndex) + { + if (pOp->Info.Memory.IsVsib) + { + AccessMap->SseAccess[pOp->Info.Memory.Index] |= ND_ACCESS_READ; + } + else + { + AccessMap->GprAccess[pOp->Info.Memory.Index] |= ND_ACCESS_READ; + } + } + } + } + else if (ND_OP_REG == pOp->Type) + { + switch (pOp->Info.Register.Type) + { + case ND_REG_GPR: + { + uint8_t k; + + for (k = 0; k < pOp->Info.Register.Count; k++) + { + AccessMap->GprAccess[pOp->Info.Register.Reg + k] |= pOp->Access.Access; + } + } + break; + case ND_REG_SEG: + AccessMap->SegAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_FPU: + AccessMap->FpuAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_MMX: + AccessMap->MmxAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_SSE: + { + uint8_t k; + + for (k = 0; k < pOp->Info.Register.Count; k++) + { + AccessMap->SseAccess[pOp->Info.Register.Reg + k] |= pOp->Access.Access; + } + } + break; + case ND_REG_CR: + AccessMap->CrAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_DR: + AccessMap->DrAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_TR: + AccessMap->TrAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_BND: + AccessMap->BndAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_MSK: + AccessMap->MskAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_SYS: + AccessMap->SysAccess[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_X87: + AccessMap->X87Access[pOp->Info.Register.Reg] |= pOp->Access.Access; + break; + case ND_REG_FLG: + AccessMap->FlagsAccess |= pOp->Access.Access; + break; + case ND_REG_RIP: + AccessMap->RipAccess |= pOp->Access.Access; + break; + case ND_REG_MXCSR: + AccessMap->MxcsrAccess |= pOp->Access.Access; + break; + case ND_REG_PKRU: + AccessMap->PkruAccess |= pOp->Access.Access; + break; + case ND_REG_SSP: + AccessMap->SspAccess |= pOp->Access.Access; + break; + default: + break; + } + } + else if (ND_OP_BANK == Instrux->Operands[i].Type) + { + uint8_t j; + + // Bank registers access. This needs special handling. Note that LOADALL/LOADALLD is not supported, as + // it is too old and it's not valid since the good old 486. + if (ND_INS_FNSAVE == Instrux->Instruction) + { + for (j = 0; j < ND_MAX_FPU_REGS; j++) + { + AccessMap->FpuAccess[j] |= ND_ACCESS_READ; + } + } + else if (ND_INS_FRSTOR == Instrux->Instruction) + { + for (j = 0; j < ND_MAX_FPU_REGS; j++) + { + AccessMap->FpuAccess[j] |= ND_ACCESS_WRITE; + } + } + + if ((ND_INS_XSAVE == Instrux->Instruction) || (ND_INS_XSAVEOPT == Instrux->Instruction) || + (ND_INS_XSAVES == Instrux->Instruction) || (ND_INS_XSAVEC == Instrux->Instruction)) + { + for (j = 0; j < ND_MAX_SSE_REGS; j++) + { + AccessMap->SseAccess[j] |= ND_ACCESS_READ; + } + } + else if ((ND_INS_XRSTOR == Instrux->Instruction) || (ND_INS_XRSTORS == Instrux->Instruction)) + { + for (j = 0; j < ND_MAX_SSE_REGS; j++) + { + AccessMap->SseAccess[j] |= ND_ACCESS_WRITE; + } + } + } + } + + return ND_STATUS_SUCCESS; +} diff --git a/bddisasm/bddisasm.vcproj b/bddisasm/bddisasm.vcproj new file mode 100644 index 0000000..6902cd7 --- /dev/null +++ b/bddisasm/bddisasm.vcproj @@ -0,0 +1,474 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bddisasm/bddisasm.vcxproj b/bddisasm/bddisasm.vcxproj new file mode 100644 index 0000000..e625ea6 --- /dev/null +++ b/bddisasm/bddisasm.vcxproj @@ -0,0 +1,458 @@ + + + + + DebugKernel + Win32 + + + DebugKernel + x64 + + + Debug + Win32 + + + Debug + x64 + + + ReleaseKernel + Win32 + + + ReleaseKernel + x64 + + + Release + Win32 + + + Release + x64 + + + + {3653AA19-048B-410E-B5C4-FF78E1D84C12} + bddisasm + Win32Proj + 10.0.18362.0 + bddisasm + + + + StaticLibrary + v142 + Unicode + true + + + StaticLibrary + WindowsKernelModeDriver10.0 + Unicode + true + Windows7 + Desktop + false + 1 + + + StaticLibrary + v142 + Unicode + + + StaticLibrary + WindowsKernelModeDriver10.0 + Unicode + Windows7 + Desktop + false + 1 + + + StaticLibrary + v142 + Unicode + true + + + StaticLibrary + WindowsKernelModeDriver10.0 + Unicode + true + Windows7 + Desktop + false + 1 + + + StaticLibrary + v142 + Unicode + + + StaticLibrary + WindowsKernelModeDriver10.0 + Unicode + Windows7 + Desktop + false + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <_ProjectFileVersion>14.0.23107.0 + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + $(SolutionDir)bin\$(Platform)\$(Configuration)\ + $(SolutionDir)_intdir\$(ProjectName)\$(Platform)\$(Configuration)\ + + + + + + + + Disabled + Speed + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + false + true + Default + MultiThreadedDebugDLL + NotUsing + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + false + + + + + + + + + Disabled + Speed + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + false + true + Default + MultiThreadedDebugDLL + NotUsing + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + /kernel /D %(AdditionalOptions) + + + false + + + + + + + + + X64 + + + /D "AMD64" %(AdditionalOptions) + Disabled + true + Speed + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + false + true + true + Default + MultiThreadedDebugDLL + false + NotUsing + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + true + + + x:\Projects-devel\dacia-hg\bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories) + false + + + + + + + + + X64 + + + /kernel /D "AMD64" %(AdditionalOptions) + Disabled + true + Speed + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_LIB;DEBUG;%(PreprocessorDefinitions) + false + true + true + Default + MultiThreadedDebugDLL + false + NotUsing + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + + true + + + x:\Projects-devel\dacia-hg\bin\$(Platform)\$(Configuration);%(AdditionalLibraryDirectories) + Native + false + + + + + + + + + MaxSpeed + true + Speed + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + false + MultiThreadedDLL + true + + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + false + + + false + + + + + + + + + MaxSpeed + true + Speed + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + false + MultiThreadedDLL + true + NotUsing + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + /kernel /D %(AdditionalOptions) + false + + + false + + + + + + + + + X64 + + + /D "AMD64" %(AdditionalOptions) + MaxSpeed + AnySuitable + true + Speed + false + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + false + true + Default + MultiThreaded + false + true + + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + false + + + true + false + + + + + + + + + + + + + X64 + + + /kernel /D "AMD64" %(AdditionalOptions) + MaxSpeed + AnySuitable + true + Speed + false + include;..\inc;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + false + true + Default + MultiThreaded + false + true + NotUsing + Level4 + true + ProgramDatabase + $(SolutionDir)bin\$(Platform)\$(Configuration)\$(ProjectName).pdb + + + + false + + + true + Native + false + + + + + + NotUsing + NotUsing + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/bddisasm/bddisasm.vcxproj.filters b/bddisasm/bddisasm.vcxproj.filters new file mode 100644 index 0000000..5ddd5ae --- /dev/null +++ b/bddisasm/bddisasm.vcxproj.filters @@ -0,0 +1,81 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hpp;hxx;hm;inl;inc;xsd + + + {8f31fedd-353c-4b9c-9e2d-bdb129e1e02b} + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav + + + {5e26c505-e8f5-4e6c-9d54-f20e36b637b8} + + + + + Source Files + + + Source Files + + + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files\public + + + Header Files\public + + + Header Files\public + + + Header Files\public + + + Header Files\public + + + Header Files\public + + + Header Files\public + + + Header Files + + + \ No newline at end of file diff --git a/bddisasm/crt.c b/bddisasm/crt.c new file mode 100644 index 0000000..1aa5889 --- /dev/null +++ b/bddisasm/crt.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#include "include/nd_crt.h" + + +// +// nd_strcat_s +// +char * +nd_strcat_s( + char *dst, + size_t dst_size, + const char *src + ) +{ + char *p; + size_t available; + + p = dst; + available = dst_size; + while (available > 0 && *p != 0) + { + p++; + available--; + } + + if (available == 0) + { + nd_memzero(dst, dst_size); + return NULL; + } + + while ((*p++ = *src++) != 0 && --available > 0); + + if (available == 0) + { + nd_memzero(dst, dst_size); + return NULL; + } + + return dst; +} diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h new file mode 100644 index 0000000..460f5e0 --- /dev/null +++ b/bddisasm/include/instructions.h @@ -0,0 +1,35360 @@ +// +// This file was auto-generated by generate_tables.py from defs.dat. DO NOT MODIFY! +// + +#ifndef _INSTRUCTIONS_H_ +#define _INSTRUCTIONS_H_ + +const ND_INSTRUCTION gInstructions[2554] = +{ + // Pos:0 Instruction:"AAA" Encoding:"0x37"/"" + { + ND_INS_AAA, ND_CAT_DECIMAL, ND_SET_I86, 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_AF, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1 Instruction:"AAD Ib" Encoding:"0xD5 ib"/"I" + { + ND_INS_AAD, ND_CAT_DECIMAL, ND_SET_I86, 1, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:2 Instruction:"AAM Ib" Encoding:"0xD4 ib"/"I" + { + ND_INS_AAM, ND_CAT_DECIMAL, ND_SET_I86, 2, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:3 Instruction:"AAS" Encoding:"0x3F"/"" + { + ND_INS_AAS, ND_CAT_DECIMAL, ND_SET_I86, 3, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_AF, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:4 Instruction:"ADC Eb,Gb" Encoding:"0x10 /r"/"MR" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:5 Instruction:"ADC Ev,Gv" Encoding:"0x11 /r"/"MR" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:6 Instruction:"ADC Gb,Eb" Encoding:"0x12 /r"/"RM" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:7 Instruction:"ADC Gv,Ev" Encoding:"0x13 /r"/"RM" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:8 Instruction:"ADC AL,Ib" Encoding:"0x14 ib"/"I" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:9 Instruction:"ADC rAX,Iz" Encoding:"0x15 iz"/"I" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:10 Instruction:"ADC Eb,Ib" Encoding:"0x80 /2 ib"/"MI" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:11 Instruction:"ADC Ev,Iz" Encoding:"0x81 /2 iz"/"MI" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:12 Instruction:"ADC Ev,Iz" Encoding:"0x82 /2 iz"/"MI" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:13 Instruction:"ADC Ev,Ib" Encoding:"0x83 /2 ib"/"MI" + { + ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:14 Instruction:"ADCX Gy,Ey" Encoding:"0x66 0x0F 0x38 0xF6 /r"/"RM" + { + ND_INS_ADCX, ND_CAT_ARITH, ND_SET_ADX, 5, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, + 0, + 0|REG_RFLAG_CF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:15 Instruction:"ADD Eb,Gb" Encoding:"0x00 /r"/"MR" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:16 Instruction:"ADD Ev,Gv" Encoding:"0x01 /r"/"MR" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:17 Instruction:"ADD Gb,Eb" Encoding:"0x02 /r"/"RM" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:18 Instruction:"ADD Gv,Ev" Encoding:"0x03 /r"/"RM" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:19 Instruction:"ADD AL,Ib" Encoding:"0x04 ib"/"I" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:20 Instruction:"ADD rAX,Iz" Encoding:"0x05 iz"/"I" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:21 Instruction:"ADD Eb,Ib" Encoding:"0x80 /0 ib"/"MI" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:22 Instruction:"ADD Ev,Iz" Encoding:"0x81 /0 iz"/"MI" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:23 Instruction:"ADD Ev,Iz" Encoding:"0x82 /0 iz"/"MI" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:24 Instruction:"ADD Ev,Ib" Encoding:"0x83 /0 ib"/"MI" + { + ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:25 Instruction:"ADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x58 /r"/"RM" + { + ND_INS_ADDPD, ND_CAT_SSE, ND_SET_SSE2, 7, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:26 Instruction:"ADDPS Vps,Wps" Encoding:"NP 0x0F 0x58 /r"/"RM" + { + ND_INS_ADDPS, ND_CAT_SSE, ND_SET_SSE, 8, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:27 Instruction:"ADDSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x58 /r"/"RM" + { + ND_INS_ADDSD, ND_CAT_SSE, ND_SET_SSE2, 9, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:28 Instruction:"ADDSS Vss,Wss" Encoding:"0xF3 0x0F 0x58 /r"/"RM" + { + ND_INS_ADDSS, ND_CAT_SSE, ND_SET_SSE, 10, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:29 Instruction:"ADDSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0xD0 /r"/"RM" + { + ND_INS_ADDSUBPD, ND_CAT_SSE, ND_SET_SSE3, 11, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:30 Instruction:"ADDSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0xD0 /r"/"RM" + { + ND_INS_ADDSUBPS, ND_CAT_SSE, ND_SET_SSE3, 12, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:31 Instruction:"ADOX Gy,Ey" Encoding:"0xF3 0x0F 0x38 0xF6 /r"/"RM" + { + ND_INS_ADOX, ND_CAT_ARITH, ND_SET_ADX, 13, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, + 0, + 0|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:32 Instruction:"AESDEC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDE /r"/"RM" + { + ND_INS_AESDEC, ND_CAT_AES, ND_SET_AES, 14, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:33 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM" + { + ND_INS_AESDECLAST, ND_CAT_AES, ND_SET_AES, 15, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:34 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM" + { + ND_INS_AESENC, ND_CAT_AES, ND_SET_AES, 16, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:35 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM" + { + ND_INS_AESENCLAST, ND_CAT_AES, ND_SET_AES, 17, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:36 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM" + { + ND_INS_AESIMC, ND_CAT_AES, ND_SET_AES, 18, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:37 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI" + { + ND_INS_AESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 19, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:38 Instruction:"ALTINST" Encoding:"0x0F 0x3F"/"" + { + ND_INS_ALTINST, ND_CAT_SYSTEM, ND_SET_CYRIX, 20, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:39 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:40 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:41 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:42 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:43 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:44 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:45 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:46 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:47 Instruction:"AND Ev,Iz" Encoding:"0x82 /4 iz"/"MI" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:48 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI" + { + ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:49 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM" + { + ND_INS_ANDN, ND_CAT_BMI1, ND_SET_BMI1, 22, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + 0|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:50 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM" + { + ND_INS_ANDNPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 23, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:51 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM" + { + ND_INS_ANDNPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 24, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:52 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM" + { + ND_INS_ANDPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 25, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:53 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM" + { + ND_INS_ANDPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 26, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:54 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR" + { + ND_INS_ARPL, ND_CAT_SYSTEM, ND_SET_I286PROT, 27, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_w, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:55 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV" + { + ND_INS_BEXTR, ND_CAT_BMI1, ND_SET_BMI1, 28, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + 0|REG_RFLAG_ZF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:56 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI" + { + ND_INS_BEXTR, ND_CAT_BITBYTE, ND_SET_TBM, 28, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:57 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM" + { + ND_INS_BLCFILL, ND_CAT_BITBYTE, ND_SET_TBM, 29, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:58 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM" + { + ND_INS_BLCI, ND_CAT_BITBYTE, ND_SET_TBM, 30, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:59 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM" + { + ND_INS_BLCIC, ND_CAT_BITBYTE, ND_SET_TBM, 31, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:60 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM" + { + ND_INS_BLCMSK, ND_CAT_BITBYTE, ND_SET_TBM, 32, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:61 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM" + { + ND_INS_BLCS, ND_CAT_BITBYTE, ND_SET_TBM, 33, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:62 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI" + { + ND_INS_BLENDPD, ND_CAT_SSE, ND_SET_SSE4, 34, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:63 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI" + { + ND_INS_BLENDPS, ND_CAT_SSE, ND_SET_SSE4, 35, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:64 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM" + { + ND_INS_BLENDVPD, ND_CAT_SSE, ND_SET_SSE4, 36, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:65 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM" + { + ND_INS_BLENDVPS, ND_CAT_SSE, ND_SET_SSE4, 37, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:66 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM" + { + ND_INS_BLSFILL, ND_CAT_BITBYTE, ND_SET_TBM, 38, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:67 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM" + { + ND_INS_BLSI, ND_CAT_BMI1, ND_SET_BMI1, 39, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:68 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM" + { + ND_INS_BLSIC, ND_CAT_BITBYTE, ND_SET_TBM, 40, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:69 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM" + { + ND_INS_BLSMSK, ND_CAT_BMI1, ND_SET_BMI1, 41, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|REG_RFLAG_ZF|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:70 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM" + { + ND_INS_BLSR, ND_CAT_BMI1, ND_SET_BMI1, 42, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:71 Instruction:"BNDCL rBl,Ey" Encoding:"0xF3 0x0F 0x1A /r"/"RM" + { + ND_INS_BNDCL, ND_CAT_MPX, ND_SET_MPX, 43, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:72 Instruction:"BNDCN rBl,Ey" Encoding:"0xF2 0x0F 0x1B /r"/"RM" + { + ND_INS_BNDCN, ND_CAT_MPX, ND_SET_MPX, 44, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:73 Instruction:"BNDCU rBl,Ey" Encoding:"0xF2 0x0F 0x1A /r"/"RM" + { + ND_INS_BNDCU, ND_CAT_MPX, ND_SET_MPX, 45, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:74 Instruction:"BNDLDX rBl,Mmib" Encoding:"0x0F 0x1A /r:mem mib"/"RM" + { + ND_INS_BNDLDX, ND_CAT_MPX, ND_SET_MPX, 46, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_mib, ND_OPF_R, 0, 0), + }, + + // Pos:75 Instruction:"BNDMK rBl,My" Encoding:"0xF3 0x0F 0x1B /r:mem"/"RM" + { + ND_INS_BNDMK, ND_CAT_MPX, ND_SET_MPX, 47, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_MODRM, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:76 Instruction:"BNDMOV rBl,mBl" Encoding:"0x66 0x0F 0x1A /r"/"RM" + { + ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 48, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_MODRM, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_W, 0, 0), + OP(ND_OPT_mB, ND_OPS_l, ND_OPF_R, 0, 0), + }, + + // Pos:77 Instruction:"BNDMOV mBl,rBl" Encoding:"0x66 0x0F 0x1B /r"/"MR" + { + ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 48, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_MODRM, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_mB, ND_OPS_l, ND_OPF_W, 0, 0), + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_R, 0, 0), + }, + + // Pos:78 Instruction:"BNDSTX Mmib,rBl" Encoding:"0x0F 0x1B /r:mem mib"/"MR" + { + ND_INS_BNDSTX, ND_CAT_MPX, ND_SET_MPX, 49, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_mib, ND_OPF_W, 0, 0), + OP(ND_OPT_rB, ND_OPS_l, ND_OPF_R, 0, 0), + }, + + // Pos:79 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM" + { + ND_INS_BOUND, ND_CAT_INTERRUPT, ND_SET_I186, 50, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_a, ND_OPF_R, 0, 0), + }, + + // Pos:80 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM" + { + ND_INS_BSF, ND_CAT_I386, ND_SET_I386, 51, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:81 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM" + { + ND_INS_BSR, ND_CAT_BITBYTE, ND_SET_I386, 52, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:82 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:83 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:84 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:85 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:86 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:87 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:88 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:89 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O" + { + ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:90 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR" + { + ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 54, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:91 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI" + { + ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 54, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:92 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI" + { + ND_INS_BTC, ND_CAT_BITBYTE, ND_SET_I386, 55, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:93 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR" + { + ND_INS_BTC, ND_CAT_I386, ND_SET_I386, 55, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:94 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR" + { + ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 56, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:95 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI" + { + ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 56, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:96 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR" + { + ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 57, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:97 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI" + { + ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 57, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:98 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV" + { + ND_INS_BZHI, ND_CAT_BMI2, ND_SET_BMI2, 58, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:99 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D" + { + ND_INS_CALLNR, ND_CAT_CALL, ND_SET_I86, 59, + ND_MOD_ANY, + ND_PREF_BND, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:100 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M" + { + ND_INS_CALLNI, ND_CAT_CALL, ND_SET_I86, 59, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_DNT, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:101 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D" + { + ND_INS_CALLFD, ND_CAT_CALL, ND_SET_I86, 60, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_A, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:102 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M" + { + ND_INS_CALLFI, ND_CAT_CALL, ND_SET_I86, 60, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:103 Instruction:"CBW" Encoding:"ds16 0x98"/"" + { + ND_INS_CBW, ND_CAT_CONVERT, ND_SET_I386, 61, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:104 Instruction:"CDQ" Encoding:"ds32 0x99"/"" + { + ND_INS_CDQ, ND_CAT_CONVERT, ND_SET_I386, 62, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:105 Instruction:"CDQE" Encoding:"ds64 0x98"/"" + { + ND_INS_CDQE, ND_CAT_CONVERT, ND_SET_I386, 63, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:106 Instruction:"CL1INVMB" Encoding:"0x0F 0x0A"/"" + { + ND_INS_CL1INVMB, ND_CAT_SYSTEM, ND_SET_SCC, 64, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:107 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/"" + { + ND_INS_CLAC, ND_CAT_SMAP, ND_SET_SMAP, 65, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, + 0, + 0, + 0, + 0|REG_RFLAG_AC, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:108 Instruction:"CLC" Encoding:"0xF8"/"" + { + ND_INS_CLC, ND_CAT_FLAGOP, ND_SET_I86, 66, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0|REG_RFLAG_CF, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:109 Instruction:"CLD" Encoding:"0xFC"/"" + { + ND_INS_CLD, ND_CAT_FLAGOP, ND_SET_I86, 67, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0|REG_RFLAG_DF, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:110 Instruction:"CLDEMOTE Mcl" Encoding:"NP 0x0F 0x1C /0:mem"/"M" + { + ND_INS_CLDEMOTE, ND_CAT_CLDEMOTE, ND_SET_CLDEMOTE, 68, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLDEMOTE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_W, 0, 0), + }, + + // Pos:111 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M" + { + ND_INS_CLEVICT0, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 69, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_N, 0, 0), + }, + + // Pos:112 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M" + { + ND_INS_CLEVICT1, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 70, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_N, 0, 0), + }, + + // Pos:113 Instruction:"CLFLUSH Mcl" Encoding:"NP 0x0F 0xAE /7:mem"/"M" + { + ND_INS_CLFLUSH, ND_CAT_MISC, ND_SET_CLFSH, 71, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSH, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:114 Instruction:"CLFLUSHOPT Mcl" Encoding:"0x66 0x0F 0xAE /7:mem"/"M" + { + ND_INS_CLFLUSHOPT, ND_CAT_MISC, ND_SET_CLFSHOPT, 72, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSHOPT, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:115 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/"" + { + ND_INS_CLGI, ND_CAT_SYSTEM, ND_SET_SVM, 73, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + }, + + // Pos:116 Instruction:"CLI" Encoding:"0xFA"/"" + { + ND_INS_CLI, ND_CAT_FLAGOP, ND_SET_I86, 74, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0|REG_RFLAG_IF, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:117 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M" + { + ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET, 75, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_RW, 0, 0), + }, + + // Pos:118 Instruction:"CLTS" Encoding:"0x0F 0x06"/"" + { + ND_INS_CLTS, ND_CAT_SYSTEM, ND_SET_I286REAL, 76, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:119 Instruction:"CLWB Mcl" Encoding:"0x66 0x0F 0xAE /6:mem"/"M" + { + ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 77, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLWB, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_W, 0, 0), + }, + + // Pos:120 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/"" + { + ND_INS_CLZERO, ND_CAT_MISC, ND_SET_CLZERO, 78, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:121 Instruction:"CMC" Encoding:"0xF5"/"" + { + ND_INS_CMC, ND_CAT_FLAGOP, ND_SET_I86, 79, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:122 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 80, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:123 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 81, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:124 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 82, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:125 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 83, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:126 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 84, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:127 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 85, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:128 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 86, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:129 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 87, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:130 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 88, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:131 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 89, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:132 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 90, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:133 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 91, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:134 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 92, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:135 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 93, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:136 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 94, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:137 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM" + { + ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 95, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:138 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:139 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:140 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:141 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:142 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:143 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:144 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:145 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:146 Instruction:"CMP Ev,Iz" Encoding:"0x82 /7 iz"/"MI" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:147 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI" + { + ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:148 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI" + { + ND_INS_CMPPD, ND_CAT_SSE, ND_SET_SSE2, 97, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:149 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI" + { + ND_INS_CMPPS, ND_CAT_SSE, ND_SET_SSE, 98, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:150 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 99, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:151 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 99, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:152 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI" + { + ND_INS_CMPSD, ND_CAT_SSE, ND_SET_SSE2, 100, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:153 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 100, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:154 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 100, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:155 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 101, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:156 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 101, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:157 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI" + { + ND_INS_CMPSS, ND_CAT_SSE, ND_SET_SSE, 102, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:158 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 103, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:159 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/"" + { + ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 103, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:160 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR" + { + ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 104, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:161 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR" + { + ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 104, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:162 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M" + { + ND_INS_CMPXCHG16B, ND_CAT_SEMAPHORE, ND_SET_CMPXCHG16B, 105, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:163 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M" + { + ND_INS_CMPXCHG8B, ND_CAT_SEMAPHORE, ND_SET_PENTIUMREAL, 106, + ND_MOD_ANY, + ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:164 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM" + { + ND_INS_COMISD, ND_CAT_SSE2, ND_SET_SSE2, 107, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:165 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM" + { + ND_INS_COMISS, ND_CAT_SSE, ND_SET_SSE, 108, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:166 Instruction:"CPUID" Encoding:"0x0F 0xA2"/"" + { + ND_INS_CPUID, ND_CAT_MISC, ND_SET_I486REAL, 109, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:167 Instruction:"CPU_READ" Encoding:"0x0F 0x3D"/"" + { + ND_INS_CPU_READ, ND_CAT_SYSTEM, ND_SET_CYRIX, 110, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:168 Instruction:"CPU_WRITE" Encoding:"0x0F 0x3C"/"" + { + ND_INS_CPU_WRITE, ND_CAT_SYSTEM, ND_SET_CYRIX, 111, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:169 Instruction:"CQO" Encoding:"ds64 0x99"/"" + { + ND_INS_CQO, ND_CAT_CONVERT, ND_SET_I386, 112, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:170 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM" + { + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:171 Instruction:"CRC32 Gy,Eb" Encoding:"0x66 0xF2 0x0F 0x38 0xF0 /r"/"RM" + { + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:172 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM" + { + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:173 Instruction:"CRC32 Gy,Ev" Encoding:"0x66 0xF2 0x0F 0x38 0xF1 /r"/"RM" + { + ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:174 Instruction:"CVTDQ2PD Vx,Wpd" Encoding:"0xF3 0x0F 0xE6 /r"/"RM" + { + ND_INS_CVTDQ2PD, ND_CAT_CONVERT, ND_SET_SSE2, 114, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:175 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM" + { + ND_INS_CVTDQ2PS, ND_CAT_CONVERT, ND_SET_SSE2, 115, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:176 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM" + { + ND_INS_CVTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 116, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:177 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM" + { + ND_INS_CVTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 117, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:178 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM" + { + ND_INS_CVTPD2PS, ND_CAT_CONVERT, ND_SET_SSE2, 118, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:179 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM" + { + ND_INS_CVTPI2PD, ND_CAT_CONVERT, ND_SET_SSE2, 119, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:180 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM" + { + ND_INS_CVTPI2PS, ND_CAT_CONVERT, ND_SET_SSE, 120, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:181 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM" + { + ND_INS_CVTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 121, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:182 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM" + { + ND_INS_CVTPS2PD, ND_CAT_CONVERT, ND_SET_SSE2, 122, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:183 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM" + { + ND_INS_CVTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 123, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:184 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM" + { + ND_INS_CVTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 124, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:185 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM" + { + ND_INS_CVTSD2SS, ND_CAT_CONVERT, ND_SET_SSE2, 125, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:186 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM" + { + ND_INS_CVTSI2SD, ND_CAT_CONVERT, ND_SET_SSE2, 126, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:187 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM" + { + ND_INS_CVTSI2SS, ND_CAT_CONVERT, ND_SET_SSE, 127, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:188 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM" + { + ND_INS_CVTSS2SD, ND_CAT_CONVERT, ND_SET_SSE2, 128, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:189 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM" + { + ND_INS_CVTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 129, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:190 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM" + { + ND_INS_CVTTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 130, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:191 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM" + { + ND_INS_CVTTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 131, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:192 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM" + { + ND_INS_CVTTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 132, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:193 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM" + { + ND_INS_CVTTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 133, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:194 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM" + { + ND_INS_CVTTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 134, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:195 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM" + { + ND_INS_CVTTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 135, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:196 Instruction:"CWD" Encoding:"ds16 0x99"/"" + { + ND_INS_CWD, ND_CAT_CONVERT, ND_SET_I386, 136, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:197 Instruction:"CWDE" Encoding:"ds32 0x98"/"" + { + ND_INS_CWDE, ND_CAT_CONVERT, ND_SET_I386, 137, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:198 Instruction:"DAA" Encoding:"0x27"/"" + { + ND_INS_DAA, ND_CAT_DECIMAL, ND_SET_I86, 138, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0|REG_RFLAG_CF|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF, + 0|REG_RFLAG_OF, + 0|REG_RFLAG_OF, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:199 Instruction:"DAS" Encoding:"0x2F"/"" + { + ND_INS_DAS, ND_CAT_DECIMAL, ND_SET_I86, 139, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0|REG_RFLAG_CF|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_OF, + 0|REG_RFLAG_OF, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:200 Instruction:"DEC Zv" Encoding:"0x48"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:201 Instruction:"DEC Zv" Encoding:"0x49"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:202 Instruction:"DEC Zv" Encoding:"0x4A"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:203 Instruction:"DEC Zv" Encoding:"0x4B"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:204 Instruction:"DEC Zv" Encoding:"0x4C"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:205 Instruction:"DEC Zv" Encoding:"0x4D"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:206 Instruction:"DEC Zv" Encoding:"0x4E"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:207 Instruction:"DEC Zv" Encoding:"0x4F"/"O" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:208 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:209 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M" + { + ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:210 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M" + { + ND_INS_DELAY, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 141, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:211 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M" + { + ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 142, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:212 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M" + { + ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 142, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:213 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM" + { + ND_INS_DIVPD, ND_CAT_SSE, ND_SET_SSE2, 143, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:214 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM" + { + ND_INS_DIVPS, ND_CAT_SSE, ND_SET_SSE, 144, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:215 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM" + { + ND_INS_DIVSD, ND_CAT_SSE, ND_SET_SSE2, 145, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:216 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM" + { + ND_INS_DIVSS, ND_CAT_SSE, ND_SET_SSE, 146, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:217 Instruction:"DMINT" Encoding:"0x0F 0x39"/"" + { + ND_INS_DMINT, ND_CAT_SYSTEM, ND_SET_CYRIX, 147, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:218 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI" + { + ND_INS_DPPD, ND_CAT_SSE, ND_SET_SSE4, 148, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:219 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI" + { + ND_INS_DPPS, ND_CAT_SSE, ND_SET_SSE4, 149, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:220 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/"" + { + ND_INS_EMMS, ND_CAT_MMX, ND_SET_MMX, 150, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MMX, + 0, + 0, + 0, + 0, + }, + + // Pos:221 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/"" + { + ND_INS_ENCLS, ND_CAT_SGX, ND_SET_SGX, 151, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + }, + + // Pos:222 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/"" + { + ND_INS_ENCLU, ND_CAT_SGX, ND_SET_SGX, 152, + ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + }, + + // Pos:223 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/"" + { + ND_INS_ENCLV, ND_CAT_SGX, ND_SET_SGX, 153, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CRW, 0, 0), + }, + + // Pos:224 Instruction:"ENDBR32" Encoding:"a0xF3 0x0F 0x1E /0xFB"/"" + { + ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET, 154, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + }, + + // Pos:225 Instruction:"ENDBR64" Encoding:"a0xF3 0x0F 0x1E /0xFA"/"" + { + ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET, 155, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + }, + + // Pos:226 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M" + { + ND_INS_ENQCMD, ND_CAT_ENQCMD, ND_SET_ENQCMD, 156, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, + 0, + 0|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_rM, ND_OPS_unknown, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:227 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M" + { + ND_INS_ENQCMDS, ND_CAT_ENQCMD, ND_SET_ENQCMD, 157, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, + 0, + 0|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_rM, ND_OPS_unknown, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:228 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II" + { + ND_INS_ENTER, ND_CAT_MISC, ND_SET_I186, 158, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:229 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI" + { + ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 159, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:230 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII" + { + ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 160, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:231 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM" + { + ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 160, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:232 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/"" + { + ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 161, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:233 Instruction:"FABS" Encoding:"0xD9 /0xE1"/"" + { + ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 162, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:234 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M" + { + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:235 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M" + { + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:236 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M" + { + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:237 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M" + { + ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:238 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M" + { + ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 164, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:239 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M" + { + ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 165, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_fa, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:240 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M" + { + ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 166, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fa, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:241 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/"" + { + ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 167, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:242 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M" + { + ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 168, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:243 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M" + { + ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 169, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:244 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M" + { + ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 170, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:245 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M" + { + ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 171, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:246 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M" + { + ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 172, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:247 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M" + { + ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 173, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:248 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M" + { + ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 174, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:249 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M" + { + ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 175, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_CW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:250 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M" + { + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:251 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M" + { + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:252 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M" + { + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:253 Instruction:"FCOM ST(i),ST(0)" Encoding:"0xDC /2:reg"/"M" + { + ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:254 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M" + { + ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 177, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_OF, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:255 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M" + { + ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 178, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_OF, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:256 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M" + { + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:257 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M" + { + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:258 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M" + { + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:259 Instruction:"FCOMP ST(i),ST(0)" Encoding:"0xDC /3:reg"/"M" + { + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:260 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M" + { + ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:261 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/"" + { + ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 180, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:262 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/"" + { + ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 181, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:263 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/"" + { + ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 182, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:264 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M" + { + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:265 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M" + { + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:266 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M" + { + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:267 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M" + { + ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:268 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M" + { + ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 184, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:269 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M" + { + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:270 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M" + { + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:271 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M" + { + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:272 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M" + { + ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:273 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M" + { + ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 186, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:274 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/"" + { + ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 187, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + }, + + // Pos:275 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M" + { + ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 188, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:276 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M" + { + ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 189, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:277 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M" + { + ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 190, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:278 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M" + { + ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 190, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:279 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M" + { + ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 191, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:280 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M" + { + ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 191, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:281 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M" + { + ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 192, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:282 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M" + { + ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 192, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:283 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M" + { + ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:284 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M" + { + ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:285 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M" + { + ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 194, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:286 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M" + { + ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 194, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:287 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M" + { + ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:288 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M" + { + ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:289 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M" + { + ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 195, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:290 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M" + { + ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 196, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:291 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M" + { + ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 196, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:292 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/"" + { + ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 197, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:293 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M" + { + ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 198, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:294 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M" + { + ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 198, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:295 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M" + { + ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 199, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:296 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M" + { + ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 199, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:297 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M" + { + ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 199, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:298 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M" + { + ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 200, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:299 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M" + { + ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 200, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:300 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M" + { + ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 200, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:301 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M" + { + ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 201, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:302 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M" + { + ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 201, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:303 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M" + { + ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 202, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:304 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M" + { + ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 202, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:305 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M" + { + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:306 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M" + { + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:307 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M" + { + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:308 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M" + { + ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:309 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/"" + { + ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 204, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:310 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M" + { + ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 205, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:311 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M" + { + ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 206, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fe, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:312 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/"" + { + ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 207, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:313 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/"" + { + ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 208, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:314 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/"" + { + ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 209, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:315 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/"" + { + ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 210, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:316 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/"" + { + ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 211, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:317 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/"" + { + ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 212, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:318 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M" + { + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:319 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M" + { + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:320 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M" + { + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:321 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M" + { + ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:322 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M" + { + ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 214, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:323 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/"" + { + ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 215, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:324 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/"" + { + ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 216, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:325 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/"" + { + ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 217, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:326 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/"" + { + ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 218, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:327 Instruction:"FNOP" Encoding:"0xDB /0xE0"/"" + { + ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 218, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:328 Instruction:"FNOP" Encoding:"0xDB /0xE4"/"" + { + ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 218, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:329 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M" + { + ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 219, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fs, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:330 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M" + { + ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 220, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:331 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M" + { + ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 221, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fe, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:332 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M" + { + ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 222, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:333 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/"" + { + ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 222, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:334 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/"" + { + ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 223, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:335 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/"" + { + ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 224, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:336 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/"" + { + ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 225, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:337 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/"" + { + ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 226, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:338 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/"" + { + ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 227, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:339 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/"" + { + ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 228, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:340 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M" + { + ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 229, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fs, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:341 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/"" + { + ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 230, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:342 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/"" + { + ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 231, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:343 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/"" + { + ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 232, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:344 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/"" + { + ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 233, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:345 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M" + { + ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:346 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M" + { + ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:347 Instruction:"FST ST(0),ST(i)" Encoding:"0xDD /2:reg"/"M" + { + ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:348 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/"" + { + ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 235, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_W, 0, 0), + }, + + // Pos:349 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M" + { + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:350 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M" + { + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:351 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M" + { + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:352 Instruction:"FSTP ST(0),ST(i)" Encoding:"0xDD /3:reg"/"M" + { + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:353 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M" + { + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:354 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M" + { + ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:355 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M" + { + ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 237, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:356 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/"" + { + ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 238, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_W, 0, 0), + }, + + // Pos:357 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M" + { + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:358 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M" + { + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:359 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M" + { + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:360 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M" + { + ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:361 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M" + { + ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 240, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:362 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M" + { + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:363 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M" + { + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:364 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M" + { + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:365 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M" + { + ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:366 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M" + { + ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 242, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:367 Instruction:"FTST" Encoding:"0xD9 /0xE4"/"" + { + ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 243, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:368 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M" + { + ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 244, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:369 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M" + { + ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 245, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_OF, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:370 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M" + { + ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 246, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_OF, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:371 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M" + { + ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 247, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:372 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/"" + { + ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 248, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:373 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/"" + { + ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 249, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:374 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M" + { + ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 250, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_RW, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:375 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M" + { + ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 250, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:376 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M" + { + ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 250, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), + OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_W, 0, 0), + OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:377 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M" + { + ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 251, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_rx, ND_OPF_R, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:378 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M" + { + ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 252, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_rx, ND_OPF_W, 0, 0), + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:379 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/"" + { + ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 253, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:380 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/"" + { + ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 254, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:381 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/"" + { + ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 255, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:382 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/"" + { + ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 256, + ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:383 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI" + { + ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 257, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:384 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI" + { + ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 258, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:385 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM" + { + ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 259, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:386 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM" + { + ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 260, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:387 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM" + { + ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 261, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:388 Instruction:"HLT" Encoding:"0xF4"/"" + { + ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 262, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:389 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM" + { + ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 263, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:390 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM" + { + ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 264, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:391 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M" + { + ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 265, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:392 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M" + { + ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 265, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:393 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM" + { + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:394 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI" + { + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:395 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI" + { + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:396 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M" + { + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:397 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M" + { + ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:398 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I" + { + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 267, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:399 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I" + { + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 267, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_z, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:400 Instruction:"IN AL,DX" Encoding:"0xEC"/"" + { + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 267, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:401 Instruction:"IN eAX,DX" Encoding:"0xED"/"" + { + ND_INS_IN, ND_CAT_IO, ND_SET_I86, 267, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_z, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:402 Instruction:"INC Zv" Encoding:"0x40"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:403 Instruction:"INC Zv" Encoding:"0x41"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:404 Instruction:"INC Zv" Encoding:"0x42"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:405 Instruction:"INC Zv" Encoding:"0x43"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:406 Instruction:"INC Zv" Encoding:"0x44"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:407 Instruction:"INC Zv" Encoding:"0x45"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:408 Instruction:"INC Zv" Encoding:"0x46"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:409 Instruction:"INC Zv" Encoding:"0x47"/"O" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:410 Instruction:"INC Eb" Encoding:"0xFE /0"/"M" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:411 Instruction:"INC Ev" Encoding:"0xFF /0"/"M" + { + ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:412 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M" + { + ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET, 269, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SSP, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:413 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M" + { + ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET, 270, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SSP, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:414 Instruction:"INSB Yb,DX" Encoding:"0x6C"/"" + { + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 271, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:415 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/"" + { + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 271, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:416 Instruction:"INSD Yz,DX" Encoding:"0x6D"/"" + { + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 272, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:417 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/"" + { + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 272, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:418 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI" + { + ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 273, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:419 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI" + { + ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 273, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:420 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII" + { + ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 274, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:421 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM" + { + ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 274, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:422 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/"" + { + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 275, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:423 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/"" + { + ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 275, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:424 Instruction:"INT Ib" Encoding:"0xCD ib"/"I" + { + ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 276, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_VM, + 0|REG_RFLAG_VM|REG_RFLAG_IF|REG_RFLAG_NT|REG_RFLAG_AC|REG_RFLAG_RF|REG_RFLAG_TF, + 0, + 0, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:425 Instruction:"INT1" Encoding:"0xF1"/"" + { + ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 277, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_VM, + 0|REG_RFLAG_VM|REG_RFLAG_IF|REG_RFLAG_NT|REG_RFLAG_AC|REG_RFLAG_RF|REG_RFLAG_TF, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:426 Instruction:"INT3" Encoding:"0xCC"/"" + { + ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 278, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_VM, + 0|REG_RFLAG_VM|REG_RFLAG_IF|REG_RFLAG_NT|REG_RFLAG_AC|REG_RFLAG_RF|REG_RFLAG_TF, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:427 Instruction:"INTO" Encoding:"0xCE"/"" + { + ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 279, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_VM, + 0|REG_RFLAG_VM|REG_RFLAG_IF|REG_RFLAG_NT|REG_RFLAG_AC|REG_RFLAG_RF|REG_RFLAG_TF, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:428 Instruction:"INVD" Encoding:"0x0F 0x08"/"" + { + ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 280, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:429 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM" + { + ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 281, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:430 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M" + { + ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 282, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:431 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/"" + { + ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 283, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:432 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/"" + { + ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 284, + ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:433 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM" + { + ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 285, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_INVPCID, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:434 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM" + { + ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 286, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:435 Instruction:"IRETD" Encoding:"ds32 0xCF"/"" + { + ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 287, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:436 Instruction:"IRETQ" Encoding:"ds64 0xCF"/"" + { + ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 288, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:437 Instruction:"IRETW" Encoding:"ds16 0xCF"/"" + { + ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 289, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:438 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 290, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:439 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 290, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:440 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 291, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:441 Instruction:"JC Jb" Encoding:"0x72 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 291, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:442 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D" + { + ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 292, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:443 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D" + { + ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 293, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:444 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 294, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:445 Instruction:"JL Jb" Encoding:"0x7C cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 294, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:446 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 295, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:447 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 295, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:448 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D" + { + ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 296, + ND_MOD_ANY, + ND_PREF_BND, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:449 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D" + { + ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 296, + ND_MOD_ANY, + ND_PREF_BND, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:450 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M" + { + ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 296, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_DNT, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:451 Instruction:"JMPE Ev" Encoding:"0x0F 0x00 /6"/"M" + { + ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 297, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:452 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D" + { + ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 297, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:453 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D" + { + ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 298, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_A, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:454 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M" + { + ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 298, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:455 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 299, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:456 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 299, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:457 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 300, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:458 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 300, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:459 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:460 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:461 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:462 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:463 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:464 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:465 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:466 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:467 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:468 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:469 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:470 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:471 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:472 Instruction:"JO Jb" Encoding:"0x70 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:473 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:474 Instruction:"JP Jb" Encoding:"0x7A cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:475 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D" + { + ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 309, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:476 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:477 Instruction:"JS Jb" Encoding:"0x78 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:478 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 311, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:479 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D" + { + ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 311, + ND_MOD_ANY, + ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:480 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM" + { + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 312, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:481 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM" + { + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 313, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:482 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM" + { + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 314, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:483 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM" + { + ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 315, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:484 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM" + { + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 316, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:485 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM" + { + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 317, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:486 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM" + { + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 318, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:487 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM" + { + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 319, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:488 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM" + { + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 320, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:489 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM" + { + ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 321, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:490 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM" + { + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 322, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:491 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM" + { + ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 323, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:492 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM" + { + ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 324, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:493 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM" + { + ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 325, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:494 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:495 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:496 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:497 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:498 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:499 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:500 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:501 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:502 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:503 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:504 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:505 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:506 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:507 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:508 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:509 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:510 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:511 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:512 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:513 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM" + { + ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:514 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM" + { + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 330, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:515 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM" + { + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 331, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:516 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM" + { + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 332, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:517 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM" + { + ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 333, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:518 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM" + { + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 334, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:519 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM" + { + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 335, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:520 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM" + { + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 336, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:521 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM" + { + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 337, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:522 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM" + { + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 338, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:523 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM" + { + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 339, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:524 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM" + { + ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 340, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:525 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM" + { + ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 341, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:526 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 342, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:527 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 343, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:528 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 344, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:529 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 345, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:530 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 346, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:531 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 347, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:532 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 348, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:533 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI" + { + ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 349, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:534 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM" + { + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 350, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:535 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM" + { + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 351, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:536 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM" + { + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 352, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:537 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM" + { + ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 353, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:538 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM" + { + ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 354, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:539 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM" + { + ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 355, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:540 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM" + { + ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 356, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:541 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM" + { + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 357, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:542 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM" + { + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 358, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:543 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM" + { + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 359, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:544 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM" + { + ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 360, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:545 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM" + { + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:546 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM" + { + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 362, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:547 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM" + { + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 363, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:548 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM" + { + ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 364, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:549 Instruction:"LAHF" Encoding:"0x9F"/"" + { + ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 365, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:550 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM" + { + ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 366, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:551 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM" + { + ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 366, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_CW, 0, 0), + OP(ND_OPT_R, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:552 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM" + { + ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 367, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:553 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M" + { + ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 368, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:554 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM" + { + ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 369, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_z, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_DS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:555 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M" + { + ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 370, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E1, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_oq, ND_OPF_R, 0, 0), + }, + + // Pos:556 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM" + { + ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 371, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_0, ND_OPF_N, 0, 0), + }, + + // Pos:557 Instruction:"LEAVE" Encoding:"0xC9"/"" + { + ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 372, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rBP, ND_OPS_ssz, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rSP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:558 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM" + { + ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 373, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_z, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_ES, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:559 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/"" + { + ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 374, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + }, + + // Pos:560 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM" + { + ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 375, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_FS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:561 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M" + { + ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 376, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), + OP(ND_OPT_SYS_GDTR, ND_OPS_s, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:562 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM" + { + ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 377, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_GS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:563 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M" + { + ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 378, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), + OP(ND_OPT_SYS_IDTR, ND_OPS_s, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:564 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M" + { + ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 379, + ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:565 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M" + { + ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 380, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:566 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M" + { + ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 381, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:567 Instruction:"LOADALL" Encoding:"0x0F 0x05"/"" + { + ND_INS_LOADALL, ND_CAT_UNDOC, ND_SET_I486REAL, 382, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:568 Instruction:"LOADALLD" Encoding:"0x0F 0x07"/"" + { + ND_INS_LOADALLD, ND_CAT_UNDOC, ND_SET_I486REAL, 383, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:569 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 384, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:570 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 384, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:571 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 385, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:572 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 385, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:573 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 386, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:574 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 386, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:575 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 387, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:576 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/"" + { + ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 387, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:577 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D" + { + ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 388, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:578 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D" + { + ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 389, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:579 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D" + { + ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 390, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_J, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:580 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM" + { + ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 391, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:581 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM" + { + ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 391, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_R, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:582 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM" + { + ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 392, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:583 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M" + { + ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 393, + ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:584 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI" + { + ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 394, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:585 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI" + { + ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 395, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:586 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM" + { + ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 396, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LZCNT, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:587 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM" + { + ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 397, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_rDI, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:588 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM" + { + ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 398, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_N, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_rDI, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:589 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM" + { + ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 399, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:590 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM" + { + ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 400, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:591 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM" + { + ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 401, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:592 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM" + { + ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 402, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:593 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/"" + { + ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 403, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MCOMMIT, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:594 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/"" + { + ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 404, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + }, + + // Pos:595 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM" + { + ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 405, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:596 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM" + { + ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 406, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:597 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM" + { + ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 407, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:598 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM" + { + ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 408, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:599 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/"" + { + ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 409, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:600 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/"" + { + ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 410, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:601 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/"" + { + ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 411, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:602 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR" + { + ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_C, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:603 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR" + { + ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_D, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:604 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM" + { + ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_C, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:605 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM" + { + ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_D, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:606 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR" + { + ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_T, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:607 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM" + { + ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_T, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:608 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:609 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:610 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:611 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:612 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_S, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:613 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_S, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:614 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_S, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:615 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_S, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:616 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_O, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:617 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_O, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:618 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_O, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:619 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_O, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:620 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:621 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:622 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:623 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:624 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:625 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:626 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:627 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:628 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:629 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:630 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:631 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:632 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:633 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:634 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:635 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:636 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:637 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI" + { + ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_MOD_ANY, + ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + }, + + // Pos:638 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM" + { + ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 413, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:639 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR" + { + ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 413, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:640 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM" + { + ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 414, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:641 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR" + { + ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 414, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:642 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM" + { + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:643 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM" + { + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:644 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR" + { + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:645 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR" + { + ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:646 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM" + { + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 416, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:647 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM" + { + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 416, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:648 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR" + { + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 416, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_P, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:649 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR" + { + ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 416, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:650 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM" + { + ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 417, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:651 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M" + { + ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 418, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIR64B, + 0, + 0, + 0, + 0, + OP(ND_OPT_rM, ND_OPS_oq, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_oq, ND_OPF_R, 0, 0), + }, + + // Pos:652 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR" + { + ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 419, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIRI, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:653 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM" + { + ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 420, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:654 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM" + { + ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 421, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:655 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR" + { + ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 421, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:656 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM" + { + ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 422, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:657 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR" + { + ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 422, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:658 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM" + { + ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 423, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:659 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR" + { + ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 423, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:660 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM" + { + ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 424, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:661 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR" + { + ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 424, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:662 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM" + { + ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:663 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM" + { + ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 426, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:664 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR" + { + ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 426, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:665 Instruction:"MOVLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM" + { + ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 427, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:666 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR" + { + ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 427, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:667 Instruction:"MOVMSKPD Gd,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM" + { + ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 428, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:668 Instruction:"MOVMSKPS Gd,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM" + { + ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 429, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:669 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR" + { + ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 430, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:670 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM" + { + ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 431, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:671 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR" + { + ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 432, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:672 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR" + { + ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 433, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:673 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR" + { + ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 434, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:674 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR" + { + ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 435, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_P, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:675 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR" + { + ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 436, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:676 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR" + { + ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 437, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:677 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:678 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:679 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:680 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_P, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:681 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:682 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:683 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_P, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:684 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR" + { + ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:685 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM" + { + ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_N, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:686 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 440, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:687 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 440, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:688 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" + { + ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 441, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:689 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" + { + ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 441, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:690 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:691 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:692 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" + { + ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 442, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:693 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" + { + ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 443, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:694 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 444, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:695 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 444, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:696 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" + { + ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 445, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:697 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" + { + ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 445, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:698 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 446, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:699 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" + { + ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 446, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:700 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" + { + ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 447, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:701 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" + { + ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 447, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:702 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM" + { + ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 448, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_z, ND_OPF_R, 0, 0), + }, + + // Pos:703 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" + { + ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 449, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:704 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" + { + ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 449, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:705 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" + { + ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 450, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:706 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" + { + ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 450, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:707 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" + { + ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 451, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:708 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" + { + ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 451, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:709 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" + { + ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 452, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:710 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" + { + ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 453, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:711 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" + { + ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 453, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:712 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" + { + ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 454, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:713 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" + { + ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 455, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:714 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" + { + ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 456, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:715 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" + { + ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 457, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:716 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" + { + ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 458, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:717 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" + { + ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 459, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:718 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" + { + ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 460, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:719 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" + { + ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 461, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:720 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" + { + ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 461, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:721 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:722 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:723 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:724 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:725 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:726 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:727 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:728 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:729 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:730 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:731 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:732 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:733 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:734 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:735 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:736 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:737 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:738 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1A /r:reg"/"RM" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:739 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r:reg"/"RM" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:740 Instruction:"NOP Gv,Ev" Encoding:"0xF3 0x0F 0x1B /r:reg"/"RM" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:741 Instruction:"NOP Ev,Gv" Encoding:"0x66 0x0F 0x1C /0:mem"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:742 Instruction:"NOP Ev,Gv" Encoding:"0xF3 0x0F 0x1C /0:mem"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:743 Instruction:"NOP Ev,Gv" Encoding:"0xF2 0x0F 0x1C /0:mem"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:744 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /0:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:745 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /1"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:746 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /2"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:747 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /3"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:748 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /4"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:749 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /5"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:750 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /6"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:751 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /7"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:752 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:753 Instruction:"NOP Mv,Gv" Encoding:"0x0F 0x1E /r:mem"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:754 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:755 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /1:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:756 Instruction:"NOP Rv,Gv" Encoding:"rexw 0x0F 0x1E /1:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:757 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /2:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:758 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /3:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:759 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /4:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:760 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /5:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:761 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /6:reg"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:762 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xF8"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:763 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xF9"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:764 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFA"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:765 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFB"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:766 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFC"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:767 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFD"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:768 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFE"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:769 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFF"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:770 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" + { + ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + }, + + // Pos:771 Instruction:"NOP" Encoding:"0x90"/"" + { + ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 462, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:772 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" + { + ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 463, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + }, + + // Pos:773 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" + { + ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 463, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + }, + + // Pos:774 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:775 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:776 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:777 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:778 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:779 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:780 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:781 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:782 Instruction:"OR Ev,Iz" Encoding:"0x82 /1 iz"/"MI" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:783 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" + { + ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:784 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" + { + ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 465, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:785 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" + { + ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 466, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:786 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" + { + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 467, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:787 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" + { + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 467, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:788 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" + { + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 467, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:789 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" + { + ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 467, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_z, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:790 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" + { + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 468, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:791 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" + { + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 468, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:792 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" + { + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:793 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" + { + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:794 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" + { + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:795 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" + { + ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:796 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" + { + ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 471, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:797 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" + { + ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 471, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:798 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" + { + ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 472, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:799 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" + { + ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 472, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:800 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" + { + ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 473, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:801 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" + { + ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 473, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:802 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" + { + ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 474, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:803 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" + { + ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 474, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:804 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" + { + ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 475, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:805 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" + { + ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 475, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:806 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" + { + ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 476, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:807 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" + { + ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 477, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:808 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" + { + ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 477, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:809 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" + { + ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 478, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:810 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" + { + ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 478, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:811 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" + { + ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 479, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:812 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" + { + ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 479, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:813 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" + { + ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 480, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:814 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" + { + ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 480, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:815 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" + { + ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 481, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:816 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" + { + ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 481, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:817 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" + { + ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 482, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:818 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" + { + ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 482, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:819 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" + { + ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 483, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:820 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" + { + ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 483, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:821 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" + { + ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 484, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:822 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" + { + ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 484, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:823 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" + { + ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 485, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:824 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" + { + ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 485, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:825 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" + { + ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 486, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:826 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" + { + ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 486, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:827 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" + { + ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 487, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:828 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" + { + ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 487, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:829 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" + { + ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 488, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:830 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" + { + ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 488, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:831 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/"" + { + ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 489, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:832 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" + { + ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 490, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:833 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" + { + ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 490, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:834 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" + { + ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 491, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:835 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" + { + ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 492, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:836 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" + { + ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 492, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:837 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" + { + ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 493, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:838 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" + { + ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 494, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:839 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" + { + ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 495, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_PCLMULQDQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:840 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" + { + ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 496, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:841 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" + { + ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 496, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:842 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" + { + ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 497, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:843 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" + { + ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 497, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:844 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" + { + ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 498, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:845 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" + { + ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 499, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:846 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" + { + ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 499, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:847 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" + { + ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 500, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:848 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" + { + ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 501, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:849 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" + { + ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 502, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:850 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" + { + ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 502, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:851 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" + { + ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 503, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:852 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" + { + ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 503, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:853 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" + { + ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 504, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:854 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" + { + ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 505, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:855 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" + { + ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 505, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:856 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" + { + ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 506, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:857 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" + { + ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 507, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:858 Instruction:"PCOMMIT" Encoding:"0x66 0x0F 0xAE /7:reg"/"" + { + ND_INS_PCOMMIT, ND_CAT_MISC, ND_SET_PCOMMIT, 508, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCOMMIT, + 0, + 0, + 0, + 0, + }, + + // Pos:859 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" + { + ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 509, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:860 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" + { + ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 510, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:861 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" + { + ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 511, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:862 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" + { + ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 512, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:863 Instruction:"PEXTRB Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" + { + ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 512, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:864 Instruction:"PEXTRD Ey,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r ib"/"MRI" + { + ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 513, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:865 Instruction:"PEXTRQ Ey,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r ib"/"MRI" + { + ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 514, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:866 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" + { + ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 515, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_N, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:867 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" + { + ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 515, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:868 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" + { + ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 515, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:869 Instruction:"PEXTRW Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" + { + ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 515, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:870 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" + { + ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 516, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:871 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" + { + ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 517, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:872 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" + { + ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 518, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:873 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" + { + ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 519, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:874 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" + { + ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 520, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:875 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" + { + ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 521, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:876 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" + { + ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 522, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:877 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" + { + ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 523, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:878 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" + { + ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 524, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:879 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" + { + ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 524, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:880 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" + { + ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 525, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:881 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" + { + ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 526, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:882 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" + { + ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 527, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:883 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" + { + ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 528, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:884 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" + { + ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 529, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:885 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" + { + ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 530, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:886 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" + { + ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 531, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:887 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" + { + ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 532, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:888 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" + { + ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 533, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:889 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" + { + ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 534, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:890 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" + { + ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 535, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:891 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" + { + ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 536, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:892 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" + { + ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 536, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:893 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" + { + ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 537, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:894 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" + { + ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 537, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:895 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" + { + ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 538, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:896 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" + { + ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 538, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:897 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" + { + ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 539, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:898 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" + { + ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 540, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:899 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" + { + ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 540, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:900 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" + { + ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 541, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:901 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" + { + ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 541, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:902 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" + { + ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 542, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:903 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" + { + ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 542, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:904 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" + { + ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 543, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:905 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" + { + ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 544, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:906 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" + { + ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 545, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:907 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" + { + ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 545, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:908 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + { + ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 546, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:909 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + { + ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 547, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:910 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" + { + ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 548, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_R, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:911 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" + { + ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 548, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:912 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" + { + ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 548, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_R, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:913 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" + { + ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 548, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:914 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" + { + ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 549, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:915 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" + { + ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 549, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:916 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" + { + ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 550, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:917 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" + { + ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 550, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:918 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" + { + ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 551, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:919 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" + { + ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 552, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:920 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" + { + ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 553, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:921 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" + { + ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 553, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:922 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" + { + ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 554, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:923 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" + { + ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 554, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:924 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" + { + ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 555, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:925 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" + { + ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 556, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:926 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" + { + ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 557, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:927 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" + { + ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 558, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:928 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" + { + ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 559, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:929 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" + { + ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 559, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:930 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" + { + ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 560, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:931 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" + { + ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 560, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:932 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" + { + ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 561, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:933 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" + { + ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 562, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:934 Instruction:"PMOVMSKB Gd,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" + { + ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 563, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_N, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:935 Instruction:"PMOVMSKB Gd,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" + { + ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 563, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:936 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" + { + ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 564, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:937 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" + { + ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 565, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:938 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" + { + ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 566, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:939 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" + { + ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 567, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:940 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" + { + ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 568, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:941 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" + { + ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 569, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:942 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" + { + ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 570, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:943 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" + { + ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 571, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:944 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" + { + ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 572, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:945 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" + { + ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 573, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:946 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" + { + ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 574, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:947 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" + { + ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 575, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:948 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" + { + ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 576, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:949 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" + { + ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 577, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:950 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" + { + ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 577, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:951 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" + { + ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 578, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:952 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" + { + ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 579, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:953 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" + { + ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 579, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:954 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" + { + ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 580, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:955 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" + { + ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 580, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:956 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" + { + ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 581, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:957 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" + { + ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 582, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:958 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" + { + ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 582, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:959 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" + { + ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 583, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:960 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" + { + ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 583, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:961 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_FS, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:962 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_GS, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:963 Instruction:"POP ES" Encoding:"0x07"/"" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_ES, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:964 Instruction:"POP SS" Encoding:"0x17"/"" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:965 Instruction:"POP DS" Encoding:"0x1F"/"" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_DS, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:966 Instruction:"POP Zv" Encoding:"0x58"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:967 Instruction:"POP Zv" Encoding:"0x59"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:968 Instruction:"POP Zv" Encoding:"0x5A"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:969 Instruction:"POP Zv" Encoding:"0x5B"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:970 Instruction:"POP Zv" Encoding:"0x5C"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:971 Instruction:"POP Zv" Encoding:"0x5D"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:972 Instruction:"POP Zv" Encoding:"0x5E"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:973 Instruction:"POP Zv" Encoding:"0x5F"/"O" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:974 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" + { + ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:975 Instruction:"POPA" Encoding:"0x61"/"" + { + ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 585, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:976 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM" + { + ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 586, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, + 0, + 0|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:977 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" + { + ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 587, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:978 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" + { + ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 588, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:979 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" + { + ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 589, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:980 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" + { + ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 590, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:981 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" + { + ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 590, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:982 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /4:mem"/"M" + { + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:983 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /5:mem"/"M" + { + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:984 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /6:mem"/"M" + { + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:985 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /7:mem"/"M" + { + ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:986 Instruction:"PREFETCHE Mcl" Encoding:"0x0F 0x0D /0:mem"/"M" + { + ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 592, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:987 Instruction:"PREFETCHM Mcl" Encoding:"0x0F 0x0D /3:mem"/"M" + { + ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 593, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:988 Instruction:"PREFETCHNTA Mcl" Encoding:"0x0F 0x18 /0:mem"/"M" + { + ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 594, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:989 Instruction:"PREFETCHT0 Mcl" Encoding:"0x0F 0x18 /1:mem"/"M" + { + ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 595, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:990 Instruction:"PREFETCHT1 Mcl" Encoding:"0x0F 0x18 /2:mem"/"M" + { + ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 596, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:991 Instruction:"PREFETCHT2 Mcl" Encoding:"0x0F 0x18 /3:mem"/"M" + { + ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 597, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:992 Instruction:"PREFETCHW Mcl" Encoding:"0x0F 0x0D /1:mem"/"M" + { + ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 598, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:993 Instruction:"PREFETCHWT1 Mcl" Encoding:"0x0F 0x0D /2:mem"/"M" + { + ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 599, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0), + }, + + // Pos:994 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" + { + ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 600, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:995 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" + { + ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 600, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:996 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" + { + ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 601, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:997 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" + { + ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 601, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:998 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" + { + ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 602, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:999 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" + { + ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 603, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1000 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" + { + ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 604, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1001 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" + { + ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 605, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1002 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" + { + ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 606, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1003 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" + { + ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 606, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1004 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" + { + ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 607, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1005 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" + { + ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 607, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1006 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" + { + ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 608, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1007 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" + { + ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 608, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1008 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" + { + ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 609, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1009 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" + { + ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 609, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1010 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" + { + ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 609, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1011 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" + { + ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 609, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1012 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" + { + ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 610, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1013 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" + { + ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 611, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1014 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" + { + ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 611, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1015 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" + { + ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 611, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1016 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" + { + ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 611, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1017 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" + { + ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 612, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1018 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" + { + ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 612, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1019 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" + { + ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 612, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1020 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" + { + ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 612, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1021 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" + { + ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 613, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, + 0, + 0|REG_RFLAG_OF|REG_RFLAG_ZF|REG_RFLAG_AF|REG_RFLAG_PF|REG_RFLAG_SF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1022 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" + { + ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 614, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1023 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" + { + ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 614, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1024 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" + { + ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 614, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1025 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" + { + ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 614, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1026 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" + { + ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 615, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1027 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" + { + ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 615, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1028 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" + { + ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 615, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1029 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" + { + ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 615, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1030 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" + { + ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 616, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1031 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" + { + ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 616, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1032 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" + { + ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 616, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1033 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" + { + ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 616, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1034 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" + { + ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 617, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1035 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" + { + ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 618, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1036 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" + { + ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 618, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1037 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" + { + ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 618, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1038 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" + { + ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 618, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1039 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" + { + ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 619, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_N, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1040 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" + { + ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 619, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_U, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1041 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" + { + ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 619, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1042 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" + { + ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 619, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1043 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" + { + ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 620, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1044 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" + { + ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 620, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1045 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" + { + ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 621, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1046 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" + { + ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 621, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1047 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" + { + ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 622, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1048 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" + { + ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 622, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1049 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" + { + ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 623, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1050 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" + { + ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 623, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1051 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" + { + ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 624, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1052 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" + { + ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 624, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1053 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" + { + ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 625, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1054 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" + { + ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 625, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1055 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" + { + ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 626, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1056 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" + { + ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 626, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1057 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" + { + ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 627, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1058 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" + { + ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 627, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1059 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" + { + ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 628, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1060 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" + { + ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 629, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1061 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" + { + ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 630, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NO66|ND_FLAG_MODRM, ND_CFF_PTWRITE, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1062 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" + { + ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 631, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1063 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" + { + ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 631, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1064 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" + { + ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 632, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1065 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" + { + ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 632, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1066 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" + { + ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 633, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1067 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" + { + ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 634, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1068 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" + { + ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 634, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1069 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" + { + ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 635, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1070 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" + { + ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 635, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1071 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" + { + ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 636, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1072 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" + { + ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 636, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1073 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" + { + ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 637, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1074 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" + { + ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 638, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1075 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" + { + ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 638, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1076 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_FS, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1077 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_GS, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1078 Instruction:"PUSH ES" Encoding:"0x06"/"" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_ES, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1079 Instruction:"PUSH CS" Encoding:"0x0E"/"" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1080 Instruction:"PUSH SS" Encoding:"0x16"/"" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1081 Instruction:"PUSH DS" Encoding:"0x1E"/"" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_DS, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1082 Instruction:"PUSH Zv" Encoding:"0x50"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1083 Instruction:"PUSH Zv" Encoding:"0x51"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1084 Instruction:"PUSH Zv" Encoding:"0x52"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1085 Instruction:"PUSH Zv" Encoding:"0x53"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1086 Instruction:"PUSH Zv" Encoding:"0x54"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1087 Instruction:"PUSH Zv" Encoding:"0x55"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1088 Instruction:"PUSH Zv" Encoding:"0x56"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1089 Instruction:"PUSH Zv" Encoding:"0x57"/"O" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_Z, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1090 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_DWS|ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1091 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_DWS|ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1092 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" + { + ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1093 Instruction:"PUSHA" Encoding:"0x60"/"" + { + ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 640, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1094 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" + { + ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 641, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1095 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" + { + ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 642, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1096 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" + { + ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 643, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1097 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" + { + ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 644, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, + 0, + 0|REG_RFLAG_OF|REG_RFLAG_ZF|REG_RFLAG_AF|REG_RFLAG_PF|REG_RFLAG_SF|REG_RFLAG_CF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1098 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" + { + ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 645, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, + 0, + 0, + 0, + OP(ND_OPT_P, ND_OPS_q, ND_OPF_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1099 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" + { + ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 645, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1100 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" + { + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1101 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" + { + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1102 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" + { + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1103 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" + { + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1104 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" + { + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1105 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" + { + ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1106 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" + { + ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 647, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1107 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" + { + ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 648, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1108 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" + { + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1109 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" + { + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1110 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" + { + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1111 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" + { + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1112 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" + { + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1113 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" + { + ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1114 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M" + { + ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 650, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_MSR_FSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1115 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M" + { + ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 651, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1116 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" + { + ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 652, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MSR, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1117 Instruction:"RDPID Rv" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" + { + ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 653, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPID, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_MSR_TSCAUX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1118 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" + { + ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 654, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1119 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" + { + ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 655, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1120 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/"" + { + ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 656, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1121 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M" + { + ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 657, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1122 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" + { + ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 657, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1123 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M" + { + ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 658, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1124 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" + { + ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 658, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1125 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M" + { + ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 659, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1126 Instruction:"RDSSPD Rd" Encoding:"a0xF3 0x0F 0x1E /1:reg"/"M" + { + ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET, 660, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_SSP, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1127 Instruction:"RDSSPQ Rq" Encoding:"a0xF3 rexw 0x0F 0x1E /1:reg"/"M" + { + ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET, 661, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_SSP, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1128 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" + { + ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 662, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MSR_TSC, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1129 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" + { + ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 663, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDTSCP, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_MSR_TSC, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR_TSCAUX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1130 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" + { + ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 664, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_w, ND_OPF_SEX_DWS|ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1131 Instruction:"RETF" Encoding:"0xCB"/"" + { + ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 664, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1132 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" + { + ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 665, + ND_MOD_ANY, + ND_PREF_BND, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_I, ND_OPS_w, ND_OPF_SEX_DWS|ND_OPF_R, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1133 Instruction:"RETN" Encoding:"0xC3"/"" + { + ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 665, + ND_MOD_ANY, + ND_PREF_BND, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1134 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" + { + ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 666, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, + 0, + 0|REG_RFLAG_OF|REG_RFLAG_ZF|REG_RFLAG_AF|REG_RFLAG_PF|REG_RFLAG_SF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1135 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" + { + ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 667, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, + 0, + 0|REG_RFLAG_OF|REG_RFLAG_ZF|REG_RFLAG_AF|REG_RFLAG_PF|REG_RFLAG_SF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1136 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" + { + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1137 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" + { + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1138 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" + { + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1139 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" + { + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1140 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" + { + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1141 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" + { + ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1142 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" + { + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1143 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" + { + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1144 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" + { + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1145 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" + { + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1146 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" + { + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1147 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" + { + ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1148 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" + { + ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 670, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1149 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" + { + ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 671, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1150 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" + { + ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 672, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1151 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" + { + ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 673, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1152 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" + { + ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 674, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1153 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM" + { + ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 675, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_S, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), + }, + + // Pos:1154 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M" + { + ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 676, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), + }, + + // Pos:1155 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" + { + ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 677, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1156 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" + { + ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 678, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1157 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" + { + ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 679, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1158 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" + { + ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET, 680, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_q, ND_OPF_RW, 0, 0), + }, + + // Pos:1159 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M" + { + ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 681, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), + }, + + // Pos:1160 Instruction:"SAHF" Encoding:"0x9E"/"" + { + ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 682, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0, + 0, + OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1161 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" + { + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1162 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" + { + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1163 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" + { + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1164 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" + { + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1165 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" + { + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1166 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" + { + ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1167 Instruction:"SALC" Encoding:"0xD6"/"" + { + ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 684, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1168 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" + { + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1169 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" + { + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1170 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" + { + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1171 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" + { + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1172 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" + { + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1173 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" + { + ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1174 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" + { + ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 686, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1175 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" + { + ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET, 687, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + OP(ND_OPT_MEM_SHS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_SSP, ND_OPS_y, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1176 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1177 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1178 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1179 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1180 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1181 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1182 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1183 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1184 Instruction:"SBB Ev,Iz" Encoding:"0x82 /3 iz"/"MI" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1185 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" + { + ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1186 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 689, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1187 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 689, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1188 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 690, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1189 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 690, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1190 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 691, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1191 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 691, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1192 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 692, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1193 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" + { + ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 692, + ND_MOD_ANY, + ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_ZF|REG_RFLAG_DF, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CR, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1194 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" + { + ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 693, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SERIALIZE, + 0, + 0, + 0, + 0, + }, + + // Pos:1195 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 694, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1196 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 695, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1197 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 696, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1198 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 697, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1199 Instruction:"SETNB Eb" Encoding:"0x0F 0x97 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 698, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1200 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 699, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_CF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1201 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 700, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1202 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 701, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1203 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 702, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1204 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 703, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1205 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 704, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1206 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 705, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1207 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 706, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_OF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1208 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 707, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_PF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1209 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 708, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_SF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1210 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" + { + ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET, 709, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET, + 0, + 0, + 0, + 0, + }, + + // Pos:1211 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" + { + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 710, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0|REG_RFLAG_ZF, + 0, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1212 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" + { + ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 711, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + }, + + // Pos:1213 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" + { + ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 712, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_W, 0, 0), + OP(ND_OPT_SYS_GDTR, ND_OPS_s, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1214 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" + { + ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 713, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1215 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" + { + ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 714, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1216 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" + { + ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 715, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1217 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" + { + ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 716, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1218 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" + { + ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 717, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1219 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" + { + ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 718, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1220 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" + { + ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 719, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1221 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" + { + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1222 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" + { + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1223 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" + { + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1224 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" + { + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1225 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" + { + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1226 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" + { + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1227 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" + { + ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 721, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1228 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" + { + ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 721, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1229 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" + { + ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 722, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1230 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" + { + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1231 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" + { + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1232 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" + { + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1233 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" + { + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_CONST_1, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1234 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" + { + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1235 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" + { + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1236 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" + { + ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 724, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1237 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" + { + ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 724, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1238 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" + { + ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 725, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1239 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" + { + ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 726, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1240 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" + { + ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 727, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1241 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" + { + ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 728, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_W, 0, 0), + OP(ND_OPT_SYS_IDTR, ND_OPS_s, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1242 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" + { + ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 729, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1243 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" + { + ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 730, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1244 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" + { + ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 730, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1245 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" + { + ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 731, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1246 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/"" + { + ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 732, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:1247 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" + { + ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 733, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1248 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" + { + ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 733, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1249 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" + { + ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 734, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1250 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" + { + ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 735, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1251 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" + { + ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 736, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1252 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" + { + ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 737, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1253 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" + { + ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 738, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1254 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" + { + ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 739, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, + 0, + 0, + 0|REG_RFLAG_AC, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1255 Instruction:"STC" Encoding:"0xF9"/"" + { + ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 740, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0|REG_RFLAG_CF, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1256 Instruction:"STD" Encoding:"0xFD"/"" + { + ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 741, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0|REG_RFLAG_DF, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1257 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" + { + ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 742, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + 0, + 0, + 0, + }, + + // Pos:1258 Instruction:"STI" Encoding:"0xFB"/"" + { + ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 743, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0|REG_RFLAG_IF, + 0, + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1259 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" + { + ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 744, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1260 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 745, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1261 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 745, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1262 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 746, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1263 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 746, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1264 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 747, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1265 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 747, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1266 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 748, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1267 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" + { + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 748, + ND_MOD_ANY, + ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0|REG_RFLAG_DF, + 0, + 0, + 0, + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1268 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" + { + ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 749, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_w, ND_OPF_W, 0, 0), + OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1269 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" + { + ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 749, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1270 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" + { + ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 750, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_oq, ND_OPF_W, 0, 0), + }, + + // Pos:1271 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1272 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1273 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1274 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1275 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1276 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1277 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1278 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1279 Instruction:"SUB Ev,Iz" Encoding:"0x82 /5 iz"/"MI" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1280 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" + { + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, + ND_MOD_ANY, + ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1281 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" + { + ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 752, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1282 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" + { + ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 753, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1283 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" + { + ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 754, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1284 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" + { + ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 755, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1285 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR" + { + ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 756, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_W, 0, 0), + OP(ND_OPT_S, ND_OPS_w, ND_OPF_R, 0, 0), + }, + + // Pos:1286 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M" + { + ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 757, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_W, 0, 0), + }, + + // Pos:1287 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M" + { + ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 758, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_s, ND_OPF_W, 0, 0), + }, + + // Pos:1288 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" + { + ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 759, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1289 Instruction:"SYSCALL" Encoding:"o64 0x0F 0x05"/"" + { + ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 760, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, ND_FLAG_O64, ND_CFF_FSC, + 0, + 0, + 0, + 0, + OP(ND_OPT_MSR_STAR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR_LSTAR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR_FMASK, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rR11, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), + }, + + // Pos:1290 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" + { + ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 761, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SEP, + 0, + 0, + 0, + 0|REG_RFLAG_IF, + OP(ND_OPT_MSR_SCS, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR_SESP, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_MSR_SEIP, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1291 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" + { + ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 762, + ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SEP, + 0, + 0, + 0, + 0, + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1292 Instruction:"SYSRET" Encoding:"o64 0x0F 0x07"/"" + { + ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 763, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 7), 0, 0, 0, 0, 0, 0, ND_FLAG_O64, ND_CFF_FSC, + 0, + 0, + 0, + 0, + OP(ND_OPT_MSR_STAR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rR11, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1293 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" + { + ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 764, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1294 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" + { + ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 765, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, ND_OPF_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1295 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" + { + ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 766, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, ND_OPF_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1296 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" + { + ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 767, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, ND_OPF_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1297 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" + { + ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 768, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, ND_OPF_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1298 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" + { + ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 769, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, ND_OPF_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1299 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1300 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1301 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1302 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1303 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1304 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1305 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1306 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" + { + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|REG_RFLAG_AF, + 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1307 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" + { + ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 771, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1308 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" + { + ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 772, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1309 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" + { + ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 773, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + }, + + // Pos:1310 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" + { + ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 774, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_t, ND_OPF_W, 0, 0), + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_R, 0, 0), + }, + + // Pos:1311 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" + { + ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 775, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + 0, + 0, + 0, + OP(ND_OPT_rT, ND_OPS_t, ND_OPF_W, 0, 0), + }, + + // Pos:1312 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/"" + { + ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 776, + ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, + 0, + 0, + 0, + 0, + }, + + // Pos:1313 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" + { + ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 777, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1314 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM" + { + ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 778, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_G, ND_OPS_v, ND_OPF_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1315 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" + { + ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 779, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + 0, + 0, + 0, + OP(ND_OPT_B, ND_OPS_y, ND_OPF_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1316 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" + { + ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 780, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1317 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" + { + ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 781, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1318 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" + { + ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 782, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1319 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" + { + ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 783, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_d, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), + }, + + // Pos:1320 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" + { + ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 784, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + 0, + 0, + 0, + }, + + // Pos:1321 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" + { + ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 785, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, + 0, + 0|REG_RFLAG_CF, + 0, + 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + OP(ND_OPT_mM, ND_OPS_b, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1322 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" + { + ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 786, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, + 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), + }, + + // Pos:1323 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" + { + ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 787, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1324 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" + { + ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 788, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1325 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" + { + ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 789, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1326 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" + { + ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 790, + ND_MOD_ANY, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1327 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" + { + ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 791, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, ND_OPF_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1328 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" + { + ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 792, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1329 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" + { + ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 793, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, ND_OPF_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1330 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" + { + ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 794, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_RW, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1331 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" + { + ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 795, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1332 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" + { + ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 795, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1333 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" + { + ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 796, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1334 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" + { + ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 796, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1335 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" + { + ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 797, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1336 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" + { + ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 797, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1337 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" + { + ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 798, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1338 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" + { + ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 798, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1339 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" + { + ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 799, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1340 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" + { + ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 800, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1341 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + { + ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 801, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1342 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + { + ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 801, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1343 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + { + ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 802, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1344 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + { + ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 802, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1345 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + { + ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 803, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1346 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + { + ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 803, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1347 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + { + ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 804, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1348 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + { + ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 804, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1349 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" + { + ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 805, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1350 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" + { + ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 806, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1351 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" + { + ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 807, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1352 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" + { + ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 808, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1353 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" + { + ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 809, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1354 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" + { + ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 809, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1355 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" + { + ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 810, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1356 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" + { + ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 810, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1357 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" + { + ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 811, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1358 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" + { + ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 811, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1359 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" + { + ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 812, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1360 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" + { + ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 812, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1361 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" + { + ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 813, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), + }, + + // Pos:1362 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" + { + ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 814, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1363 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" + { + ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 815, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1364 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" + { + ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 816, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1365 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" + { + ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 817, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1366 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" + { + ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 818, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1367 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" + { + ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 819, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1368 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" + { + ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 820, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1369 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" + { + ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 821, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1370 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" + { + ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 822, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1371 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" + { + ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 823, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1372 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" + { + ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 824, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1373 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" + { + ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 825, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1374 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" + { + ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 826, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1375 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" + { + ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 827, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1376 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" + { + ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 828, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1377 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" + { + ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 829, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1378 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" + { + ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 830, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_M, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1379 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" + { + ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 831, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_u, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1380 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" + { + ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 831, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1381 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" + { + ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 832, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1382 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" + { + ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 832, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1383 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" + { + ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 833, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1384 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" + { + ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 833, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1385 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + { + ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 834, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1386 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" + { + ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 835, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1387 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" + { + ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 835, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1388 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" + { + ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 836, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_rK, ND_OPS_q, ND_OPF_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1389 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" + { + ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 836, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1390 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" + { + ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 836, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1391 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" + { + ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 837, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1392 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" + { + ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 837, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1393 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" + { + ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 838, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1394 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" + { + ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 838, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1395 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" + { + ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 839, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1396 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" + { + ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 840, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1397 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" + { + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 841, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1398 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" + { + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 841, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1399 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" + { + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 841, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1400 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" + { + ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 842, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1401 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" + { + ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 842, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1402 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" + { + ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 843, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1403 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" + { + ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 844, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1404 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" + { + ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 845, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1405 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" + { + ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 845, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1406 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" + { + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 846, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1407 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" + { + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 846, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1408 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" + { + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 846, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), + }, + + // Pos:1409 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" + { + ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 847, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1410 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" + { + ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 848, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1411 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" + { + ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 849, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1412 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" + { + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 850, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1413 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" + { + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 850, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1414 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" + { + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 850, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1415 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" + { + ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 851, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1416 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" + { + ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 851, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1417 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" + { + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 852, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1418 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" + { + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 852, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), + }, + + // Pos:1419 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" + { + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 852, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + }, + + // Pos:1420 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" + { + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 853, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1421 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" + { + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 853, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_q, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1422 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" + { + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 853, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1423 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" + { + ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 854, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1424 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" + { + ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 855, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1425 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" + { + ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 856, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1426 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" + { + ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 857, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1427 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" + { + ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 858, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1428 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" + { + ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 859, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1429 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" + { + ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 859, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1430 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" + { + ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 860, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1431 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" + { + ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 860, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1432 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" + { + ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 861, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1433 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" + { + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 862, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1434 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" + { + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 862, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1435 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" + { + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 862, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1436 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + { + ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 863, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1437 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + { + ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 863, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1438 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" + { + ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 864, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1439 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" + { + ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 864, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1440 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" + { + ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 865, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1441 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" + { + ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 865, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1442 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" + { + ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 866, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1443 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" + { + ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 867, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1444 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" + { + ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 867, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + }, + + // Pos:1445 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" + { + ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 868, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1446 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" + { + ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 869, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1447 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" + { + ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 870, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1448 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" + { + ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 871, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1449 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" + { + ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 871, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1450 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" + { + ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 872, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1451 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" + { + ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 873, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1452 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" + { + ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 874, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1453 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" + { + ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 875, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1454 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" + { + ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 875, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1455 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" + { + ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 876, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1456 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" + { + ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 877, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1457 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" + { + ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 877, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1458 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" + { + ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 878, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_G, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), + }, + + // Pos:1459 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" + { + ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 879, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1460 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" + { + ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 880, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1461 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" + { + ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 881, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1462 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" + { + ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 882, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1463 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" + { + ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 883, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1464 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" + { + ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 883, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1465 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" + { + ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 884, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), + }, + + // Pos:1466 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" + { + ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 885, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1467 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" + { + ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 886, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + + // Pos:1468 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" + { + ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 886, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_pd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), + }, + + // Pos:1469 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" + { + ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 887, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + + // Pos:1470 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" + { + ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 887, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ps, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), + }, + + // Pos:1471 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" + { + ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 888, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1472 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" + { + ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 888, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_sd, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), + }, + + // Pos:1473 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" + { + ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 889, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), + }, + + // Pos:1474 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" + { + ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 889, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), + }, + + // Pos:1475 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" + { + ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 890, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), + }, + + // Pos:1476 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" + { + ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 891, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1477 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" + { + ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 892, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1478 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" + { + ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 893, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1479 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" + { + ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 894, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, + 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0|REG_RFLAG_ZF, + 0, + 0, + OP(ND_OPT_E, ND_OPS_w, ND_OPF_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), + }, + + // Pos:1480 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" + { + ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 895, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + + // Pos:1481 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" + { + ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 896, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + + // Pos:1482 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" + { + ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 897, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1483 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" + { + ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 898, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), + }, + + // Pos:1484 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" + { + ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 899, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1485 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" + { + ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 900, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1486 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" + { + ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 901, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1487 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" + { + ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 902, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1488 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" + { + ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 903, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1489 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" + { + ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 904, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1490 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" + { + ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 905, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1491 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" + { + ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 906, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1492 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" + { + ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 907, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_dq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_u, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1493 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" + { + ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 908, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_W, ND_OPS_qq, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), + OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), + OP(ND_OPT_V, ND_OPS_oq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1494 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + { + ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 909, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_M, ND_OPS_d, ND_OPF_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), + }, + + // Pos:1495 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + { + ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 909, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, + 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + 0, + 0, + 0, + 0, + OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), + OP(ND_OPT_V