diff --git a/bddisasm/bddisasm.c b/bddisasm/bddisasm.c
index a4beb2a..24e9fc5 100644
--- a/bddisasm/bddisasm.c
+++ b/bddisasm/bddisasm.c
@@ -198,6 +198,13 @@ static const uint16_t gOperandMap[] =
     ND_OPE_M,       // ND_OPT_FPU_STX
 
     ND_OPE_S,       // ND_OPT_SSE_XMM0
+    ND_OPE_S,       // ND_OPT_SSE_XMM1
+    ND_OPE_S,       // ND_OPT_SSE_XMM2
+    ND_OPE_S,       // ND_OPT_SSE_XMM3
+    ND_OPE_S,       // ND_OPT_SSE_XMM4
+    ND_OPE_S,       // ND_OPT_SSE_XMM5
+    ND_OPE_S,       // ND_OPT_SSE_XMM6
+    ND_OPE_S,       // ND_OPT_SSE_XMM7
 
     ND_OPE_S,       // ND_OPT_MEM_rBX_AL (as used by XLAT)
     ND_OPE_S,       // ND_OPT_MEM_rDI (as used by masked moves)
@@ -1680,6 +1687,16 @@ NdParseOperand(
         size = ND_SIZE_1KB;
         break;
 
+    case ND_OPS_384:
+        // 384 bit Key Locker handle.
+        size = ND_SIZE_384BIT;
+        break;
+
+    case ND_OPS_512:
+        // 512 bit Key Locker handle.
+        size = ND_SIZE_512BIT;
+        break;
+
     case ND_OPS_unknown:
         size = ND_SIZE_UNKNOWN;
         break;
@@ -1873,11 +1890,18 @@ NdParseOperand(
         break;
 
     case ND_OPT_SSE_XMM0:
-        // Operand is the XMM0 register.
+    case ND_OPT_SSE_XMM1:
+    case ND_OPT_SSE_XMM2:
+    case ND_OPT_SSE_XMM3:
+    case ND_OPT_SSE_XMM4:
+    case ND_OPT_SSE_XMM5:
+    case ND_OPT_SSE_XMM6:
+    case ND_OPT_SSE_XMM7:
+        // Operand is a hard-coded XMM register.
         operand->Type = ND_OP_REG;
         operand->Info.Register.Type = ND_REG_SSE;
         operand->Info.Register.Size = ND_SIZE_128BIT;
-        operand->Info.Register.Reg = 0;
+        operand->Info.Register.Reg = opt - ND_OPT_SSE_XMM0;
         break;
 
     // Special operands. These are always implicit, and can't be encoded inside the instruction.
@@ -4682,6 +4706,10 @@ NdToText(
                     res = nd_strcat_s(Buffer, BufferSize, "ymmword ptr ");
                     RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
                     break;
+                case 48:
+                    res = nd_strcat_s(Buffer, BufferSize, "m384 ptr ");
+                    RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
+                    break;
                 case 64:
                     res = nd_strcat_s(Buffer, BufferSize, "zmmword ptr ");
                     RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h
index 31799e5..de33720 100644
--- a/bddisasm/include/instructions.h
+++ b/bddisasm/include/instructions.h
@@ -5,7 +5,7 @@
 #ifndef INSTRUCTIONS_H
 #define INSTRUCTIONS_H
 
-const ND_INSTRUCTION gInstructions[2565] = 
+const ND_INSTRUCTION gInstructions[2576] = 
 {
     // Pos:0 Instruction:"AAA" Encoding:"0x37"/""
     {
@@ -563,9 +563,43 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:33 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM"
+    // Pos:33 Instruction:"AESDEC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDD /r:mem"/"RM"
     {
-        ND_INS_AESDECLAST, ND_CAT_AES, ND_SET_AES, 15, 
+        ND_INS_AESDEC128KL, ND_CAT_AESKL, ND_SET_KL, 15, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, 
+        0,
+        0|NDR_RFLAG_ZF,
+        0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+        {
+            OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:34 Instruction:"AESDEC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDF /r:mem"/"RM"
+    {
+        ND_INS_AESDEC256KL, ND_CAT_AESKL, ND_SET_KL, 16, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, 
+        0,
+        0|NDR_RFLAG_ZF,
+        0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+        {
+            OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:35 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM"
+    {
+        ND_INS_AESDECLAST, ND_CAT_AES, ND_SET_AES, 17, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -579,9 +613,43 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:34 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM"
+    // Pos:36 Instruction:"AESDECWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /1:mem"/"M"
+    {
+        ND_INS_AESDECWIDE128KL, ND_CAT_WIDE_KL, ND_SET_KL, 18, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, 
+        0,
+        0|NDR_RFLAG_ZF,
+        0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+        {
+            OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 8), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:37 Instruction:"AESDECWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /3:mem"/"M"
+    {
+        ND_INS_AESDECWIDE256KL, ND_CAT_WIDE_KL, ND_SET_KL, 19, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, 
+        0,
+        0|NDR_RFLAG_ZF,
+        0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+        {
+            OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 8), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:38 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM"
     {
-        ND_INS_AESENC, ND_CAT_AES, ND_SET_AES, 16, 
+        ND_INS_AESENC, ND_CAT_AES, ND_SET_AES, 20, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -595,9 +663,43 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:35 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM"
+    // Pos:39 Instruction:"AESENC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDC /r:mem"/"RM"
     {
-        ND_INS_AESENCLAST, ND_CAT_AES, ND_SET_AES, 17, 
+        ND_INS_AESENC128KL, ND_CAT_AESKL, ND_SET_KL, 21, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, 
+        0,
+        0|NDR_RFLAG_ZF,
+        0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+        {
+            OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:40 Instruction:"AESENC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDE /r:mem"/"RM"
+    {
+        ND_INS_AESENC256KL, ND_CAT_AESKL, ND_SET_KL, 22, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, 
+        0,
+        0|NDR_RFLAG_ZF,
+        0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+        {
+            OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:41 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM"
+    {
+        ND_INS_AESENCLAST, ND_CAT_AES, ND_SET_AES, 23, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -611,9 +713,43 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:36 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM"
+    // Pos:42 Instruction:"AESENCWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /0:mem"/"M"
+    {
+        ND_INS_AESENCWIDE128KL, ND_CAT_WIDE_KL, ND_SET_KL, 24, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, 
+        0,
+        0|NDR_RFLAG_ZF,
+        0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+        {
+            OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 8), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:43 Instruction:"AESENCWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /2:mem"/"M"
     {
-        ND_INS_AESIMC, ND_CAT_AES, ND_SET_AES, 18, 
+        ND_INS_AESENCWIDE256KL, ND_CAT_WIDE_KL, ND_SET_KL, 25, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, 
+        0,
+        0|NDR_RFLAG_ZF,
+        0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+        {
+            OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 8), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:44 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM"
+    {
+        ND_INS_AESIMC, ND_CAT_AES, ND_SET_AES, 26, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -627,9 +763,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:37 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI"
+    // Pos:45 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI"
     {
-        ND_INS_AESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 19, 
+        ND_INS_AESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 27, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -644,9 +780,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:38 Instruction:"ALTINST" Encoding:"0x0F 0x3F"/""
+    // Pos:46 Instruction:"ALTINST" Encoding:"0x0F 0x3F"/""
     {
-        ND_INS_ALTINST, ND_CAT_SYSTEM, ND_SET_CYRIX, 20, 
+        ND_INS_ALTINST, ND_CAT_SYSTEM, ND_SET_CYRIX, 28, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -659,9 +795,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:39 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR"
+    // Pos:47 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR"
     {
-        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, 
+        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -676,9 +812,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:40 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR"
+    // Pos:48 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR"
     {
-        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, 
+        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -693,9 +829,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:41 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM"
+    // Pos:49 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM"
     {
-        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, 
+        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -710,9 +846,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:42 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM"
+    // Pos:50 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM"
     {
-        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, 
+        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -727,9 +863,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:43 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I"
+    // Pos:51 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I"
     {
-        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, 
+        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -744,9 +880,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:44 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I"
+    // Pos:52 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I"
     {
-        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, 
+        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -761,9 +897,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:45 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI"
+    // Pos:53 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI"
     {
-        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, 
+        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -778,9 +914,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:46 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI"
+    // Pos:54 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI"
     {
-        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, 
+        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -795,9 +931,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:47 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI"
+    // Pos:55 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI"
     {
-        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, 
+        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -812,9 +948,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:48 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI"
+    // Pos:56 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI"
     {
-        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, 
+        ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 29, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -829,9 +965,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:49 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM"
+    // Pos:57 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM"
     {
-        ND_INS_ANDN, ND_CAT_BMI1, ND_SET_BMI1, 22, 
+        ND_INS_ANDN, ND_CAT_BMI1, ND_SET_BMI1, 30, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 
@@ -847,9 +983,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:50 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM"
+    // Pos:58 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM"
     {
-        ND_INS_ANDNPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 23, 
+        ND_INS_ANDNPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 31, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -863,9 +999,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:51 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM"
+    // Pos:59 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM"
     {
-        ND_INS_ANDNPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 24, 
+        ND_INS_ANDNPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 32, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -879,9 +1015,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:52 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM"
+    // Pos:60 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM"
     {
-        ND_INS_ANDPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 25, 
+        ND_INS_ANDPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 33, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -895,9 +1031,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:53 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM"
+    // Pos:61 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM"
     {
-        ND_INS_ANDPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 26, 
+        ND_INS_ANDPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 34, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -911,9 +1047,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:54 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR"
+    // Pos:62 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR"
     {
-        ND_INS_ARPL, ND_CAT_SYSTEM, ND_SET_I286PROT, 27, 
+        ND_INS_ARPL, ND_CAT_SYSTEM, ND_SET_I286PROT, 35, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -928,9 +1064,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:55 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:63 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_BEXTR, ND_CAT_BMI1, ND_SET_BMI1, 28, 
+        ND_INS_BEXTR, ND_CAT_BMI1, ND_SET_BMI1, 36, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 
@@ -946,9 +1082,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:56 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI"
+    // Pos:64 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI"
     {
-        ND_INS_BEXTR, ND_CAT_BITBYTE, ND_SET_TBM, 28, 
+        ND_INS_BEXTR, ND_CAT_BITBYTE, ND_SET_TBM, 36, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -963,9 +1099,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:57 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM"
+    // Pos:65 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM"
     {
-        ND_INS_BLCFILL, ND_CAT_BITBYTE, ND_SET_TBM, 29, 
+        ND_INS_BLCFILL, ND_CAT_BITBYTE, ND_SET_TBM, 37, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -979,9 +1115,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:58 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM"
+    // Pos:66 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM"
     {
-        ND_INS_BLCI, ND_CAT_BITBYTE, ND_SET_TBM, 30, 
+        ND_INS_BLCI, ND_CAT_BITBYTE, ND_SET_TBM, 38, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -995,9 +1131,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:59 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM"
+    // Pos:67 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM"
     {
-        ND_INS_BLCIC, ND_CAT_BITBYTE, ND_SET_TBM, 31, 
+        ND_INS_BLCIC, ND_CAT_BITBYTE, ND_SET_TBM, 39, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -1011,9 +1147,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:60 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM"
+    // Pos:68 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM"
     {
-        ND_INS_BLCMSK, ND_CAT_BITBYTE, ND_SET_TBM, 32, 
+        ND_INS_BLCMSK, ND_CAT_BITBYTE, ND_SET_TBM, 40, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -1027,9 +1163,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:61 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM"
+    // Pos:69 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM"
     {
-        ND_INS_BLCS, ND_CAT_BITBYTE, ND_SET_TBM, 33, 
+        ND_INS_BLCS, ND_CAT_BITBYTE, ND_SET_TBM, 41, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -1043,9 +1179,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:62 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI"
+    // Pos:70 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI"
     {
-        ND_INS_BLENDPD, ND_CAT_SSE, ND_SET_SSE4, 34, 
+        ND_INS_BLENDPD, ND_CAT_SSE, ND_SET_SSE4, 42, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -1060,9 +1196,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:63 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI"
+    // Pos:71 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI"
     {
-        ND_INS_BLENDPS, ND_CAT_SSE, ND_SET_SSE4, 35, 
+        ND_INS_BLENDPS, ND_CAT_SSE, ND_SET_SSE4, 43, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -1077,9 +1213,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:64 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM"
+    // Pos:72 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM"
     {
-        ND_INS_BLENDVPD, ND_CAT_SSE, ND_SET_SSE4, 36, 
+        ND_INS_BLENDVPD, ND_CAT_SSE, ND_SET_SSE4, 44, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -1094,9 +1230,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:65 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM"
+    // Pos:73 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM"
     {
-        ND_INS_BLENDVPS, ND_CAT_SSE, ND_SET_SSE4, 37, 
+        ND_INS_BLENDVPS, ND_CAT_SSE, ND_SET_SSE4, 45, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -1111,9 +1247,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:66 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM"
+    // Pos:74 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM"
     {
-        ND_INS_BLSFILL, ND_CAT_BITBYTE, ND_SET_TBM, 38, 
+        ND_INS_BLSFILL, ND_CAT_BITBYTE, ND_SET_TBM, 46, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -1127,9 +1263,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:67 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM"
+    // Pos:75 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM"
     {
-        ND_INS_BLSI, ND_CAT_BMI1, ND_SET_BMI1, 39, 
+        ND_INS_BLSI, ND_CAT_BMI1, ND_SET_BMI1, 47, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 
@@ -1144,9 +1280,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:68 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM"
+    // Pos:76 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM"
     {
-        ND_INS_BLSIC, ND_CAT_BITBYTE, ND_SET_TBM, 40, 
+        ND_INS_BLSIC, ND_CAT_BITBYTE, ND_SET_TBM, 48, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -1160,9 +1296,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:69 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM"
+    // Pos:77 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM"
     {
-        ND_INS_BLSMSK, ND_CAT_BMI1, ND_SET_BMI1, 41, 
+        ND_INS_BLSMSK, ND_CAT_BMI1, ND_SET_BMI1, 49, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 
@@ -1177,9 +1313,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:70 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM"
+    // Pos:78 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM"
     {
-        ND_INS_BLSR, ND_CAT_BMI1, ND_SET_BMI1, 42, 
+        ND_INS_BLSR, ND_CAT_BMI1, ND_SET_BMI1, 50, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 
@@ -1194,9 +1330,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:71 Instruction:"BNDCL rBl,Ey" Encoding:"mpx 0xF3 0x0F 0x1A /r"/"RM"
+    // Pos:79 Instruction:"BNDCL rBl,Ey" Encoding:"mpx 0xF3 0x0F 0x1A /r"/"RM"
     {
-        ND_INS_BNDCL, ND_CAT_MPX, ND_SET_MPX, 43, 
+        ND_INS_BNDCL, ND_CAT_MPX, ND_SET_MPX, 51, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 
@@ -1210,9 +1346,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:72 Instruction:"BNDCN rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1B /r"/"RM"
+    // Pos:80 Instruction:"BNDCN rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1B /r"/"RM"
     {
-        ND_INS_BNDCN, ND_CAT_MPX, ND_SET_MPX, 44, 
+        ND_INS_BNDCN, ND_CAT_MPX, ND_SET_MPX, 52, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 
@@ -1226,9 +1362,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:73 Instruction:"BNDCU rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1A /r"/"RM"
+    // Pos:81 Instruction:"BNDCU rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1A /r"/"RM"
     {
-        ND_INS_BNDCU, ND_CAT_MPX, ND_SET_MPX, 45, 
+        ND_INS_BNDCU, ND_CAT_MPX, ND_SET_MPX, 53, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 
@@ -1242,9 +1378,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:74 Instruction:"BNDLDX rBl,Mmib" Encoding:"mpx 0x0F 0x1A /r:mem mib"/"RM"
+    // Pos:82 Instruction:"BNDLDX rBl,Mmib" Encoding:"mpx 0x0F 0x1A /r:mem mib"/"RM"
     {
-        ND_INS_BNDLDX, ND_CAT_MPX, ND_SET_MPX, 46, 
+        ND_INS_BNDLDX, ND_CAT_MPX, ND_SET_MPX, 54, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, 
@@ -1258,9 +1394,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:75 Instruction:"BNDMK rBl,My" Encoding:"mpx 0xF3 0x0F 0x1B /r:mem"/"RM"
+    // Pos:83 Instruction:"BNDMK rBl,My" Encoding:"mpx 0xF3 0x0F 0x1B /r:mem"/"RM"
     {
-        ND_INS_BNDMK, ND_CAT_MPX, ND_SET_MPX, 47, 
+        ND_INS_BNDMK, ND_CAT_MPX, ND_SET_MPX, 55, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 
@@ -1274,9 +1410,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:76 Instruction:"BNDMOV rBl,mBl" Encoding:"mpx 0x66 0x0F 0x1A /r"/"RM"
+    // Pos:84 Instruction:"BNDMOV rBl,mBl" Encoding:"mpx 0x66 0x0F 0x1A /r"/"RM"
     {
-        ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 48, 
+        ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 56, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 
@@ -1290,9 +1426,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:77 Instruction:"BNDMOV mBl,rBl" Encoding:"mpx 0x66 0x0F 0x1B /r"/"MR"
+    // Pos:85 Instruction:"BNDMOV mBl,rBl" Encoding:"mpx 0x66 0x0F 0x1B /r"/"MR"
     {
-        ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 48, 
+        ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 56, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 
@@ -1306,9 +1442,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:78 Instruction:"BNDSTX Mmib,rBl" Encoding:"mpx 0x0F 0x1B /r:mem mib"/"MR"
+    // Pos:86 Instruction:"BNDSTX Mmib,rBl" Encoding:"mpx 0x0F 0x1B /r:mem mib"/"MR"
     {
-        ND_INS_BNDSTX, ND_CAT_MPX, ND_SET_MPX, 49, 
+        ND_INS_BNDSTX, ND_CAT_MPX, ND_SET_MPX, 57, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, 
@@ -1322,9 +1458,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:79 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM"
+    // Pos:87 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM"
     {
-        ND_INS_BOUND, ND_CAT_INTERRUPT, ND_SET_I186, 50, 
+        ND_INS_BOUND, ND_CAT_INTERRUPT, ND_SET_I186, 58, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -1338,9 +1474,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:80 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM"
+    // Pos:88 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM"
     {
-        ND_INS_BSF, ND_CAT_I386, ND_SET_I386, 51, 
+        ND_INS_BSF, ND_CAT_I386, ND_SET_I386, 59, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -1355,9 +1491,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:81 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM"
+    // Pos:89 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM"
     {
-        ND_INS_BSR, ND_CAT_BITBYTE, ND_SET_I386, 52, 
+        ND_INS_BSR, ND_CAT_BITBYTE, ND_SET_I386, 60, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -1372,9 +1508,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:82 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O"
+    // Pos:90 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O"
     {
-        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, 
+        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1387,9 +1523,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:83 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O"
+    // Pos:91 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O"
     {
-        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, 
+        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1402,9 +1538,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:84 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O"
+    // Pos:92 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O"
     {
-        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, 
+        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1417,9 +1553,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:85 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O"
+    // Pos:93 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O"
     {
-        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, 
+        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1432,9 +1568,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:86 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O"
+    // Pos:94 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O"
     {
-        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, 
+        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1447,9 +1583,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:87 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O"
+    // Pos:95 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O"
     {
-        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, 
+        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1462,9 +1598,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:88 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O"
+    // Pos:96 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O"
     {
-        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, 
+        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1477,9 +1613,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:89 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O"
+    // Pos:97 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O"
     {
-        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, 
+        ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 61, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1492,9 +1628,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:90 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR"
+    // Pos:98 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR"
     {
-        ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 54, 
+        ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 62, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 
@@ -1509,9 +1645,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:91 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI"
+    // Pos:99 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI"
     {
-        ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 54, 
+        ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 62, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -1526,9 +1662,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:92 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI"
+    // Pos:100 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI"
     {
-        ND_INS_BTC, ND_CAT_BITBYTE, ND_SET_I386, 55, 
+        ND_INS_BTC, ND_CAT_BITBYTE, ND_SET_I386, 63, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -1543,9 +1679,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:93 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR"
+    // Pos:101 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR"
     {
-        ND_INS_BTC, ND_CAT_I386, ND_SET_I386, 55, 
+        ND_INS_BTC, ND_CAT_I386, ND_SET_I386, 63, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 
@@ -1560,9 +1696,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:94 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR"
+    // Pos:102 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR"
     {
-        ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 56, 
+        ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 64, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 
@@ -1577,9 +1713,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:95 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI"
+    // Pos:103 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI"
     {
-        ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 56, 
+        ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 64, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -1594,9 +1730,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:96 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR"
+    // Pos:104 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR"
     {
-        ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 57, 
+        ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 65, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 
@@ -1611,9 +1747,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:97 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI"
+    // Pos:105 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI"
     {
-        ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 57, 
+        ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 65, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -1628,9 +1764,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:98 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV"
+    // Pos:106 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV"
     {
-        ND_INS_BZHI, ND_CAT_BMI2, ND_SET_BMI2, 58, 
+        ND_INS_BZHI, ND_CAT_BMI2, ND_SET_BMI2, 66, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -1646,9 +1782,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:99 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D"
+    // Pos:107 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D"
     {
-        ND_INS_CALLNR, ND_CAT_CALL, ND_SET_I86, 59, 
+        ND_INS_CALLNR, ND_CAT_CALL, ND_SET_I86, 67, 
         ND_PREF_BND, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -1664,9 +1800,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:100 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M"
+    // Pos:108 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M"
     {
-        ND_INS_CALLNI, ND_CAT_CALL, ND_SET_I86, 59, 
+        ND_INS_CALLNI, ND_CAT_CALL, ND_SET_I86, 67, 
         ND_PREF_BND|ND_PREF_DNT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, 
@@ -1682,9 +1818,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:101 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D"
+    // Pos:109 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D"
     {
-        ND_INS_CALLFD, ND_CAT_CALL, ND_SET_I86, 60, 
+        ND_INS_CALLFD, ND_CAT_CALL, ND_SET_I86, 68, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -1701,9 +1837,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:102 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M"
+    // Pos:110 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M"
     {
-        ND_INS_CALLFI, ND_CAT_CALL, ND_SET_I86, 60, 
+        ND_INS_CALLFI, ND_CAT_CALL, ND_SET_I86, 68, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, 
@@ -1720,9 +1856,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:103 Instruction:"CBW" Encoding:"ds16 0x98"/""
+    // Pos:111 Instruction:"CBW" Encoding:"ds16 0x98"/""
     {
-        ND_INS_CBW, ND_CAT_CONVERT, ND_SET_I386, 61, 
+        ND_INS_CBW, ND_CAT_CONVERT, ND_SET_I386, 69, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1736,9 +1872,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:104 Instruction:"CDQ" Encoding:"ds32 0x99"/""
+    // Pos:112 Instruction:"CDQ" Encoding:"ds32 0x99"/""
     {
-        ND_INS_CDQ, ND_CAT_CONVERT, ND_SET_I386, 62, 
+        ND_INS_CDQ, ND_CAT_CONVERT, ND_SET_I386, 70, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1752,9 +1888,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:105 Instruction:"CDQE" Encoding:"ds64 0x98"/""
+    // Pos:113 Instruction:"CDQE" Encoding:"ds64 0x98"/""
     {
-        ND_INS_CDQE, ND_CAT_CONVERT, ND_SET_I386, 63, 
+        ND_INS_CDQE, ND_CAT_CONVERT, ND_SET_I386, 71, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1768,9 +1904,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:106 Instruction:"CL1INVMB" Encoding:"0x0F 0x0A"/""
+    // Pos:114 Instruction:"CL1INVMB" Encoding:"0x0F 0x0A"/""
     {
-        ND_INS_CL1INVMB, ND_CAT_SYSTEM, ND_SET_SCC, 64, 
+        ND_INS_CL1INVMB, ND_CAT_SYSTEM, ND_SET_SCC, 72, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1783,9 +1919,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:107 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/""
+    // Pos:115 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/""
     {
-        ND_INS_CLAC, ND_CAT_SMAP, ND_SET_SMAP, 65, 
+        ND_INS_CLAC, ND_CAT_SMAP, ND_SET_SMAP, 73, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, 
@@ -1798,9 +1934,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:108 Instruction:"CLC" Encoding:"0xF8"/""
+    // Pos:116 Instruction:"CLC" Encoding:"0xF8"/""
     {
-        ND_INS_CLC, ND_CAT_FLAGOP, ND_SET_I86, 66, 
+        ND_INS_CLC, ND_CAT_FLAGOP, ND_SET_I86, 74, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1813,9 +1949,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:109 Instruction:"CLD" Encoding:"0xFC"/""
+    // Pos:117 Instruction:"CLD" Encoding:"0xFC"/""
     {
-        ND_INS_CLD, ND_CAT_FLAGOP, ND_SET_I86, 67, 
+        ND_INS_CLD, ND_CAT_FLAGOP, ND_SET_I86, 75, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1828,9 +1964,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:110 Instruction:"CLDEMOTE Mb" Encoding:"cldm NP 0x0F 0x1C /0:mem"/"M"
+    // Pos:118 Instruction:"CLDEMOTE Mb" Encoding:"cldm NP 0x0F 0x1C /0:mem"/"M"
     {
-        ND_INS_CLDEMOTE, ND_CAT_CLDEMOTE, ND_SET_CLDEMOTE, 68, 
+        ND_INS_CLDEMOTE, ND_CAT_CLDEMOTE, ND_SET_CLDEMOTE, 76, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLDEMOTE, 
@@ -1843,9 +1979,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:111 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M"
+    // Pos:119 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M"
     {
-        ND_INS_CLEVICT0, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 69, 
+        ND_INS_CLEVICT0, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 77, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -1858,9 +1994,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:112 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M"
+    // Pos:120 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M"
     {
-        ND_INS_CLEVICT1, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 70, 
+        ND_INS_CLEVICT1, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 78, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -1873,9 +2009,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:113 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M"
+    // Pos:121 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M"
     {
-        ND_INS_CLFLUSH, ND_CAT_MISC, ND_SET_CLFSH, 71, 
+        ND_INS_CLFLUSH, ND_CAT_MISC, ND_SET_CLFSH, 79, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSH, 
@@ -1888,9 +2024,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:114 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M"
+    // Pos:122 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M"
     {
-        ND_INS_CLFLUSHOPT, ND_CAT_MISC, ND_SET_CLFSHOPT, 72, 
+        ND_INS_CLFLUSHOPT, ND_CAT_MISC, ND_SET_CLFSHOPT, 80, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSHOPT, 
@@ -1903,9 +2039,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:115 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/""
+    // Pos:123 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/""
     {
-        ND_INS_CLGI, ND_CAT_SYSTEM, ND_SET_SVM, 73, 
+        ND_INS_CLGI, ND_CAT_SYSTEM, ND_SET_SVM, 81, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -1918,9 +2054,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:116 Instruction:"CLI" Encoding:"0xFA"/""
+    // Pos:124 Instruction:"CLI" Encoding:"0xFA"/""
     {
-        ND_INS_CLI, ND_CAT_FLAGOP, ND_SET_I86, 74, 
+        ND_INS_CLI, ND_CAT_FLAGOP, ND_SET_I86, 82, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1933,9 +2069,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:117 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M"
+    // Pos:125 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M"
     {
-        ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET_SS, 75, 
+        ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET_SS, 83, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -1949,9 +2085,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:118 Instruction:"CLTS" Encoding:"0x0F 0x06"/""
+    // Pos:126 Instruction:"CLTS" Encoding:"0x0F 0x06"/""
     {
-        ND_INS_CLTS, ND_CAT_SYSTEM, ND_SET_I286REAL, 76, 
+        ND_INS_CLTS, ND_CAT_SYSTEM, ND_SET_I286REAL, 84, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -1964,9 +2100,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:119 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M"
+    // Pos:127 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M"
     {
-        ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 77, 
+        ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 85, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLWB, 
@@ -1979,9 +2115,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:120 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/""
+    // Pos:128 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/""
     {
-        ND_INS_CLZERO, ND_CAT_MISC, ND_SET_CLZERO, 78, 
+        ND_INS_CLZERO, ND_CAT_MISC, ND_SET_CLZERO, 86, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -1994,9 +2130,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:121 Instruction:"CMC" Encoding:"0xF5"/""
+    // Pos:129 Instruction:"CMC" Encoding:"0xF5"/""
     {
-        ND_INS_CMC, ND_CAT_FLAGOP, ND_SET_I86, 79, 
+        ND_INS_CMC, ND_CAT_FLAGOP, ND_SET_I86, 87, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2009,9 +2145,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:122 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM"
+    // Pos:130 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 80, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 88, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2026,9 +2162,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:123 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM"
+    // Pos:131 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 81, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 89, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2043,9 +2179,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:124 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM"
+    // Pos:132 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 82, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 90, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2060,9 +2196,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:125 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM"
+    // Pos:133 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 83, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 91, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2077,9 +2213,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:126 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM"
+    // Pos:134 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 84, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 92, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2094,9 +2230,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:127 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM"
+    // Pos:135 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 85, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 93, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2111,9 +2247,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:128 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM"
+    // Pos:136 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 86, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 94, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2128,9 +2264,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:129 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM"
+    // Pos:137 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 87, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 95, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2145,9 +2281,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:130 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM"
+    // Pos:138 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 88, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 96, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2162,9 +2298,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:131 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM"
+    // Pos:139 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 89, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 97, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2179,9 +2315,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:132 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM"
+    // Pos:140 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 90, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 98, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2196,9 +2332,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:133 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM"
+    // Pos:141 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 91, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 99, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2213,9 +2349,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:134 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM"
+    // Pos:142 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 92, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 100, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2230,9 +2366,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:135 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM"
+    // Pos:143 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 93, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 101, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2247,9 +2383,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:136 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM"
+    // Pos:144 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 94, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 102, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2264,9 +2400,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:137 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM"
+    // Pos:145 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM"
     {
-        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 95, 
+        ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 103, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 
@@ -2281,9 +2417,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:138 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR"
+    // Pos:146 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR"
     {
-        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, 
+        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -2298,9 +2434,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:139 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR"
+    // Pos:147 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR"
     {
-        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, 
+        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -2315,9 +2451,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:140 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM"
+    // Pos:148 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM"
     {
-        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, 
+        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -2332,9 +2468,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:141 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM"
+    // Pos:149 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM"
     {
-        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, 
+        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -2349,9 +2485,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:142 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I"
+    // Pos:150 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I"
     {
-        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, 
+        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2366,9 +2502,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:143 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I"
+    // Pos:151 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I"
     {
-        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, 
+        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2383,9 +2519,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:144 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI"
+    // Pos:152 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI"
     {
-        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, 
+        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -2400,9 +2536,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:145 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI"
+    // Pos:153 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI"
     {
-        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, 
+        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -2417,9 +2553,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:146 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI"
+    // Pos:154 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI"
     {
-        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, 
+        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -2434,9 +2570,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:147 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI"
+    // Pos:155 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI"
     {
-        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, 
+        ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 104, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -2451,9 +2587,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:148 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI"
+    // Pos:156 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI"
     {
-        ND_INS_CMPPD, ND_CAT_SSE, ND_SET_SSE2, 97, 
+        ND_INS_CMPPD, ND_CAT_SSE, ND_SET_SSE2, 105, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -2468,9 +2604,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:149 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI"
+    // Pos:157 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI"
     {
-        ND_INS_CMPPS, ND_CAT_SSE, ND_SET_SSE, 98, 
+        ND_INS_CMPPS, ND_CAT_SSE, ND_SET_SSE, 106, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -2485,9 +2621,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:150 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/""
+    // Pos:158 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/""
     {
-        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 99, 
+        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 107, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2504,9 +2640,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:151 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/""
+    // Pos:159 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/""
     {
-        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 99, 
+        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 107, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2524,9 +2660,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:152 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI"
+    // Pos:160 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI"
     {
-        ND_INS_CMPSD, ND_CAT_SSE, ND_SET_SSE2, 100, 
+        ND_INS_CMPSD, ND_CAT_SSE, ND_SET_SSE2, 108, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -2541,9 +2677,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:153 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/""
+    // Pos:161 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/""
     {
-        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 100, 
+        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 108, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2560,9 +2696,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:154 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/""
+    // Pos:162 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/""
     {
-        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 100, 
+        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 108, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2580,9 +2716,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:155 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/""
+    // Pos:163 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/""
     {
-        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 101, 
+        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 109, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2599,9 +2735,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:156 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/""
+    // Pos:164 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/""
     {
-        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 101, 
+        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 109, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2619,9 +2755,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:157 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI"
+    // Pos:165 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI"
     {
-        ND_INS_CMPSS, ND_CAT_SSE, ND_SET_SSE, 102, 
+        ND_INS_CMPSS, ND_CAT_SSE, ND_SET_SSE, 110, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -2636,9 +2772,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:158 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/""
+    // Pos:166 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/""
     {
-        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 103, 
+        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 111, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2655,9 +2791,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:159 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/""
+    // Pos:167 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/""
     {
-        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 103, 
+        ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 111, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2675,9 +2811,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:160 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR"
+    // Pos:168 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR"
     {
-        ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 104, 
+        ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 112, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -2693,9 +2829,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:161 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR"
+    // Pos:169 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR"
     {
-        ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 104, 
+        ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 112, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -2711,9 +2847,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:162 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M"
+    // Pos:170 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M"
     {
-        ND_INS_CMPXCHG16B, ND_CAT_SEMAPHORE, ND_SET_CMPXCHG16B, 105, 
+        ND_INS_CMPXCHG16B, ND_CAT_SEMAPHORE, ND_SET_CMPXCHG16B, 113, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, 
@@ -2731,9 +2867,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:163 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M"
+    // Pos:171 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M"
     {
-        ND_INS_CMPXCHG8B, ND_CAT_SEMAPHORE, ND_SET_PENTIUMREAL, 106, 
+        ND_INS_CMPXCHG8B, ND_CAT_SEMAPHORE, ND_SET_PENTIUMREAL, 114, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, 
@@ -2751,9 +2887,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:164 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM"
+    // Pos:172 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM"
     {
-        ND_INS_COMISD, ND_CAT_SSE2, ND_SET_SSE2, 107, 
+        ND_INS_COMISD, ND_CAT_SSE2, ND_SET_SSE2, 115, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -2768,9 +2904,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:165 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM"
+    // Pos:173 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM"
     {
-        ND_INS_COMISS, ND_CAT_SSE, ND_SET_SSE, 108, 
+        ND_INS_COMISS, ND_CAT_SSE, ND_SET_SSE, 116, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -2785,9 +2921,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:166 Instruction:"CPUID" Encoding:"0x0F 0xA2"/""
+    // Pos:174 Instruction:"CPUID" Encoding:"0x0F 0xA2"/""
     {
-        ND_INS_CPUID, ND_CAT_MISC, ND_SET_I486REAL, 109, 
+        ND_INS_CPUID, ND_CAT_MISC, ND_SET_I486REAL, 117, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -2803,9 +2939,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:167 Instruction:"CPU_READ" Encoding:"0x0F 0x3D"/""
+    // Pos:175 Instruction:"CPU_READ" Encoding:"0x0F 0x3D"/""
     {
-        ND_INS_CPU_READ, ND_CAT_SYSTEM, ND_SET_CYRIX, 110, 
+        ND_INS_CPU_READ, ND_CAT_SYSTEM, ND_SET_CYRIX, 118, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2818,9 +2954,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:168 Instruction:"CPU_WRITE" Encoding:"0x0F 0x3C"/""
+    // Pos:176 Instruction:"CPU_WRITE" Encoding:"0x0F 0x3C"/""
     {
-        ND_INS_CPU_WRITE, ND_CAT_SYSTEM, ND_SET_CYRIX, 111, 
+        ND_INS_CPU_WRITE, ND_CAT_SYSTEM, ND_SET_CYRIX, 119, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2833,9 +2969,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:169 Instruction:"CQO" Encoding:"ds64 0x99"/""
+    // Pos:177 Instruction:"CQO" Encoding:"ds64 0x99"/""
     {
-        ND_INS_CQO, ND_CAT_CONVERT, ND_SET_I386, 112, 
+        ND_INS_CQO, ND_CAT_CONVERT, ND_SET_I386, 120, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -2849,9 +2985,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:170 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM"
+    // Pos:178 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM"
     {
-        ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, 
+        ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 121, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, 
@@ -2865,9 +3001,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:171 Instruction:"CRC32 Gy,Eb" Encoding:"0x66 0xF2 0x0F 0x38 0xF0 /r"/"RM"
+    // Pos:179 Instruction:"CRC32 Gy,Eb" Encoding:"0x66 0xF2 0x0F 0x38 0xF0 /r"/"RM"
     {
-        ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, 
+        ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 121, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, 
@@ -2881,9 +3017,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:172 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM"
+    // Pos:180 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM"
     {
-        ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, 
+        ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 121, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, 
@@ -2897,9 +3033,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:173 Instruction:"CRC32 Gy,Ev" Encoding:"0x66 0xF2 0x0F 0x38 0xF1 /r"/"RM"
+    // Pos:181 Instruction:"CRC32 Gy,Ev" Encoding:"0x66 0xF2 0x0F 0x38 0xF1 /r"/"RM"
     {
-        ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, 
+        ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 121, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, 
@@ -2913,9 +3049,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:174 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM"
+    // Pos:182 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM"
     {
-        ND_INS_CVTDQ2PD, ND_CAT_CONVERT, ND_SET_SSE2, 114, 
+        ND_INS_CVTDQ2PD, ND_CAT_CONVERT, ND_SET_SSE2, 122, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -2929,9 +3065,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:175 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM"
+    // Pos:183 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM"
     {
-        ND_INS_CVTDQ2PS, ND_CAT_CONVERT, ND_SET_SSE2, 115, 
+        ND_INS_CVTDQ2PS, ND_CAT_CONVERT, ND_SET_SSE2, 123, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -2945,9 +3081,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:176 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM"
+    // Pos:184 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM"
     {
-        ND_INS_CVTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 116, 
+        ND_INS_CVTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 124, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -2961,9 +3097,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:177 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM"
+    // Pos:185 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM"
     {
-        ND_INS_CVTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 117, 
+        ND_INS_CVTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 125, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -2977,9 +3113,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:178 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM"
+    // Pos:186 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM"
     {
-        ND_INS_CVTPD2PS, ND_CAT_CONVERT, ND_SET_SSE2, 118, 
+        ND_INS_CVTPD2PS, ND_CAT_CONVERT, ND_SET_SSE2, 126, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -2993,9 +3129,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:179 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM"
+    // Pos:187 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM"
     {
-        ND_INS_CVTPI2PD, ND_CAT_CONVERT, ND_SET_SSE2, 119, 
+        ND_INS_CVTPI2PD, ND_CAT_CONVERT, ND_SET_SSE2, 127, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3009,9 +3145,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:180 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM"
+    // Pos:188 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM"
     {
-        ND_INS_CVTPI2PS, ND_CAT_CONVERT, ND_SET_SSE, 120, 
+        ND_INS_CVTPI2PS, ND_CAT_CONVERT, ND_SET_SSE, 128, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -3025,9 +3161,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:181 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM"
+    // Pos:189 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM"
     {
-        ND_INS_CVTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 121, 
+        ND_INS_CVTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 129, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3041,9 +3177,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:182 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM"
+    // Pos:190 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM"
     {
-        ND_INS_CVTPS2PD, ND_CAT_CONVERT, ND_SET_SSE2, 122, 
+        ND_INS_CVTPS2PD, ND_CAT_CONVERT, ND_SET_SSE2, 130, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3057,9 +3193,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:183 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM"
+    // Pos:191 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM"
     {
-        ND_INS_CVTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 123, 
+        ND_INS_CVTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 131, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -3073,9 +3209,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:184 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM"
+    // Pos:192 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM"
     {
-        ND_INS_CVTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 124, 
+        ND_INS_CVTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 132, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3089,9 +3225,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:185 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM"
+    // Pos:193 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM"
     {
-        ND_INS_CVTSD2SS, ND_CAT_CONVERT, ND_SET_SSE2, 125, 
+        ND_INS_CVTSD2SS, ND_CAT_CONVERT, ND_SET_SSE2, 133, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3105,9 +3241,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:186 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM"
+    // Pos:194 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM"
     {
-        ND_INS_CVTSI2SD, ND_CAT_CONVERT, ND_SET_SSE2, 126, 
+        ND_INS_CVTSI2SD, ND_CAT_CONVERT, ND_SET_SSE2, 134, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3121,9 +3257,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:187 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM"
+    // Pos:195 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM"
     {
-        ND_INS_CVTSI2SS, ND_CAT_CONVERT, ND_SET_SSE, 127, 
+        ND_INS_CVTSI2SS, ND_CAT_CONVERT, ND_SET_SSE, 135, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -3137,9 +3273,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:188 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM"
+    // Pos:196 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM"
     {
-        ND_INS_CVTSS2SD, ND_CAT_CONVERT, ND_SET_SSE2, 128, 
+        ND_INS_CVTSS2SD, ND_CAT_CONVERT, ND_SET_SSE2, 136, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3153,9 +3289,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:189 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM"
+    // Pos:197 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM"
     {
-        ND_INS_CVTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 129, 
+        ND_INS_CVTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 137, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -3169,9 +3305,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:190 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM"
+    // Pos:198 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM"
     {
-        ND_INS_CVTTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 130, 
+        ND_INS_CVTTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 138, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3185,9 +3321,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:191 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM"
+    // Pos:199 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM"
     {
-        ND_INS_CVTTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 131, 
+        ND_INS_CVTTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 139, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3201,9 +3337,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:192 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM"
+    // Pos:200 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM"
     {
-        ND_INS_CVTTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 132, 
+        ND_INS_CVTTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 140, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3217,9 +3353,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:193 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM"
+    // Pos:201 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM"
     {
-        ND_INS_CVTTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 133, 
+        ND_INS_CVTTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 141, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -3233,9 +3369,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:194 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM"
+    // Pos:202 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM"
     {
-        ND_INS_CVTTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 134, 
+        ND_INS_CVTTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 142, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3249,9 +3385,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:195 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM"
+    // Pos:203 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM"
     {
-        ND_INS_CVTTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 135, 
+        ND_INS_CVTTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 143, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -3265,9 +3401,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:196 Instruction:"CWD" Encoding:"ds16 0x99"/""
+    // Pos:204 Instruction:"CWD" Encoding:"ds16 0x99"/""
     {
-        ND_INS_CWD, ND_CAT_CONVERT, ND_SET_I386, 136, 
+        ND_INS_CWD, ND_CAT_CONVERT, ND_SET_I386, 144, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3281,9 +3417,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:197 Instruction:"CWDE" Encoding:"ds32 0x98"/""
+    // Pos:205 Instruction:"CWDE" Encoding:"ds32 0x98"/""
     {
-        ND_INS_CWDE, ND_CAT_CONVERT, ND_SET_I386, 137, 
+        ND_INS_CWDE, ND_CAT_CONVERT, ND_SET_I386, 145, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3297,9 +3433,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:198 Instruction:"DAA" Encoding:"0x27"/""
+    // Pos:206 Instruction:"DAA" Encoding:"0x27"/""
     {
-        ND_INS_DAA, ND_CAT_DECIMAL, ND_SET_I86, 138, 
+        ND_INS_DAA, ND_CAT_DECIMAL, ND_SET_I86, 146, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -3313,9 +3449,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:199 Instruction:"DAS" Encoding:"0x2F"/""
+    // Pos:207 Instruction:"DAS" Encoding:"0x2F"/""
     {
-        ND_INS_DAS, ND_CAT_DECIMAL, ND_SET_I86, 139, 
+        ND_INS_DAS, ND_CAT_DECIMAL, ND_SET_I86, 147, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -3329,9 +3465,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:200 Instruction:"DEC Zv" Encoding:"0x48"/"O"
+    // Pos:208 Instruction:"DEC Zv" Encoding:"0x48"/"O"
     {
-        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, 
+        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -3345,9 +3481,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:201 Instruction:"DEC Zv" Encoding:"0x49"/"O"
+    // Pos:209 Instruction:"DEC Zv" Encoding:"0x49"/"O"
     {
-        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, 
+        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -3361,9 +3497,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:202 Instruction:"DEC Zv" Encoding:"0x4A"/"O"
+    // Pos:210 Instruction:"DEC Zv" Encoding:"0x4A"/"O"
     {
-        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, 
+        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -3377,9 +3513,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:203 Instruction:"DEC Zv" Encoding:"0x4B"/"O"
+    // Pos:211 Instruction:"DEC Zv" Encoding:"0x4B"/"O"
     {
-        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, 
+        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -3393,9 +3529,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:204 Instruction:"DEC Zv" Encoding:"0x4C"/"O"
+    // Pos:212 Instruction:"DEC Zv" Encoding:"0x4C"/"O"
     {
-        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, 
+        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -3409,9 +3545,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:205 Instruction:"DEC Zv" Encoding:"0x4D"/"O"
+    // Pos:213 Instruction:"DEC Zv" Encoding:"0x4D"/"O"
     {
-        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, 
+        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -3425,9 +3561,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:206 Instruction:"DEC Zv" Encoding:"0x4E"/"O"
+    // Pos:214 Instruction:"DEC Zv" Encoding:"0x4E"/"O"
     {
-        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, 
+        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -3441,9 +3577,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:207 Instruction:"DEC Zv" Encoding:"0x4F"/"O"
+    // Pos:215 Instruction:"DEC Zv" Encoding:"0x4F"/"O"
     {
-        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, 
+        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -3457,9 +3593,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:208 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M"
+    // Pos:216 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M"
     {
-        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, 
+        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3473,9 +3609,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:209 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M"
+    // Pos:217 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M"
     {
-        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, 
+        ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 148, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3489,9 +3625,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:210 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M"
+    // Pos:218 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M"
     {
-        ND_INS_DELAY, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 141, 
+        ND_INS_DELAY, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 149, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3504,9 +3640,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:211 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M"
+    // Pos:219 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M"
     {
-        ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 142, 
+        ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 150, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3523,9 +3659,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:212 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M"
+    // Pos:220 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M"
     {
-        ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 142, 
+        ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 150, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3541,9 +3677,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:213 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM"
+    // Pos:221 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM"
     {
-        ND_INS_DIVPD, ND_CAT_SSE, ND_SET_SSE2, 143, 
+        ND_INS_DIVPD, ND_CAT_SSE, ND_SET_SSE2, 151, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3557,9 +3693,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:214 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM"
+    // Pos:222 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM"
     {
-        ND_INS_DIVPS, ND_CAT_SSE, ND_SET_SSE, 144, 
+        ND_INS_DIVPS, ND_CAT_SSE, ND_SET_SSE, 152, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -3573,9 +3709,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:215 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM"
+    // Pos:223 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM"
     {
-        ND_INS_DIVSD, ND_CAT_SSE, ND_SET_SSE2, 145, 
+        ND_INS_DIVSD, ND_CAT_SSE, ND_SET_SSE2, 153, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -3589,9 +3725,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:216 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM"
+    // Pos:224 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM"
     {
-        ND_INS_DIVSS, ND_CAT_SSE, ND_SET_SSE, 146, 
+        ND_INS_DIVSS, ND_CAT_SSE, ND_SET_SSE, 154, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -3605,9 +3741,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:217 Instruction:"DMINT" Encoding:"0x0F 0x39"/""
+    // Pos:225 Instruction:"DMINT" Encoding:"0x0F 0x39"/""
     {
-        ND_INS_DMINT, ND_CAT_SYSTEM, ND_SET_CYRIX, 147, 
+        ND_INS_DMINT, ND_CAT_SYSTEM, ND_SET_CYRIX, 155, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3620,9 +3756,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:218 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI"
+    // Pos:226 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI"
     {
-        ND_INS_DPPD, ND_CAT_SSE, ND_SET_SSE4, 148, 
+        ND_INS_DPPD, ND_CAT_SSE, ND_SET_SSE4, 156, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -3637,9 +3773,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:219 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI"
+    // Pos:227 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI"
     {
-        ND_INS_DPPS, ND_CAT_SSE, ND_SET_SSE4, 149, 
+        ND_INS_DPPS, ND_CAT_SSE, ND_SET_SSE4, 157, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -3654,9 +3790,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:220 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/""
+    // Pos:228 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/""
     {
-        ND_INS_EMMS, ND_CAT_MMX, ND_SET_MMX, 150, 
+        ND_INS_EMMS, ND_CAT_MMX, ND_SET_MMX, 158, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MMX, 
@@ -3669,9 +3805,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:221 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/""
+    // Pos:229 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/""
     {
-        ND_INS_ENCLS, ND_CAT_SGX, ND_SET_SGX, 151, 
+        ND_INS_ENCLS, ND_CAT_SGX, ND_SET_SGX, 159, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, 
@@ -3687,9 +3823,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:222 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/""
+    // Pos:230 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/""
     {
-        ND_INS_ENCLU, ND_CAT_SGX, ND_SET_SGX, 152, 
+        ND_INS_ENCLU, ND_CAT_SGX, ND_SET_SGX, 160, 
         0, 
         ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, 
@@ -3705,9 +3841,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:223 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/""
+    // Pos:231 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/""
     {
-        ND_INS_ENCLV, ND_CAT_SGX, ND_SET_SGX, 153, 
+        ND_INS_ENCLV, ND_CAT_SGX, ND_SET_SGX, 161, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, 
@@ -3723,9 +3859,48 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:224 Instruction:"ENDBR32" Encoding:"cet a0xF3 0x0F 0x1E /0xFB"/""
+    // Pos:232 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFA /r:reg"/"RM"
     {
-        ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 154, 
+        ND_INS_ENCODEKEY128, ND_CAT_AESKL, ND_SET_KL, 162, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, 
+        0,
+        0,
+        0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+        {
+            OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 3), 
+            OP(ND_OPT_SSE_XMM4, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 3), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:233 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFB /r:reg"/"RM"
+    {
+        ND_INS_ENCODEKEY256, ND_CAT_AESKL, ND_SET_KL, 163, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, 
+        0,
+        0,
+        0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+        {
+            OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 2), 
+            OP(ND_OPT_SSE_XMM2, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 5), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:234 Instruction:"ENDBR32" Encoding:"cet a0xF3 0x0F 0x1E /0xFB"/""
+    {
+        ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 164, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, 
@@ -3738,9 +3913,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:225 Instruction:"ENDBR64" Encoding:"cet a0xF3 0x0F 0x1E /0xFA"/""
+    // Pos:235 Instruction:"ENDBR64" Encoding:"cet a0xF3 0x0F 0x1E /0xFA"/""
     {
-        ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 155, 
+        ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 165, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, 
@@ -3753,9 +3928,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:226 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M"
+    // Pos:236 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M"
     {
-        ND_INS_ENQCMD, ND_CAT_ENQCMD, ND_SET_ENQCMD, 156, 
+        ND_INS_ENQCMD, ND_CAT_ENQCMD, ND_SET_ENQCMD, 166, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, 
@@ -3770,9 +3945,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:227 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M"
+    // Pos:237 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M"
     {
-        ND_INS_ENQCMDS, ND_CAT_ENQCMD, ND_SET_ENQCMD, 157, 
+        ND_INS_ENQCMDS, ND_CAT_ENQCMD, ND_SET_ENQCMD, 167, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, 
@@ -3787,9 +3962,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:228 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II"
+    // Pos:238 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II"
     {
-        ND_INS_ENTER, ND_CAT_MISC, ND_SET_I186, 158, 
+        ND_INS_ENTER, ND_CAT_MISC, ND_SET_I186, 168, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -3806,9 +3981,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:229 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI"
+    // Pos:239 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI"
     {
-        ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 159, 
+        ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 169, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -3823,9 +3998,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:230 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII"
+    // Pos:240 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII"
     {
-        ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 160, 
+        ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 170, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
@@ -3840,9 +4015,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:231 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM"
+    // Pos:241 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM"
     {
-        ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 160, 
+        ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 170, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
@@ -3856,9 +4031,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:232 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/""
+    // Pos:242 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/""
     {
-        ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 161, 
+        ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 171, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3871,9 +4046,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:233 Instruction:"FABS" Encoding:"0xD9 /0xE1"/""
+    // Pos:243 Instruction:"FABS" Encoding:"0xD9 /0xE1"/""
     {
-        ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 162, 
+        ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 172, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3886,9 +4061,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:234 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M"
+    // Pos:244 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M"
     {
-        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, 
+        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 173, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3903,9 +4078,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:235 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M"
+    // Pos:245 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M"
     {
-        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, 
+        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 173, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3920,9 +4095,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:236 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M"
+    // Pos:246 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M"
     {
-        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, 
+        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 173, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3937,9 +4112,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:237 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M"
+    // Pos:247 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M"
     {
-        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, 
+        ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 173, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3954,9 +4129,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:238 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M"
+    // Pos:248 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M"
     {
-        ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 164, 
+        ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 174, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3971,9 +4146,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:239 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M"
+    // Pos:249 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M"
     {
-        ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 165, 
+        ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 175, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -3988,9 +4163,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:240 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M"
+    // Pos:250 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M"
     {
-        ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 166, 
+        ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 176, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4005,9 +4180,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:241 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/""
+    // Pos:251 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/""
     {
-        ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 167, 
+        ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 177, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4020,9 +4195,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:242 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M"
+    // Pos:252 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M"
     {
-        ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 168, 
+        ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 178, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4038,9 +4213,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:243 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M"
+    // Pos:253 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M"
     {
-        ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 169, 
+        ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 179, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4056,9 +4231,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:244 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M"
+    // Pos:254 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M"
     {
-        ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 170, 
+        ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 180, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4074,9 +4249,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:245 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M"
+    // Pos:255 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M"
     {
-        ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 171, 
+        ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 181, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4092,9 +4267,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:246 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M"
+    // Pos:256 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M"
     {
-        ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 172, 
+        ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 182, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4110,9 +4285,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:247 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M"
+    // Pos:257 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M"
     {
-        ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 173, 
+        ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 183, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4128,9 +4303,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:248 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M"
+    // Pos:258 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M"
     {
-        ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 174, 
+        ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 184, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4146,9 +4321,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:249 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M"
+    // Pos:259 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M"
     {
-        ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 175, 
+        ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 185, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4164,9 +4339,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:250 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M"
+    // Pos:260 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M"
     {
-        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, 
+        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 186, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4181,9 +4356,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:251 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M"
+    // Pos:261 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M"
     {
-        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, 
+        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 186, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4198,9 +4373,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:252 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M"
+    // Pos:262 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M"
     {
-        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, 
+        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 186, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4215,9 +4390,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:253 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M"
+    // Pos:263 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M"
     {
-        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, 
+        ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 186, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4232,9 +4407,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:254 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M"
+    // Pos:264 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M"
     {
-        ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 177, 
+        ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 187, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4250,9 +4425,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:255 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M"
+    // Pos:265 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M"
     {
-        ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 178, 
+        ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 188, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4268,9 +4443,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:256 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M"
+    // Pos:266 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M"
     {
-        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, 
+        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4285,9 +4460,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:257 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M"
+    // Pos:267 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M"
     {
-        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, 
+        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4302,9 +4477,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:258 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M"
+    // Pos:268 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M"
     {
-        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, 
+        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4319,9 +4494,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:259 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M"
+    // Pos:269 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M"
     {
-        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, 
+        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4336,9 +4511,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:260 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M"
+    // Pos:270 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M"
     {
-        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, 
+        ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 189, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4353,9 +4528,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:261 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/""
+    // Pos:271 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/""
     {
-        ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 180, 
+        ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 190, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4368,9 +4543,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:262 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/""
+    // Pos:272 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/""
     {
-        ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 181, 
+        ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 191, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4383,9 +4558,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:263 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/""
+    // Pos:273 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/""
     {
-        ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 182, 
+        ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 192, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4398,9 +4573,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:264 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M"
+    // Pos:274 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M"
     {
-        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, 
+        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4415,9 +4590,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:265 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M"
+    // Pos:275 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M"
     {
-        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, 
+        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4432,9 +4607,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:266 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M"
+    // Pos:276 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M"
     {
-        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, 
+        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4449,9 +4624,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:267 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M"
+    // Pos:277 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M"
     {
-        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, 
+        ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4466,9 +4641,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:268 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M"
+    // Pos:278 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M"
     {
-        ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 184, 
+        ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 194, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4483,9 +4658,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:269 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M"
+    // Pos:279 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M"
     {
-        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, 
+        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 195, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4500,9 +4675,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:270 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M"
+    // Pos:280 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M"
     {
-        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, 
+        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 195, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4517,9 +4692,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:271 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M"
+    // Pos:281 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M"
     {
-        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, 
+        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 195, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4534,9 +4709,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:272 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M"
+    // Pos:282 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M"
     {
-        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, 
+        ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 195, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4551,9 +4726,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:273 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M"
+    // Pos:283 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M"
     {
-        ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 186, 
+        ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 196, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4568,9 +4743,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:274 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/""
+    // Pos:284 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/""
     {
-        ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 187, 
+        ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 197, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_3DNOW, 
@@ -4583,9 +4758,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:275 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M"
+    // Pos:285 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M"
     {
-        ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 188, 
+        ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 198, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4599,9 +4774,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:276 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M"
+    // Pos:286 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M"
     {
-        ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 189, 
+        ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 199, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4615,9 +4790,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:277 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M"
+    // Pos:287 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M"
     {
-        ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 190, 
+        ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 200, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4632,9 +4807,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:278 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M"
+    // Pos:288 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M"
     {
-        ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 190, 
+        ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 200, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4649,9 +4824,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:279 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M"
+    // Pos:289 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M"
     {
-        ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 191, 
+        ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 201, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4666,9 +4841,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:280 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M"
+    // Pos:290 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M"
     {
-        ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 191, 
+        ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 201, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4683,9 +4858,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:281 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M"
+    // Pos:291 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M"
     {
-        ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 192, 
+        ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 202, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4700,9 +4875,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:282 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M"
+    // Pos:292 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M"
     {
-        ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 192, 
+        ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 202, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4717,9 +4892,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:283 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M"
+    // Pos:293 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M"
     {
-        ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, 
+        ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 203, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4734,9 +4909,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:284 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M"
+    // Pos:294 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M"
     {
-        ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, 
+        ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 203, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4751,9 +4926,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:285 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M"
+    // Pos:295 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M"
     {
-        ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 194, 
+        ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 204, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4768,9 +4943,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:286 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M"
+    // Pos:296 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M"
     {
-        ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 194, 
+        ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 204, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4785,9 +4960,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:287 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M"
+    // Pos:297 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M"
     {
-        ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 195, 
+        ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 205, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4802,9 +4977,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:288 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M"
+    // Pos:298 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M"
     {
-        ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 195, 
+        ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 205, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4819,9 +4994,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:289 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M"
+    // Pos:299 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M"
     {
-        ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 195, 
+        ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 205, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4836,9 +5011,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:290 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M"
+    // Pos:300 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M"
     {
-        ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 196, 
+        ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 206, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4853,9 +5028,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:291 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M"
+    // Pos:301 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M"
     {
-        ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 196, 
+        ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 206, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4870,9 +5045,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:292 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/""
+    // Pos:302 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/""
     {
-        ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 197, 
+        ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 207, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4885,9 +5060,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:293 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M"
+    // Pos:303 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M"
     {
-        ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 198, 
+        ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 208, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4902,9 +5077,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:294 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M"
+    // Pos:304 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M"
     {
-        ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 198, 
+        ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 208, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4919,9 +5094,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:295 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M"
+    // Pos:305 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M"
     {
-        ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 199, 
+        ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 209, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4936,9 +5111,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:296 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M"
+    // Pos:306 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M"
     {
-        ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 199, 
+        ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 209, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4953,9 +5128,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:297 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M"
+    // Pos:307 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M"
     {
-        ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 199, 
+        ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 209, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4970,9 +5145,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:298 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M"
+    // Pos:308 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M"
     {
-        ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 200, 
+        ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 210, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -4987,9 +5162,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:299 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M"
+    // Pos:309 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M"
     {
-        ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 200, 
+        ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 210, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5004,9 +5179,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:300 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M"
+    // Pos:310 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M"
     {
-        ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 200, 
+        ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 210, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5021,9 +5196,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:301 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M"
+    // Pos:311 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M"
     {
-        ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 201, 
+        ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 211, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5038,9 +5213,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:302 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M"
+    // Pos:312 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M"
     {
-        ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 201, 
+        ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 211, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5055,9 +5230,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:303 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M"
+    // Pos:313 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M"
     {
-        ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 202, 
+        ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 212, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5072,9 +5247,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:304 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M"
+    // Pos:314 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M"
     {
-        ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 202, 
+        ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 212, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5089,9 +5264,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:305 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M"
+    // Pos:315 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M"
     {
-        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, 
+        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 213, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5106,9 +5281,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:306 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M"
+    // Pos:316 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M"
     {
-        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, 
+        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 213, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5123,9 +5298,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:307 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M"
+    // Pos:317 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M"
     {
-        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, 
+        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 213, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5140,9 +5315,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:308 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M"
+    // Pos:318 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M"
     {
-        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, 
+        ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 213, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5157,9 +5332,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:309 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/""
+    // Pos:319 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/""
     {
-        ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 204, 
+        ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 214, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5172,9 +5347,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:310 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M"
+    // Pos:320 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M"
     {
-        ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 205, 
+        ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 215, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5189,9 +5364,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:311 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M"
+    // Pos:321 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M"
     {
-        ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 206, 
+        ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 216, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5205,9 +5380,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:312 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/""
+    // Pos:322 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/""
     {
-        ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 207, 
+        ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 217, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5220,9 +5395,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:313 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/""
+    // Pos:323 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/""
     {
-        ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 208, 
+        ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 218, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5235,9 +5410,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:314 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/""
+    // Pos:324 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/""
     {
-        ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 209, 
+        ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 219, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5250,9 +5425,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:315 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/""
+    // Pos:325 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/""
     {
-        ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 210, 
+        ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 220, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5265,9 +5440,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:316 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/""
+    // Pos:326 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/""
     {
-        ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 211, 
+        ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 221, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5280,9 +5455,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:317 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/""
+    // Pos:327 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/""
     {
-        ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 212, 
+        ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 222, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5295,9 +5470,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:318 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M"
+    // Pos:328 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M"
     {
-        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, 
+        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 223, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5312,9 +5487,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:319 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M"
+    // Pos:329 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M"
     {
-        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, 
+        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 223, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5329,9 +5504,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:320 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M"
+    // Pos:330 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M"
     {
-        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, 
+        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 223, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5346,9 +5521,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:321 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M"
+    // Pos:331 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M"
     {
-        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, 
+        ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 223, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5363,9 +5538,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:322 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M"
+    // Pos:332 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M"
     {
-        ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 214, 
+        ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 224, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5380,9 +5555,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:323 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/""
+    // Pos:333 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/""
     {
-        ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 215, 
+        ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 225, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5395,9 +5570,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:324 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/""
+    // Pos:334 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/""
     {
-        ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 216, 
+        ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 226, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5410,9 +5585,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:325 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/""
+    // Pos:335 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/""
     {
-        ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 217, 
+        ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 227, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5427,9 +5602,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:326 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/""
+    // Pos:336 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/""
     {
-        ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 218, 
+        ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 228, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5442,9 +5617,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:327 Instruction:"FNOP" Encoding:"0xDB /0xE0"/""
+    // Pos:337 Instruction:"FNOP" Encoding:"0xDB /0xE0"/""
     {
-        ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 218, 
+        ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 228, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5457,9 +5632,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:328 Instruction:"FNOP" Encoding:"0xDB /0xE4"/""
+    // Pos:338 Instruction:"FNOP" Encoding:"0xDB /0xE4"/""
     {
-        ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 218, 
+        ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 228, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5472,9 +5647,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:329 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M"
+    // Pos:339 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M"
     {
-        ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 219, 
+        ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 229, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5490,9 +5665,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:330 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M"
+    // Pos:340 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M"
     {
-        ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 220, 
+        ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 230, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5507,9 +5682,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:331 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M"
+    // Pos:341 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M"
     {
-        ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 221, 
+        ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 231, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5523,9 +5698,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:332 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M"
+    // Pos:342 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M"
     {
-        ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 222, 
+        ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 232, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5539,9 +5714,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:333 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/""
+    // Pos:343 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/""
     {
-        ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 222, 
+        ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 232, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5555,9 +5730,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:334 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/""
+    // Pos:344 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/""
     {
-        ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 223, 
+        ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 233, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5570,9 +5745,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:335 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/""
+    // Pos:345 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/""
     {
-        ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 224, 
+        ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 234, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5585,9 +5760,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:336 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/""
+    // Pos:346 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/""
     {
-        ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 225, 
+        ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 235, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5600,9 +5775,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:337 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/""
+    // Pos:347 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/""
     {
-        ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 226, 
+        ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 236, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5615,9 +5790,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:338 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/""
+    // Pos:348 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/""
     {
-        ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 227, 
+        ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 237, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5630,9 +5805,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:339 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/""
+    // Pos:349 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/""
     {
-        ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 228, 
+        ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 238, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5645,9 +5820,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:340 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M"
+    // Pos:350 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M"
     {
-        ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 229, 
+        ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 239, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5661,9 +5836,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:341 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/""
+    // Pos:351 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/""
     {
-        ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 230, 
+        ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 240, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5676,9 +5851,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:342 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/""
+    // Pos:352 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/""
     {
-        ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 231, 
+        ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 241, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5691,9 +5866,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:343 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/""
+    // Pos:353 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/""
     {
-        ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 232, 
+        ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 242, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5706,9 +5881,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:344 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/""
+    // Pos:354 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/""
     {
-        ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 233, 
+        ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 243, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5721,9 +5896,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:345 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M"
+    // Pos:355 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M"
     {
-        ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, 
+        ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 244, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5738,9 +5913,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:346 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M"
+    // Pos:356 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M"
     {
-        ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, 
+        ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 244, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5755,9 +5930,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:347 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M"
+    // Pos:357 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M"
     {
-        ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, 
+        ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 244, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5772,9 +5947,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:348 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/""
+    // Pos:358 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/""
     {
-        ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 235, 
+        ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 245, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5787,9 +5962,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:349 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M"
+    // Pos:359 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M"
     {
-        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, 
+        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5804,9 +5979,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:350 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M"
+    // Pos:360 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M"
     {
-        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, 
+        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5821,9 +5996,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:351 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M"
+    // Pos:361 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M"
     {
-        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, 
+        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5838,9 +6013,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:352 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M"
+    // Pos:362 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M"
     {
-        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, 
+        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5855,9 +6030,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:353 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M"
+    // Pos:363 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M"
     {
-        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, 
+        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5872,9 +6047,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:354 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M"
+    // Pos:364 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M"
     {
-        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, 
+        ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5889,9 +6064,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:355 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M"
+    // Pos:365 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M"
     {
-        ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 237, 
+        ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 247, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5906,9 +6081,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:356 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/""
+    // Pos:366 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/""
     {
-        ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 238, 
+        ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 248, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5921,9 +6096,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:357 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M"
+    // Pos:367 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M"
     {
-        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, 
+        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 249, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5938,9 +6113,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:358 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M"
+    // Pos:368 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M"
     {
-        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, 
+        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 249, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5955,9 +6130,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:359 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M"
+    // Pos:369 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M"
     {
-        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, 
+        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 249, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5972,9 +6147,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:360 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M"
+    // Pos:370 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M"
     {
-        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, 
+        ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 249, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -5989,9 +6164,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:361 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M"
+    // Pos:371 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M"
     {
-        ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 240, 
+        ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 250, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6006,9 +6181,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:362 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M"
+    // Pos:372 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M"
     {
-        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, 
+        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 251, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6023,9 +6198,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:363 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M"
+    // Pos:373 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M"
     {
-        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, 
+        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 251, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6040,9 +6215,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:364 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M"
+    // Pos:374 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M"
     {
-        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, 
+        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 251, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6057,9 +6232,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:365 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M"
+    // Pos:375 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M"
     {
-        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, 
+        ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 251, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6074,9 +6249,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:366 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M"
+    // Pos:376 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M"
     {
-        ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 242, 
+        ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 252, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6091,9 +6266,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:367 Instruction:"FTST" Encoding:"0xD9 /0xE4"/""
+    // Pos:377 Instruction:"FTST" Encoding:"0xD9 /0xE4"/""
     {
-        ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 243, 
+        ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 253, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6106,9 +6281,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:368 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M"
+    // Pos:378 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M"
     {
-        ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 244, 
+        ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 254, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6123,9 +6298,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:369 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M"
+    // Pos:379 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M"
     {
-        ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 245, 
+        ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 255, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6141,9 +6316,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:370 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M"
+    // Pos:380 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M"
     {
-        ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 246, 
+        ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 256, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6159,9 +6334,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:371 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M"
+    // Pos:381 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M"
     {
-        ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 247, 
+        ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 257, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6176,9 +6351,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:372 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/""
+    // Pos:382 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/""
     {
-        ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 248, 
+        ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 258, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6191,9 +6366,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:373 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/""
+    // Pos:383 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/""
     {
-        ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 249, 
+        ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 259, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6206,9 +6381,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:374 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M"
+    // Pos:384 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M"
     {
-        ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 250, 
+        ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 260, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6223,9 +6398,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:375 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M"
+    // Pos:385 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M"
     {
-        ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 250, 
+        ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 260, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6240,9 +6415,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:376 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M"
+    // Pos:386 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M"
     {
-        ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 250, 
+        ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 260, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6257,9 +6432,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:377 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M"
+    // Pos:387 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M"
     {
-        ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 251, 
+        ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 261, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 
@@ -6273,9 +6448,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:378 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M"
+    // Pos:388 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M"
     {
-        ND_INS_FXRSTOR64, ND_CAT_SSE, ND_SET_FXSAVE, 252, 
+        ND_INS_FXRSTOR64, ND_CAT_SSE, ND_SET_FXSAVE, 262, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 
@@ -6289,9 +6464,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:379 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M"
+    // Pos:389 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M"
     {
-        ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 253, 
+        ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 263, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 
@@ -6305,9 +6480,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:380 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M"
+    // Pos:390 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M"
     {
-        ND_INS_FXSAVE64, ND_CAT_SSE, ND_SET_FXSAVE, 254, 
+        ND_INS_FXSAVE64, ND_CAT_SSE, ND_SET_FXSAVE, 264, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 
@@ -6321,9 +6496,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:381 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/""
+    // Pos:391 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/""
     {
-        ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 255, 
+        ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 265, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6336,9 +6511,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:382 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/""
+    // Pos:392 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/""
     {
-        ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 256, 
+        ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 266, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6351,9 +6526,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:383 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/""
+    // Pos:393 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/""
     {
-        ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 257, 
+        ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 267, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6366,9 +6541,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:384 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/""
+    // Pos:394 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/""
     {
-        ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 258, 
+        ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 268, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SMX, 
@@ -6382,9 +6557,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:385 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI"
+    // Pos:395 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI"
     {
-        ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 259, 
+        ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 269, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -6399,9 +6574,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:386 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI"
+    // Pos:396 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI"
     {
-        ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 260, 
+        ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 270, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -6416,9 +6591,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:387 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM"
+    // Pos:397 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM"
     {
-        ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 261, 
+        ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 271, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -6432,9 +6607,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:388 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM"
+    // Pos:398 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM"
     {
-        ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 262, 
+        ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 272, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -6448,9 +6623,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:389 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM"
+    // Pos:399 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM"
     {
-        ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 263, 
+        ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 273, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -6464,9 +6639,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:390 Instruction:"HLT" Encoding:"0xF4"/""
+    // Pos:400 Instruction:"HLT" Encoding:"0xF4"/""
     {
-        ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 264, 
+        ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 274, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6479,9 +6654,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:391 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM"
+    // Pos:401 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM"
     {
-        ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 265, 
+        ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 275, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -6495,9 +6670,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:392 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM"
+    // Pos:402 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM"
     {
-        ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 266, 
+        ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 276, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -6511,9 +6686,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:393 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M"
+    // Pos:403 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M"
     {
-        ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 267, 
+        ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 277, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6530,9 +6705,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:394 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M"
+    // Pos:404 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M"
     {
-        ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 267, 
+        ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 277, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6548,9 +6723,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:395 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM"
+    // Pos:405 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 278, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6565,9 +6740,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:396 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI"
+    // Pos:406 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 278, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6583,9 +6758,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:397 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI"
+    // Pos:407 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 278, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6601,9 +6776,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:398 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M"
+    // Pos:408 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 278, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6619,9 +6794,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:399 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M"
+    // Pos:409 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 278, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6637,9 +6812,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:400 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I"
+    // Pos:410 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I"
     {
-        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, 
+        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 279, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6654,9 +6829,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:401 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I"
+    // Pos:411 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I"
     {
-        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, 
+        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 279, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6671,9 +6846,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:402 Instruction:"IN AL,DX" Encoding:"0xEC"/""
+    // Pos:412 Instruction:"IN AL,DX" Encoding:"0xEC"/""
     {
-        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, 
+        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 279, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6688,9 +6863,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:403 Instruction:"IN eAX,DX" Encoding:"0xED"/""
+    // Pos:413 Instruction:"IN eAX,DX" Encoding:"0xED"/""
     {
-        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, 
+        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 279, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6705,9 +6880,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:404 Instruction:"INC Zv" Encoding:"0x40"/"O"
+    // Pos:414 Instruction:"INC Zv" Encoding:"0x40"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6721,9 +6896,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:405 Instruction:"INC Zv" Encoding:"0x41"/"O"
+    // Pos:415 Instruction:"INC Zv" Encoding:"0x41"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6737,9 +6912,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:406 Instruction:"INC Zv" Encoding:"0x42"/"O"
+    // Pos:416 Instruction:"INC Zv" Encoding:"0x42"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6753,9 +6928,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:407 Instruction:"INC Zv" Encoding:"0x43"/"O"
+    // Pos:417 Instruction:"INC Zv" Encoding:"0x43"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6769,9 +6944,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:408 Instruction:"INC Zv" Encoding:"0x44"/"O"
+    // Pos:418 Instruction:"INC Zv" Encoding:"0x44"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6785,9 +6960,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:409 Instruction:"INC Zv" Encoding:"0x45"/"O"
+    // Pos:419 Instruction:"INC Zv" Encoding:"0x45"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6801,9 +6976,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:410 Instruction:"INC Zv" Encoding:"0x46"/"O"
+    // Pos:420 Instruction:"INC Zv" Encoding:"0x46"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6817,9 +6992,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:411 Instruction:"INC Zv" Encoding:"0x47"/"O"
+    // Pos:421 Instruction:"INC Zv" Encoding:"0x47"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -6833,9 +7008,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:412 Instruction:"INC Eb" Encoding:"0xFE /0"/"M"
+    // Pos:422 Instruction:"INC Eb" Encoding:"0xFE /0"/"M"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6849,9 +7024,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:413 Instruction:"INC Ev" Encoding:"0xFF /0"/"M"
+    // Pos:423 Instruction:"INC Ev" Encoding:"0xFF /0"/"M"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 280, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -6865,9 +7040,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:414 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M"
+    // Pos:424 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M"
     {
-        ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 271, 
+        ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 281, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -6882,9 +7057,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:415 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M"
+    // Pos:425 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M"
     {
-        ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 272, 
+        ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 282, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -6899,9 +7074,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:416 Instruction:"INSB Yb,DX" Encoding:"0x6C"/""
+    // Pos:426 Instruction:"INSB Yb,DX" Encoding:"0x6C"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 273, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 283, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6917,9 +7092,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:417 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/""
+    // Pos:427 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 273, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 283, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6936,9 +7111,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:418 Instruction:"INSD Yz,DX" Encoding:"0x6D"/""
+    // Pos:428 Instruction:"INSD Yz,DX" Encoding:"0x6D"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 274, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 284, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6954,9 +7129,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:419 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/""
+    // Pos:429 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 274, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 284, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -6973,9 +7148,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:420 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI"
+    // Pos:430 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI"
     {
-        ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 275, 
+        ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 285, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -6990,9 +7165,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:421 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI"
+    // Pos:431 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI"
     {
-        ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 275, 
+        ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 285, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -7007,9 +7182,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:422 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII"
+    // Pos:432 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII"
     {
-        ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 276, 
+        ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 286, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
@@ -7025,9 +7200,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:423 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM"
+    // Pos:433 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM"
     {
-        ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 276, 
+        ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 286, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
@@ -7041,9 +7216,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:424 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/""
+    // Pos:434 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 277, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 287, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7059,9 +7234,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:425 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/""
+    // Pos:435 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 277, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 287, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7078,9 +7253,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:426 Instruction:"INT Ib" Encoding:"0xCD ib"/"I"
+    // Pos:436 Instruction:"INT Ib" Encoding:"0xCD ib"/"I"
     {
-        ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 278, 
+        ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 288, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7098,9 +7273,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:427 Instruction:"INT1" Encoding:"0xF1"/""
+    // Pos:437 Instruction:"INT1" Encoding:"0xF1"/""
     {
-        ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 279, 
+        ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 289, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7116,9 +7291,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:428 Instruction:"INT3" Encoding:"0xCC"/""
+    // Pos:438 Instruction:"INT3" Encoding:"0xCC"/""
     {
-        ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 280, 
+        ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 290, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7135,9 +7310,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:429 Instruction:"INTO" Encoding:"0xCE"/""
+    // Pos:439 Instruction:"INTO" Encoding:"0xCE"/""
     {
-        ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 281, 
+        ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 291, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -7154,9 +7329,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:430 Instruction:"INVD" Encoding:"0x0F 0x08"/""
+    // Pos:440 Instruction:"INVD" Encoding:"0x0F 0x08"/""
     {
-        ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 282, 
+        ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 292, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -7169,9 +7344,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:431 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM"
+    // Pos:441 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM"
     {
-        ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 283, 
+        ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 293, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -7186,9 +7361,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:432 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M"
+    // Pos:442 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M"
     {
-        ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 284, 
+        ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 294, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, 
@@ -7201,9 +7376,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:433 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/""
+    // Pos:443 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/""
     {
-        ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 285, 
+        ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 295, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -7217,9 +7392,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:434 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/""
+    // Pos:444 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/""
     {
-        ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 286, 
+        ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 296, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, 
@@ -7234,9 +7409,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:435 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM"
+    // Pos:445 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM"
     {
-        ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 287, 
+        ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 297, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_INVPCID, 
@@ -7250,9 +7425,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:436 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM"
+    // Pos:446 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM"
     {
-        ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 288, 
+        ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 298, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -7267,9 +7442,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:437 Instruction:"IRETD" Encoding:"ds32 0xCF"/""
+    // Pos:447 Instruction:"IRETD" Encoding:"ds32 0xCF"/""
     {
-        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 289, 
+        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 299, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -7286,9 +7461,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:438 Instruction:"IRETQ" Encoding:"ds64 0xCF"/""
+    // Pos:448 Instruction:"IRETQ" Encoding:"ds64 0xCF"/""
     {
-        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 290, 
+        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 300, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -7305,9 +7480,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:439 Instruction:"IRETW" Encoding:"ds16 0xCF"/""
+    // Pos:449 Instruction:"IRETW" Encoding:"ds16 0xCF"/""
     {
-        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 291, 
+        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 301, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -7324,9 +7499,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:440 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D"
+    // Pos:450 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 292, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7341,9 +7516,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:441 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D"
+    // Pos:451 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 292, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7358,9 +7533,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:442 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D"
+    // Pos:452 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 293, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7375,9 +7550,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:443 Instruction:"JC Jb" Encoding:"0x72 cb"/"D"
+    // Pos:453 Instruction:"JC Jb" Encoding:"0x72 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 293, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7392,9 +7567,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:444 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D"
+    // Pos:454 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D"
     {
-        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 294, 
+        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 304, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -7409,9 +7584,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:445 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D"
+    // Pos:455 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D"
     {
-        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 295, 
+        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 305, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -7426,9 +7601,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:446 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D"
+    // Pos:456 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 296, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7443,9 +7618,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:447 Instruction:"JL Jb" Encoding:"0x7C cb"/"D"
+    // Pos:457 Instruction:"JL Jb" Encoding:"0x7C cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 296, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7460,9 +7635,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:448 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D"
+    // Pos:458 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 297, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7477,9 +7652,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:449 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D"
+    // Pos:459 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 297, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7494,9 +7669,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:450 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D"
+    // Pos:460 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D"
     {
-        ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 298, 
+        ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 308, 
         ND_PREF_BND, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -7510,9 +7685,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:451 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D"
+    // Pos:461 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D"
     {
-        ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 298, 
+        ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 308, 
         ND_PREF_BND, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -7526,9 +7701,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:452 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M"
+    // Pos:462 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M"
     {
-        ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 298, 
+        ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 308, 
         ND_PREF_BND|ND_PREF_DNT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, 
@@ -7542,9 +7717,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:453 Instruction:"JMPE Ev" Encoding:"0x0F 0x00 /6"/"M"
+    // Pos:463 Instruction:"JMPE Ev" Encoding:"0x0F 0x00 /6"/"M"
     {
-        ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 299, 
+        ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 309, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -7558,9 +7733,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:454 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D"
+    // Pos:464 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D"
     {
-        ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 299, 
+        ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 309, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -7574,9 +7749,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:455 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D"
+    // Pos:465 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D"
     {
-        ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 300, 
+        ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 310, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -7591,9 +7766,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:456 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M"
+    // Pos:466 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M"
     {
-        ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 300, 
+        ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 310, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, 
@@ -7608,9 +7783,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:457 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D"
+    // Pos:467 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 311, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7625,9 +7800,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:458 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D"
+    // Pos:468 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 311, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7642,9 +7817,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:459 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D"
+    // Pos:469 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7659,9 +7834,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:460 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D"
+    // Pos:470 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7676,9 +7851,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:461 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D"
+    // Pos:471 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7693,9 +7868,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:462 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D"
+    // Pos:472 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7710,9 +7885,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:463 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D"
+    // Pos:473 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 314, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7727,9 +7902,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:464 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D"
+    // Pos:474 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 314, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7744,9 +7919,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:465 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D"
+    // Pos:475 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 315, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7761,9 +7936,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:466 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D"
+    // Pos:476 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 315, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7778,9 +7953,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:467 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D"
+    // Pos:477 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 316, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7795,9 +7970,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:468 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D"
+    // Pos:478 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 316, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7812,9 +7987,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:469 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D"
+    // Pos:479 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 317, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7829,9 +8004,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:470 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D"
+    // Pos:480 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 317, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7846,9 +8021,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:471 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D"
+    // Pos:481 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 318, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7863,9 +8038,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:472 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D"
+    // Pos:482 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 318, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7880,9 +8055,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:473 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D"
+    // Pos:483 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 319, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7897,9 +8072,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:474 Instruction:"JO Jb" Encoding:"0x70 cb"/"D"
+    // Pos:484 Instruction:"JO Jb" Encoding:"0x70 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 319, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7914,9 +8089,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:475 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D"
+    // Pos:485 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 320, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7931,9 +8106,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:476 Instruction:"JP Jb" Encoding:"0x7A cb"/"D"
+    // Pos:486 Instruction:"JP Jb" Encoding:"0x7A cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 320, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7948,9 +8123,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:477 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D"
+    // Pos:487 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D"
     {
-        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 311, 
+        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 321, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -7965,9 +8140,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:478 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D"
+    // Pos:488 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 322, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7982,9 +8157,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:479 Instruction:"JS Jb" Encoding:"0x78 cb"/"D"
+    // Pos:489 Instruction:"JS Jb" Encoding:"0x78 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 322, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -7999,9 +8174,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:480 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D"
+    // Pos:490 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 323, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8016,9 +8191,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:481 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D"
+    // Pos:491 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 323, 
         ND_PREF_BND|ND_PREF_BHINT, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
@@ -8033,9 +8208,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:482 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM"
+    // Pos:492 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM"
     {
-        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 314, 
+        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 324, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8050,9 +8225,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:483 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM"
+    // Pos:493 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM"
     {
-        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 315, 
+        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 325, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8067,9 +8242,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:484 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM"
+    // Pos:494 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM"
     {
-        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 316, 
+        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 326, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8084,9 +8259,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:485 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM"
+    // Pos:495 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM"
     {
-        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 317, 
+        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 327, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8101,9 +8276,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:486 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM"
+    // Pos:496 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM"
     {
-        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 318, 
+        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8118,9 +8293,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:487 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM"
+    // Pos:497 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM"
     {
-        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 319, 
+        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 329, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8135,9 +8310,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:488 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM"
+    // Pos:498 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM"
     {
-        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 320, 
+        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 330, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8152,9 +8327,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:489 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM"
+    // Pos:499 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM"
     {
-        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 321, 
+        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 331, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8169,9 +8344,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:490 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM"
+    // Pos:500 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM"
     {
-        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 322, 
+        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 332, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8186,9 +8361,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:491 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM"
+    // Pos:501 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM"
     {
-        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 323, 
+        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 333, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8203,9 +8378,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:492 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM"
+    // Pos:502 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM"
     {
-        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 324, 
+        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 334, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8220,9 +8395,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:493 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM"
+    // Pos:503 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM"
     {
-        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 325, 
+        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 335, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8237,9 +8412,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:494 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM"
+    // Pos:504 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM"
     {
-        ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 326, 
+        ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 336, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -8253,9 +8428,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:495 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM"
+    // Pos:505 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM"
     {
-        ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 327, 
+        ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 337, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -8269,9 +8444,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:496 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM"
+    // Pos:506 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 338, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8285,9 +8460,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:497 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM"
+    // Pos:507 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 338, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8301,9 +8476,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:498 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR"
+    // Pos:508 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 338, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8317,9 +8492,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:499 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM"
+    // Pos:509 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 338, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8333,9 +8508,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:500 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM"
+    // Pos:510 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 338, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8349,9 +8524,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:501 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM"
+    // Pos:511 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 339, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8365,9 +8540,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:502 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM"
+    // Pos:512 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 339, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8381,9 +8556,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:503 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR"
+    // Pos:513 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 339, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8397,9 +8572,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:504 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM"
+    // Pos:514 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 339, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8413,9 +8588,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:505 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM"
+    // Pos:515 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 339, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8429,9 +8604,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:506 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM"
+    // Pos:516 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8445,9 +8620,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:507 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM"
+    // Pos:517 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8461,9 +8636,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:508 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR"
+    // Pos:518 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8477,9 +8652,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:509 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM"
+    // Pos:519 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8493,9 +8668,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:510 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM"
+    // Pos:520 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 340, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8509,9 +8684,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:511 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM"
+    // Pos:521 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8525,9 +8700,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:512 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM"
+    // Pos:522 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8541,9 +8716,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:513 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR"
+    // Pos:523 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8557,9 +8732,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:514 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM"
+    // Pos:524 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8573,9 +8748,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:515 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM"
+    // Pos:525 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8589,9 +8764,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:516 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM"
+    // Pos:526 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM"
     {
-        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 332, 
+        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 342, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8605,9 +8780,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:517 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM"
+    // Pos:527 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM"
     {
-        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 333, 
+        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 343, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8621,9 +8796,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:518 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM"
+    // Pos:528 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM"
     {
-        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 334, 
+        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 344, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8637,9 +8812,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:519 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM"
+    // Pos:529 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM"
     {
-        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 335, 
+        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 345, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8653,9 +8828,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:520 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM"
+    // Pos:530 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM"
     {
-        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 336, 
+        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 346, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8670,9 +8845,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:521 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM"
+    // Pos:531 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM"
     {
-        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 337, 
+        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 347, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8687,9 +8862,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:522 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM"
+    // Pos:532 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM"
     {
-        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 338, 
+        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 348, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8704,9 +8879,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:523 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM"
+    // Pos:533 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM"
     {
-        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 339, 
+        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 349, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8721,9 +8896,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:524 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM"
+    // Pos:534 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM"
     {
-        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 340, 
+        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 350, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8738,9 +8913,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:525 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM"
+    // Pos:535 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM"
     {
-        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 341, 
+        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 351, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8755,9 +8930,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:526 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM"
+    // Pos:536 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM"
     {
-        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 342, 
+        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 352, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8772,9 +8947,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:527 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM"
+    // Pos:537 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM"
     {
-        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 343, 
+        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 353, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8789,9 +8964,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:528 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI"
+    // Pos:538 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 344, 
+        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 354, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8806,9 +8981,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:529 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI"
+    // Pos:539 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 345, 
+        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 355, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8823,9 +8998,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:530 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI"
+    // Pos:540 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 346, 
+        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 356, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8840,9 +9015,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:531 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI"
+    // Pos:541 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 347, 
+        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 357, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8857,9 +9032,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:532 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI"
+    // Pos:542 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 348, 
+        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 358, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8874,9 +9049,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:533 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI"
+    // Pos:543 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 349, 
+        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 359, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8891,9 +9066,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:534 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI"
+    // Pos:544 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 350, 
+        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 360, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8908,9 +9083,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:535 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI"
+    // Pos:545 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 351, 
+        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 361, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -8925,9 +9100,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:536 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM"
+    // Pos:546 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM"
     {
-        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 352, 
+        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 362, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8941,9 +9116,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:537 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM"
+    // Pos:547 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM"
     {
-        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 353, 
+        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8957,9 +9132,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:538 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM"
+    // Pos:548 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM"
     {
-        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 354, 
+        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 364, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -8973,9 +9148,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:539 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM"
+    // Pos:549 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM"
     {
-        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 355, 
+        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 365, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -8989,9 +9164,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:540 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM"
+    // Pos:550 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM"
     {
-        ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 356, 
+        ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 366, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -9006,9 +9181,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:541 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM"
+    // Pos:551 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM"
     {
-        ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 357, 
+        ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 367, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9023,9 +9198,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:542 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM"
+    // Pos:552 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM"
     {
-        ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 358, 
+        ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 368, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9040,9 +9215,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:543 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM"
+    // Pos:553 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM"
     {
-        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 359, 
+        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 369, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -9057,9 +9232,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:544 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM"
+    // Pos:554 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM"
     {
-        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 360, 
+        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 370, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9074,9 +9249,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:545 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM"
+    // Pos:555 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM"
     {
-        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 361, 
+        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 371, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9091,9 +9266,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:546 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM"
+    // Pos:556 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM"
     {
-        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 362, 
+        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 372, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -9108,9 +9283,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:547 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM"
+    // Pos:557 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM"
     {
-        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 363, 
+        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 373, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
@@ -9125,9 +9300,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:548 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM"
+    // Pos:558 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM"
     {
-        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 364, 
+        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 374, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9142,9 +9317,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:549 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM"
+    // Pos:559 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM"
     {
-        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 365, 
+        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 375, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
@@ -9159,9 +9334,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:550 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM"
+    // Pos:560 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM"
     {
-        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 366, 
+        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 376, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
@@ -9176,9 +9351,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:551 Instruction:"LAHF" Encoding:"0x9F"/""
+    // Pos:561 Instruction:"LAHF" Encoding:"0x9F"/""
     {
-        ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 367, 
+        ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 377, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9192,9 +9367,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:552 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM"
+    // Pos:562 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM"
     {
-        ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 368, 
+        ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 378, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9209,9 +9384,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:553 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM"
+    // Pos:563 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM"
     {
-        ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 368, 
+        ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 378, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9226,9 +9401,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:554 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM"
+    // Pos:564 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM"
     {
-        ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 369, 
+        ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 379, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -9242,9 +9417,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:555 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M"
+    // Pos:565 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M"
     {
-        ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 370, 
+        ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 380, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -9258,9 +9433,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:556 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM"
+    // Pos:566 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM"
     {
-        ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 371, 
+        ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 381, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -9275,9 +9450,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:557 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M"
+    // Pos:567 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M"
     {
-        ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 372, 
+        ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 382, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E1, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -9290,9 +9465,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:558 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM"
+    // Pos:568 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM"
     {
-        ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 373, 
+        ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 383, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, 
@@ -9306,9 +9481,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:559 Instruction:"LEAVE" Encoding:"0xC9"/""
+    // Pos:569 Instruction:"LEAVE" Encoding:"0xC9"/""
     {
-        ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 374, 
+        ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 384, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -9324,9 +9499,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:560 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM"
+    // Pos:570 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM"
     {
-        ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 375, 
+        ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 385, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -9341,9 +9516,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:561 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/""
+    // Pos:571 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/""
     {
-        ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 376, 
+        ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 386, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -9356,9 +9531,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:562 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM"
+    // Pos:572 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM"
     {
-        ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 377, 
+        ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 387, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9373,9 +9548,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:563 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M"
+    // Pos:573 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M"
     {
-        ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 378, 
+        ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 388, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -9389,9 +9564,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:564 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM"
+    // Pos:574 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM"
     {
-        ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 379, 
+        ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 389, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9406,9 +9581,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:565 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M"
+    // Pos:575 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M"
     {
-        ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 380, 
+        ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 390, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -9422,9 +9597,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:566 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M"
+    // Pos:576 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M"
     {
-        ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 381, 
+        ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 391, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -9438,9 +9613,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:567 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M"
+    // Pos:577 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M"
     {
-        ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 382, 
+        ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 392, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 
@@ -9453,9 +9628,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:568 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M"
+    // Pos:578 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M"
     {
-        ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 383, 
+        ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 393, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -9469,9 +9644,28 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:569 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/""
+    // Pos:579 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM"
+    {
+        ND_INS_LOADIWKEY, ND_CAT_KL, ND_SET_KL, 394, 
+        0, 
+        ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
+        0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, 
+        0,
+        0|NDR_RFLAG_ZF,
+        0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF,
+        {
+            OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:580 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 384, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 395, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9487,9 +9681,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:570 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/""
+    // Pos:581 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 384, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 395, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9506,9 +9700,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:571 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/""
+    // Pos:582 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 385, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 396, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9524,9 +9718,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:572 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/""
+    // Pos:583 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 385, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 396, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9543,9 +9737,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:573 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/""
+    // Pos:584 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 386, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 397, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9561,9 +9755,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:574 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/""
+    // Pos:585 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 386, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 397, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9580,9 +9774,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:575 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/""
+    // Pos:586 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 387, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 398, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9598,9 +9792,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:576 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/""
+    // Pos:587 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/""
     {
-        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 387, 
+        ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 398, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -9617,9 +9811,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:577 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D"
+    // Pos:588 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D"
     {
-        ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 388, 
+        ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 399, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -9635,9 +9829,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:578 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D"
+    // Pos:589 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D"
     {
-        ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 389, 
+        ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 400, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -9653,9 +9847,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:579 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D"
+    // Pos:590 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D"
     {
-        ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 390, 
+        ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 401, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -9671,9 +9865,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:580 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM"
+    // Pos:591 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM"
     {
-        ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 391, 
+        ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 402, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9688,9 +9882,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:581 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM"
+    // Pos:592 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM"
     {
-        ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 391, 
+        ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 402, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9705,9 +9899,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:582 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM"
+    // Pos:593 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM"
     {
-        ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 392, 
+        ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 403, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -9722,9 +9916,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:583 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M"
+    // Pos:594 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M"
     {
-        ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 393, 
+        ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 404, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -9738,9 +9932,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:584 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI"
+    // Pos:595 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI"
     {
-        ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 394, 
+        ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 405, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 
@@ -9755,9 +9949,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:585 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI"
+    // Pos:596 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI"
     {
-        ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 395, 
+        ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 406, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 
@@ -9772,9 +9966,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:586 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM"
+    // Pos:597 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM"
     {
-        ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 396, 
+        ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 407, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LZCNT, 
@@ -9789,9 +9983,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:587 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM"
+    // Pos:598 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM"
     {
-        ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 397, 
+        ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 408, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -9806,9 +10000,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:588 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM"
+    // Pos:599 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM"
     {
-        ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 398, 
+        ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 409, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -9823,9 +10017,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:589 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM"
+    // Pos:600 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM"
     {
-        ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 399, 
+        ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 410, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -9839,9 +10033,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:590 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM"
+    // Pos:601 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM"
     {
-        ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 400, 
+        ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 411, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -9855,9 +10049,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:591 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM"
+    // Pos:602 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM"
     {
-        ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 401, 
+        ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 412, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -9871,9 +10065,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:592 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM"
+    // Pos:603 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM"
     {
-        ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 402, 
+        ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 413, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -9887,9 +10081,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:593 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/""
+    // Pos:604 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/""
     {
-        ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 403, 
+        ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 414, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MCOMMIT, 
@@ -9902,9 +10096,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:594 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/""
+    // Pos:605 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/""
     {
-        ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 404, 
+        ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 415, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -9917,9 +10111,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:595 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM"
+    // Pos:606 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM"
     {
-        ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 405, 
+        ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 416, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -9933,9 +10127,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:596 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM"
+    // Pos:607 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM"
     {
-        ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 406, 
+        ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 417, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -9949,9 +10143,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:597 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM"
+    // Pos:608 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM"
     {
-        ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 407, 
+        ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 418, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -9965,9 +10159,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:598 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM"
+    // Pos:609 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM"
     {
-        ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 408, 
+        ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 419, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -9981,9 +10175,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:599 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/""
+    // Pos:610 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/""
     {
-        ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 409, 
+        ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 420, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, 
@@ -9998,9 +10192,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:600 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/""
+    // Pos:611 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/""
     {
-        ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 410, 
+        ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 421, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10015,9 +10209,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:601 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/""
+    // Pos:612 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/""
     {
-        ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 411, 
+        ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 422, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10030,9 +10224,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:602 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR"
+    // Pos:613 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR"
     {
-        ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, 
@@ -10046,9 +10240,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:603 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR"
+    // Pos:614 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR"
     {
-        ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, 
@@ -10062,9 +10256,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:604 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM"
+    // Pos:615 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM"
     {
-        ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -10078,9 +10272,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:605 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM"
+    // Pos:616 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM"
     {
-        ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
@@ -10094,9 +10288,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:606 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR"
+    // Pos:617 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR"
     {
-        ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, 
@@ -10110,9 +10304,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:607 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM"
+    // Pos:618 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM"
     {
-        ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, 
@@ -10126,9 +10320,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:608 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR"
+    // Pos:619 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10142,9 +10336,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:609 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR"
+    // Pos:620 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10158,9 +10352,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:610 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM"
+    // Pos:621 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10174,9 +10368,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:611 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM"
+    // Pos:622 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10190,9 +10384,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:612 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR"
+    // Pos:623 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10206,9 +10400,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:613 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR"
+    // Pos:624 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10222,9 +10416,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:614 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM"
+    // Pos:625 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10238,9 +10432,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:615 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM"
+    // Pos:626 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10254,9 +10448,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:616 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D"
+    // Pos:627 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10270,9 +10464,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:617 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D"
+    // Pos:628 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10286,9 +10480,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:618 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D"
+    // Pos:629 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10302,9 +10496,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:619 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D"
+    // Pos:630 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10318,9 +10512,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:620 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI"
+    // Pos:631 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10334,9 +10528,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:621 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI"
+    // Pos:632 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10350,9 +10544,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:622 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI"
+    // Pos:633 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10366,9 +10560,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:623 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI"
+    // Pos:634 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10382,9 +10576,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:624 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI"
+    // Pos:635 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10398,9 +10592,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:625 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI"
+    // Pos:636 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10414,9 +10608,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:626 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI"
+    // Pos:637 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10430,9 +10624,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:627 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI"
+    // Pos:638 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10446,9 +10640,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:628 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI"
+    // Pos:639 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10462,9 +10656,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:629 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI"
+    // Pos:640 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10478,9 +10672,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:630 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI"
+    // Pos:641 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10494,9 +10688,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:631 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI"
+    // Pos:642 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10510,9 +10704,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:632 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI"
+    // Pos:643 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10526,9 +10720,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:633 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI"
+    // Pos:644 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10542,9 +10736,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:634 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI"
+    // Pos:645 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10558,9 +10752,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:635 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI"
+    // Pos:646 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10574,9 +10768,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:636 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI"
+    // Pos:647 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10590,9 +10784,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:637 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI"
+    // Pos:648 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI"
     {
-        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, 
+        ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 423, 
         ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -10606,9 +10800,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:638 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM"
+    // Pos:649 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM"
     {
-        ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 413, 
+        ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 424, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10622,9 +10816,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:639 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR"
+    // Pos:650 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR"
     {
-        ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 413, 
+        ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 424, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10638,9 +10832,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:640 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM"
+    // Pos:651 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM"
     {
-        ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 414, 
+        ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -10654,9 +10848,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:641 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR"
+    // Pos:652 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR"
     {
-        ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 414, 
+        ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -10670,9 +10864,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:642 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM"
+    // Pos:653 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM"
     {
-        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, 
+        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 426, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, 
@@ -10686,9 +10880,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:643 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM"
+    // Pos:654 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM"
     {
-        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, 
+        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 426, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, 
@@ -10702,9 +10896,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:644 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR"
+    // Pos:655 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR"
     {
-        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, 
+        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 426, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, 
@@ -10718,9 +10912,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:645 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR"
+    // Pos:656 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR"
     {
-        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, 
+        ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 426, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, 
@@ -10734,9 +10928,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:646 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM"
+    // Pos:657 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM"
     {
-        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 416, 
+        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -10750,9 +10944,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:647 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM"
+    // Pos:658 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM"
     {
-        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 416, 
+        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10766,9 +10960,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:648 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR"
+    // Pos:659 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR"
     {
-        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 416, 
+        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -10782,9 +10976,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:649 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR"
+    // Pos:660 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR"
     {
-        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 416, 
+        ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 427, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10798,9 +10992,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:650 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM"
+    // Pos:661 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM"
     {
-        ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 417, 
+        ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 428, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -10814,9 +11008,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:651 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M"
+    // Pos:662 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M"
     {
-        ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 418, 
+        ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 429, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIR64B, 
@@ -10830,9 +11024,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:652 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR"
+    // Pos:663 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR"
     {
-        ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 419, 
+        ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 430, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIRI, 
@@ -10846,9 +11040,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:653 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM"
+    // Pos:664 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM"
     {
-        ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 420, 
+        ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 431, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10862,9 +11056,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:654 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM"
+    // Pos:665 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM"
     {
-        ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 421, 
+        ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 432, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10878,9 +11072,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:655 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR"
+    // Pos:666 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR"
     {
-        ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 421, 
+        ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 432, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10894,9 +11088,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:656 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM"
+    // Pos:667 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM"
     {
-        ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 422, 
+        ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 433, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10910,9 +11104,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:657 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR"
+    // Pos:668 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR"
     {
-        ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 422, 
+        ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 433, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10926,9 +11120,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:658 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM"
+    // Pos:669 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM"
     {
-        ND_INS_MOVHLPS, ND_CAT_DATAXFER, ND_SET_SSE, 423, 
+        ND_INS_MOVHLPS, ND_CAT_DATAXFER, ND_SET_SSE, 434, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -10942,9 +11136,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:659 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM"
+    // Pos:670 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM"
     {
-        ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 424, 
+        ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 435, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10958,9 +11152,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:660 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR"
+    // Pos:671 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR"
     {
-        ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 424, 
+        ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 435, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -10974,9 +11168,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:661 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM"
+    // Pos:672 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM"
     {
-        ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, 
+        ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 436, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -10990,9 +11184,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:662 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR"
+    // Pos:673 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR"
     {
-        ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, 
+        ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 436, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11006,9 +11200,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:663 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM"
+    // Pos:674 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM"
     {
-        ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 426, 
+        ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 437, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11022,9 +11216,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:664 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM"
+    // Pos:675 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM"
     {
-        ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 427, 
+        ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 438, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11038,9 +11232,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:665 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR"
+    // Pos:676 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR"
     {
-        ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 427, 
+        ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 438, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11054,9 +11248,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:666 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR"
+    // Pos:677 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR"
     {
-        ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 428, 
+        ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 439, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11070,9 +11264,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:667 Instruction:"MOVMSKPD Gd,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM"
+    // Pos:678 Instruction:"MOVMSKPD Gd,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM"
     {
-        ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 429, 
+        ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 440, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11086,9 +11280,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:668 Instruction:"MOVMSKPS Gd,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM"
+    // Pos:679 Instruction:"MOVMSKPS Gd,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM"
     {
-        ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 430, 
+        ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 441, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11102,9 +11296,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:669 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR"
+    // Pos:680 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR"
     {
-        ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 431, 
+        ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 442, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11118,9 +11312,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:670 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM"
+    // Pos:681 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM"
     {
-        ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 432, 
+        ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 443, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -11134,9 +11328,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:671 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR"
+    // Pos:682 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR"
     {
-        ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 433, 
+        ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 444, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -11150,9 +11344,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:672 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR"
+    // Pos:683 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR"
     {
-        ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 434, 
+        ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 445, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11166,9 +11360,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:673 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR"
+    // Pos:684 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR"
     {
-        ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 435, 
+        ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 446, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11182,9 +11376,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:674 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR"
+    // Pos:685 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR"
     {
-        ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 436, 
+        ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 447, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -11198,9 +11392,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:675 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR"
+    // Pos:686 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR"
     {
-        ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 437, 
+        ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 448, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
@@ -11214,9 +11408,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:676 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR"
+    // Pos:687 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR"
     {
-        ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 438, 
+        ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 449, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
@@ -11230,9 +11424,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:677 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM"
+    // Pos:688 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 450, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -11246,9 +11440,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:678 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM"
+    // Pos:689 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 450, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11262,9 +11456,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:679 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM"
+    // Pos:690 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 439, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 450, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -11278,9 +11472,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:680 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR"
+    // Pos:691 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 439, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 450, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -11294,9 +11488,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:681 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR"
+    // Pos:692 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 450, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11310,9 +11504,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:682 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM"
+    // Pos:693 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 450, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11326,9 +11520,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:683 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR"
+    // Pos:694 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 439, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 450, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -11342,9 +11536,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:684 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR"
+    // Pos:695 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 450, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11358,9 +11552,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:685 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM"
+    // Pos:696 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM"
     {
-        ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 440, 
+        ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 451, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11374,9 +11568,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:686 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/""
+    // Pos:697 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 452, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -11393,9 +11587,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:687 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/""
+    // Pos:698 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 452, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -11413,9 +11607,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:688 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM"
+    // Pos:699 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM"
     {
-        ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 442, 
+        ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 453, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11429,9 +11623,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:689 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR"
+    // Pos:700 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR"
     {
-        ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 442, 
+        ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 453, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11445,9 +11639,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:690 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/""
+    // Pos:701 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 442, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 453, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -11464,9 +11658,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:691 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/""
+    // Pos:702 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 442, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 453, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -11484,9 +11678,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:692 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM"
+    // Pos:703 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM"
     {
-        ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 443, 
+        ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 454, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -11500,9 +11694,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:693 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM"
+    // Pos:704 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM"
     {
-        ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 444, 
+        ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 455, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
@@ -11516,9 +11710,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:694 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/""
+    // Pos:705 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 445, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 456, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -11535,9 +11729,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:695 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/""
+    // Pos:706 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 445, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 456, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -11555,9 +11749,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:696 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM"
+    // Pos:707 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM"
     {
-        ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 446, 
+        ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 457, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11571,9 +11765,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:697 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR"
+    // Pos:708 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR"
     {
-        ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 446, 
+        ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 457, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11587,9 +11781,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:698 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/""
+    // Pos:709 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 447, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 458, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -11606,9 +11800,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:699 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/""
+    // Pos:710 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 447, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 458, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -11626,9 +11820,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:700 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM"
+    // Pos:711 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM"
     {
-        ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 448, 
+        ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 459, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11642,9 +11836,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:701 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM"
+    // Pos:712 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM"
     {
-        ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 448, 
+        ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 459, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11658,9 +11852,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:702 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM"
+    // Pos:713 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM"
     {
-        ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 449, 
+        ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 460, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -11674,9 +11868,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:703 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM"
+    // Pos:714 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM"
     {
-        ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 450, 
+        ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 461, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11690,9 +11884,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:704 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR"
+    // Pos:715 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR"
     {
-        ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 450, 
+        ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 461, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11706,9 +11900,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:705 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM"
+    // Pos:716 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM"
     {
-        ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 451, 
+        ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 462, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11722,9 +11916,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:706 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR"
+    // Pos:717 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR"
     {
-        ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 451, 
+        ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 462, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11738,9 +11932,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:707 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM"
+    // Pos:718 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM"
     {
-        ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 452, 
+        ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 463, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11754,9 +11948,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:708 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM"
+    // Pos:719 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM"
     {
-        ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 452, 
+        ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 463, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11770,9 +11964,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:709 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI"
+    // Pos:720 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI"
     {
-        ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 453, 
+        ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 464, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -11787,9 +11981,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:710 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M"
+    // Pos:721 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M"
     {
-        ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 454, 
+        ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 465, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11805,9 +11999,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:711 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M"
+    // Pos:722 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M"
     {
-        ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 454, 
+        ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 465, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11823,9 +12017,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:712 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM"
+    // Pos:723 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM"
     {
-        ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 455, 
+        ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 466, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11839,9 +12033,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:713 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM"
+    // Pos:724 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM"
     {
-        ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 456, 
+        ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 467, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11855,9 +12049,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:714 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM"
+    // Pos:725 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM"
     {
-        ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 457, 
+        ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 468, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -11871,9 +12065,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:715 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM"
+    // Pos:726 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM"
     {
-        ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 458, 
+        ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 469, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -11887,9 +12081,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:716 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM"
+    // Pos:727 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM"
     {
-        ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 459, 
+        ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 470, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -11905,9 +12099,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:717 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/""
+    // Pos:728 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/""
     {
-        ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 460, 
+        ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 471, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, 
@@ -11921,9 +12115,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:718 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/""
+    // Pos:729 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/""
     {
-        ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 461, 
+        ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 472, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11938,9 +12132,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:719 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M"
+    // Pos:730 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M"
     {
-        ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 462, 
+        ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 473, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11954,9 +12148,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:720 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M"
+    // Pos:731 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M"
     {
-        ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 462, 
+        ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 473, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11970,9 +12164,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:721 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR"
+    // Pos:732 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -11986,9 +12180,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:722 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR"
+    // Pos:733 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12002,9 +12196,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:723 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR"
+    // Pos:734 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12018,9 +12212,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:724 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR"
+    // Pos:735 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12034,9 +12228,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:725 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR"
+    // Pos:736 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12050,9 +12244,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:726 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR"
+    // Pos:737 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12066,9 +12260,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:727 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR"
+    // Pos:738 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12082,9 +12276,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:728 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR"
+    // Pos:739 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12098,9 +12292,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:729 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M"
+    // Pos:740 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12113,9 +12307,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:730 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M"
+    // Pos:741 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12128,9 +12322,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:731 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M"
+    // Pos:742 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12143,9 +12337,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:732 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M"
+    // Pos:743 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12158,9 +12352,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:733 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M"
+    // Pos:744 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12173,9 +12367,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:734 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M"
+    // Pos:745 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12188,9 +12382,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:735 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M"
+    // Pos:746 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12203,9 +12397,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:736 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M"
+    // Pos:747 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12218,9 +12412,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:737 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M"
+    // Pos:748 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12233,9 +12427,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:738 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1A /r"/"RM"
+    // Pos:749 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1A /r"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12249,9 +12443,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:739 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM"
+    // Pos:750 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12265,9 +12459,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:740 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR"
+    // Pos:751 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12281,9 +12475,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:741 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR"
+    // Pos:752 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12297,9 +12491,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:742 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR"
+    // Pos:753 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12313,9 +12507,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:743 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR"
+    // Pos:754 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12329,9 +12523,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:744 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1A /r:reg"/"RM"
+    // Pos:755 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1A /r:reg"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12345,9 +12539,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:745 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1B /r:reg"/"RM"
+    // Pos:756 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1B /r:reg"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12361,9 +12555,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:746 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM"
+    // Pos:757 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12377,9 +12571,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:747 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR"
+    // Pos:758 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12393,9 +12587,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:748 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR"
+    // Pos:759 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12409,9 +12603,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:749 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR"
+    // Pos:760 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12425,9 +12619,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:750 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR"
+    // Pos:761 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12441,9 +12635,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:751 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR"
+    // Pos:762 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12457,9 +12651,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:752 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR"
+    // Pos:763 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12473,9 +12667,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:753 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR"
+    // Pos:764 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12489,9 +12683,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:754 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR"
+    // Pos:765 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12505,9 +12699,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:755 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR"
+    // Pos:766 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12521,9 +12715,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:756 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR"
+    // Pos:767 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12537,9 +12731,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:757 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR"
+    // Pos:768 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12553,9 +12747,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:758 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /r:mem"/"MR"
+    // Pos:769 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /r:mem"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12569,9 +12763,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:759 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR"
+    // Pos:770 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12585,9 +12779,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:760 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR"
+    // Pos:771 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12601,9 +12795,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:761 Instruction:"NOP Rv,Gv" Encoding:"cet rexw 0x0F 0x1E /1:reg"/"MR"
+    // Pos:772 Instruction:"NOP Rv,Gv" Encoding:"cet rexw 0x0F 0x1E /1:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12617,9 +12811,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:762 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR"
+    // Pos:773 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12633,9 +12827,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:763 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR"
+    // Pos:774 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12649,9 +12843,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:764 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR"
+    // Pos:775 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12665,9 +12859,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:765 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR"
+    // Pos:776 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12681,9 +12875,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:766 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR"
+    // Pos:777 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12697,9 +12891,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:767 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR"
+    // Pos:778 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12713,9 +12907,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:768 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR"
+    // Pos:779 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12729,9 +12923,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:769 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR"
+    // Pos:780 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12745,9 +12939,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:770 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR"
+    // Pos:781 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12761,9 +12955,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:771 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR"
+    // Pos:782 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12777,9 +12971,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:772 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR"
+    // Pos:783 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12793,9 +12987,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:773 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR"
+    // Pos:784 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12809,9 +13003,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:774 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR"
+    // Pos:785 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12825,9 +13019,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:775 Instruction:"NOP" Encoding:"0x90"/""
+    // Pos:786 Instruction:"NOP" Encoding:"0x90"/""
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 463, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 474, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -12840,9 +13034,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:776 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M"
+    // Pos:787 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M"
     {
-        ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 464, 
+        ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 475, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12855,9 +13049,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:777 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M"
+    // Pos:788 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M"
     {
-        ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 464, 
+        ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 475, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12870,9 +13064,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:778 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR"
+    // Pos:789 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12887,9 +13081,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:779 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR"
+    // Pos:790 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12904,9 +13098,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:780 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM"
+    // Pos:791 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12921,9 +13115,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:781 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM"
+    // Pos:792 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12938,9 +13132,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:782 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I"
+    // Pos:793 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -12955,9 +13149,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:783 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I"
+    // Pos:794 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -12972,9 +13166,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:784 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI"
+    // Pos:795 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -12989,9 +13183,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:785 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI"
+    // Pos:796 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13006,9 +13200,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:786 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI"
+    // Pos:797 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -13023,9 +13217,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:787 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI"
+    // Pos:798 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 476, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -13040,9 +13234,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:788 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM"
+    // Pos:799 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM"
     {
-        ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 466, 
+        ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 477, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13056,9 +13250,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:789 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM"
+    // Pos:800 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM"
     {
-        ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 467, 
+        ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 478, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -13072,9 +13266,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:790 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I"
+    // Pos:801 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I"
     {
-        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, 
+        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 479, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13089,9 +13283,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:791 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I"
+    // Pos:802 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I"
     {
-        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, 
+        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 479, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13106,9 +13300,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:792 Instruction:"OUT DX,AL" Encoding:"0xEE"/""
+    // Pos:803 Instruction:"OUT DX,AL" Encoding:"0xEE"/""
     {
-        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, 
+        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 479, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13123,9 +13317,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:793 Instruction:"OUT DX,eAX" Encoding:"0xEF"/""
+    // Pos:804 Instruction:"OUT DX,eAX" Encoding:"0xEF"/""
     {
-        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, 
+        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 479, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13140,9 +13334,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:794 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/""
+    // Pos:805 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 480, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13158,9 +13352,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:795 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/""
+    // Pos:806 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 480, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13177,9 +13371,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:796 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/""
+    // Pos:807 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 481, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13195,9 +13389,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:797 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/""
+    // Pos:808 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 481, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13214,9 +13408,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:798 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/""
+    // Pos:809 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 471, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 482, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13232,9 +13426,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:799 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/""
+    // Pos:810 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 471, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 482, 
         ND_PREF_REP, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -13251,9 +13445,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:800 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM"
+    // Pos:811 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM"
     {
-        ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 472, 
+        ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 483, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -13267,9 +13461,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:801 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM"
+    // Pos:812 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM"
     {
-        ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 472, 
+        ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 483, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -13283,9 +13477,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:802 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM"
+    // Pos:813 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM"
     {
-        ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 473, 
+        ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 484, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -13299,9 +13493,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:803 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM"
+    // Pos:814 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM"
     {
-        ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 473, 
+        ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 484, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -13315,9 +13509,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:804 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM"
+    // Pos:815 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM"
     {
-        ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 474, 
+        ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 485, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -13331,9 +13525,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:805 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM"
+    // Pos:816 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM"
     {
-        ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 474, 
+        ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 485, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -13347,9 +13541,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:806 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM"
+    // Pos:817 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM"
     {
-        ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 475, 
+        ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 486, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13363,9 +13557,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:807 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM"
+    // Pos:818 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM"
     {
-        ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 475, 
+        ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 486, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13379,9 +13573,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:808 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM"
+    // Pos:819 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM"
     {
-        ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 476, 
+        ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 487, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13395,9 +13589,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:809 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM"
+    // Pos:820 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM"
     {
-        ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 476, 
+        ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 487, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13411,9 +13605,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:810 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM"
+    // Pos:821 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM"
     {
-        ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 477, 
+        ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 488, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -13427,9 +13621,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:811 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM"
+    // Pos:822 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM"
     {
-        ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 478, 
+        ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 489, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13443,9 +13637,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:812 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM"
+    // Pos:823 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM"
     {
-        ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 478, 
+        ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 489, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13459,9 +13653,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:813 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM"
+    // Pos:824 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM"
     {
-        ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 479, 
+        ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 490, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13475,9 +13669,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:814 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM"
+    // Pos:825 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM"
     {
-        ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 479, 
+        ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 490, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13491,9 +13685,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:815 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM"
+    // Pos:826 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM"
     {
-        ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 480, 
+        ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 491, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13507,9 +13701,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:816 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM"
+    // Pos:827 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM"
     {
-        ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 480, 
+        ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 491, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13523,9 +13717,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:817 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM"
+    // Pos:828 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM"
     {
-        ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 481, 
+        ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 492, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -13539,9 +13733,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:818 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM"
+    // Pos:829 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM"
     {
-        ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 481, 
+        ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 492, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13555,9 +13749,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:819 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM"
+    // Pos:830 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM"
     {
-        ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 482, 
+        ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 493, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13571,9 +13765,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:820 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM"
+    // Pos:831 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM"
     {
-        ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 482, 
+        ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 493, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13587,9 +13781,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:821 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM"
+    // Pos:832 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM"
     {
-        ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 483, 
+        ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 494, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13603,9 +13797,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:822 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM"
+    // Pos:833 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM"
     {
-        ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 483, 
+        ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 494, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13619,9 +13813,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:823 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM"
+    // Pos:834 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM"
     {
-        ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 484, 
+        ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 495, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13635,9 +13829,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:824 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM"
+    // Pos:835 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM"
     {
-        ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 484, 
+        ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 495, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13651,9 +13845,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:825 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM"
+    // Pos:836 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM"
     {
-        ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 485, 
+        ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 496, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13667,9 +13861,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:826 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM"
+    // Pos:837 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM"
     {
-        ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 485, 
+        ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 496, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13683,9 +13877,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:827 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM"
+    // Pos:838 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM"
     {
-        ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 486, 
+        ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 497, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13699,9 +13893,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:828 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM"
+    // Pos:839 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM"
     {
-        ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 486, 
+        ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 497, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13715,9 +13909,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:829 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI"
+    // Pos:840 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI"
     {
-        ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 487, 
+        ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 498, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -13732,9 +13926,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:830 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI"
+    // Pos:841 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI"
     {
-        ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 487, 
+        ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 498, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -13749,9 +13943,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:831 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM"
+    // Pos:842 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM"
     {
-        ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 488, 
+        ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 499, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13765,9 +13959,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:832 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM"
+    // Pos:843 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM"
     {
-        ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 488, 
+        ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 499, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13781,9 +13975,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:833 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM"
+    // Pos:844 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM"
     {
-        ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 489, 
+        ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 500, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13797,9 +13991,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:834 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM"
+    // Pos:845 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM"
     {
-        ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 489, 
+        ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 500, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13813,9 +14007,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:835 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/""
+    // Pos:846 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/""
     {
-        ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 490, 
+        ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 501, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -13828,9 +14022,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:836 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM"
+    // Pos:847 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM"
     {
-        ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 491, 
+        ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 502, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13844,9 +14038,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:837 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM"
+    // Pos:848 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM"
     {
-        ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 491, 
+        ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 502, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13860,9 +14054,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:838 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM"
+    // Pos:849 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM"
     {
-        ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 492, 
+        ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 503, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -13876,9 +14070,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:839 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM"
+    // Pos:850 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM"
     {
-        ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 493, 
+        ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 504, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13892,9 +14086,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:840 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM"
+    // Pos:851 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM"
     {
-        ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 493, 
+        ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 504, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13908,9 +14102,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:841 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM"
+    // Pos:852 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM"
     {
-        ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 494, 
+        ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 505, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -13925,9 +14119,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:842 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI"
+    // Pos:853 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI"
     {
-        ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 495, 
+        ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 506, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -13942,9 +14136,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:843 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI"
+    // Pos:854 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI"
     {
-        ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 496, 
+        ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 507, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_PCLMULQDQ, 
@@ -13959,9 +14153,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:844 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM"
+    // Pos:855 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM"
     {
-        ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 497, 
+        ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 508, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -13975,9 +14169,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:845 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM"
+    // Pos:856 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM"
     {
-        ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 497, 
+        ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 508, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -13991,9 +14185,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:846 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM"
+    // Pos:857 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM"
     {
-        ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 498, 
+        ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 509, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14007,9 +14201,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:847 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM"
+    // Pos:858 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM"
     {
-        ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 498, 
+        ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 509, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14023,9 +14217,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:848 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM"
+    // Pos:859 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM"
     {
-        ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 499, 
+        ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 510, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14039,9 +14233,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:849 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM"
+    // Pos:860 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM"
     {
-        ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 500, 
+        ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 511, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14055,9 +14249,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:850 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM"
+    // Pos:861 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM"
     {
-        ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 500, 
+        ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 511, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14071,9 +14265,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:851 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI"
+    // Pos:862 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI"
     {
-        ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 501, 
+        ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 512, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14092,9 +14286,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:852 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI"
+    // Pos:863 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI"
     {
-        ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 502, 
+        ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 513, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14113,9 +14307,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:853 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM"
+    // Pos:864 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM"
     {
-        ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 503, 
+        ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 514, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14129,9 +14323,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:854 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM"
+    // Pos:865 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM"
     {
-        ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 503, 
+        ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 514, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14145,9 +14339,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:855 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM"
+    // Pos:866 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM"
     {
-        ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 504, 
+        ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 515, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14161,9 +14355,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:856 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM"
+    // Pos:867 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM"
     {
-        ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 504, 
+        ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 515, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14177,9 +14371,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:857 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM"
+    // Pos:868 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM"
     {
-        ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 505, 
+        ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 516, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14193,9 +14387,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:858 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM"
+    // Pos:869 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM"
     {
-        ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 506, 
+        ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 517, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14209,9 +14403,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:859 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM"
+    // Pos:870 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM"
     {
-        ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 506, 
+        ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 517, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14225,9 +14419,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:860 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI"
+    // Pos:871 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI"
     {
-        ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 507, 
+        ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 518, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14244,9 +14438,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:861 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI"
+    // Pos:872 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI"
     {
-        ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 508, 
+        ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 519, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14263,9 +14457,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:862 Instruction:"PCOMMIT" Encoding:"0x66 0x0F 0xAE /7:reg"/""
+    // Pos:873 Instruction:"PCOMMIT" Encoding:"0x66 0x0F 0xAE /7:reg"/""
     {
-        ND_INS_PCOMMIT, ND_CAT_MISC, ND_SET_PCOMMIT, 509, 
+        ND_INS_PCOMMIT, ND_CAT_MISC, ND_SET_PCOMMIT, 520, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCOMMIT, 
@@ -14278,9 +14472,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:863 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/""
+    // Pos:874 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/""
     {
-        ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 510, 
+        ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 521, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, 
@@ -14296,9 +14490,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:864 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM"
+    // Pos:875 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM"
     {
-        ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 511, 
+        ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 522, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -14313,9 +14507,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:865 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM"
+    // Pos:876 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM"
     {
-        ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 512, 
+        ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 523, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -14330,9 +14524,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:866 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI"
+    // Pos:877 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI"
     {
-        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 513, 
+        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 524, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14347,9 +14541,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:867 Instruction:"PEXTRB Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI"
+    // Pos:878 Instruction:"PEXTRB Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI"
     {
-        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 513, 
+        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 524, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14364,9 +14558,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:868 Instruction:"PEXTRD Ey,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r ib"/"MRI"
+    // Pos:879 Instruction:"PEXTRD Ey,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r ib"/"MRI"
     {
-        ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 514, 
+        ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 525, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14381,9 +14575,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:869 Instruction:"PEXTRQ Ey,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r ib"/"MRI"
+    // Pos:880 Instruction:"PEXTRQ Ey,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r ib"/"MRI"
     {
-        ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 515, 
+        ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 526, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14398,9 +14592,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:870 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI"
+    // Pos:881 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 516, 
+        ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 527, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14415,9 +14609,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:871 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI"
+    // Pos:882 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 516, 
+        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 527, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14432,9 +14626,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:872 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI"
+    // Pos:883 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI"
     {
-        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 516, 
+        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 527, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14449,9 +14643,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:873 Instruction:"PEXTRW Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI"
+    // Pos:884 Instruction:"PEXTRW Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI"
     {
-        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 516, 
+        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 527, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14466,9 +14660,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:874 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM"
+    // Pos:885 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM"
     {
-        ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 517, 
+        ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 528, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14482,9 +14676,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:875 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM"
+    // Pos:886 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM"
     {
-        ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 518, 
+        ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 529, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14498,9 +14692,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:876 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM"
+    // Pos:887 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM"
     {
-        ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 519, 
+        ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 530, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14514,9 +14708,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:877 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM"
+    // Pos:888 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM"
     {
-        ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 520, 
+        ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 531, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14530,9 +14724,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:878 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM"
+    // Pos:889 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM"
     {
-        ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 521, 
+        ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 532, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14546,9 +14740,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:879 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM"
+    // Pos:890 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM"
     {
-        ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 522, 
+        ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 533, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14562,9 +14756,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:880 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM"
+    // Pos:891 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM"
     {
-        ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 523, 
+        ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 534, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14578,9 +14772,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:881 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM"
+    // Pos:892 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM"
     {
-        ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 524, 
+        ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 535, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14594,9 +14788,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:882 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM"
+    // Pos:893 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM"
     {
-        ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 525, 
+        ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 536, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14610,9 +14804,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:883 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM"
+    // Pos:894 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM"
     {
-        ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 526, 
+        ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 537, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14626,9 +14820,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:884 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM"
+    // Pos:895 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM"
     {
-        ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 527, 
+        ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 538, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14642,9 +14836,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:885 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM"
+    // Pos:896 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM"
     {
-        ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 528, 
+        ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 539, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14658,9 +14852,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:886 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM"
+    // Pos:897 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM"
     {
-        ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 529, 
+        ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 540, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14674,9 +14868,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:887 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM"
+    // Pos:898 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM"
     {
-        ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 530, 
+        ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 541, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14690,9 +14884,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:888 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM"
+    // Pos:899 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM"
     {
-        ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 531, 
+        ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 542, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14706,9 +14900,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:889 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM"
+    // Pos:900 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM"
     {
-        ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 532, 
+        ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 543, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14722,9 +14916,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:890 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM"
+    // Pos:901 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM"
     {
-        ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 533, 
+        ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 544, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14738,9 +14932,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:891 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM"
+    // Pos:902 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM"
     {
-        ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 534, 
+        ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 545, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14754,9 +14948,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:892 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM"
+    // Pos:903 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM"
     {
-        ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 535, 
+        ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 546, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14770,9 +14964,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:893 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM"
+    // Pos:904 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM"
     {
-        ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 536, 
+        ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 547, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14786,9 +14980,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:894 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM"
+    // Pos:905 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM"
     {
-        ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 537, 
+        ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 548, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -14802,9 +14996,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:895 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM"
+    // Pos:906 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM"
     {
-        ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 538, 
+        ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 549, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -14818,9 +15012,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:896 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM"
+    // Pos:907 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM"
     {
-        ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 538, 
+        ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 549, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -14834,9 +15028,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:897 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM"
+    // Pos:908 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM"
     {
-        ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 539, 
+        ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 550, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -14850,9 +15044,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:898 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM"
+    // Pos:909 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM"
     {
-        ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 539, 
+        ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 550, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -14866,9 +15060,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:899 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM"
+    // Pos:910 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM"
     {
-        ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 540, 
+        ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -14882,9 +15076,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:900 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM"
+    // Pos:911 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM"
     {
-        ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 540, 
+        ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -14898,9 +15092,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:901 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM"
+    // Pos:912 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM"
     {
-        ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 541, 
+        ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 552, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14914,9 +15108,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:902 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM"
+    // Pos:913 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM"
     {
-        ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 542, 
+        ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 553, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -14930,9 +15124,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:903 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM"
+    // Pos:914 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM"
     {
-        ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 542, 
+        ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 553, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -14946,9 +15140,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:904 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM"
+    // Pos:915 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM"
     {
-        ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 543, 
+        ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 554, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -14962,9 +15156,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:905 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM"
+    // Pos:916 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM"
     {
-        ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 543, 
+        ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 554, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -14978,9 +15172,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:906 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM"
+    // Pos:917 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM"
     {
-        ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 544, 
+        ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 555, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -14994,9 +15188,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:907 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM"
+    // Pos:918 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM"
     {
-        ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 544, 
+        ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 555, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15010,9 +15204,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:908 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM"
+    // Pos:919 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM"
     {
-        ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 545, 
+        ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 556, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15026,9 +15220,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:909 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM"
+    // Pos:920 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM"
     {
-        ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 546, 
+        ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 557, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15042,9 +15236,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:910 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI"
+    // Pos:921 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI"
     {
-        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 547, 
+        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15059,9 +15253,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:911 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI"
+    // Pos:922 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI"
     {
-        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 547, 
+        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15076,9 +15270,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:912 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
+    // Pos:923 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
     {
-        ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 548, 
+        ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 559, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15093,9 +15287,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:913 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
+    // Pos:924 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
     {
-        ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 549, 
+        ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 560, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15110,9 +15304,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:914 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI"
+    // Pos:925 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 550, 
+        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 561, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15127,9 +15321,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:915 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI"
+    // Pos:926 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 550, 
+        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 561, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15144,9 +15338,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:916 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI"
+    // Pos:927 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 550, 
+        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 561, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15161,9 +15355,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:917 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI"
+    // Pos:928 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 550, 
+        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 561, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15178,9 +15372,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:918 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM"
+    // Pos:929 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM"
     {
-        ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 551, 
+        ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 562, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15194,9 +15388,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:919 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM"
+    // Pos:930 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM"
     {
-        ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 551, 
+        ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 562, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15210,9 +15404,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:920 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM"
+    // Pos:931 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM"
     {
-        ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 552, 
+        ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 563, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15226,9 +15420,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:921 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM"
+    // Pos:932 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM"
     {
-        ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 552, 
+        ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 563, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15242,9 +15436,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:922 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM"
+    // Pos:933 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM"
     {
-        ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 553, 
+        ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 564, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15258,9 +15452,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:923 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM"
+    // Pos:934 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM"
     {
-        ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 554, 
+        ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 565, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15274,9 +15468,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:924 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM"
+    // Pos:935 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM"
     {
-        ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 555, 
+        ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 566, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15290,9 +15484,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:925 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM"
+    // Pos:936 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM"
     {
-        ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 555, 
+        ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 566, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15306,9 +15500,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:926 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM"
+    // Pos:937 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM"
     {
-        ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 556, 
+        ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 567, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15322,9 +15516,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:927 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM"
+    // Pos:938 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM"
     {
-        ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 556, 
+        ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 567, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15338,9 +15532,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:928 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM"
+    // Pos:939 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM"
     {
-        ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 557, 
+        ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 568, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15354,9 +15548,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:929 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM"
+    // Pos:940 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM"
     {
-        ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 558, 
+        ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 569, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15370,9 +15564,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:930 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM"
+    // Pos:941 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM"
     {
-        ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 559, 
+        ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 570, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15386,9 +15580,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:931 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM"
+    // Pos:942 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM"
     {
-        ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 560, 
+        ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 571, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15402,9 +15596,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:932 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM"
+    // Pos:943 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM"
     {
-        ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 561, 
+        ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 572, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15418,9 +15612,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:933 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM"
+    // Pos:944 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM"
     {
-        ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 561, 
+        ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 572, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15434,9 +15628,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:934 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM"
+    // Pos:945 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM"
     {
-        ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 562, 
+        ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 573, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15450,9 +15644,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:935 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM"
+    // Pos:946 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM"
     {
-        ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 562, 
+        ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 573, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15466,9 +15660,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:936 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM"
+    // Pos:947 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM"
     {
-        ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 563, 
+        ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 574, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15482,9 +15676,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:937 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM"
+    // Pos:948 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM"
     {
-        ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 564, 
+        ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 575, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15498,9 +15692,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:938 Instruction:"PMOVMSKB Gd,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM"
+    // Pos:949 Instruction:"PMOVMSKB Gd,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM"
     {
-        ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 565, 
+        ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 576, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -15514,9 +15708,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:939 Instruction:"PMOVMSKB Gd,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM"
+    // Pos:950 Instruction:"PMOVMSKB Gd,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM"
     {
-        ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 565, 
+        ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 576, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15530,9 +15724,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:940 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM"
+    // Pos:951 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM"
     {
-        ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 566, 
+        ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 577, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15546,9 +15740,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:941 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM"
+    // Pos:952 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM"
     {
-        ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 567, 
+        ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 578, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15562,9 +15756,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:942 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM"
+    // Pos:953 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM"
     {
-        ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 568, 
+        ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 579, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15578,9 +15772,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:943 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM"
+    // Pos:954 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM"
     {
-        ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 569, 
+        ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 580, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15594,9 +15788,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:944 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM"
+    // Pos:955 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM"
     {
-        ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 570, 
+        ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 581, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15610,9 +15804,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:945 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM"
+    // Pos:956 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM"
     {
-        ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 571, 
+        ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 582, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15626,9 +15820,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:946 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM"
+    // Pos:957 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM"
     {
-        ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 572, 
+        ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 583, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15642,9 +15836,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:947 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM"
+    // Pos:958 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM"
     {
-        ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 573, 
+        ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 584, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15658,9 +15852,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:948 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM"
+    // Pos:959 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM"
     {
-        ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 574, 
+        ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 585, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15674,9 +15868,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:949 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM"
+    // Pos:960 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM"
     {
-        ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 575, 
+        ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 586, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15690,9 +15884,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:950 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM"
+    // Pos:961 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM"
     {
-        ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 576, 
+        ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 587, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15706,9 +15900,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:951 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM"
+    // Pos:962 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM"
     {
-        ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 577, 
+        ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 588, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15722,9 +15916,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:952 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM"
+    // Pos:963 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM"
     {
-        ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 578, 
+        ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 589, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15738,9 +15932,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:953 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM"
+    // Pos:964 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM"
     {
-        ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 579, 
+        ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 590, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15754,9 +15948,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:954 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM"
+    // Pos:965 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM"
     {
-        ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 579, 
+        ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 590, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15770,9 +15964,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:955 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM"
+    // Pos:966 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM"
     {
-        ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 580, 
+        ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 591, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15786,9 +15980,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:956 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM"
+    // Pos:967 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM"
     {
-        ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 581, 
+        ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 592, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15802,9 +15996,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:957 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM"
+    // Pos:968 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM"
     {
-        ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 581, 
+        ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 592, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15818,9 +16012,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:958 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM"
+    // Pos:969 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM"
     {
-        ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 582, 
+        ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 593, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15834,9 +16028,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:959 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM"
+    // Pos:970 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM"
     {
-        ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 582, 
+        ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 593, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15850,9 +16044,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:960 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM"
+    // Pos:971 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM"
     {
-        ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 583, 
+        ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 594, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15866,9 +16060,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:961 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM"
+    // Pos:972 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM"
     {
-        ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 584, 
+        ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 595, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15882,9 +16076,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:962 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM"
+    // Pos:973 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM"
     {
-        ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 584, 
+        ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 595, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15898,9 +16092,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:963 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM"
+    // Pos:974 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM"
     {
-        ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 585, 
+        ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 596, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -15914,9 +16108,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:964 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM"
+    // Pos:975 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM"
     {
-        ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 585, 
+        ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 596, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15930,9 +16124,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:965 Instruction:"POP FS" Encoding:"0x0F 0xA1"/""
+    // Pos:976 Instruction:"POP FS" Encoding:"0x0F 0xA1"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -15946,9 +16140,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:966 Instruction:"POP GS" Encoding:"0x0F 0xA9"/""
+    // Pos:977 Instruction:"POP GS" Encoding:"0x0F 0xA9"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -15962,9 +16156,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:967 Instruction:"POP ES" Encoding:"0x07"/""
+    // Pos:978 Instruction:"POP ES" Encoding:"0x07"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -15978,9 +16172,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:968 Instruction:"POP SS" Encoding:"0x17"/""
+    // Pos:979 Instruction:"POP SS" Encoding:"0x17"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -15994,9 +16188,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:969 Instruction:"POP DS" Encoding:"0x1F"/""
+    // Pos:980 Instruction:"POP DS" Encoding:"0x1F"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16010,9 +16204,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:970 Instruction:"POP Zv" Encoding:"0x58"/"O"
+    // Pos:981 Instruction:"POP Zv" Encoding:"0x58"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16026,9 +16220,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:971 Instruction:"POP Zv" Encoding:"0x59"/"O"
+    // Pos:982 Instruction:"POP Zv" Encoding:"0x59"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16042,9 +16236,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:972 Instruction:"POP Zv" Encoding:"0x5A"/"O"
+    // Pos:983 Instruction:"POP Zv" Encoding:"0x5A"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16058,9 +16252,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:973 Instruction:"POP Zv" Encoding:"0x5B"/"O"
+    // Pos:984 Instruction:"POP Zv" Encoding:"0x5B"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16074,9 +16268,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:974 Instruction:"POP Zv" Encoding:"0x5C"/"O"
+    // Pos:985 Instruction:"POP Zv" Encoding:"0x5C"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16090,9 +16284,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:975 Instruction:"POP Zv" Encoding:"0x5D"/"O"
+    // Pos:986 Instruction:"POP Zv" Encoding:"0x5D"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16106,9 +16300,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:976 Instruction:"POP Zv" Encoding:"0x5E"/"O"
+    // Pos:987 Instruction:"POP Zv" Encoding:"0x5E"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16122,9 +16316,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:977 Instruction:"POP Zv" Encoding:"0x5F"/"O"
+    // Pos:988 Instruction:"POP Zv" Encoding:"0x5F"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16138,9 +16332,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:978 Instruction:"POP Ev" Encoding:"0x8F /0"/"M"
+    // Pos:989 Instruction:"POP Ev" Encoding:"0x8F /0"/"M"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 597, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, 
@@ -16154,9 +16348,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:979 Instruction:"POPA" Encoding:"ds16 0x61"/""
+    // Pos:990 Instruction:"POPA" Encoding:"ds16 0x61"/""
     {
-        ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 587, 
+        ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 598, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16170,9 +16364,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:980 Instruction:"POPAD" Encoding:"ds32 0x61"/""
+    // Pos:991 Instruction:"POPAD" Encoding:"ds32 0x61"/""
     {
-        ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 588, 
+        ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 599, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16186,9 +16380,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:981 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM"
+    // Pos:992 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM"
     {
-        ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 589, 
+        ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 600, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, 
@@ -16203,9 +16397,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:982 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/""
+    // Pos:993 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/""
     {
-        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 590, 
+        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 601, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16219,9 +16413,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:983 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/""
+    // Pos:994 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/""
     {
-        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 591, 
+        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 602, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16235,9 +16429,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:984 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/""
+    // Pos:995 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/""
     {
-        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 592, 
+        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 603, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16251,9 +16445,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:985 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM"
+    // Pos:996 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM"
     {
-        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 593, 
+        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 604, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16267,9 +16461,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:986 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM"
+    // Pos:997 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM"
     {
-        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 593, 
+        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 604, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16283,9 +16477,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:987 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M"
+    // Pos:998 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 594, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 605, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16298,9 +16492,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:988 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M"
+    // Pos:999 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 594, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 605, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16313,9 +16507,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:989 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M"
+    // Pos:1000 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 594, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 605, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16328,9 +16522,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:990 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M"
+    // Pos:1001 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 594, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 605, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16343,9 +16537,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:991 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M"
+    // Pos:1002 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M"
     {
-        ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 595, 
+        ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 606, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16358,9 +16552,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:992 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M"
+    // Pos:1003 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M"
     {
-        ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 596, 
+        ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 607, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16373,9 +16567,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:993 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M"
+    // Pos:1004 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M"
     {
-        ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 597, 
+        ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 608, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -16388,9 +16582,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:994 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M"
+    // Pos:1005 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M"
     {
-        ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 598, 
+        ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 609, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -16403,9 +16597,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:995 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M"
+    // Pos:1006 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M"
     {
-        ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 599, 
+        ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 610, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -16418,9 +16612,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:996 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M"
+    // Pos:1007 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M"
     {
-        ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 600, 
+        ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 611, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -16433,9 +16627,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:997 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M"
+    // Pos:1008 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M"
     {
-        ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 601, 
+        ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 612, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16448,9 +16642,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:998 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M"
+    // Pos:1009 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M"
     {
-        ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 602, 
+        ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 613, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -16463,9 +16657,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:999 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM"
+    // Pos:1010 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM"
     {
-        ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 603, 
+        ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 614, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16479,9 +16673,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1000 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM"
+    // Pos:1011 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM"
     {
-        ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 603, 
+        ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 614, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16495,9 +16689,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1001 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM"
+    // Pos:1012 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM"
     {
-        ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 604, 
+        ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 615, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -16511,9 +16705,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1002 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM"
+    // Pos:1013 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM"
     {
-        ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 604, 
+        ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 615, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -16527,9 +16721,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1003 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1014 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 605, 
+        ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 616, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16544,9 +16738,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1004 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1015 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 606, 
+        ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 617, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16561,9 +16755,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1005 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1016 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 607, 
+        ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 618, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16578,9 +16772,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1006 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1017 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 608, 
+        ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 619, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16595,9 +16789,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1007 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM"
+    // Pos:1018 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM"
     {
-        ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 609, 
+        ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 620, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -16611,9 +16805,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1008 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM"
+    // Pos:1019 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM"
     {
-        ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 609, 
+        ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 620, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -16627,9 +16821,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1009 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM"
+    // Pos:1020 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM"
     {
-        ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 610, 
+        ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 621, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -16643,9 +16837,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1010 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM"
+    // Pos:1021 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM"
     {
-        ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 610, 
+        ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 621, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -16659,9 +16853,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1011 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM"
+    // Pos:1022 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM"
     {
-        ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 611, 
+        ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 622, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -16675,9 +16869,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1012 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM"
+    // Pos:1023 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM"
     {
-        ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 611, 
+        ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 622, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -16691,9 +16885,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1013 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI"
+    // Pos:1024 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 612, 
+        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 623, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16707,9 +16901,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1014 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI"
+    // Pos:1025 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 612, 
+        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 623, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16723,9 +16917,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1015 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM"
+    // Pos:1026 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM"
     {
-        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 612, 
+        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 623, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16739,9 +16933,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1016 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM"
+    // Pos:1027 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM"
     {
-        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 612, 
+        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 623, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16755,9 +16949,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1017 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI"
+    // Pos:1028 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI"
     {
-        ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 613, 
+        ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 624, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16771,9 +16965,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1018 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI"
+    // Pos:1029 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 614, 
+        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 625, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16787,9 +16981,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1019 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI"
+    // Pos:1030 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 614, 
+        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 625, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16803,9 +16997,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1020 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM"
+    // Pos:1031 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM"
     {
-        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 614, 
+        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 625, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16819,9 +17013,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1021 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM"
+    // Pos:1032 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM"
     {
-        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 614, 
+        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 625, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16835,9 +17029,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1022 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI"
+    // Pos:1033 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 615, 
+        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 626, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16851,9 +17045,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1023 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI"
+    // Pos:1034 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 615, 
+        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 626, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16867,9 +17061,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1024 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM"
+    // Pos:1035 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM"
     {
-        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 615, 
+        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 626, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16883,9 +17077,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1025 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM"
+    // Pos:1036 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM"
     {
-        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 615, 
+        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 626, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16899,9 +17093,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1026 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/""
+    // Pos:1037 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/""
     {
-        ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 616, 
+        ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 627, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 
@@ -16915,9 +17109,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1027 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI"
+    // Pos:1038 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 617, 
+        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 628, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16931,9 +17125,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1028 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI"
+    // Pos:1039 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 617, 
+        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 628, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16947,9 +17141,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1029 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM"
+    // Pos:1040 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM"
     {
-        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 617, 
+        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 628, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16963,9 +17157,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1030 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM"
+    // Pos:1041 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM"
     {
-        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 617, 
+        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 628, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16979,9 +17173,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1031 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI"
+    // Pos:1042 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 618, 
+        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 629, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16995,9 +17189,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1032 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI"
+    // Pos:1043 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 618, 
+        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 629, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17011,9 +17205,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1033 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM"
+    // Pos:1044 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM"
     {
-        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 618, 
+        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 629, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17027,9 +17221,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1034 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM"
+    // Pos:1045 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM"
     {
-        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 618, 
+        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 629, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17043,9 +17237,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1035 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI"
+    // Pos:1046 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 619, 
+        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 630, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17059,9 +17253,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1036 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI"
+    // Pos:1047 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 619, 
+        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 630, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17075,9 +17269,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1037 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM"
+    // Pos:1048 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM"
     {
-        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 619, 
+        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 630, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17091,9 +17285,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1038 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM"
+    // Pos:1049 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM"
     {
-        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 619, 
+        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 630, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17107,9 +17301,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1039 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI"
+    // Pos:1050 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI"
     {
-        ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 620, 
+        ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 631, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17123,9 +17317,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1040 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI"
+    // Pos:1051 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 621, 
+        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 632, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17139,9 +17333,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1041 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI"
+    // Pos:1052 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 621, 
+        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 632, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17155,9 +17349,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1042 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM"
+    // Pos:1053 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM"
     {
-        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 621, 
+        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 632, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17171,9 +17365,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1043 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM"
+    // Pos:1054 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM"
     {
-        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 621, 
+        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 632, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17187,9 +17381,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1044 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI"
+    // Pos:1055 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 622, 
+        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 633, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17203,9 +17397,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1045 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI"
+    // Pos:1056 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 622, 
+        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 633, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17219,9 +17413,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1046 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM"
+    // Pos:1057 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM"
     {
-        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 622, 
+        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 633, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17235,9 +17429,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1047 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM"
+    // Pos:1058 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM"
     {
-        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 622, 
+        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 633, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17251,9 +17445,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1048 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM"
+    // Pos:1059 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM"
     {
-        ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 623, 
+        ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 634, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17267,9 +17461,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1049 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM"
+    // Pos:1060 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM"
     {
-        ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 623, 
+        ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 634, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17283,9 +17477,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1050 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM"
+    // Pos:1061 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM"
     {
-        ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 624, 
+        ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 635, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17299,9 +17493,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1051 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM"
+    // Pos:1062 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM"
     {
-        ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 624, 
+        ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 635, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17315,9 +17509,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1052 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM"
+    // Pos:1063 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM"
     {
-        ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 625, 
+        ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 636, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17331,9 +17525,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1053 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM"
+    // Pos:1064 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM"
     {
-        ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 625, 
+        ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 636, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17347,9 +17541,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1054 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM"
+    // Pos:1065 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM"
     {
-        ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 626, 
+        ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 637, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17363,9 +17557,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1055 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM"
+    // Pos:1066 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM"
     {
-        ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 626, 
+        ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 637, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17379,9 +17573,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1056 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM"
+    // Pos:1067 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM"
     {
-        ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 627, 
+        ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 638, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17395,9 +17589,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1057 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM"
+    // Pos:1068 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM"
     {
-        ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 627, 
+        ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 638, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17411,9 +17605,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1058 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM"
+    // Pos:1069 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM"
     {
-        ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 628, 
+        ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 639, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17427,9 +17621,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1059 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM"
+    // Pos:1070 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM"
     {
-        ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 628, 
+        ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 639, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17443,9 +17637,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1060 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM"
+    // Pos:1071 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM"
     {
-        ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 629, 
+        ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 640, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17459,9 +17653,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1061 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM"
+    // Pos:1072 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM"
     {
-        ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 629, 
+        ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 640, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17475,9 +17669,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1062 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM"
+    // Pos:1073 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM"
     {
-        ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 630, 
+        ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 641, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17491,9 +17685,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1063 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM"
+    // Pos:1074 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM"
     {
-        ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 630, 
+        ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 641, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17507,9 +17701,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1064 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM"
+    // Pos:1075 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM"
     {
-        ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 631, 
+        ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 642, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -17523,9 +17717,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1065 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM"
+    // Pos:1076 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM"
     {
-        ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 632, 
+        ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 643, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -17540,9 +17734,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1066 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M"
+    // Pos:1077 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M"
     {
-        ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 633, 
+        ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 644, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NO66|ND_FLAG_MODRM, ND_CFF_PTWRITE, 
@@ -17555,9 +17749,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1067 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM"
+    // Pos:1078 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM"
     {
-        ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 634, 
+        ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 645, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17571,9 +17765,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1068 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM"
+    // Pos:1079 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM"
     {
-        ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 634, 
+        ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 645, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17587,9 +17781,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1069 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM"
+    // Pos:1080 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM"
     {
-        ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 635, 
+        ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 646, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17603,9 +17797,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1070 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM"
+    // Pos:1081 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM"
     {
-        ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 635, 
+        ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 646, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17619,9 +17813,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1071 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM"
+    // Pos:1082 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM"
     {
-        ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 636, 
+        ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 647, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17635,9 +17829,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1072 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM"
+    // Pos:1083 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM"
     {
-        ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 637, 
+        ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 648, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17651,9 +17845,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1073 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM"
+    // Pos:1084 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM"
     {
-        ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 637, 
+        ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 648, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17667,9 +17861,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1074 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM"
+    // Pos:1085 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM"
     {
-        ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 638, 
+        ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 649, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17683,9 +17877,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1075 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM"
+    // Pos:1086 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM"
     {
-        ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 638, 
+        ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 649, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17699,9 +17893,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1076 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM"
+    // Pos:1087 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM"
     {
-        ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 639, 
+        ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 650, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17715,9 +17909,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1077 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM"
+    // Pos:1088 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM"
     {
-        ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 639, 
+        ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 650, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17731,9 +17925,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1078 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM"
+    // Pos:1089 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM"
     {
-        ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 640, 
+        ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 651, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17747,9 +17941,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1079 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM"
+    // Pos:1090 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM"
     {
-        ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 641, 
+        ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 652, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17763,9 +17957,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1080 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM"
+    // Pos:1091 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM"
     {
-        ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 641, 
+        ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 652, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17779,9 +17973,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1081 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/""
+    // Pos:1092 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -17795,9 +17989,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1082 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/""
+    // Pos:1093 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -17811,9 +18005,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1083 Instruction:"PUSH ES" Encoding:"0x06"/""
+    // Pos:1094 Instruction:"PUSH ES" Encoding:"0x06"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -17827,9 +18021,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1084 Instruction:"PUSH CS" Encoding:"0x0E"/""
+    // Pos:1095 Instruction:"PUSH CS" Encoding:"0x0E"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -17843,9 +18037,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1085 Instruction:"PUSH SS" Encoding:"0x16"/""
+    // Pos:1096 Instruction:"PUSH SS" Encoding:"0x16"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -17859,9 +18053,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1086 Instruction:"PUSH DS" Encoding:"0x1E"/""
+    // Pos:1097 Instruction:"PUSH DS" Encoding:"0x1E"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -17875,9 +18069,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1087 Instruction:"PUSH Zv" Encoding:"0x50"/"O"
+    // Pos:1098 Instruction:"PUSH Zv" Encoding:"0x50"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -17891,9 +18085,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1088 Instruction:"PUSH Zv" Encoding:"0x51"/"O"
+    // Pos:1099 Instruction:"PUSH Zv" Encoding:"0x51"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -17907,9 +18101,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1089 Instruction:"PUSH Zv" Encoding:"0x52"/"O"
+    // Pos:1100 Instruction:"PUSH Zv" Encoding:"0x52"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -17923,9 +18117,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1090 Instruction:"PUSH Zv" Encoding:"0x53"/"O"
+    // Pos:1101 Instruction:"PUSH Zv" Encoding:"0x53"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -17939,9 +18133,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1091 Instruction:"PUSH Zv" Encoding:"0x54"/"O"
+    // Pos:1102 Instruction:"PUSH Zv" Encoding:"0x54"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -17955,9 +18149,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1092 Instruction:"PUSH Zv" Encoding:"0x55"/"O"
+    // Pos:1103 Instruction:"PUSH Zv" Encoding:"0x55"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -17971,9 +18165,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1093 Instruction:"PUSH Zv" Encoding:"0x56"/"O"
+    // Pos:1104 Instruction:"PUSH Zv" Encoding:"0x56"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -17987,9 +18181,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1094 Instruction:"PUSH Zv" Encoding:"0x57"/"O"
+    // Pos:1105 Instruction:"PUSH Zv" Encoding:"0x57"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18003,9 +18197,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1095 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I"
+    // Pos:1106 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18019,9 +18213,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1096 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I"
+    // Pos:1107 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18035,9 +18229,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1097 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M"
+    // Pos:1108 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 653, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, 
@@ -18051,9 +18245,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1098 Instruction:"PUSHA" Encoding:"ds16 0x60"/""
+    // Pos:1109 Instruction:"PUSHA" Encoding:"ds16 0x60"/""
     {
-        ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 643, 
+        ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 654, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18067,9 +18261,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1099 Instruction:"PUSHAD" Encoding:"ds32 0x60"/""
+    // Pos:1110 Instruction:"PUSHAD" Encoding:"ds32 0x60"/""
     {
-        ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 644, 
+        ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 655, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18083,9 +18277,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1100 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/""
+    // Pos:1111 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/""
     {
-        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 645, 
+        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18099,9 +18293,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1101 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/""
+    // Pos:1112 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/""
     {
-        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 646, 
+        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 657, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18115,9 +18309,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1102 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/""
+    // Pos:1113 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/""
     {
-        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 647, 
+        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 658, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18131,9 +18325,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1103 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/""
+    // Pos:1114 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/""
     {
-        ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 648, 
+        ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 659, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, 
@@ -18149,9 +18343,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1104 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM"
+    // Pos:1115 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM"
     {
-        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 649, 
+        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 660, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18165,9 +18359,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1105 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM"
+    // Pos:1116 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM"
     {
-        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 649, 
+        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 660, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18181,9 +18375,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1106 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI"
+    // Pos:1117 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18198,9 +18392,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1107 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI"
+    // Pos:1118 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18215,9 +18409,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1108 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1"
+    // Pos:1119 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18232,9 +18426,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1109 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1"
+    // Pos:1120 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18249,9 +18443,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1110 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC"
+    // Pos:1121 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18266,9 +18460,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1111 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC"
+    // Pos:1122 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 661, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18283,9 +18477,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1112 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM"
+    // Pos:1123 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM"
     {
-        ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 651, 
+        ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 662, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -18299,9 +18493,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1113 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM"
+    // Pos:1124 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM"
     {
-        ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 652, 
+        ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 663, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -18315,9 +18509,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1114 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI"
+    // Pos:1125 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18332,9 +18526,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1115 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI"
+    // Pos:1126 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18349,9 +18543,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1116 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1"
+    // Pos:1127 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18366,9 +18560,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1117 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1"
+    // Pos:1128 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18383,9 +18577,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1118 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC"
+    // Pos:1129 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18400,9 +18594,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1119 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC"
+    // Pos:1130 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18417,9 +18611,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1120 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M"
+    // Pos:1131 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M"
     {
-        ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 654, 
+        ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 665, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
@@ -18433,9 +18627,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1121 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M"
+    // Pos:1132 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M"
     {
-        ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 655, 
+        ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 666, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
@@ -18449,9 +18643,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1122 Instruction:"RDMSR" Encoding:"0x0F 0x32"/""
+    // Pos:1133 Instruction:"RDMSR" Encoding:"0x0F 0x32"/""
     {
-        ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 656, 
+        ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 667, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MSR, 
@@ -18467,9 +18661,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1123 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M"
+    // Pos:1134 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M"
     {
-        ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 657, 
+        ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 668, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPID, 
@@ -18483,9 +18677,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1124 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/""
+    // Pos:1135 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/""
     {
-        ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 658, 
+        ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 669, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, 
@@ -18501,9 +18695,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1125 Instruction:"RDPMC" Encoding:"0x0F 0x33"/""
+    // Pos:1136 Instruction:"RDPMC" Encoding:"0x0F 0x33"/""
     {
-        ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 659, 
+        ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 670, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -18519,9 +18713,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1126 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/""
+    // Pos:1137 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/""
     {
-        ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 660, 
+        ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 671, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, 
@@ -18537,9 +18731,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1127 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M"
+    // Pos:1138 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M"
     {
-        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 661, 
+        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 672, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, 
@@ -18553,9 +18747,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1128 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M"
+    // Pos:1139 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M"
     {
-        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 661, 
+        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 672, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, 
@@ -18569,9 +18763,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1129 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M"
+    // Pos:1140 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M"
     {
-        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 662, 
+        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 673, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, 
@@ -18585,9 +18779,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1130 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M"
+    // Pos:1141 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M"
     {
-        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 662, 
+        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 673, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, 
@@ -18601,9 +18795,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1131 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M"
+    // Pos:1142 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M"
     {
-        ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 663, 
+        ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 674, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18616,9 +18810,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1132 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M"
+    // Pos:1143 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M"
     {
-        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 664, 
+        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 675, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -18632,9 +18826,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1133 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M"
+    // Pos:1144 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M"
     {
-        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 665, 
+        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 676, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -18648,9 +18842,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1134 Instruction:"RDTSC" Encoding:"0x0F 0x31"/""
+    // Pos:1145 Instruction:"RDTSC" Encoding:"0x0F 0x31"/""
     {
-        ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 666, 
+        ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 677, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -18665,9 +18859,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1135 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/""
+    // Pos:1146 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/""
     {
-        ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 667, 
+        ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 678, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDTSCP, 
@@ -18684,9 +18878,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1136 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I"
+    // Pos:1147 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I"
     {
-        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 668, 
+        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -18703,9 +18897,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1137 Instruction:"RETF" Encoding:"0xCB"/""
+    // Pos:1148 Instruction:"RETF" Encoding:"0xCB"/""
     {
-        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 668, 
+        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -18721,9 +18915,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1138 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I"
+    // Pos:1149 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I"
     {
-        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 669, 
+        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 680, 
         ND_PREF_BND, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -18740,9 +18934,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1139 Instruction:"RETN" Encoding:"0xC3"/""
+    // Pos:1150 Instruction:"RETN" Encoding:"0xC3"/""
     {
-        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 669, 
+        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 680, 
         ND_PREF_BND, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -18757,9 +18951,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1140 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/""
+    // Pos:1151 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/""
     {
-        ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 670, 
+        ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 681, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 
@@ -18775,9 +18969,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1141 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/""
+    // Pos:1152 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/""
     {
-        ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 671, 
+        ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 682, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 
@@ -18792,9 +18986,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1142 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI"
+    // Pos:1153 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18809,9 +19003,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1143 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI"
+    // Pos:1154 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18826,9 +19020,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1144 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1"
+    // Pos:1155 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18843,9 +19037,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1145 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1"
+    // Pos:1156 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18860,9 +19054,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1146 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC"
+    // Pos:1157 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18877,9 +19071,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1147 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC"
+    // Pos:1158 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 683, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18894,9 +19088,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1148 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI"
+    // Pos:1159 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18911,9 +19105,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1149 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI"
+    // Pos:1160 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18928,9 +19122,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1150 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1"
+    // Pos:1161 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18945,9 +19139,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1151 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1"
+    // Pos:1162 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18962,9 +19156,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1152 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC"
+    // Pos:1163 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18979,9 +19173,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1153 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC"
+    // Pos:1164 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 684, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -18996,9 +19190,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1154 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI"
+    // Pos:1165 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI"
     {
-        ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 674, 
+        ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 685, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -19013,9 +19207,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1155 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI"
+    // Pos:1166 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI"
     {
-        ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 675, 
+        ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 686, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -19030,9 +19224,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1156 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI"
+    // Pos:1167 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI"
     {
-        ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 676, 
+        ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -19047,9 +19241,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1157 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI"
+    // Pos:1168 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI"
     {
-        ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 677, 
+        ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 688, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -19064,9 +19258,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1158 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI"
+    // Pos:1169 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI"
     {
-        ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 678, 
+        ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 689, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -19081,9 +19275,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1159 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM"
+    // Pos:1170 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM"
     {
-        ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 679, 
+        ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 690, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19097,9 +19291,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1160 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M"
+    // Pos:1171 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M"
     {
-        ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 680, 
+        ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 691, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19112,9 +19306,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1161 Instruction:"RSM" Encoding:"0x0F 0xAA"/""
+    // Pos:1172 Instruction:"RSM" Encoding:"0x0F 0xAA"/""
     {
-        ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 681, 
+        ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 692, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -19129,9 +19323,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1162 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM"
+    // Pos:1173 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM"
     {
-        ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 682, 
+        ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 693, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -19145,9 +19339,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1163 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM"
+    // Pos:1174 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM"
     {
-        ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 683, 
+        ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 694, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -19161,9 +19355,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1164 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M"
+    // Pos:1175 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M"
     {
-        ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 684, 
+        ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 695, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -19177,9 +19371,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1165 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M"
+    // Pos:1176 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M"
     {
-        ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 685, 
+        ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 696, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19192,9 +19386,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1166 Instruction:"SAHF" Encoding:"0x9E"/""
+    // Pos:1177 Instruction:"SAHF" Encoding:"0x9E"/""
     {
-        ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 686, 
+        ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 697, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19208,9 +19402,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1167 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI"
+    // Pos:1178 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19225,9 +19419,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1168 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI"
+    // Pos:1179 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19242,9 +19436,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1169 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1"
+    // Pos:1180 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19259,9 +19453,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1170 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1"
+    // Pos:1181 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19276,9 +19470,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1171 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC"
+    // Pos:1182 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19293,9 +19487,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1172 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC"
+    // Pos:1183 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 698, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19310,9 +19504,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1173 Instruction:"SALC" Encoding:"0xD6"/""
+    // Pos:1184 Instruction:"SALC" Encoding:"0xD6"/""
     {
-        ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 688, 
+        ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 699, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19326,9 +19520,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1174 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI"
+    // Pos:1185 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19343,9 +19537,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1175 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI"
+    // Pos:1186 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19360,9 +19554,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1176 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1"
+    // Pos:1187 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19377,9 +19571,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1177 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1"
+    // Pos:1188 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19394,9 +19588,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1178 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC"
+    // Pos:1189 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19411,9 +19605,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1179 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC"
+    // Pos:1190 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 700, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19428,9 +19622,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1180 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:1191 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 690, 
+        ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 701, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -19445,9 +19639,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1181 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/""
+    // Pos:1192 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/""
     {
-        ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 691, 
+        ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 702, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -19461,9 +19655,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1182 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR"
+    // Pos:1193 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19478,9 +19672,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1183 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR"
+    // Pos:1194 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19495,9 +19689,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1184 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM"
+    // Pos:1195 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19512,9 +19706,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1185 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM"
+    // Pos:1196 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19529,9 +19723,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1186 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I"
+    // Pos:1197 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19546,9 +19740,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1187 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I"
+    // Pos:1198 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19563,9 +19757,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1188 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI"
+    // Pos:1199 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19580,9 +19774,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1189 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI"
+    // Pos:1200 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19597,9 +19791,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1190 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI"
+    // Pos:1201 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -19614,9 +19808,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1191 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI"
+    // Pos:1202 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 703, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19631,9 +19825,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1192 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/""
+    // Pos:1203 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 693, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 704, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19649,9 +19843,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1193 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/""
+    // Pos:1204 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 693, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 704, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19668,9 +19862,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1194 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/""
+    // Pos:1205 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 694, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 705, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19686,9 +19880,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1195 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/""
+    // Pos:1206 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 694, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 705, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19705,9 +19899,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1196 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/""
+    // Pos:1207 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 695, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 706, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19723,9 +19917,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1197 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/""
+    // Pos:1208 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 695, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 706, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19742,9 +19936,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1198 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/""
+    // Pos:1209 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 696, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 707, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19760,9 +19954,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1199 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/""
+    // Pos:1210 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 696, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 707, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19779,9 +19973,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1200 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/""
+    // Pos:1211 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/""
     {
-        ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 697, 
+        ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 708, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -19794,9 +19988,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1201 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/""
+    // Pos:1212 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/""
     {
-        ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 698, 
+        ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 709, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -19813,9 +20007,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1202 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/""
+    // Pos:1213 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/""
     {
-        ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 699, 
+        ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 710, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -19828,9 +20022,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1203 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/""
+    // Pos:1214 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/""
     {
-        ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 700, 
+        ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 711, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_SERIALIZE, 
@@ -19843,9 +20037,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1204 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M"
+    // Pos:1215 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 701, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 712, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -19859,9 +20053,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1205 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M"
+    // Pos:1216 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 702, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 713, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -19875,9 +20069,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1206 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M"
+    // Pos:1217 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 703, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 714, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -19891,9 +20085,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1207 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M"
+    // Pos:1218 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 704, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 715, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -19907,9 +20101,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1208 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M"
+    // Pos:1219 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 705, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 716, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -19923,9 +20117,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1209 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M"
+    // Pos:1220 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 706, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 717, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -19939,9 +20133,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1210 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M"
+    // Pos:1221 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 707, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 718, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -19955,9 +20149,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1211 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M"
+    // Pos:1222 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 708, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 719, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -19971,9 +20165,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1212 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M"
+    // Pos:1223 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 709, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 720, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -19987,9 +20181,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1213 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M"
+    // Pos:1224 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 710, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 721, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20003,9 +20197,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1214 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M"
+    // Pos:1225 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 711, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 722, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20019,9 +20213,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1215 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M"
+    // Pos:1226 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 712, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 723, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20035,9 +20229,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1216 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M"
+    // Pos:1227 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 713, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 724, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20051,9 +20245,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1217 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M"
+    // Pos:1228 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 714, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 725, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20067,9 +20261,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1218 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M"
+    // Pos:1229 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 715, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 726, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20083,9 +20277,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1219 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/""
+    // Pos:1230 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/""
     {
-        ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 716, 
+        ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 727, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -20099,9 +20293,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1220 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M"
+    // Pos:1231 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 717, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 728, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20115,9 +20309,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1221 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/""
+    // Pos:1232 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/""
     {
-        ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 718, 
+        ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 729, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -20130,9 +20324,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1222 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M"
+    // Pos:1233 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M"
     {
-        ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 719, 
+        ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 730, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20146,9 +20340,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1223 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM"
+    // Pos:1234 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM"
     {
-        ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 720, 
+        ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 731, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20162,9 +20356,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1224 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM"
+    // Pos:1235 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM"
     {
-        ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 721, 
+        ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 732, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20178,9 +20372,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1225 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM"
+    // Pos:1236 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM"
     {
-        ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 722, 
+        ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 733, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20194,9 +20388,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1226 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI"
+    // Pos:1237 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI"
     {
-        ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 723, 
+        ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 734, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20211,9 +20405,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1227 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM"
+    // Pos:1238 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM"
     {
-        ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 724, 
+        ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 735, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20227,9 +20421,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1228 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM"
+    // Pos:1239 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM"
     {
-        ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 725, 
+        ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 736, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20243,9 +20437,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1229 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM"
+    // Pos:1240 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM"
     {
-        ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 726, 
+        ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 737, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -20260,9 +20454,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1230 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI"
+    // Pos:1241 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 727, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 738, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20277,9 +20471,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1231 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI"
+    // Pos:1242 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 727, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 738, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20294,9 +20488,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1232 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1"
+    // Pos:1243 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 727, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 738, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20311,9 +20505,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1233 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1"
+    // Pos:1244 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 727, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 738, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20328,9 +20522,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1234 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC"
+    // Pos:1245 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 727, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 738, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20345,9 +20539,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1235 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC"
+    // Pos:1246 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 727, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 738, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20362,9 +20556,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1236 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI"
+    // Pos:1247 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI"
     {
-        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 728, 
+        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 739, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20380,9 +20574,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1237 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC"
+    // Pos:1248 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC"
     {
-        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 728, 
+        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 739, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20398,9 +20592,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1238 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:1249 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 729, 
+        ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 740, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -20415,9 +20609,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1239 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI"
+    // Pos:1250 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 730, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 741, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20432,9 +20626,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1240 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI"
+    // Pos:1251 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 730, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 741, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20449,9 +20643,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1241 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1"
+    // Pos:1252 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 730, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 741, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20466,9 +20660,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1242 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1"
+    // Pos:1253 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 730, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 741, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20483,9 +20677,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1243 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC"
+    // Pos:1254 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 730, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 741, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20500,9 +20694,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1244 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC"
+    // Pos:1255 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 730, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 741, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20517,9 +20711,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1245 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI"
+    // Pos:1256 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI"
     {
-        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 731, 
+        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 742, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20535,9 +20729,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1246 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC"
+    // Pos:1257 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC"
     {
-        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 731, 
+        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 742, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20553,9 +20747,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1247 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:1258 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 732, 
+        ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 743, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -20570,9 +20764,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1248 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI"
+    // Pos:1259 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI"
     {
-        ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 733, 
+        ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 744, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -20587,9 +20781,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1249 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI"
+    // Pos:1260 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI"
     {
-        ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 734, 
+        ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 745, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -20604,9 +20798,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1250 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M"
+    // Pos:1261 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M"
     {
-        ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 735, 
+        ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 746, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20620,9 +20814,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1251 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/""
+    // Pos:1262 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/""
     {
-        ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 736, 
+        ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 747, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -20635,9 +20829,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1252 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M"
+    // Pos:1263 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M"
     {
-        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 737, 
+        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 748, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20651,9 +20845,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1253 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M"
+    // Pos:1264 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M"
     {
-        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 737, 
+        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 748, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20667,9 +20861,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1254 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M"
+    // Pos:1265 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M"
     {
-        ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 738, 
+        ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 749, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 
@@ -20682,9 +20876,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1255 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/""
+    // Pos:1266 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/""
     {
-        ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 739, 
+        ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 750, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20697,9 +20891,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1256 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M"
+    // Pos:1267 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M"
     {
-        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 740, 
+        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 751, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20713,9 +20907,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1257 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M"
+    // Pos:1268 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M"
     {
-        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 740, 
+        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 751, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20729,9 +20923,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1258 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M"
+    // Pos:1269 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M"
     {
-        ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 741, 
+        ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 752, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20744,9 +20938,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1259 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM"
+    // Pos:1270 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 742, 
+        ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 753, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -20760,9 +20954,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1260 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM"
+    // Pos:1271 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 743, 
+        ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 754, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -20776,9 +20970,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1261 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM"
+    // Pos:1272 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 744, 
+        ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 755, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -20792,9 +20986,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1262 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM"
+    // Pos:1273 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 745, 
+        ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 756, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -20808,9 +21002,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1263 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/""
+    // Pos:1274 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/""
     {
-        ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 746, 
+        ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 757, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, 
@@ -20823,9 +21017,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1264 Instruction:"STC" Encoding:"0xF9"/""
+    // Pos:1275 Instruction:"STC" Encoding:"0xF9"/""
     {
-        ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 747, 
+        ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 758, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20838,9 +21032,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1265 Instruction:"STD" Encoding:"0xFD"/""
+    // Pos:1276 Instruction:"STD" Encoding:"0xFD"/""
     {
-        ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 748, 
+        ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 759, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20853,9 +21047,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1266 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/""
+    // Pos:1277 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/""
     {
-        ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 749, 
+        ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 760, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -20868,9 +21062,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1267 Instruction:"STI" Encoding:"0xFB"/""
+    // Pos:1278 Instruction:"STI" Encoding:"0xFB"/""
     {
-        ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 750, 
+        ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 761, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20883,9 +21077,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1268 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M"
+    // Pos:1279 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M"
     {
-        ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 751, 
+        ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 762, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -20899,9 +21093,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1269 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/""
+    // Pos:1280 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 752, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 763, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20917,9 +21111,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1270 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/""
+    // Pos:1281 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 752, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 763, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20936,9 +21130,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1271 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/""
+    // Pos:1282 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 753, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 764, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20954,9 +21148,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1272 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/""
+    // Pos:1283 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 753, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 764, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20973,9 +21167,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1273 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/""
+    // Pos:1284 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 754, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 765, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20991,9 +21185,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1274 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/""
+    // Pos:1285 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 754, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 765, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21010,9 +21204,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1275 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/""
+    // Pos:1286 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 755, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 766, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21028,9 +21222,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1276 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/""
+    // Pos:1287 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 755, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 766, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21047,9 +21241,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1277 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M"
+    // Pos:1288 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M"
     {
-        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 756, 
+        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 767, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21063,9 +21257,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1278 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M"
+    // Pos:1289 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M"
     {
-        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 756, 
+        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 767, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21079,9 +21273,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1279 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M"
+    // Pos:1290 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M"
     {
-        ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 757, 
+        ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 768, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -21094,9 +21288,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1280 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR"
+    // Pos:1291 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21111,9 +21305,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1281 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR"
+    // Pos:1292 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21128,9 +21322,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1282 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM"
+    // Pos:1293 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21145,9 +21339,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1283 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM"
+    // Pos:1294 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21162,9 +21356,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1284 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I"
+    // Pos:1295 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21179,9 +21373,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1285 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I"
+    // Pos:1296 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21196,9 +21390,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1286 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI"
+    // Pos:1297 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21213,9 +21407,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1287 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI"
+    // Pos:1298 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21230,9 +21424,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1288 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI"
+    // Pos:1299 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -21247,9 +21441,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1289 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI"
+    // Pos:1300 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 769, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21264,9 +21458,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1290 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM"
+    // Pos:1301 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 759, 
+        ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 770, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -21280,9 +21474,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1291 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM"
+    // Pos:1302 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 760, 
+        ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 771, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -21296,9 +21490,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1292 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM"
+    // Pos:1303 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 761, 
+        ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 772, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -21312,9 +21506,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1293 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM"
+    // Pos:1304 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 762, 
+        ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 773, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -21328,9 +21522,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1294 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR"
+    // Pos:1305 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR"
     {
-        ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 763, 
+        ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 774, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21344,9 +21538,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1295 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M"
+    // Pos:1306 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M"
     {
-        ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 764, 
+        ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 775, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21359,9 +21553,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1296 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M"
+    // Pos:1307 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M"
     {
-        ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 765, 
+        ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 776, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21374,9 +21568,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1297 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/""
+    // Pos:1308 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/""
     {
-        ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 766, 
+        ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 777, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -21390,9 +21584,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1298 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/""
+    // Pos:1309 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/""
     {
-        ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 767, 
+        ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 778, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 10), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_FSC, 
@@ -21414,9 +21608,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1299 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/""
+    // Pos:1310 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/""
     {
-        ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 768, 
+        ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 779, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SEP, 
@@ -21437,9 +21631,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1300 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/""
+    // Pos:1311 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/""
     {
-        ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 769, 
+        ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 780, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_SEP, 
@@ -21456,9 +21650,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1301 Instruction:"SYSRET" Encoding:"0x0F 0x07"/""
+    // Pos:1312 Instruction:"SYSRET" Encoding:"0x0F 0x07"/""
     {
-        ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 770, 
+        ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 781, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_FSC, 
@@ -21478,9 +21672,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1302 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM"
+    // Pos:1313 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM"
     {
-        ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 771, 
+        ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 782, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -21494,9 +21688,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1303 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/""
+    // Pos:1314 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/""
     {
-        ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 772, 
+        ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 783, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21509,9 +21703,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1304 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/""
+    // Pos:1315 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/""
     {
-        ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 773, 
+        ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 784, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, 
@@ -21526,9 +21720,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1305 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1316 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 774, 
+        ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 785, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
@@ -21543,9 +21737,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1306 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1317 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 775, 
+        ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 786, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
@@ -21560,9 +21754,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1307 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1318 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 776, 
+        ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 787, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
@@ -21577,9 +21771,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1308 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1319 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 777, 
+        ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 788, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
@@ -21594,9 +21788,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1309 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR"
+    // Pos:1320 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21611,9 +21805,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1310 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR"
+    // Pos:1321 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21628,9 +21822,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1311 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I"
+    // Pos:1322 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21645,9 +21839,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1312 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I"
+    // Pos:1323 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21662,9 +21856,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1313 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI"
+    // Pos:1324 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21679,9 +21873,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1314 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI"
+    // Pos:1325 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21696,9 +21890,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1315 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI"
+    // Pos:1326 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21713,9 +21907,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1316 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI"
+    // Pos:1327 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 789, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21730,9 +21924,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1317 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M"
+    // Pos:1328 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M"
     {
-        ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 779, 
+        ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 790, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -21746,9 +21940,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1318 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M"
+    // Pos:1329 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M"
     {
-        ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 780, 
+        ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 791, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -21762,9 +21956,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1319 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/""
+    // Pos:1330 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/""
     {
-        ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 781, 
+        ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 792, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -21777,9 +21971,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1320 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M"
+    // Pos:1331 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M"
     {
-        ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 782, 
+        ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 793, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -21793,9 +21987,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1321 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/""
+    // Pos:1332 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/""
     {
-        ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 783, 
+        ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 794, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -21808,9 +22002,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1322 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/""
+    // Pos:1333 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/""
     {
-        ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 784, 
+        ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 795, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, 
@@ -21823,9 +22017,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1323 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M"
+    // Pos:1334 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M"
     {
-        ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 785, 
+        ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 796, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 
@@ -21841,9 +22035,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1324 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM"
+    // Pos:1335 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM"
     {
-        ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 786, 
+        ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 797, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 
@@ -21858,9 +22052,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1325 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM"
+    // Pos:1336 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM"
     {
-        ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 787, 
+        ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 798, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -21874,9 +22068,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1326 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM"
+    // Pos:1337 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM"
     {
-        ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 788, 
+        ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 799, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -21891,9 +22085,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1327 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM"
+    // Pos:1338 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM"
     {
-        ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 789, 
+        ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 800, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -21908,9 +22102,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1328 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM"
+    // Pos:1339 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM"
     {
-        ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 790, 
+        ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 801, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21924,9 +22118,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1329 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM"
+    // Pos:1340 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM"
     {
-        ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 791, 
+        ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 802, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21940,9 +22134,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1330 Instruction:"UD2" Encoding:"0x0F 0x0B"/""
+    // Pos:1341 Instruction:"UD2" Encoding:"0x0F 0x0B"/""
     {
-        ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 792, 
+        ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 803, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21955,9 +22149,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1331 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M"
+    // Pos:1342 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M"
     {
-        ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 793, 
+        ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 804, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 
@@ -21971,9 +22165,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1332 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M"
+    // Pos:1343 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M"
     {
-        ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 794, 
+        ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 805, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 
@@ -21988,9 +22182,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1333 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM"
+    // Pos:1344 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM"
     {
-        ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 795, 
+        ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 806, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -22004,9 +22198,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1334 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM"
+    // Pos:1345 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM"
     {
-        ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 796, 
+        ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 807, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -22020,9 +22214,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1335 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM"
+    // Pos:1346 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM"
     {
-        ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 797, 
+        ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 808, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -22036,9 +22230,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1336 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM"
+    // Pos:1347 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM"
     {
-        ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 798, 
+        ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 809, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -22052,9 +22246,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1337 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM"
+    // Pos:1348 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM"
     {
-        ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 799, 
+        ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 810, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
@@ -22070,9 +22264,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1338 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM"
+    // Pos:1349 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM"
     {
-        ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 800, 
+        ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 811, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
@@ -22088,9 +22282,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1339 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM"
+    // Pos:1350 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM"
     {
-        ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 801, 
+        ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 812, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
@@ -22106,9 +22300,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1340 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM"
+    // Pos:1351 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM"
     {
-        ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 802, 
+        ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 813, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
@@ -22124,9 +22318,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1341 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM"
+    // Pos:1352 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 803, 
+        ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 814, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22142,9 +22336,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1342 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM"
+    // Pos:1353 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 803, 
+        ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 814, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22159,9 +22353,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1343 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM"
+    // Pos:1354 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 804, 
+        ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 815, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22177,9 +22371,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1344 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM"
+    // Pos:1355 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 804, 
+        ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 815, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22194,9 +22388,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1345 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM"
+    // Pos:1356 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 805, 
+        ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 816, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22212,9 +22406,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1346 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM"
+    // Pos:1357 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 805, 
+        ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 816, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22229,9 +22423,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1347 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM"
+    // Pos:1358 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 806, 
+        ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 817, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22247,9 +22441,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1348 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM"
+    // Pos:1359 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 806, 
+        ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 817, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22264,9 +22458,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1349 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM"
+    // Pos:1360 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM"
     {
-        ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 807, 
+        ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 818, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22281,9 +22475,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1350 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM"
+    // Pos:1361 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM"
     {
-        ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 808, 
+        ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 819, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22298,9 +22492,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1351 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
+    // Pos:1362 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
     {
-        ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 809, 
+        ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 820, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
@@ -22315,9 +22509,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1352 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
+    // Pos:1363 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
     {
-        ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 809, 
+        ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 820, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -22332,9 +22526,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1353 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
+    // Pos:1364 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
     {
-        ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 810, 
+        ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 821, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
@@ -22349,9 +22543,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1354 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
+    // Pos:1365 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
     {
-        ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 810, 
+        ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 821, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -22366,9 +22560,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1355 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
+    // Pos:1366 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
     {
-        ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 811, 
+        ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 822, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
@@ -22383,9 +22577,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1356 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
+    // Pos:1367 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
     {
-        ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 811, 
+        ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 822, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -22400,9 +22594,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1357 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
+    // Pos:1368 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
     {
-        ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 812, 
+        ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 823, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
@@ -22417,9 +22611,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1358 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
+    // Pos:1369 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
     {
-        ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 812, 
+        ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 823, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -22434,9 +22628,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1359 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM"
+    // Pos:1370 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM"
     {
-        ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 813, 
+        ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 824, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -22450,9 +22644,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1360 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI"
+    // Pos:1371 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI"
     {
-        ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 814, 
+        ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 825, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -22467,9 +22661,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1361 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI"
+    // Pos:1372 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI"
     {
-        ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 815, 
+        ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 826, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22486,9 +22680,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1362 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI"
+    // Pos:1373 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI"
     {
-        ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 816, 
+        ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 827, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22505,9 +22699,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1363 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM"
+    // Pos:1374 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM"
     {
-        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 817, 
+        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 828, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22523,9 +22717,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1364 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM"
+    // Pos:1375 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM"
     {
-        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 817, 
+        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 828, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22540,9 +22734,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1365 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM"
+    // Pos:1376 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM"
     {
-        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 818, 
+        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 829, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22558,9 +22752,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1366 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM"
+    // Pos:1377 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM"
     {
-        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 818, 
+        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 829, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22575,9 +22769,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1367 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM"
+    // Pos:1378 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM"
     {
-        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 819, 
+        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 830, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22593,9 +22787,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1368 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM"
+    // Pos:1379 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM"
     {
-        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 819, 
+        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 830, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22610,9 +22804,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1369 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM"
+    // Pos:1380 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM"
     {
-        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 820, 
+        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 831, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22628,9 +22822,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1370 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM"
+    // Pos:1381 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM"
     {
-        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 820, 
+        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 831, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22645,9 +22839,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1371 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM"
+    // Pos:1382 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM"
     {
-        ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 821, 
+        ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 832, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22663,9 +22857,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1372 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM"
+    // Pos:1383 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM"
     {
-        ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 822, 
+        ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 833, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22681,9 +22875,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1373 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI"
+    // Pos:1384 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI"
     {
-        ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 823, 
+        ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 834, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22699,9 +22893,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1374 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI"
+    // Pos:1385 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI"
     {
-        ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 824, 
+        ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 835, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22717,9 +22911,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1375 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML"
+    // Pos:1386 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML"
     {
-        ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 825, 
+        ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 836, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22735,9 +22929,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1376 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML"
+    // Pos:1387 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML"
     {
-        ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 826, 
+        ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 837, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22753,9 +22947,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1377 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM"
+    // Pos:1388 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM"
     {
-        ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 827, 
+        ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 838, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22769,9 +22963,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1378 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM"
+    // Pos:1389 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM"
     {
-        ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 828, 
+        ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 839, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22786,9 +22980,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1379 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM"
+    // Pos:1390 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 829, 
+        ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 840, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22803,9 +22997,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1380 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM"
+    // Pos:1391 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 830, 
+        ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 841, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22820,9 +23014,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1381 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM"
+    // Pos:1392 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 831, 
+        ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 842, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22837,9 +23031,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1382 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM"
+    // Pos:1393 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 832, 
+        ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 843, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22854,9 +23048,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1383 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM"
+    // Pos:1394 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM"
     {
-        ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 833, 
+        ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 844, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -22870,9 +23064,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1384 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM"
+    // Pos:1395 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM"
     {
-        ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 834, 
+        ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 845, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22887,9 +23081,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1385 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM"
+    // Pos:1396 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 835, 
+        ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 846, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22904,9 +23098,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1386 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM"
+    // Pos:1397 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 836, 
+        ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 847, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22921,9 +23115,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1387 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM"
+    // Pos:1398 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 837, 
+        ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 848, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -22938,9 +23132,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1388 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM"
+    // Pos:1399 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 838, 
+        ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 849, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22955,9 +23149,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1389 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM"
+    // Pos:1400 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM"
     {
-        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 839, 
+        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 850, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -22972,9 +23166,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1390 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM"
+    // Pos:1401 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM"
     {
-        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 839, 
+        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 850, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -22988,9 +23182,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1391 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM"
+    // Pos:1402 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM"
     {
-        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 840, 
+        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 851, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23005,9 +23199,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1392 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM"
+    // Pos:1403 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM"
     {
-        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 840, 
+        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 851, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23021,9 +23215,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1393 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI"
+    // Pos:1404 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 841, 
+        ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 852, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23040,9 +23234,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1394 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1405 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 841, 
+        ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 852, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23058,9 +23252,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1395 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
+    // Pos:1406 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 842, 
+        ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 853, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23077,9 +23271,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1396 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1407 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 842, 
+        ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 853, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23095,9 +23289,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1397 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI"
+    // Pos:1408 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 843, 
+        ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 854, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23114,9 +23308,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1398 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1409 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 843, 
+        ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 854, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23132,9 +23326,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1399 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI"
+    // Pos:1410 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 844, 
+        ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 855, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23151,9 +23345,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1400 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1411 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 844, 
+        ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 855, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23169,9 +23363,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1401 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM"
+    // Pos:1412 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 845, 
+        ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 856, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23186,9 +23380,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1402 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM"
+    // Pos:1413 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 845, 
+        ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 856, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23203,9 +23397,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1403 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM"
+    // Pos:1414 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 846, 
+        ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 857, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23220,9 +23414,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1404 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM"
+    // Pos:1415 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 846, 
+        ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 857, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23237,9 +23431,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1405 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR"
+    // Pos:1416 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR"
     {
-        ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 847, 
+        ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 858, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23254,9 +23448,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1406 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR"
+    // Pos:1417 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR"
     {
-        ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 848, 
+        ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 859, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23271,9 +23465,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1407 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM"
+    // Pos:1418 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 849, 
+        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 860, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23288,9 +23482,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1408 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM"
+    // Pos:1419 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 849, 
+        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 860, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23304,9 +23498,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1409 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM"
+    // Pos:1420 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 849, 
+        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 860, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23320,9 +23514,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1410 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1421 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 850, 
+        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 861, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23337,9 +23531,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1411 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM"
+    // Pos:1422 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM"
     {
-        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 850, 
+        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 861, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23353,9 +23547,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1412 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM"
+    // Pos:1423 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM"
     {
-        ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 851, 
+        ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 862, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
@@ -23371,9 +23565,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1413 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM"
+    // Pos:1424 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM"
     {
-        ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 852, 
+        ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 863, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
@@ -23388,9 +23582,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1414 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM"
+    // Pos:1425 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 853, 
+        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 864, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23405,9 +23599,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1415 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM"
+    // Pos:1426 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 853, 
+        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 864, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23421,9 +23615,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1416 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM"
+    // Pos:1427 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM"
     {
-        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 854, 
+        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 865, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23438,9 +23632,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1417 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM"
+    // Pos:1428 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 854, 
+        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 865, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23454,9 +23648,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1418 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM"
+    // Pos:1429 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 854, 
+        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 865, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23470,9 +23664,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1419 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM"
+    // Pos:1430 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM"
     {
-        ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 855, 
+        ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 866, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23487,9 +23681,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1420 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM"
+    // Pos:1431 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 856, 
+        ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 867, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23504,9 +23698,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1421 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM"
+    // Pos:1432 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 857, 
+        ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 868, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23521,9 +23715,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1422 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM"
+    // Pos:1433 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM"
     {
-        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 858, 
+        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 869, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23538,9 +23732,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1423 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM"
+    // Pos:1434 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM"
     {
-        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 858, 
+        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 869, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
@@ -23554,9 +23748,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1424 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM"
+    // Pos:1435 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM"
     {
-        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 858, 
+        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 869, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
@@ -23570,9 +23764,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1425 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1436 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 859, 
+        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 870, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23587,9 +23781,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1426 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM"
+    // Pos:1437 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM"
     {
-        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 859, 
+        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 870, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23603,9 +23797,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1427 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM"
+    // Pos:1438 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM"
     {
-        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 860, 
+        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 871, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23620,9 +23814,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1428 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM"
+    // Pos:1439 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 860, 
+        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 871, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23636,9 +23830,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1429 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM"
+    // Pos:1440 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 860, 
+        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 871, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23652,9 +23846,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1430 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI"
+    // Pos:1441 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI"
     {
-        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 861, 
+        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 872, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23670,9 +23864,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1431 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI"
+    // Pos:1442 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI"
     {
-        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 861, 
+        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 872, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
@@ -23687,9 +23881,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1432 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI"
+    // Pos:1443 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI"
     {
-        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 861, 
+        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 872, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
@@ -23704,9 +23898,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1433 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM"
+    // Pos:1444 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM"
     {
-        ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 862, 
+        ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 873, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23721,9 +23915,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1434 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1445 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 863, 
+        ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 874, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23738,9 +23932,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1435 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1446 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 864, 
+        ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 875, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23755,9 +23949,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1436 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM"
+    // Pos:1447 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 865, 
+        ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 876, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23772,9 +23966,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1437 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM"
+    // Pos:1448 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 866, 
+        ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 877, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23789,9 +23983,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1438 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM"
+    // Pos:1449 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 867, 
+        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 878, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23805,9 +23999,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1439 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM"
+    // Pos:1450 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 867, 
+        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 878, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23821,9 +24015,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1440 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM"
+    // Pos:1451 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM"
     {
-        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 868, 
+        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 879, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23839,9 +24033,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1441 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM"
+    // Pos:1452 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM"
     {
-        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 868, 
+        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 879, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23856,9 +24050,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1442 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM"
+    // Pos:1453 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM"
     {
-        ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 869, 
+        ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 880, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23872,9 +24066,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1443 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM"
+    // Pos:1454 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 870, 
+        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 881, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23889,9 +24083,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1444 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM"
+    // Pos:1455 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 870, 
+        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 881, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23906,9 +24100,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1445 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1456 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 870, 
+        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 881, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23923,9 +24117,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1446 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1457 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 871, 
+        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 882, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23940,9 +24134,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1447 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1458 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 871, 
+        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 882, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23957,9 +24151,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1448 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM"
+    // Pos:1459 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM"
     {
-        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 872, 
+        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 883, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23975,9 +24169,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1449 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM"
+    // Pos:1460 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM"
     {
-        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 872, 
+        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 883, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23992,9 +24186,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1450 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM"
+    // Pos:1461 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 873, 
+        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 884, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24008,9 +24202,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1451 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM"
+    // Pos:1462 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 873, 
+        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 884, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24024,9 +24218,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1452 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM"
+    // Pos:1463 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM"
     {
-        ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 874, 
+        ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 885, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24040,9 +24234,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1453 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM"
+    // Pos:1464 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 875, 
+        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 886, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24057,9 +24251,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1454 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM"
+    // Pos:1465 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 875, 
+        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 886, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24073,9 +24267,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1455 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1466 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 876, 
+        ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 887, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24090,9 +24284,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1456 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM"
+    // Pos:1467 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 877, 
+        ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 888, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24107,9 +24301,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1457 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM"
+    // Pos:1468 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 878, 
+        ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 889, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24124,9 +24318,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1458 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1469 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 879, 
+        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 890, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24141,9 +24335,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1459 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM"
+    // Pos:1470 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM"
     {
-        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 879, 
+        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 890, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24157,9 +24351,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1460 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1471 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 880, 
+        ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 891, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24174,9 +24368,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1461 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1472 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 881, 
+        ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 892, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24191,9 +24385,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1462 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1473 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 882, 
+        ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 893, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24208,9 +24402,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1463 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM"
+    // Pos:1474 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 883, 
+        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 894, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24224,9 +24418,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1464 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM"
+    // Pos:1475 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 883, 
+        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 894, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24240,9 +24434,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1465 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM"
+    // Pos:1476 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM"
     {
-        ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 884, 
+        ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 895, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24256,9 +24450,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1466 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM"
+    // Pos:1477 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 885, 
+        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 896, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24272,9 +24466,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1467 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM"
+    // Pos:1478 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 885, 
+        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 896, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24288,9 +24482,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1468 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM"
+    // Pos:1479 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM"
     {
-        ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 886, 
+        ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 897, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24304,9 +24498,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1469 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1480 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 887, 
+        ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 898, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24321,9 +24515,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1470 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1481 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 888, 
+        ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 899, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24338,9 +24532,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1471 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1482 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 889, 
+        ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 900, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24355,9 +24549,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1472 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1483 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 890, 
+        ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 901, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24372,9 +24566,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1473 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM"
+    // Pos:1484 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 891, 
+        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 902, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24389,9 +24583,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1474 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM"
+    // Pos:1485 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 891, 
+        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 902, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24406,9 +24600,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1475 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM"
+    // Pos:1486 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 892, 
+        ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 903, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24423,9 +24617,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1476 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI"
+    // Pos:1487 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI"
     {
-        ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 893, 
+        ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 904, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -24442,9 +24636,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1477 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM"
+    // Pos:1488 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 894, 
+        ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 905, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24460,9 +24654,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1478 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM"
+    // Pos:1489 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 894, 
+        ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 905, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24477,9 +24671,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1479 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM"
+    // Pos:1490 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 895, 
+        ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 906, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24495,9 +24689,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1480 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM"
+    // Pos:1491 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 895, 
+        ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 906, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24512,9 +24706,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1481 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM"
+    // Pos:1492 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 896, 
+        ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 907, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24530,9 +24724,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1482 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM"
+    // Pos:1493 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 896, 
+        ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 907, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24547,9 +24741,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1483 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM"
+    // Pos:1494 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 897, 
+        ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 908, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24565,9 +24759,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1484 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM"
+    // Pos:1495 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 897, 
+        ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 908, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24582,9 +24776,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1485 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM"
+    // Pos:1496 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM"
     {
-        ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 898, 
+        ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 909, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
@@ -24600,9 +24794,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1486 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI"
+    // Pos:1497 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI"
     {
-        ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 899, 
+        ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 910, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24618,9 +24812,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1487 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI"
+    // Pos:1498 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI"
     {
-        ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 900, 
+        ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 911, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24636,9 +24830,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1488 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M"
+    // Pos:1499 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M"
     {
-        ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 901, 
+        ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 912, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -24652,9 +24846,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1489 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M"
+    // Pos:1500 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M"
     {
-        ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 902, 
+        ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 913, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -24668,9 +24862,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1490 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM"
+    // Pos:1501 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM"
     {
-        ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 903, 
+        ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 914, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -24685,9 +24879,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1491 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM"
+    // Pos:1502 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM"
     {
-        ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 904, 
+        ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 915, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -24702,9 +24896,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1492 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM"
+    // Pos:1503 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM"
     {
-        ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 905, 
+        ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 916, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24719,9 +24913,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1493 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM"
+    // Pos:1504 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM"
     {
-        ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 906, 
+        ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 917, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24736,9 +24930,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1494 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI"
+    // Pos:1505 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI"
     {
-        ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 907, 
+        ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 918, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24753,9 +24947,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1495 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI"
+    // Pos:1506 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 908, 
+        ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 919, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24771,9 +24965,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1496 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI"
+    // Pos:1507 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 909, 
+        ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 920, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24789,9 +24983,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1497 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI"
+    // Pos:1508 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 910, 
+        ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 921, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24807,9 +25001,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1498 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI"
+    // Pos:1509 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 911, 
+        ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 922, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24825,9 +25019,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1499 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI"
+    // Pos:1510 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI"
     {
-        ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 912, 
+        ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 923, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -24842,9 +25036,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1500 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI"
+    // Pos:1511 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 913, 
+        ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 924, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24860,9 +25054,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1501 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI"
+    // Pos:1512 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 914, 
+        ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 925, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24878,9 +25072,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1502 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI"
+    // Pos:1513 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 915, 
+        ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 926, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24896,9 +25090,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1503 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI"
+    // Pos:1514 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 916, 
+        ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 927, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24914,9 +25108,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1504 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
+    // Pos:1515 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 917, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 928, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24931,9 +25125,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1505 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
+    // Pos:1516 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 917, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 928, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24948,9 +25142,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1506 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
+    // Pos:1517 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 917, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 928, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24965,9 +25159,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1507 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
+    // Pos:1518 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 917, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 928, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24982,9 +25176,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1508 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI"
+    // Pos:1519 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 918, 
+        ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 929, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25001,9 +25195,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1509 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI"
+    // Pos:1520 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 919, 
+        ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 930, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25020,9 +25214,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1510 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI"
+    // Pos:1521 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 920, 
+        ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 931, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25039,9 +25233,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1511 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI"
+    // Pos:1522 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 921, 
+        ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 932, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25058,9 +25252,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1512 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM"
+    // Pos:1523 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM"
     {
-        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 922, 
+        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 933, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25076,9 +25270,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1513 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM"
+    // Pos:1524 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM"
     {
-        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 922, 
+        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 933, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25093,9 +25287,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1514 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM"
+    // Pos:1525 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM"
     {
-        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 923, 
+        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 934, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25111,9 +25305,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1515 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM"
+    // Pos:1526 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM"
     {
-        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 923, 
+        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 934, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25128,9 +25322,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1516 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM"
+    // Pos:1527 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM"
     {
-        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 924, 
+        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 935, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25146,9 +25340,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1517 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM"
+    // Pos:1528 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM"
     {
-        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 924, 
+        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 935, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25163,9 +25357,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1518 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM"
+    // Pos:1529 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM"
     {
-        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 925, 
+        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 936, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25181,9 +25375,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1519 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM"
+    // Pos:1530 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM"
     {
-        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 925, 
+        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 936, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25198,9 +25392,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1520 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM"
+    // Pos:1531 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM"
     {
-        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 926, 
+        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 937, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25216,9 +25410,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1521 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM"
+    // Pos:1532 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM"
     {
-        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 926, 
+        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 937, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25233,9 +25427,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1522 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM"
+    // Pos:1533 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM"
     {
-        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 927, 
+        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 938, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25251,9 +25445,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1523 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM"
+    // Pos:1534 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM"
     {
-        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 927, 
+        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 938, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25268,9 +25462,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1524 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM"
+    // Pos:1535 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM"
     {
-        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 928, 
+        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 939, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25286,9 +25480,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1525 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM"
+    // Pos:1536 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM"
     {
-        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 928, 
+        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 939, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25303,9 +25497,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1526 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM"
+    // Pos:1537 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM"
     {
-        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 929, 
+        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 940, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25321,9 +25515,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1527 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM"
+    // Pos:1538 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM"
     {
-        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 929, 
+        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 940, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25338,9 +25532,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1528 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM"
+    // Pos:1539 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM"
     {
-        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 930, 
+        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 941, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25356,9 +25550,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1529 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM"
+    // Pos:1540 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM"
     {
-        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 930, 
+        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 941, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25373,9 +25567,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1530 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM"
+    // Pos:1541 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM"
     {
-        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 931, 
+        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 942, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25391,9 +25585,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1531 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM"
+    // Pos:1542 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM"
     {
-        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 931, 
+        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 942, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25408,9 +25602,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1532 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM"
+    // Pos:1543 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM"
     {
-        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 932, 
+        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 943, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25426,9 +25620,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1533 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM"
+    // Pos:1544 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM"
     {
-        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 932, 
+        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 943, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25443,9 +25637,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1534 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM"
+    // Pos:1545 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM"
     {
-        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 933, 
+        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 944, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25461,9 +25655,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1535 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM"
+    // Pos:1546 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM"
     {
-        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 933, 
+        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 944, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25478,9 +25672,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1536 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML"
+    // Pos:1547 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML"
     {
-        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 934, 
+        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 945, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25496,9 +25690,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1537 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM"
+    // Pos:1548 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM"
     {
-        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 934, 
+        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 945, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25514,9 +25708,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1538 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML"
+    // Pos:1549 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML"
     {
-        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 935, 
+        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 946, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25532,9 +25726,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1539 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM"
+    // Pos:1550 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM"
     {
-        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 935, 
+        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 946, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25550,9 +25744,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1540 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML"
+    // Pos:1551 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML"
     {
-        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 936, 
+        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 947, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25568,9 +25762,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1541 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM"
+    // Pos:1552 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 936, 
+        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 947, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25586,9 +25780,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1542 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML"
+    // Pos:1553 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML"
     {
-        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 937, 
+        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 948, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25604,9 +25798,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1543 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM"
+    // Pos:1554 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 937, 
+        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 948, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25622,9 +25816,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1544 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM"
+    // Pos:1555 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 938, 
+        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 949, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25640,9 +25834,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1545 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM"
+    // Pos:1556 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 938, 
+        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 949, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25657,9 +25851,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1546 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM"
+    // Pos:1557 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 939, 
+        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 950, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25675,9 +25869,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1547 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM"
+    // Pos:1558 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 939, 
+        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 950, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25692,9 +25886,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1548 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM"
+    // Pos:1559 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 940, 
+        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 951, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25710,9 +25904,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1549 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM"
+    // Pos:1560 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 940, 
+        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 951, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25727,9 +25921,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1550 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM"
+    // Pos:1561 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 941, 
+        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 952, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25745,9 +25939,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1551 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM"
+    // Pos:1562 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 941, 
+        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 952, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25762,9 +25956,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1552 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM"
+    // Pos:1563 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 942, 
+        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 953, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25780,9 +25974,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1553 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM"
+    // Pos:1564 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 942, 
+        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 953, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25797,9 +25991,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1554 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM"
+    // Pos:1565 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 943, 
+        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 954, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25815,9 +26009,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1555 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM"
+    // Pos:1566 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 943, 
+        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 954, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25832,9 +26026,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1556 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML"
+    // Pos:1567 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML"
     {
-        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 944, 
+        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 955, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25850,9 +26044,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1557 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM"
+    // Pos:1568 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 944, 
+        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 955, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25868,9 +26062,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1558 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML"
+    // Pos:1569 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML"
     {
-        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 945, 
+        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 956, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25886,9 +26080,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1559 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM"
+    // Pos:1570 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 945, 
+        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 956, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -25904,9 +26098,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1560 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM"
+    // Pos:1571 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM"
     {
-        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 946, 
+        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 957, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25922,9 +26116,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1561 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM"
+    // Pos:1572 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM"
     {
-        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 946, 
+        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 957, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25939,9 +26133,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1562 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM"
+    // Pos:1573 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM"
     {
-        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 947, 
+        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 958, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25957,9 +26151,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1563 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM"
+    // Pos:1574 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM"
     {
-        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 947, 
+        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 958, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -25974,9 +26168,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1564 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM"
+    // Pos:1575 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM"
     {
-        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 948, 
+        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 959, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25992,9 +26186,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1565 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM"
+    // Pos:1576 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM"
     {
-        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 948, 
+        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 959, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26009,9 +26203,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1566 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM"
+    // Pos:1577 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM"
     {
-        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 949, 
+        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 960, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26027,9 +26221,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1567 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM"
+    // Pos:1578 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM"
     {
-        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 949, 
+        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 960, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26044,9 +26238,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1568 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM"
+    // Pos:1579 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM"
     {
-        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 950, 
+        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 961, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26062,9 +26256,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1569 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM"
+    // Pos:1580 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM"
     {
-        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 950, 
+        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 961, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26079,9 +26273,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1570 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM"
+    // Pos:1581 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM"
     {
-        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 951, 
+        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 962, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26097,9 +26291,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1571 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM"
+    // Pos:1582 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM"
     {
-        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 951, 
+        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 962, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26114,9 +26308,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1572 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM"
+    // Pos:1583 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM"
     {
-        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 952, 
+        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 963, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26132,9 +26326,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1573 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM"
+    // Pos:1584 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM"
     {
-        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 952, 
+        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 963, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26149,9 +26343,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1574 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM"
+    // Pos:1585 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM"
     {
-        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 953, 
+        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 964, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26167,9 +26361,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1575 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM"
+    // Pos:1586 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM"
     {
-        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 953, 
+        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 964, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26184,9 +26378,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1576 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM"
+    // Pos:1587 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM"
     {
-        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 954, 
+        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 965, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26202,9 +26396,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1577 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM"
+    // Pos:1588 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM"
     {
-        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 954, 
+        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 965, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26219,9 +26413,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1578 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM"
+    // Pos:1589 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM"
     {
-        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 955, 
+        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 966, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26237,9 +26431,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1579 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM"
+    // Pos:1590 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM"
     {
-        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 955, 
+        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 966, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26254,9 +26448,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1580 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM"
+    // Pos:1591 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM"
     {
-        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 956, 
+        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 967, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26272,9 +26466,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1581 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM"
+    // Pos:1592 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM"
     {
-        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 956, 
+        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 967, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26289,9 +26483,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1582 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM"
+    // Pos:1593 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM"
     {
-        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 957, 
+        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 968, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26307,9 +26501,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1583 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM"
+    // Pos:1594 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM"
     {
-        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 957, 
+        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 968, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26324,9 +26518,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1584 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM"
+    // Pos:1595 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 958, 
+        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 969, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26342,9 +26536,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1585 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM"
+    // Pos:1596 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 958, 
+        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 969, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26359,9 +26553,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1586 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM"
+    // Pos:1597 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 959, 
+        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 970, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26377,9 +26571,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1587 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM"
+    // Pos:1598 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 959, 
+        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 970, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26394,9 +26588,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1588 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM"
+    // Pos:1599 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 960, 
+        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 971, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26412,9 +26606,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1589 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM"
+    // Pos:1600 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 960, 
+        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 971, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26429,9 +26623,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1590 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM"
+    // Pos:1601 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 961, 
+        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 972, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26447,9 +26641,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1591 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM"
+    // Pos:1602 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 961, 
+        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 972, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26464,9 +26658,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1592 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM"
+    // Pos:1603 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 962, 
+        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 973, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26482,9 +26676,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1593 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM"
+    // Pos:1604 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 962, 
+        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 973, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26499,9 +26693,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1594 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM"
+    // Pos:1605 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 963, 
+        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 974, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26517,9 +26711,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1595 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM"
+    // Pos:1606 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 963, 
+        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 974, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26534,9 +26728,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1596 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML"
+    // Pos:1607 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML"
     {
-        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 964, 
+        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 975, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26552,9 +26746,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1597 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM"
+    // Pos:1608 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 964, 
+        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 975, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26570,9 +26764,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1598 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML"
+    // Pos:1609 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML"
     {
-        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 965, 
+        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 976, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26588,9 +26782,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1599 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM"
+    // Pos:1610 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 965, 
+        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 976, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26606,9 +26800,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1600 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML"
+    // Pos:1611 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML"
     {
-        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 966, 
+        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 977, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26624,9 +26818,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1601 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM"
+    // Pos:1612 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 966, 
+        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 977, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26642,9 +26836,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1602 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML"
+    // Pos:1613 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML"
     {
-        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 967, 
+        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 978, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26660,9 +26854,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1603 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM"
+    // Pos:1614 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 967, 
+        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 978, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26678,9 +26872,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1604 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML"
+    // Pos:1615 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML"
     {
-        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 968, 
+        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 979, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26696,9 +26890,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1605 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM"
+    // Pos:1616 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 968, 
+        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 979, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26714,9 +26908,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1606 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML"
+    // Pos:1617 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML"
     {
-        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 969, 
+        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 980, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26732,9 +26926,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1607 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM"
+    // Pos:1618 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 969, 
+        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 980, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -26750,9 +26944,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1608 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM"
+    // Pos:1619 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM"
     {
-        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 970, 
+        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 981, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26768,9 +26962,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1609 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM"
+    // Pos:1620 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM"
     {
-        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 970, 
+        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 981, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26785,9 +26979,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1610 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM"
+    // Pos:1621 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM"
     {
-        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 971, 
+        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 982, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26803,9 +26997,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1611 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM"
+    // Pos:1622 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM"
     {
-        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 971, 
+        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 982, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26820,9 +27014,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1612 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM"
+    // Pos:1623 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM"
     {
-        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 972, 
+        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 983, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26838,9 +27032,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1613 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM"
+    // Pos:1624 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM"
     {
-        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 972, 
+        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 983, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26855,9 +27049,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1614 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM"
+    // Pos:1625 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM"
     {
-        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 973, 
+        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 984, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26873,9 +27067,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1615 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM"
+    // Pos:1626 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM"
     {
-        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 973, 
+        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 984, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26890,9 +27084,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1616 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM"
+    // Pos:1627 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM"
     {
-        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 974, 
+        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 985, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26908,9 +27102,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1617 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM"
+    // Pos:1628 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM"
     {
-        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 974, 
+        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 985, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26925,9 +27119,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1618 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM"
+    // Pos:1629 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM"
     {
-        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 975, 
+        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 986, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26943,9 +27137,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1619 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM"
+    // Pos:1630 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM"
     {
-        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 975, 
+        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 986, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26960,9 +27154,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1620 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM"
+    // Pos:1631 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM"
     {
-        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 976, 
+        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 987, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26978,9 +27172,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1621 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM"
+    // Pos:1632 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM"
     {
-        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 976, 
+        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 987, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -26995,9 +27189,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1622 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM"
+    // Pos:1633 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM"
     {
-        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 977, 
+        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 988, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27013,9 +27207,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1623 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM"
+    // Pos:1634 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM"
     {
-        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 977, 
+        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 988, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27030,9 +27224,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1624 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM"
+    // Pos:1635 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM"
     {
-        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 978, 
+        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 989, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27048,9 +27242,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1625 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM"
+    // Pos:1636 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM"
     {
-        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 978, 
+        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 989, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27065,9 +27259,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1626 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM"
+    // Pos:1637 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM"
     {
-        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 979, 
+        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 990, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27083,9 +27277,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1627 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM"
+    // Pos:1638 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM"
     {
-        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 979, 
+        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 990, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27100,9 +27294,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1628 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM"
+    // Pos:1639 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM"
     {
-        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 980, 
+        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 991, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27118,9 +27312,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1629 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM"
+    // Pos:1640 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM"
     {
-        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 980, 
+        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 991, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27135,9 +27329,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1630 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM"
+    // Pos:1641 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM"
     {
-        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 981, 
+        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 992, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27153,9 +27347,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1631 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM"
+    // Pos:1642 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM"
     {
-        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 981, 
+        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 992, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27170,9 +27364,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1632 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML"
+    // Pos:1643 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML"
     {
-        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 982, 
+        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 993, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27188,9 +27382,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1633 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM"
+    // Pos:1644 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 982, 
+        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 993, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27206,9 +27400,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1634 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML"
+    // Pos:1645 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML"
     {
-        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 983, 
+        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 994, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27224,9 +27418,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1635 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM"
+    // Pos:1646 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 983, 
+        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 994, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27242,9 +27436,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1636 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML"
+    // Pos:1647 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML"
     {
-        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 984, 
+        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 995, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27260,9 +27454,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1637 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM"
+    // Pos:1648 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 984, 
+        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 995, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27278,9 +27472,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1638 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML"
+    // Pos:1649 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML"
     {
-        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 985, 
+        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 996, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27296,9 +27490,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1639 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM"
+    // Pos:1650 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 985, 
+        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 996, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27314,9 +27508,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1640 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM"
+    // Pos:1651 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 986, 
+        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 997, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27332,9 +27526,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1641 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM"
+    // Pos:1652 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM"
     {
-        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 986, 
+        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 997, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27349,9 +27543,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1642 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM"
+    // Pos:1653 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 987, 
+        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 998, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27367,9 +27561,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1643 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM"
+    // Pos:1654 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM"
     {
-        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 987, 
+        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 998, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27384,9 +27578,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1644 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM"
+    // Pos:1655 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 988, 
+        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 999, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27402,9 +27596,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1645 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM"
+    // Pos:1656 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM"
     {
-        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 988, 
+        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 999, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27419,9 +27613,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1646 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM"
+    // Pos:1657 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 989, 
+        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1000, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27437,9 +27631,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1647 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM"
+    // Pos:1658 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM"
     {
-        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 989, 
+        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1000, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27454,9 +27648,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1648 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM"
+    // Pos:1659 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 990, 
+        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1001, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27472,9 +27666,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1649 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM"
+    // Pos:1660 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM"
     {
-        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 990, 
+        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1001, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27489,9 +27683,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1650 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM"
+    // Pos:1661 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 991, 
+        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1002, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27507,9 +27701,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1651 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM"
+    // Pos:1662 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM"
     {
-        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 991, 
+        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1002, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27524,9 +27718,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1652 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM"
+    // Pos:1663 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 992, 
+        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1003, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27542,9 +27736,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1653 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM"
+    // Pos:1664 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM"
     {
-        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 992, 
+        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1003, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27559,9 +27753,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1654 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM"
+    // Pos:1665 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 993, 
+        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1004, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27577,9 +27771,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1655 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM"
+    // Pos:1666 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM"
     {
-        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 993, 
+        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1004, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27594,9 +27788,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1656 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM"
+    // Pos:1667 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 994, 
+        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1005, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27612,9 +27806,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1657 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM"
+    // Pos:1668 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM"
     {
-        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 994, 
+        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1005, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27629,9 +27823,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1658 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM"
+    // Pos:1669 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 995, 
+        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1006, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27647,9 +27841,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1659 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM"
+    // Pos:1670 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM"
     {
-        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 995, 
+        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1006, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27664,9 +27858,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1660 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM"
+    // Pos:1671 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 996, 
+        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1007, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27682,9 +27876,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1661 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM"
+    // Pos:1672 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM"
     {
-        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 996, 
+        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1007, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27699,9 +27893,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1662 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM"
+    // Pos:1673 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 997, 
+        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1008, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27717,9 +27911,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1663 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM"
+    // Pos:1674 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM"
     {
-        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 997, 
+        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1008, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27734,9 +27928,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1664 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML"
+    // Pos:1675 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 998, 
+        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1009, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27752,9 +27946,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1665 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM"
+    // Pos:1676 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 998, 
+        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1009, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27770,9 +27964,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1666 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML"
+    // Pos:1677 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 999, 
+        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1010, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27788,9 +27982,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1667 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM"
+    // Pos:1678 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 999, 
+        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1010, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27806,9 +28000,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1668 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML"
+    // Pos:1679 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1000, 
+        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1011, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27824,9 +28018,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1669 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM"
+    // Pos:1680 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1000, 
+        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1011, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27842,9 +28036,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1670 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML"
+    // Pos:1681 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1001, 
+        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1012, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27860,9 +28054,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1671 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM"
+    // Pos:1682 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1001, 
+        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1012, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27878,9 +28072,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1672 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI"
+    // Pos:1683 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1002, 
+        ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1013, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -27896,9 +28090,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1673 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI"
+    // Pos:1684 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1003, 
+        ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1014, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -27914,9 +28108,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1674 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI"
+    // Pos:1685 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1004, 
+        ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1015, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -27932,9 +28126,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1675 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI"
+    // Pos:1686 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1005, 
+        ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1016, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -27950,9 +28144,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1676 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM"
+    // Pos:1687 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM"
     {
-        ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1006, 
+        ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1017, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -27966,9 +28160,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1677 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM"
+    // Pos:1688 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM"
     {
-        ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1007, 
+        ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1018, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -27982,9 +28176,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1678 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM"
+    // Pos:1689 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM"
     {
-        ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1008, 
+        ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1019, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -27998,9 +28192,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1679 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM"
+    // Pos:1690 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM"
     {
-        ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1009, 
+        ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1020, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -28014,9 +28208,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1680 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM"
+    // Pos:1691 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1010, 
+        ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1021, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28031,9 +28225,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1681 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV"
+    // Pos:1692 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1010, 
+        ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1021, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -28048,9 +28242,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1682 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM"
+    // Pos:1693 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1011, 
+        ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1022, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28065,9 +28259,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1683 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV"
+    // Pos:1694 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1011, 
+        ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1022, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -28082,9 +28276,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1684 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA"
+    // Pos:1695 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1012, 
+        ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1023, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28098,9 +28292,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1685 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA"
+    // Pos:1696 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1013, 
+        ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1024, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28114,9 +28308,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1686 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA"
+    // Pos:1697 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1014, 
+        ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1025, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28130,9 +28324,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1687 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA"
+    // Pos:1698 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1015, 
+        ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1026, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28146,9 +28340,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1688 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA"
+    // Pos:1699 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1016, 
+        ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1027, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28162,9 +28356,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1689 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA"
+    // Pos:1700 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1017, 
+        ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1028, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28178,9 +28372,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1690 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA"
+    // Pos:1701 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1018, 
+        ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1029, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28194,9 +28388,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1691 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA"
+    // Pos:1702 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1019, 
+        ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1030, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -28210,9 +28404,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1692 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM"
+    // Pos:1703 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1020, 
+        ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1031, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28227,9 +28421,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1693 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV"
+    // Pos:1704 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1020, 
+        ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1031, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -28244,9 +28438,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1694 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM"
+    // Pos:1705 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1021, 
+        ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1032, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28261,9 +28455,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1695 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV"
+    // Pos:1706 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1021, 
+        ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1032, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -28278,9 +28472,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1696 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM"
+    // Pos:1707 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM"
     {
-        ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1022, 
+        ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1033, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28295,9 +28489,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1697 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM"
+    // Pos:1708 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM"
     {
-        ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1023, 
+        ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1034, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28312,9 +28506,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1698 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM"
+    // Pos:1709 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM"
     {
-        ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1024, 
+        ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1035, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28330,9 +28524,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1699 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM"
+    // Pos:1710 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM"
     {
-        ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1025, 
+        ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1036, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28348,9 +28542,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1700 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI"
+    // Pos:1711 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI"
     {
-        ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1026, 
+        ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1037, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28366,9 +28560,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1701 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI"
+    // Pos:1712 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI"
     {
-        ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1027, 
+        ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1038, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28384,9 +28578,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1702 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI"
+    // Pos:1713 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI"
     {
-        ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1028, 
+        ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1039, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28403,9 +28597,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1703 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI"
+    // Pos:1714 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI"
     {
-        ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1029, 
+        ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1040, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28422,9 +28616,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1704 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI"
+    // Pos:1715 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI"
     {
-        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1030, 
+        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1041, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -28441,9 +28635,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1705 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI"
+    // Pos:1716 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI"
     {
-        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1030, 
+        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1041, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -28459,9 +28653,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1706 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI"
+    // Pos:1717 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI"
     {
-        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1031, 
+        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1042, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -28478,9 +28672,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1707 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI"
+    // Pos:1718 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI"
     {
-        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1031, 
+        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1042, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -28496,9 +28690,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1708 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM"
+    // Pos:1719 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM"
     {
-        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1032, 
+        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1043, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -28514,9 +28708,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1709 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM"
+    // Pos:1720 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM"
     {
-        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1032, 
+        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1043, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -28531,9 +28725,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1710 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM"
+    // Pos:1721 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM"
     {
-        ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1033, 
+        ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1044, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28548,9 +28742,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1711 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM"
+    // Pos:1722 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM"
     {
-        ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1034, 
+        ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1045, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28565,9 +28759,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1712 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM"
+    // Pos:1723 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM"
     {
-        ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1035, 
+        ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1046, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28582,9 +28776,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1713 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM"
+    // Pos:1724 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM"
     {
-        ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1036, 
+        ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1047, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28599,9 +28793,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1714 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI"
+    // Pos:1725 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI"
     {
-        ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1037, 
+        ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1048, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28617,9 +28811,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1715 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI"
+    // Pos:1726 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1038, 
+        ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1049, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28636,9 +28830,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1716 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI"
+    // Pos:1727 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1039, 
+        ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1050, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -28655,9 +28849,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1717 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI"
+    // Pos:1728 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1040, 
+        ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1051, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -28674,9 +28868,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1718 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI"
+    // Pos:1729 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1041, 
+        ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1052, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28693,9 +28887,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1719 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI"
+    // Pos:1730 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI"
     {
-        ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1042, 
+        ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1053, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -28711,9 +28905,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1720 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI"
+    // Pos:1731 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1043, 
+        ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1054, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28730,9 +28924,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1721 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI"
+    // Pos:1732 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1044, 
+        ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1055, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -28749,9 +28943,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1722 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI"
+    // Pos:1733 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1045, 
+        ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1056, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -28768,9 +28962,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1723 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI"
+    // Pos:1734 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1046, 
+        ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1057, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28787,9 +28981,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1724 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
+    // Pos:1735 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1047, 
+        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1058, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28805,9 +28999,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1725 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
+    // Pos:1736 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1047, 
+        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1058, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28823,9 +29017,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1726 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
+    // Pos:1737 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1047, 
+        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1058, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28841,9 +29035,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1727 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
+    // Pos:1738 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1047, 
+        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1058, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28859,9 +29053,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1728 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM"
+    // Pos:1739 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM"
     {
-        ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1048, 
+        ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1059, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28875,9 +29069,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1729 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M"
+    // Pos:1740 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M"
     {
-        ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1049, 
+        ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1060, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, 
@@ -28891,9 +29085,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1730 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM"
+    // Pos:1741 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM"
     {
-        ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1050, 
+        ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1061, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28908,9 +29102,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1731 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM"
+    // Pos:1742 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM"
     {
-        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1051, 
+        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1062, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28925,9 +29119,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1732 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR"
+    // Pos:1743 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR"
     {
-        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1051, 
+        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1062, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28942,9 +29136,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1733 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM"
+    // Pos:1744 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM"
     {
-        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1052, 
+        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1063, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28959,9 +29153,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1734 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR"
+    // Pos:1745 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR"
     {
-        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1052, 
+        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1063, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -28976,9 +29170,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1735 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM"
+    // Pos:1746 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1053, 
+        ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1064, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28994,9 +29188,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1736 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM"
+    // Pos:1747 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1053, 
+        ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1064, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29011,9 +29205,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1737 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM"
+    // Pos:1748 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1054, 
+        ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1065, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29029,9 +29223,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1738 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM"
+    // Pos:1749 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1054, 
+        ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1065, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29046,9 +29240,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1739 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM"
+    // Pos:1750 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1055, 
+        ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1066, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29064,9 +29258,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1740 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM"
+    // Pos:1751 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1055, 
+        ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1066, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29081,9 +29275,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1741 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM"
+    // Pos:1752 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1056, 
+        ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1067, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29099,9 +29293,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1742 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM"
+    // Pos:1753 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1056, 
+        ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1067, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29116,9 +29310,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1743 Instruction:"VMCALL" Encoding:"0x0F 0x01 /0xC1"/""
+    // Pos:1754 Instruction:"VMCALL" Encoding:"0x0F 0x01 /0xC1"/""
     {
-        ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1057, 
+        ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1068, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -29131,9 +29325,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1744 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M"
+    // Pos:1755 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M"
     {
-        ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1058, 
+        ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1069, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -29147,9 +29341,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1745 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/""
+    // Pos:1756 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/""
     {
-        ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1059, 
+        ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1070, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -29162,9 +29356,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1746 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/""
+    // Pos:1757 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1060, 
+        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1071, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -29177,9 +29371,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1747 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/""
+    // Pos:1758 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1060, 
+        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1071, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -29192,9 +29386,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1748 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM"
+    // Pos:1759 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1061, 
+        ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1072, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29210,9 +29404,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1749 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM"
+    // Pos:1760 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1061, 
+        ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1072, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29227,9 +29421,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1750 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM"
+    // Pos:1761 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1062, 
+        ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1073, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29245,9 +29439,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1751 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM"
+    // Pos:1762 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1062, 
+        ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1073, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29262,9 +29456,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1752 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM"
+    // Pos:1763 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1063, 
+        ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1074, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29280,9 +29474,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1753 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM"
+    // Pos:1764 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1063, 
+        ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1074, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29297,9 +29491,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1754 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM"
+    // Pos:1765 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1064, 
+        ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1075, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29315,9 +29509,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1755 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM"
+    // Pos:1766 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1064, 
+        ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1075, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29332,9 +29526,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1756 Instruction:"VMLAUNCH" Encoding:"0x0F 0x01 /0xC2"/""
+    // Pos:1767 Instruction:"VMLAUNCH" Encoding:"0x0F 0x01 /0xC2"/""
     {
-        ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1065, 
+        ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1076, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -29347,9 +29541,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1757 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/""
+    // Pos:1768 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/""
     {
-        ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1066, 
+        ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1077, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -29362,9 +29556,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1758 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/""
+    // Pos:1769 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1067, 
+        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1078, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -29377,9 +29571,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1759 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/""
+    // Pos:1770 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1067, 
+        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1078, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -29392,9 +29586,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1760 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM"
+    // Pos:1771 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1068, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1079, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29409,9 +29603,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1761 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR"
+    // Pos:1772 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1068, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1079, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29426,9 +29620,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1762 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM"
+    // Pos:1773 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1068, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1079, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29442,9 +29636,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1763 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR"
+    // Pos:1774 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1068, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1079, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29458,9 +29652,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1764 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM"
+    // Pos:1775 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1069, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1080, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29475,9 +29669,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1765 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR"
+    // Pos:1776 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1069, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1080, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29492,9 +29686,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1766 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM"
+    // Pos:1777 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1069, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1080, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29508,9 +29702,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1767 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR"
+    // Pos:1778 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1069, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1080, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29524,9 +29718,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1768 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
+    // Pos:1779 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1070, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1081, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29540,9 +29734,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1769 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
+    // Pos:1780 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1070, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1081, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29556,9 +29750,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1770 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
+    // Pos:1781 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1070, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1081, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29572,9 +29766,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1771 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
+    // Pos:1782 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1070, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1081, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29588,9 +29782,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1772 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM"
+    // Pos:1783 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1071, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1082, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29605,9 +29799,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1773 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM"
+    // Pos:1784 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1071, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1082, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29622,9 +29816,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1774 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM"
+    // Pos:1785 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1071, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1082, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29639,9 +29833,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1775 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM"
+    // Pos:1786 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1071, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1082, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29655,9 +29849,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1776 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM"
+    // Pos:1787 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1071, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1082, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29671,9 +29865,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1777 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM"
+    // Pos:1788 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM"
     {
-        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1072, 
+        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1083, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29687,9 +29881,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1778 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR"
+    // Pos:1789 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR"
     {
-        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1072, 
+        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1083, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29703,9 +29897,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1779 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM"
+    // Pos:1790 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1073, 
+        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29720,9 +29914,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1780 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR"
+    // Pos:1791 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1073, 
+        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29737,9 +29931,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1781 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM"
+    // Pos:1792 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1074, 
+        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29754,9 +29948,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1782 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR"
+    // Pos:1793 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1074, 
+        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29771,9 +29965,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1783 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM"
+    // Pos:1794 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM"
     {
-        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1075, 
+        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1086, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29787,9 +29981,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1784 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR"
+    // Pos:1795 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR"
     {
-        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1075, 
+        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1086, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29803,9 +29997,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1785 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM"
+    // Pos:1796 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1076, 
+        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1087, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -29820,9 +30014,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1786 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR"
+    // Pos:1797 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1076, 
+        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1087, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -29837,9 +30031,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1787 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM"
+    // Pos:1798 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1077, 
+        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29854,9 +30048,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1788 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR"
+    // Pos:1799 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1077, 
+        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29871,9 +30065,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1789 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM"
+    // Pos:1800 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1078, 
+        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29888,9 +30082,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1790 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR"
+    // Pos:1801 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1078, 
+        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29905,9 +30099,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1791 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM"
+    // Pos:1802 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1079, 
+        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1090, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -29922,9 +30116,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1792 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR"
+    // Pos:1803 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1079, 
+        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1090, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -29939,9 +30133,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1793 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM"
+    // Pos:1804 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM"
     {
-        ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1080, 
+        ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1091, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29956,9 +30150,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1794 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM"
+    // Pos:1805 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM"
     {
-        ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1080, 
+        ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1091, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -29973,9 +30167,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1795 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM"
+    // Pos:1806 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1081, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29990,9 +30184,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1796 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR"
+    // Pos:1807 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1081, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30006,9 +30200,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1797 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM"
+    // Pos:1808 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1081, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1092, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30023,9 +30217,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1798 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR"
+    // Pos:1809 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1081, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1092, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30039,9 +30233,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1799 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM"
+    // Pos:1810 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1082, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1093, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30056,9 +30250,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1800 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR"
+    // Pos:1811 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1082, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1093, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30072,9 +30266,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1801 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM"
+    // Pos:1812 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1082, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1093, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30089,9 +30283,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1802 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR"
+    // Pos:1813 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1082, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1093, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30105,9 +30299,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1803 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM"
+    // Pos:1814 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM"
     {
-        ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1083, 
+        ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1094, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30122,9 +30316,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1804 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM"
+    // Pos:1815 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM"
     {
-        ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1083, 
+        ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1094, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30139,9 +30333,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1805 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM"
+    // Pos:1816 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1095, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30156,9 +30350,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1806 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR"
+    // Pos:1817 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1095, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30172,9 +30366,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1807 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM"
+    // Pos:1818 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1084, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1095, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30189,9 +30383,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1808 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR"
+    // Pos:1819 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1084, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1095, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30205,9 +30399,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1809 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM"
+    // Pos:1820 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1096, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30222,9 +30416,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1810 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR"
+    // Pos:1821 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1096, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30238,9 +30432,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1811 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM"
+    // Pos:1822 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1085, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1096, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30255,9 +30449,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1812 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR"
+    // Pos:1823 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1085, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1096, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30271,9 +30465,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1813 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM"
+    // Pos:1824 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM"
     {
-        ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1086, 
+        ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1097, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30287,9 +30481,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1814 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM"
+    // Pos:1825 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM"
     {
-        ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1087, 
+        ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1098, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30303,9 +30497,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1815 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR"
+    // Pos:1826 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR"
     {
-        ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
+        ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1099, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30319,9 +30513,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1816 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR"
+    // Pos:1827 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR"
     {
-        ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1088, 
+        ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1099, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30335,9 +30529,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1817 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM"
+    // Pos:1828 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM"
     {
-        ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
+        ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1100, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30351,9 +30545,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1818 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM"
+    // Pos:1829 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM"
     {
-        ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1089, 
+        ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1100, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30367,9 +30561,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1819 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR"
+    // Pos:1830 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1090, 
+        ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1101, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30383,9 +30577,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1820 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR"
+    // Pos:1831 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1090, 
+        ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1101, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30399,9 +30593,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1821 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR"
+    // Pos:1832 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1091, 
+        ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1102, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30415,9 +30609,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1822 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR"
+    // Pos:1833 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1091, 
+        ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1102, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30431,9 +30625,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1823 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
+    // Pos:1834 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30447,9 +30641,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1824 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
+    // Pos:1835 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30463,9 +30657,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1825 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM"
+    // Pos:1836 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30479,9 +30673,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1826 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR"
+    // Pos:1837 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30495,9 +30689,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1827 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
+    // Pos:1838 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1092, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30511,9 +30705,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1828 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
+    // Pos:1839 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1092, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30527,9 +30721,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1829 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM"
+    // Pos:1840 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1092, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30543,9 +30737,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1830 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR"
+    // Pos:1841 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1092, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30559,9 +30753,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1831 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM"
+    // Pos:1842 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1093, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1104, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30576,9 +30770,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1832 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM"
+    // Pos:1843 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1093, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1104, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30594,9 +30788,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1833 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR"
+    // Pos:1844 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1093, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1104, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30611,9 +30805,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1834 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR"
+    // Pos:1845 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1093, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1104, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30629,9 +30823,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1835 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM"
+    // Pos:1846 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1093, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1104, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30646,9 +30840,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1836 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM"
+    // Pos:1847 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1093, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1104, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30662,9 +30856,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1837 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR"
+    // Pos:1848 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1093, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1104, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30679,9 +30873,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1838 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR"
+    // Pos:1849 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1093, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1104, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30695,9 +30889,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1839 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM"
+    // Pos:1850 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM"
     {
-        ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1094, 
+        ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1105, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30712,9 +30906,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1840 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM"
+    // Pos:1851 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM"
     {
-        ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1094, 
+        ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1105, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30728,9 +30922,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1841 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM"
+    // Pos:1852 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1095, 
+        ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1106, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30745,9 +30939,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1842 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM"
+    // Pos:1853 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM"
     {
-        ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1095, 
+        ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1106, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30761,9 +30955,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1843 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM"
+    // Pos:1854 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1096, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30778,9 +30972,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1844 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
+    // Pos:1855 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1096, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30796,9 +30990,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1845 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR"
+    // Pos:1856 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1096, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30813,9 +31007,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1846 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
+    // Pos:1857 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1096, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1107, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30831,9 +31025,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1847 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM"
+    // Pos:1858 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1096, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1107, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30848,9 +31042,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1848 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM"
+    // Pos:1859 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1096, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1107, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30864,9 +31058,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1849 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR"
+    // Pos:1860 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1096, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1107, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30881,9 +31075,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1850 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR"
+    // Pos:1861 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1096, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1107, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30897,9 +31091,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1851 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM"
+    // Pos:1862 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1097, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1108, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30914,9 +31108,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1852 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR"
+    // Pos:1863 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1097, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1108, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30931,9 +31125,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1853 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM"
+    // Pos:1864 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1097, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1108, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30947,9 +31141,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1854 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR"
+    // Pos:1865 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1097, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1108, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -30963,9 +31157,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1855 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM"
+    // Pos:1866 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1098, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1109, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30980,9 +31174,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1856 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR"
+    // Pos:1867 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1098, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1109, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30997,9 +31191,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1857 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM"
+    // Pos:1868 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1098, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1109, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31013,9 +31207,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1858 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR"
+    // Pos:1869 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1098, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1109, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31029,9 +31223,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1859 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI"
+    // Pos:1870 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI"
     {
-        ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1099, 
+        ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1110, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31047,9 +31241,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1860 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M"
+    // Pos:1871 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M"
     {
-        ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1100, 
+        ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1111, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31063,9 +31257,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1861 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M"
+    // Pos:1872 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M"
     {
-        ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1101, 
+        ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1112, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31079,9 +31273,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1862 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR"
+    // Pos:1873 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR"
     {
-        ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1102, 
+        ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1113, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31096,9 +31290,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1863 Instruction:"VMRESUME" Encoding:"0x0F 0x01 /0xC3"/""
+    // Pos:1874 Instruction:"VMRESUME" Encoding:"0x0F 0x01 /0xC3"/""
     {
-        ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1103, 
+        ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1114, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31111,9 +31305,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1864 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/""
+    // Pos:1875 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/""
     {
-        ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1104, 
+        ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1115, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -31126,9 +31320,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1865 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/""
+    // Pos:1876 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/""
     {
-        ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1105, 
+        ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1116, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -31141,9 +31335,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1866 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM"
+    // Pos:1877 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1106, 
+        ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1117, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31159,9 +31353,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1867 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM"
+    // Pos:1878 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1106, 
+        ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1117, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31176,9 +31370,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1868 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM"
+    // Pos:1879 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1107, 
+        ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1118, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31194,9 +31388,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1869 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM"
+    // Pos:1880 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1107, 
+        ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1118, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31211,9 +31405,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1870 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM"
+    // Pos:1881 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1108, 
+        ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1119, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31229,9 +31423,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1871 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM"
+    // Pos:1882 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1108, 
+        ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1119, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31246,9 +31440,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1872 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM"
+    // Pos:1883 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1109, 
+        ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1120, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31264,9 +31458,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1873 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM"
+    // Pos:1884 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1109, 
+        ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1120, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31281,9 +31475,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1874 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM"
+    // Pos:1885 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM"
     {
-        ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1110, 
+        ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1121, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31298,9 +31492,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1875 Instruction:"VMXOFF" Encoding:"0x0F 0x01 /0xC4"/""
+    // Pos:1886 Instruction:"VMXOFF" Encoding:"0x0F 0x01 /0xC4"/""
     {
-        ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1111, 
+        ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1122, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31313,9 +31507,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1876 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M"
+    // Pos:1887 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M"
     {
-        ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1112, 
+        ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1123, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31329,9 +31523,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1877 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM"
+    // Pos:1888 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM"
     {
-        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1113, 
+        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1124, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -31347,9 +31541,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1878 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM"
+    // Pos:1889 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM"
     {
-        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1113, 
+        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1124, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31364,9 +31558,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1879 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM"
+    // Pos:1890 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM"
     {
-        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1114, 
+        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1125, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -31382,9 +31576,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1880 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM"
+    // Pos:1891 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM"
     {
-        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1114, 
+        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1125, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31399,9 +31593,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1881 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM"
+    // Pos:1892 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM"
     {
-        ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1115, 
+        ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1126, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, 
@@ -31416,9 +31610,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1882 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM"
+    // Pos:1893 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM"
     {
-        ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1116, 
+        ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1127, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, 
@@ -31433,9 +31627,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1883 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM"
+    // Pos:1894 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM"
     {
-        ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1117, 
+        ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1128, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, 
@@ -31451,9 +31645,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1884 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM"
+    // Pos:1895 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM"
     {
-        ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1118, 
+        ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1129, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, 
@@ -31469,9 +31663,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1885 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM"
+    // Pos:1896 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM"
     {
-        ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1119, 
+        ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1130, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31486,9 +31680,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1886 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM"
+    // Pos:1897 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM"
     {
-        ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1119, 
+        ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1130, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31502,9 +31696,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1887 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM"
+    // Pos:1898 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM"
     {
-        ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1120, 
+        ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1131, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31519,9 +31713,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1888 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM"
+    // Pos:1899 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM"
     {
-        ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1120, 
+        ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1131, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31535,9 +31729,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1889 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM"
+    // Pos:1900 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM"
     {
-        ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1121, 
+        ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1132, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31552,9 +31746,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1890 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM"
+    // Pos:1901 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM"
     {
-        ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1122, 
+        ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1133, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31569,9 +31763,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1891 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM"
+    // Pos:1902 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM"
     {
-        ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1122, 
+        ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1133, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31585,9 +31779,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1892 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM"
+    // Pos:1903 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM"
     {
-        ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1123, 
+        ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1134, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31603,9 +31797,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1893 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM"
+    // Pos:1904 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM"
     {
-        ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1123, 
+        ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1134, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31620,9 +31814,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1894 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM"
+    // Pos:1905 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM"
     {
-        ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1124, 
+        ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1135, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31638,9 +31832,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1895 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM"
+    // Pos:1906 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM"
     {
-        ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1124, 
+        ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1135, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31655,9 +31849,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1896 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM"
+    // Pos:1907 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM"
     {
-        ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1125, 
+        ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1136, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31673,9 +31867,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1897 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM"
+    // Pos:1908 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM"
     {
-        ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1125, 
+        ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1136, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31690,9 +31884,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1898 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM"
+    // Pos:1909 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM"
     {
-        ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1126, 
+        ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1137, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31708,9 +31902,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1899 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM"
+    // Pos:1910 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM"
     {
-        ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1126, 
+        ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1137, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31725,9 +31919,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1900 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM"
+    // Pos:1911 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM"
     {
-        ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1127, 
+        ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1138, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31743,9 +31937,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1901 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM"
+    // Pos:1912 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM"
     {
-        ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1127, 
+        ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1138, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31760,9 +31954,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1902 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM"
+    // Pos:1913 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM"
     {
-        ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1128, 
+        ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1139, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31778,9 +31972,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1903 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM"
+    // Pos:1914 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM"
     {
-        ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1128, 
+        ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1139, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31795,9 +31989,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1904 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM"
+    // Pos:1915 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM"
     {
-        ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1129, 
+        ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1140, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31813,9 +32007,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1905 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM"
+    // Pos:1916 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM"
     {
-        ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1129, 
+        ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1140, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31830,9 +32024,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1906 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM"
+    // Pos:1917 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM"
     {
-        ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1130, 
+        ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1141, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31848,9 +32042,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1907 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM"
+    // Pos:1918 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM"
     {
-        ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1130, 
+        ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1141, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31865,9 +32059,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1908 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM"
+    // Pos:1919 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM"
     {
-        ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1131, 
+        ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1142, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31883,9 +32077,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1909 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM"
+    // Pos:1920 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM"
     {
-        ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1131, 
+        ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1142, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31900,9 +32094,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1910 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM"
+    // Pos:1921 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM"
     {
-        ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1132, 
+        ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1143, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31918,9 +32112,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1911 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM"
+    // Pos:1922 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM"
     {
-        ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1132, 
+        ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1143, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31935,9 +32129,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1912 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM"
+    // Pos:1923 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM"
     {
-        ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1133, 
+        ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1144, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31953,9 +32147,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1913 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM"
+    // Pos:1924 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM"
     {
-        ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1133, 
+        ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1144, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31970,9 +32164,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1914 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM"
+    // Pos:1925 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM"
     {
-        ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1134, 
+        ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1145, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -31988,9 +32182,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1915 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM"
+    // Pos:1926 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM"
     {
-        ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1134, 
+        ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1145, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32005,9 +32199,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1916 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI"
+    // Pos:1927 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI"
     {
-        ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1135, 
+        ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1146, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32024,9 +32218,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1917 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI"
+    // Pos:1928 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI"
     {
-        ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1135, 
+        ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1146, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32042,9 +32236,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1918 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM"
+    // Pos:1929 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM"
     {
-        ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1136, 
+        ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1147, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32059,9 +32253,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1919 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM"
+    // Pos:1930 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM"
     {
-        ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1137, 
+        ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1148, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32077,9 +32271,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1920 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM"
+    // Pos:1931 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM"
     {
-        ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1138, 
+        ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1149, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32094,9 +32288,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1921 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM"
+    // Pos:1932 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM"
     {
-        ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1139, 
+        ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1150, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32112,9 +32306,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1922 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM"
+    // Pos:1933 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM"
     {
-        ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1140, 
+        ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1151, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32130,9 +32324,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1923 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM"
+    // Pos:1934 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM"
     {
-        ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1141, 
+        ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1152, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32148,9 +32342,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1924 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM"
+    // Pos:1935 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM"
     {
-        ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1142, 
+        ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1153, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32166,9 +32360,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1925 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM"
+    // Pos:1936 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM"
     {
-        ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1142, 
+        ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1153, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32183,9 +32377,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1926 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM"
+    // Pos:1937 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM"
     {
-        ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1143, 
+        ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1154, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32201,9 +32395,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1927 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM"
+    // Pos:1938 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM"
     {
-        ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1143, 
+        ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1154, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32218,9 +32412,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1928 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI"
+    // Pos:1939 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI"
     {
-        ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1144, 
+        ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1155, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -32236,9 +32430,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1929 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM"
+    // Pos:1940 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1145, 
+        ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1156, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32254,9 +32448,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1930 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM"
+    // Pos:1941 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1146, 
+        ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1157, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32272,9 +32466,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1931 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM"
+    // Pos:1942 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1147, 
+        ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1158, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32290,9 +32484,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1932 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM"
+    // Pos:1943 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1148, 
+        ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1159, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32308,9 +32502,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1933 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML"
+    // Pos:1944 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML"
     {
-        ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1149, 
+        ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1160, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32326,9 +32520,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1934 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI"
+    // Pos:1945 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI"
     {
-        ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1150, 
+        ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1161, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32344,9 +32538,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1935 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1946 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1151, 
+        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1162, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32361,9 +32555,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1936 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM"
+    // Pos:1947 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1151, 
+        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1162, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32378,9 +32572,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1937 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM"
+    // Pos:1948 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM"
     {
-        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1151, 
+        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1162, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -32394,9 +32588,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1938 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM"
+    // Pos:1949 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1152, 
+        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1163, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32411,9 +32605,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1939 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM"
+    // Pos:1950 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1152, 
+        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1163, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32428,9 +32622,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1940 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM"
+    // Pos:1951 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM"
     {
-        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1152, 
+        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1163, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -32444,9 +32638,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1941 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM"
+    // Pos:1952 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM"
     {
-        ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1153, 
+        ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1164, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -32460,9 +32654,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1942 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM"
+    // Pos:1953 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM"
     {
-        ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1154, 
+        ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1165, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -32476,9 +32670,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1943 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM"
+    // Pos:1954 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1155, 
+        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1166, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32493,9 +32687,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1944 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM"
+    // Pos:1955 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1155, 
+        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1166, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32510,9 +32704,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1945 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM"
+    // Pos:1956 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM"
     {
-        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1155, 
+        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1166, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -32526,9 +32720,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1946 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1957 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1156, 
+        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1167, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32543,9 +32737,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1947 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM"
+    // Pos:1958 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1156, 
+        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1167, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32560,9 +32754,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1948 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM"
+    // Pos:1959 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM"
     {
-        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1156, 
+        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1167, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -32576,9 +32770,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1949 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
+    // Pos:1960 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
     {
-        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1157, 
+        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1168, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, 
@@ -32594,9 +32788,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1950 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
+    // Pos:1961 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
     {
-        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1157, 
+        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1168, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, 
@@ -32612,9 +32806,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1951 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML"
+    // Pos:1962 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML"
     {
-        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1158, 
+        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1169, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -32630,9 +32824,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1952 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM"
+    // Pos:1963 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM"
     {
-        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1158, 
+        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1169, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -32648,9 +32842,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1953 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI"
+    // Pos:1964 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1159, 
+        ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1170, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32667,9 +32861,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1954 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI"
+    // Pos:1965 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1160, 
+        ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1171, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32686,9 +32880,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1955 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM"
+    // Pos:1966 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1161, 
+        ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1172, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32704,9 +32898,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1956 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM"
+    // Pos:1967 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM"
     {
-        ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1161, 
+        ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1172, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32721,9 +32915,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1957 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM"
+    // Pos:1968 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1162, 
+        ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1173, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32739,9 +32933,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1958 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM"
+    // Pos:1969 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM"
     {
-        ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1162, 
+        ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1173, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32756,9 +32950,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1959 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM"
+    // Pos:1970 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1163, 
+        ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1174, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32774,9 +32968,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1960 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM"
+    // Pos:1971 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM"
     {
-        ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1163, 
+        ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1174, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32791,9 +32985,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1961 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM"
+    // Pos:1972 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1164, 
+        ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1175, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32809,9 +33003,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1962 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM"
+    // Pos:1973 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM"
     {
-        ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1164, 
+        ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1175, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32826,9 +33020,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1963 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI"
+    // Pos:1974 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI"
     {
-        ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1165, 
+        ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1176, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32847,9 +33041,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1964 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI"
+    // Pos:1975 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI"
     {
-        ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1166, 
+        ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1177, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32868,9 +33062,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1965 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM"
+    // Pos:1976 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1167, 
+        ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1178, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32886,9 +33080,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1966 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM"
+    // Pos:1977 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM"
     {
-        ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1167, 
+        ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1178, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32903,9 +33097,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1967 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM"
+    // Pos:1978 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1168, 
+        ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1179, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32921,9 +33115,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1968 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM"
+    // Pos:1979 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM"
     {
-        ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1168, 
+        ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1179, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32938,9 +33132,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1969 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM"
+    // Pos:1980 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1169, 
+        ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1180, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32956,9 +33150,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1970 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM"
+    // Pos:1981 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM"
     {
-        ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1169, 
+        ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1180, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32973,9 +33167,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1971 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM"
+    // Pos:1982 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1170, 
+        ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1181, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32991,9 +33185,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1972 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM"
+    // Pos:1983 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM"
     {
-        ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1170, 
+        ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1181, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33008,9 +33202,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1973 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI"
+    // Pos:1984 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI"
     {
-        ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1171, 
+        ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1182, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33027,9 +33221,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1974 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI"
+    // Pos:1985 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI"
     {
-        ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1172, 
+        ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1183, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33046,9 +33240,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1975 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI"
+    // Pos:1986 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1173, 
+        ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1184, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33065,9 +33259,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1976 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI"
+    // Pos:1987 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1174, 
+        ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1185, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -33084,9 +33278,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1977 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI"
+    // Pos:1988 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1175, 
+        ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1186, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33103,9 +33297,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1978 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI"
+    // Pos:1989 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1176, 
+        ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1187, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33122,9 +33316,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1979 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI"
+    // Pos:1990 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1177, 
+        ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1188, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -33141,9 +33335,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1980 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI"
+    // Pos:1991 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1178, 
+        ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1189, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -33160,9 +33354,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1981 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI"
+    // Pos:1992 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI"
     {
-        ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1179, 
+        ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1190, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33178,9 +33372,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1982 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI"
+    // Pos:1993 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI"
     {
-        ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1180, 
+        ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1191, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33196,9 +33390,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1983 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR"
+    // Pos:1994 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1181, 
+        ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1192, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -33213,9 +33407,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1984 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR"
+    // Pos:1995 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1182, 
+        ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1193, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33230,9 +33424,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1985 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR"
+    // Pos:1996 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1183, 
+        ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1194, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33247,9 +33441,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1986 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR"
+    // Pos:1997 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1184, 
+        ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1195, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -33264,9 +33458,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1987 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI"
+    // Pos:1998 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI"
     {
-        ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1185, 
+        ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1196, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33282,9 +33476,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1988 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI"
+    // Pos:1999 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1186, 
+        ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1197, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33300,9 +33494,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1989 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI"
+    // Pos:2000 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1187, 
+        ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1198, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33318,9 +33512,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1990 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI"
+    // Pos:2001 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1188, 
+        ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1199, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33336,9 +33530,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1991 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI"
+    // Pos:2002 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1189, 
+        ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1200, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33354,9 +33548,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1992 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI"
+    // Pos:2003 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI"
     {
-        ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1190, 
+        ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1201, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33372,9 +33566,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1993 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM"
+    // Pos:2004 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM"
     {
-        ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1191, 
+        ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1202, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -33389,9 +33583,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1994 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM"
+    // Pos:2005 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM"
     {
-        ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1192, 
+        ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1203, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -33406,9 +33600,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1995 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM"
+    // Pos:2006 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM"
     {
-        ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1193, 
+        ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1204, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
@@ -33424,9 +33618,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1996 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM"
+    // Pos:2007 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM"
     {
-        ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1194, 
+        ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1205, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
@@ -33442,9 +33636,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1997 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM"
+    // Pos:2008 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM"
     {
-        ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1195, 
+        ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1206, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
@@ -33460,9 +33654,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1998 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM"
+    // Pos:2009 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM"
     {
-        ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1196, 
+        ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1207, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
@@ -33478,9 +33672,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:1999 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI"
+    // Pos:2010 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI"
     {
-        ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1197, 
+        ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1208, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33496,9 +33690,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2000 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI"
+    // Pos:2011 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI"
     {
-        ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1198, 
+        ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1209, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -33514,9 +33708,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2001 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM"
+    // Pos:2012 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM"
     {
-        ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1199, 
+        ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1210, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
@@ -33532,9 +33726,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2002 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM"
+    // Pos:2013 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM"
     {
-        ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1200, 
+        ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1211, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33550,9 +33744,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2003 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM"
+    // Pos:2014 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM"
     {
-        ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1200, 
+        ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1211, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -33567,9 +33761,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2004 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM"
+    // Pos:2015 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM"
     {
-        ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1201, 
+        ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1212, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
@@ -33585,9 +33779,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2005 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM"
+    // Pos:2016 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM"
     {
-        ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1202, 
+        ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1213, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33603,9 +33797,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2006 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM"
+    // Pos:2017 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM"
     {
-        ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1203, 
+        ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1214, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33621,9 +33815,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2007 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM"
+    // Pos:2018 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM"
     {
-        ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1204, 
+        ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1215, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33639,9 +33833,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2008 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM"
+    // Pos:2019 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM"
     {
-        ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1205, 
+        ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1216, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33657,9 +33851,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2009 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM"
+    // Pos:2020 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM"
     {
-        ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1206, 
+        ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1217, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -33675,9 +33869,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2010 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML"
+    // Pos:2021 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML"
     {
-        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1207, 
+        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1218, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33694,9 +33888,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2011 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM"
+    // Pos:2022 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM"
     {
-        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1207, 
+        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1218, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33713,9 +33907,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2012 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML"
+    // Pos:2023 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML"
     {
-        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1208, 
+        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1219, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33732,9 +33926,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2013 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM"
+    // Pos:2024 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM"
     {
-        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1208, 
+        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1219, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -33751,9 +33945,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2014 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM"
+    // Pos:2025 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1209, 
+        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1220, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33769,9 +33963,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2015 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI"
+    // Pos:2026 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1209, 
+        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1220, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33787,9 +33981,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2016 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM"
+    // Pos:2027 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1209, 
+        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1220, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33804,9 +33998,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2017 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI"
+    // Pos:2028 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1209, 
+        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1220, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33821,9 +34015,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2018 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM"
+    // Pos:2029 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1210, 
+        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1221, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33839,9 +34033,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2019 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI"
+    // Pos:2030 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1210, 
+        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1221, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33857,9 +34051,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2020 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM"
+    // Pos:2031 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1210, 
+        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1221, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33874,9 +34068,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2021 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI"
+    // Pos:2032 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1210, 
+        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1221, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33891,9 +34085,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2022 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM"
+    // Pos:2033 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1211, 
+        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1222, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33909,9 +34103,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2023 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM"
+    // Pos:2034 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1211, 
+        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1222, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33927,9 +34121,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2024 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI"
+    // Pos:2035 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1211, 
+        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1222, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33945,9 +34139,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2025 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI"
+    // Pos:2036 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1211, 
+        ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1222, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -33962,9 +34156,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2026 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM"
+    // Pos:2037 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1212, 
+        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1223, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33980,9 +34174,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2027 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM"
+    // Pos:2038 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1212, 
+        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1223, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33998,9 +34192,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2028 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM"
+    // Pos:2039 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM"
     {
-        ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1212, 
+        ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1223, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -34015,9 +34209,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2029 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM"
+    // Pos:2040 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM"
     {
-        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1213, 
+        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1224, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34033,9 +34227,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2030 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI"
+    // Pos:2041 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI"
     {
-        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1213, 
+        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1224, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34051,9 +34245,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2031 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI"
+    // Pos:2042 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI"
     {
-        ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1213, 
+        ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1224, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -34068,9 +34262,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2032 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM"
+    // Pos:2043 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM"
     {
-        ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1214, 
+        ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1225, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
@@ -34086,9 +34280,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2033 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM"
+    // Pos:2044 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM"
     {
-        ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1215, 
+        ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1226, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34104,9 +34298,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2034 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM"
+    // Pos:2045 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM"
     {
-        ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1216, 
+        ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1227, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34122,9 +34316,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2035 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM"
+    // Pos:2046 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM"
     {
-        ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1217, 
+        ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1228, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34140,9 +34334,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2036 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM"
+    // Pos:2047 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM"
     {
-        ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1218, 
+        ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1229, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34158,9 +34352,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2037 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM"
+    // Pos:2048 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM"
     {
-        ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1219, 
+        ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1230, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34176,9 +34370,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2038 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM"
+    // Pos:2049 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM"
     {
-        ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1220, 
+        ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1231, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34194,9 +34388,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2039 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM"
+    // Pos:2050 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM"
     {
-        ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1221, 
+        ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1232, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -34211,9 +34405,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2040 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM"
+    // Pos:2051 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM"
     {
-        ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1222, 
+        ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1233, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34228,9 +34422,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2041 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM"
+    // Pos:2052 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM"
     {
-        ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1223, 
+        ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1234, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34245,9 +34439,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2042 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM"
+    // Pos:2053 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM"
     {
-        ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1224, 
+        ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1235, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -34262,9 +34456,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2043 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
+    // Pos:2054 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1225, 
+        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34279,9 +34473,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2044 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
+    // Pos:2055 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1225, 
+        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34296,9 +34490,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2045 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
+    // Pos:2056 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1225, 
+        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34313,9 +34507,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2046 Instruction:"VPEXTRB Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
+    // Pos:2057 Instruction:"VPEXTRB Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1225, 
+        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34330,9 +34524,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2047 Instruction:"VPEXTRD Ed,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI"
+    // Pos:2058 Instruction:"VPEXTRD Ed,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI"
     {
-        ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1226, 
+        ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1237, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -34347,9 +34541,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2048 Instruction:"VPEXTRD Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI"
+    // Pos:2059 Instruction:"VPEXTRD Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI"
     {
-        ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1226, 
+        ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1237, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34364,9 +34558,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2049 Instruction:"VPEXTRQ Eq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI"
+    // Pos:2060 Instruction:"VPEXTRQ Eq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI"
     {
-        ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1227, 
+        ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1238, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -34381,9 +34575,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2050 Instruction:"VPEXTRQ Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI"
+    // Pos:2061 Instruction:"VPEXTRQ Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI"
     {
-        ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1227, 
+        ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1238, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34398,9 +34592,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2051 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
+    // Pos:2062 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1228, 
+        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1239, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34415,9 +34609,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2052 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
+    // Pos:2063 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1228, 
+        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1239, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34432,9 +34626,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2053 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
+    // Pos:2064 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1228, 
+        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1239, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34449,9 +34643,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2054 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
+    // Pos:2065 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1228, 
+        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1239, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34466,9 +34660,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2055 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
+    // Pos:2066 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1228, 
+        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1239, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34483,9 +34677,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2056 Instruction:"VPEXTRW Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
+    // Pos:2067 Instruction:"VPEXTRW Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1228, 
+        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1239, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34500,9 +34694,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2057 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM"
+    // Pos:2068 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1229, 
+        ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1240, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34517,9 +34711,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2058 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV"
+    // Pos:2069 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1229, 
+        ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1240, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -34534,9 +34728,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2059 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM"
+    // Pos:2070 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1230, 
+        ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1241, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34551,9 +34745,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2060 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV"
+    // Pos:2071 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1230, 
+        ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1241, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -34568,9 +34762,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2061 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM"
+    // Pos:2072 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1231, 
+        ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1242, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34585,9 +34779,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2062 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV"
+    // Pos:2073 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1231, 
+        ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1242, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -34602,9 +34796,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2063 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM"
+    // Pos:2074 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1232, 
+        ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1243, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34619,9 +34813,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2064 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV"
+    // Pos:2075 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1232, 
+        ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1243, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -34636,9 +34830,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2065 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM"
+    // Pos:2076 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM"
     {
-        ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1233, 
+        ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1244, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34652,9 +34846,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2066 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM"
+    // Pos:2077 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM"
     {
-        ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1234, 
+        ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1245, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34668,9 +34862,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2067 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM"
+    // Pos:2078 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM"
     {
-        ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1235, 
+        ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1246, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34684,9 +34878,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2068 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM"
+    // Pos:2079 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM"
     {
-        ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1236, 
+        ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1247, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34701,9 +34895,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2069 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM"
+    // Pos:2080 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM"
     {
-        ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1237, 
+        ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1248, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34717,9 +34911,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2070 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM"
+    // Pos:2081 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM"
     {
-        ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1238, 
+        ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1249, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34734,9 +34928,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2071 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM"
+    // Pos:2082 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM"
     {
-        ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1239, 
+        ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1250, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34750,9 +34944,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2072 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM"
+    // Pos:2083 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM"
     {
-        ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1240, 
+        ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1251, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34766,9 +34960,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2073 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM"
+    // Pos:2084 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM"
     {
-        ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1241, 
+        ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1252, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34782,9 +34976,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2074 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM"
+    // Pos:2085 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM"
     {
-        ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1242, 
+        ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1253, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34798,9 +34992,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2075 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM"
+    // Pos:2086 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM"
     {
-        ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1243, 
+        ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1254, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34814,9 +35008,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2076 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM"
+    // Pos:2087 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM"
     {
-        ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1244, 
+        ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1255, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34830,9 +35024,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2077 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM"
+    // Pos:2088 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM"
     {
-        ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1245, 
+        ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1256, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34847,9 +35041,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2078 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM"
+    // Pos:2089 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM"
     {
-        ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1246, 
+        ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1257, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34863,9 +35057,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2079 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM"
+    // Pos:2090 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM"
     {
-        ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1247, 
+        ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1258, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34879,9 +35073,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2080 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM"
+    // Pos:2091 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM"
     {
-        ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1248, 
+        ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1259, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34895,9 +35089,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2081 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM"
+    // Pos:2092 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM"
     {
-        ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1249, 
+        ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1260, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34911,9 +35105,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2082 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM"
+    // Pos:2093 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM"
     {
-        ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1250, 
+        ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1261, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34928,9 +35122,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2083 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM"
+    // Pos:2094 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM"
     {
-        ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1251, 
+        ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1262, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34944,9 +35138,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2084 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM"
+    // Pos:2095 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM"
     {
-        ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1252, 
+        ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1263, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34961,9 +35155,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2085 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM"
+    // Pos:2096 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM"
     {
-        ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1253, 
+        ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1264, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34978,9 +35172,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2086 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM"
+    // Pos:2097 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM"
     {
-        ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1254, 
+        ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1265, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -34994,9 +35188,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2087 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
+    // Pos:2098 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1255, 
+        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1266, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35012,9 +35206,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2088 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
+    // Pos:2099 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1255, 
+        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1266, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35030,9 +35224,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2089 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
+    // Pos:2100 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1255, 
+        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1266, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35048,9 +35242,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2090 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
+    // Pos:2101 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1255, 
+        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1266, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35066,9 +35260,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2091 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
+    // Pos:2102 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1256, 
+        ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1267, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -35084,9 +35278,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2092 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
+    // Pos:2103 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1256, 
+        ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1267, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35102,9 +35296,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2093 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
+    // Pos:2104 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1257, 
+        ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1268, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -35120,9 +35314,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2094 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
+    // Pos:2105 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1257, 
+        ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1268, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35138,9 +35332,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2095 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
+    // Pos:2106 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1258, 
+        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1269, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35156,9 +35350,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2096 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
+    // Pos:2107 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1258, 
+        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1269, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35174,9 +35368,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2097 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
+    // Pos:2108 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1258, 
+        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1269, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35192,9 +35386,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2098 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
+    // Pos:2109 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1258, 
+        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1269, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35210,9 +35404,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2099 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM"
+    // Pos:2110 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM"
     {
-        ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1259, 
+        ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1270, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -35227,9 +35421,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2100 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM"
+    // Pos:2111 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM"
     {
-        ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1260, 
+        ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1271, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -35244,9 +35438,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2101 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML"
+    // Pos:2112 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML"
     {
-        ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1261, 
+        ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1272, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35262,9 +35456,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2102 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML"
+    // Pos:2113 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML"
     {
-        ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1262, 
+        ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1273, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35280,9 +35474,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2103 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML"
+    // Pos:2114 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML"
     {
-        ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1263, 
+        ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1274, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35298,9 +35492,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2104 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML"
+    // Pos:2115 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML"
     {
-        ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1264, 
+        ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1275, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35316,9 +35510,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2105 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML"
+    // Pos:2116 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML"
     {
-        ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1265, 
+        ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1276, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35334,9 +35528,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2106 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML"
+    // Pos:2117 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML"
     {
-        ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1266, 
+        ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1277, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35352,9 +35546,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2107 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML"
+    // Pos:2118 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML"
     {
-        ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1267, 
+        ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1278, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35370,9 +35564,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2108 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML"
+    // Pos:2119 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML"
     {
-        ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1268, 
+        ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1279, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35388,9 +35582,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2109 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML"
+    // Pos:2120 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML"
     {
-        ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1269, 
+        ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1280, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35406,9 +35600,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2110 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML"
+    // Pos:2121 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML"
     {
-        ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1270, 
+        ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1281, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35424,9 +35618,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2111 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML"
+    // Pos:2122 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML"
     {
-        ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1271, 
+        ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1282, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35442,9 +35636,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2112 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML"
+    // Pos:2123 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML"
     {
-        ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1272, 
+        ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1283, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35460,9 +35654,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2113 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM"
+    // Pos:2124 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM"
     {
-        ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1273, 
+        ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1284, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, 
@@ -35478,9 +35672,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2114 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM"
+    // Pos:2125 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM"
     {
-        ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1274, 
+        ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1285, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, 
@@ -35496,9 +35690,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2115 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM"
+    // Pos:2126 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM"
     {
-        ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1275, 
+        ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1286, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35514,9 +35708,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2116 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM"
+    // Pos:2127 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM"
     {
-        ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1275, 
+        ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1286, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35531,9 +35725,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2117 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM"
+    // Pos:2128 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM"
     {
-        ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1276, 
+        ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1287, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35549,9 +35743,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2118 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM"
+    // Pos:2129 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM"
     {
-        ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1276, 
+        ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1287, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35566,9 +35760,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2119 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM"
+    // Pos:2130 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM"
     {
-        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1277, 
+        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1288, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35583,9 +35777,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2120 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR"
+    // Pos:2131 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR"
     {
-        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1277, 
+        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1288, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35600,9 +35794,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2121 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM"
+    // Pos:2132 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM"
     {
-        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1278, 
+        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1289, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35617,9 +35811,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2122 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR"
+    // Pos:2133 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR"
     {
-        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1278, 
+        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1289, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35634,9 +35828,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2123 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM"
+    // Pos:2134 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM"
     {
-        ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1279, 
+        ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1290, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35652,9 +35846,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2124 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM"
+    // Pos:2135 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM"
     {
-        ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1279, 
+        ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1290, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35669,9 +35863,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2125 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM"
+    // Pos:2136 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM"
     {
-        ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1280, 
+        ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1291, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35687,9 +35881,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2126 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM"
+    // Pos:2137 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM"
     {
-        ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1280, 
+        ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1291, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35704,9 +35898,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2127 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM"
+    // Pos:2138 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM"
     {
-        ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1281, 
+        ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1292, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35722,9 +35916,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2128 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM"
+    // Pos:2139 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM"
     {
-        ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1282, 
+        ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1293, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35740,9 +35934,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2129 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM"
+    // Pos:2140 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM"
     {
-        ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1282, 
+        ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1293, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35757,9 +35951,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2130 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM"
+    // Pos:2141 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM"
     {
-        ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1283, 
+        ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1294, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35775,9 +35969,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2131 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM"
+    // Pos:2142 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM"
     {
-        ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1283, 
+        ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1294, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35792,9 +35986,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2132 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM"
+    // Pos:2143 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM"
     {
-        ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1284, 
+        ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1295, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35810,9 +36004,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2133 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM"
+    // Pos:2144 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM"
     {
-        ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1284, 
+        ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1295, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35827,9 +36021,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2134 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM"
+    // Pos:2145 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM"
     {
-        ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1285, 
+        ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1296, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35845,9 +36039,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2135 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM"
+    // Pos:2146 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM"
     {
-        ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1286, 
+        ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1297, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35863,9 +36057,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2136 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM"
+    // Pos:2147 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM"
     {
-        ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1286, 
+        ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1297, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35880,9 +36074,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2137 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM"
+    // Pos:2148 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM"
     {
-        ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1287, 
+        ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1298, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35898,9 +36092,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2138 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM"
+    // Pos:2149 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM"
     {
-        ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1287, 
+        ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1298, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35915,9 +36109,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2139 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM"
+    // Pos:2150 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM"
     {
-        ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1288, 
+        ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1299, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35933,9 +36127,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2140 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM"
+    // Pos:2151 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM"
     {
-        ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1288, 
+        ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1299, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35950,9 +36144,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2141 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM"
+    // Pos:2152 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM"
     {
-        ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1289, 
+        ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1300, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35968,9 +36162,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2142 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM"
+    // Pos:2153 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM"
     {
-        ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1290, 
+        ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1301, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35986,9 +36180,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2143 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM"
+    // Pos:2154 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM"
     {
-        ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1290, 
+        ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1301, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36003,9 +36197,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2144 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM"
+    // Pos:2155 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM"
     {
-        ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1291, 
+        ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1302, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36021,9 +36215,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2145 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM"
+    // Pos:2156 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM"
     {
-        ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1291, 
+        ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1302, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36038,9 +36232,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2146 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM"
+    // Pos:2157 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM"
     {
-        ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1292, 
+        ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1303, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36056,9 +36250,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2147 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM"
+    // Pos:2158 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM"
     {
-        ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1292, 
+        ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1303, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36073,9 +36267,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2148 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM"
+    // Pos:2159 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM"
     {
-        ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1293, 
+        ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1304, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36091,9 +36285,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2149 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM"
+    // Pos:2160 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM"
     {
-        ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1294, 
+        ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1305, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36109,9 +36303,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2150 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM"
+    // Pos:2161 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM"
     {
-        ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1294, 
+        ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1305, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36126,9 +36320,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2151 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM"
+    // Pos:2162 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM"
     {
-        ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1295, 
+        ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1306, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36142,9 +36336,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2152 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM"
+    // Pos:2163 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM"
     {
-        ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1296, 
+        ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1307, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -36158,9 +36352,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2153 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR"
+    // Pos:2164 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR"
     {
-        ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1297, 
+        ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1308, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36175,9 +36369,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2154 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR"
+    // Pos:2165 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR"
     {
-        ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1298, 
+        ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1309, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36192,9 +36386,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2155 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM"
+    // Pos:2166 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1299, 
+        ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1310, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36208,9 +36402,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2156 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM"
+    // Pos:2167 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1300, 
+        ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1311, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -36224,9 +36418,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2157 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM"
+    // Pos:2168 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1301, 
+        ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1312, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -36240,9 +36434,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2158 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM"
+    // Pos:2169 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1302, 
+        ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1313, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36256,9 +36450,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2159 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM"
+    // Pos:2170 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM"
     {
-        ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1303, 
+        ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1314, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36272,9 +36466,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2160 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM"
+    // Pos:2171 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM"
     {
-        ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1304, 
+        ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1315, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -36288,9 +36482,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2161 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR"
+    // Pos:2172 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR"
     {
-        ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1305, 
+        ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1316, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36305,9 +36499,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2162 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR"
+    // Pos:2173 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR"
     {
-        ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1306, 
+        ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1317, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36322,9 +36516,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2163 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR"
+    // Pos:2174 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR"
     {
-        ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1307, 
+        ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1318, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36339,9 +36533,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2164 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR"
+    // Pos:2175 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR"
     {
-        ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1308, 
+        ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1319, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36356,9 +36550,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2165 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR"
+    // Pos:2176 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR"
     {
-        ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1309, 
+        ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1320, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36373,9 +36567,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2166 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR"
+    // Pos:2177 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR"
     {
-        ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1310, 
+        ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1321, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36390,9 +36584,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2167 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR"
+    // Pos:2178 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR"
     {
-        ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1311, 
+        ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1322, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36407,9 +36601,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2168 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR"
+    // Pos:2179 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR"
     {
-        ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1312, 
+        ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1323, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36424,9 +36618,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2169 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR"
+    // Pos:2180 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR"
     {
-        ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1313, 
+        ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1324, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36441,9 +36635,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2170 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM"
+    // Pos:2181 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM"
     {
-        ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1314, 
+        ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1325, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36458,9 +36652,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2171 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM"
+    // Pos:2182 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM"
     {
-        ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1314, 
+        ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1325, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36474,9 +36668,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2172 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM"
+    // Pos:2183 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM"
     {
-        ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1314, 
+        ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1325, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36490,9 +36684,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2173 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM"
+    // Pos:2184 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM"
     {
-        ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1315, 
+        ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1326, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36507,9 +36701,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2174 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM"
+    // Pos:2185 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM"
     {
-        ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1315, 
+        ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1326, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36523,9 +36717,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2175 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM"
+    // Pos:2186 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM"
     {
-        ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1315, 
+        ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1326, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36539,9 +36733,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2176 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM"
+    // Pos:2187 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM"
     {
-        ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1316, 
+        ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1327, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36556,9 +36750,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2177 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM"
+    // Pos:2188 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM"
     {
-        ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1316, 
+        ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1327, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36572,9 +36766,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2178 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM"
+    // Pos:2189 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM"
     {
-        ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1316, 
+        ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1327, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36588,9 +36782,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2179 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM"
+    // Pos:2190 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM"
     {
-        ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1317, 
+        ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1328, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36605,9 +36799,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2180 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM"
+    // Pos:2191 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM"
     {
-        ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1317, 
+        ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1328, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36621,9 +36815,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2181 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM"
+    // Pos:2192 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM"
     {
-        ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1317, 
+        ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1328, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36637,9 +36831,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2182 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM"
+    // Pos:2193 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM"
     {
-        ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1318, 
+        ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1329, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36654,9 +36848,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2183 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM"
+    // Pos:2194 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM"
     {
-        ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1318, 
+        ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1329, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36670,9 +36864,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2184 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM"
+    // Pos:2195 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM"
     {
-        ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1318, 
+        ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1329, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36686,9 +36880,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2185 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM"
+    // Pos:2196 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM"
     {
-        ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1319, 
+        ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1330, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36703,9 +36897,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2186 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM"
+    // Pos:2197 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM"
     {
-        ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1319, 
+        ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1330, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36719,9 +36913,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2187 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM"
+    // Pos:2198 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM"
     {
-        ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1319, 
+        ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1330, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36735,9 +36929,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2188 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR"
+    // Pos:2199 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR"
     {
-        ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1320, 
+        ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1331, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36752,9 +36946,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2189 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR"
+    // Pos:2200 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR"
     {
-        ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1321, 
+        ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1332, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36769,9 +36963,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2190 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR"
+    // Pos:2201 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR"
     {
-        ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1322, 
+        ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1333, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36786,9 +36980,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2191 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR"
+    // Pos:2202 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR"
     {
-        ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1323, 
+        ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1334, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36803,9 +36997,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2192 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR"
+    // Pos:2203 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR"
     {
-        ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1324, 
+        ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1335, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36820,9 +37014,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2193 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR"
+    // Pos:2204 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR"
     {
-        ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1325, 
+        ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1336, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36837,9 +37031,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2194 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM"
+    // Pos:2205 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM"
     {
-        ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1326, 
+        ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1337, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36853,9 +37047,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2195 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR"
+    // Pos:2206 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR"
     {
-        ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1327, 
+        ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1338, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36870,9 +37064,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2196 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM"
+    // Pos:2207 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM"
     {
-        ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1328, 
+        ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1339, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36887,9 +37081,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2197 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM"
+    // Pos:2208 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM"
     {
-        ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1328, 
+        ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1339, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36903,9 +37097,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2198 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM"
+    // Pos:2209 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM"
     {
-        ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1328, 
+        ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1339, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36919,9 +37113,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2199 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM"
+    // Pos:2210 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM"
     {
-        ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1329, 
+        ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1340, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36936,9 +37130,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2200 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM"
+    // Pos:2211 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM"
     {
-        ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1329, 
+        ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1340, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36952,9 +37146,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2201 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM"
+    // Pos:2212 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM"
     {
-        ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1329, 
+        ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1340, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36968,9 +37162,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2202 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM"
+    // Pos:2213 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM"
     {
-        ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1330, 
+        ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36985,9 +37179,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2203 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM"
+    // Pos:2214 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM"
     {
-        ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1330, 
+        ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37001,9 +37195,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2204 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM"
+    // Pos:2215 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM"
     {
-        ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1330, 
+        ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37017,9 +37211,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2205 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM"
+    // Pos:2216 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM"
     {
-        ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1331, 
+        ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1342, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37034,9 +37228,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2206 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM"
+    // Pos:2217 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM"
     {
-        ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1331, 
+        ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1342, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37050,9 +37244,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2207 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM"
+    // Pos:2218 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM"
     {
-        ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1331, 
+        ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1342, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37066,9 +37260,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2208 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM"
+    // Pos:2219 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM"
     {
-        ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1332, 
+        ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1343, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37083,9 +37277,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2209 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM"
+    // Pos:2220 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM"
     {
-        ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1332, 
+        ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1343, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37099,9 +37293,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2210 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM"
+    // Pos:2221 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM"
     {
-        ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1332, 
+        ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1343, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37115,9 +37309,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2211 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM"
+    // Pos:2222 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM"
     {
-        ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1333, 
+        ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1344, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37132,9 +37326,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2212 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM"
+    // Pos:2223 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM"
     {
-        ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1333, 
+        ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1344, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37148,9 +37342,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2213 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM"
+    // Pos:2224 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM"
     {
-        ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1333, 
+        ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1344, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37164,9 +37358,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2214 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM"
+    // Pos:2225 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM"
     {
-        ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1334, 
+        ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1345, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37182,9 +37376,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2215 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM"
+    // Pos:2226 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM"
     {
-        ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1334, 
+        ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1345, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37199,9 +37393,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2216 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM"
+    // Pos:2227 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM"
     {
-        ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1335, 
+        ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1346, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37217,9 +37411,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2217 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM"
+    // Pos:2228 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM"
     {
-        ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1335, 
+        ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1346, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37234,9 +37428,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2218 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM"
+    // Pos:2229 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM"
     {
-        ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1336, 
+        ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1347, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37252,9 +37446,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2219 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM"
+    // Pos:2230 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM"
     {
-        ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1336, 
+        ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1347, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37269,9 +37463,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2220 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM"
+    // Pos:2231 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM"
     {
-        ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1337, 
+        ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1348, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37287,9 +37481,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2221 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM"
+    // Pos:2232 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM"
     {
-        ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1337, 
+        ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1348, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37304,9 +37498,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2222 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM"
+    // Pos:2233 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM"
     {
-        ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1338, 
+        ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1349, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37322,9 +37516,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2223 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM"
+    // Pos:2234 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM"
     {
-        ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1338, 
+        ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1349, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37339,9 +37533,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2224 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM"
+    // Pos:2235 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM"
     {
-        ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1339, 
+        ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1350, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -37357,9 +37551,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2225 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM"
+    // Pos:2236 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM"
     {
-        ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1340, 
+        ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1351, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37375,9 +37569,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2226 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM"
+    // Pos:2237 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM"
     {
-        ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1340, 
+        ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1351, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37392,9 +37586,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2227 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM"
+    // Pos:2238 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM"
     {
-        ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1341, 
+        ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1352, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
@@ -37410,9 +37604,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2228 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM"
+    // Pos:2239 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM"
     {
-        ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1342, 
+        ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1353, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37428,9 +37622,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2229 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM"
+    // Pos:2240 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM"
     {
-        ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1342, 
+        ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1353, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37445,9 +37639,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2230 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM"
+    // Pos:2241 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM"
     {
-        ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1343, 
+        ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1354, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 
@@ -37462,9 +37656,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2231 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM"
+    // Pos:2242 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM"
     {
-        ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1344, 
+        ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1355, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, 
@@ -37479,9 +37673,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2232 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM"
+    // Pos:2243 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM"
     {
-        ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1345, 
+        ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1356, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, 
@@ -37496,9 +37690,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2233 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM"
+    // Pos:2244 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM"
     {
-        ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1346, 
+        ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1357, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 
@@ -37513,9 +37707,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2234 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM"
+    // Pos:2245 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM"
     {
-        ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1347, 
+        ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1358, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37530,9 +37724,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2235 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM"
+    // Pos:2246 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM"
     {
-        ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1348, 
+        ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1359, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37548,9 +37742,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2236 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM"
+    // Pos:2247 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM"
     {
-        ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1349, 
+        ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1360, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37566,9 +37760,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2237 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML"
+    // Pos:2248 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML"
     {
-        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1350, 
+        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1361, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37584,9 +37778,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2238 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM"
+    // Pos:2249 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM"
     {
-        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1350, 
+        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1361, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37602,9 +37796,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2239 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI"
+    // Pos:2250 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI"
     {
-        ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1351, 
+        ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1362, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37620,9 +37814,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2240 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI"
+    // Pos:2251 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI"
     {
-        ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1352, 
+        ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1363, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37638,9 +37832,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2241 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM"
+    // Pos:2252 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM"
     {
-        ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1353, 
+        ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1364, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37656,9 +37850,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2242 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM"
+    // Pos:2253 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM"
     {
-        ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1354, 
+        ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1365, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37674,9 +37868,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2243 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI"
+    // Pos:2254 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI"
     {
-        ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1355, 
+        ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1366, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37692,9 +37886,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2244 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI"
+    // Pos:2255 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI"
     {
-        ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1356, 
+        ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1367, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37710,9 +37904,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2245 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM"
+    // Pos:2256 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM"
     {
-        ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1357, 
+        ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1368, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37728,9 +37922,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2246 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM"
+    // Pos:2257 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM"
     {
-        ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1358, 
+        ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1369, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37746,9 +37940,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2247 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI"
+    // Pos:2258 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI"
     {
-        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1359, 
+        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1370, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37763,9 +37957,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2248 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV"
+    // Pos:2259 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV"
     {
-        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1359, 
+        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1370, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37780,9 +37974,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2249 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM"
+    // Pos:2260 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM"
     {
-        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1359, 
+        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1370, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37797,9 +37991,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2250 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI"
+    // Pos:2261 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI"
     {
-        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1360, 
+        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1371, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37814,9 +38008,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2251 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV"
+    // Pos:2262 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV"
     {
-        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1360, 
+        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1371, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37831,9 +38025,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2252 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM"
+    // Pos:2263 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM"
     {
-        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1360, 
+        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1371, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37848,9 +38042,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2253 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI"
+    // Pos:2264 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI"
     {
-        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1361, 
+        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1372, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37865,9 +38059,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2254 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV"
+    // Pos:2265 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV"
     {
-        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1361, 
+        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1372, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37882,9 +38076,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2255 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM"
+    // Pos:2266 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM"
     {
-        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1361, 
+        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1372, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37899,9 +38093,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2256 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI"
+    // Pos:2267 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI"
     {
-        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1362, 
+        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1373, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37916,9 +38110,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2257 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV"
+    // Pos:2268 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV"
     {
-        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1362, 
+        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1373, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37933,9 +38127,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2258 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM"
+    // Pos:2269 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM"
     {
-        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1362, 
+        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1373, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37950,9 +38144,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2259 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
+    // Pos:2270 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
     {
-        ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1363, 
+        ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1374, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37967,9 +38161,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2260 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
+    // Pos:2271 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
     {
-        ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1363, 
+        ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1374, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37984,9 +38178,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2261 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR"
+    // Pos:2272 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1364, 
+        ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1375, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38001,9 +38195,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2262 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR"
+    // Pos:2273 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1365, 
+        ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1376, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38018,9 +38212,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2263 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR"
+    // Pos:2274 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1366, 
+        ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1377, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38035,9 +38229,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2264 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR"
+    // Pos:2275 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1367, 
+        ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1378, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38052,9 +38246,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2265 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV"
+    // Pos:2276 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV"
     {
-        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1368, 
+        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1379, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38069,9 +38263,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2266 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM"
+    // Pos:2277 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM"
     {
-        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1368, 
+        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1379, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38086,9 +38280,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2267 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV"
+    // Pos:2278 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV"
     {
-        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1369, 
+        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1380, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38103,9 +38297,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2268 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM"
+    // Pos:2279 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM"
     {
-        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1369, 
+        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1380, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38120,9 +38314,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2269 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV"
+    // Pos:2280 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV"
     {
-        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1370, 
+        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1381, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38137,9 +38331,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2270 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM"
+    // Pos:2281 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM"
     {
-        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1370, 
+        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1381, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38154,9 +38348,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2271 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV"
+    // Pos:2282 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV"
     {
-        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1371, 
+        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1382, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38171,9 +38365,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2272 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM"
+    // Pos:2283 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM"
     {
-        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1371, 
+        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1382, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38188,9 +38382,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2273 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV"
+    // Pos:2284 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1372, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1383, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38205,9 +38399,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2274 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM"
+    // Pos:2285 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1372, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1383, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38222,9 +38416,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2275 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM"
+    // Pos:2286 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1372, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1383, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38239,9 +38433,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2276 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM"
+    // Pos:2287 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1372, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1383, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38256,9 +38450,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2277 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV"
+    // Pos:2288 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV"
     {
-        ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1373, 
+        ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1384, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38273,9 +38467,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2278 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI"
+    // Pos:2289 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1374, 
+        ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1385, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38292,9 +38486,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2279 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI"
+    // Pos:2290 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1375, 
+        ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1386, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38311,9 +38505,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2280 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM"
+    // Pos:2291 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM"
     {
-        ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1376, 
+        ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1387, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38329,9 +38523,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2281 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM"
+    // Pos:2292 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM"
     {
-        ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1377, 
+        ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1388, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38347,9 +38541,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2282 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM"
+    // Pos:2293 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM"
     {
-        ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1378, 
+        ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1389, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38365,9 +38559,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2283 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI"
+    // Pos:2294 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1379, 
+        ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1390, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38384,9 +38578,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2284 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV"
+    // Pos:2295 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV"
     {
-        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1380, 
+        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1391, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38401,9 +38595,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2285 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM"
+    // Pos:2296 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM"
     {
-        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1380, 
+        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1391, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38418,9 +38612,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2286 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV"
+    // Pos:2297 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV"
     {
-        ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1381, 
+        ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1392, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38435,9 +38629,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2287 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI"
+    // Pos:2298 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1382, 
+        ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1393, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38454,9 +38648,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2288 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI"
+    // Pos:2299 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1383, 
+        ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1394, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38473,9 +38667,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2289 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM"
+    // Pos:2300 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM"
     {
-        ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1384, 
+        ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1395, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38491,9 +38685,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2290 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM"
+    // Pos:2301 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM"
     {
-        ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1385, 
+        ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1396, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38509,9 +38703,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2291 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM"
+    // Pos:2302 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM"
     {
-        ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1386, 
+        ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1397, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38527,9 +38721,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2292 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI"
+    // Pos:2303 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1387, 
+        ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1398, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -38546,9 +38740,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2293 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM"
+    // Pos:2304 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM"
     {
-        ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1388, 
+        ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1399, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38564,9 +38758,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2294 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM"
+    // Pos:2305 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM"
     {
-        ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1388, 
+        ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1399, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38581,9 +38775,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2295 Instruction:"VPSHUFBITQMB rK{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM"
+    // Pos:2306 Instruction:"VPSHUFBITQMB rK{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM"
     {
-        ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1389, 
+        ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1400, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 
@@ -38599,9 +38793,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2296 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI"
+    // Pos:2307 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI"
     {
-        ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1390, 
+        ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1401, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38617,9 +38811,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2297 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI"
+    // Pos:2308 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI"
     {
-        ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1390, 
+        ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1401, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38634,9 +38828,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2298 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI"
+    // Pos:2309 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI"
     {
-        ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1391, 
+        ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1402, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38652,9 +38846,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2299 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI"
+    // Pos:2310 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI"
     {
-        ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1391, 
+        ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1402, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38669,9 +38863,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2300 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI"
+    // Pos:2311 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI"
     {
-        ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1392, 
+        ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1403, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38687,9 +38881,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2301 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI"
+    // Pos:2312 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI"
     {
-        ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1392, 
+        ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1403, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38704,9 +38898,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2302 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM"
+    // Pos:2313 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM"
     {
-        ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1393, 
+        ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1404, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38721,9 +38915,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2303 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM"
+    // Pos:2314 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM"
     {
-        ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1394, 
+        ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1405, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38738,9 +38932,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2304 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM"
+    // Pos:2315 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM"
     {
-        ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1395, 
+        ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1406, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38755,9 +38949,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2305 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI"
+    // Pos:2316 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1396, 
+        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1407, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38773,9 +38967,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2306 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM"
+    // Pos:2317 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1396, 
+        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1407, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38791,9 +38985,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2307 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI"
+    // Pos:2318 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1396, 
+        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1407, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38808,9 +39002,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2308 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM"
+    // Pos:2319 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1396, 
+        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1407, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38825,9 +39019,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2309 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI"
+    // Pos:2320 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI"
     {
-        ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1397, 
+        ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1408, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38842,9 +39036,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2310 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI"
+    // Pos:2321 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI"
     {
-        ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1397, 
+        ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1408, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38859,9 +39053,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2311 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI"
+    // Pos:2322 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1398, 
+        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1409, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38877,9 +39071,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2312 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM"
+    // Pos:2323 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1398, 
+        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1409, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38895,9 +39089,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2313 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI"
+    // Pos:2324 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1398, 
+        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1409, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38912,9 +39106,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2314 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM"
+    // Pos:2325 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1398, 
+        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1409, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38929,9 +39123,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2315 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM"
+    // Pos:2326 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM"
     {
-        ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1399, 
+        ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1410, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38947,9 +39141,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2316 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM"
+    // Pos:2327 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM"
     {
-        ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1399, 
+        ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1410, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -38964,9 +39158,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2317 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM"
+    // Pos:2328 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM"
     {
-        ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1400, 
+        ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1411, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38982,9 +39176,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2318 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM"
+    // Pos:2329 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM"
     {
-        ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1400, 
+        ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1411, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -38999,9 +39193,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2319 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM"
+    // Pos:2330 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM"
     {
-        ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1401, 
+        ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1412, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39017,9 +39211,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2320 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI"
+    // Pos:2331 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1402, 
+        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1413, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39035,9 +39229,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2321 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM"
+    // Pos:2332 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1402, 
+        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1413, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39053,9 +39247,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2322 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI"
+    // Pos:2333 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1402, 
+        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1413, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39070,9 +39264,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2323 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM"
+    // Pos:2334 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1402, 
+        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1413, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39087,9 +39281,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2324 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI"
+    // Pos:2335 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1403, 
+        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1414, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39105,9 +39299,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2325 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM"
+    // Pos:2336 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1403, 
+        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1414, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39123,9 +39317,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2326 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI"
+    // Pos:2337 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1403, 
+        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1414, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39140,9 +39334,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2327 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM"
+    // Pos:2338 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1403, 
+        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1414, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39157,9 +39351,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2328 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI"
+    // Pos:2339 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI"
     {
-        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1404, 
+        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1415, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39175,9 +39369,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2329 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM"
+    // Pos:2340 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM"
     {
-        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1404, 
+        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1415, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39193,9 +39387,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2330 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM"
+    // Pos:2341 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM"
     {
-        ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1405, 
+        ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1416, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39211,9 +39405,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2331 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM"
+    // Pos:2342 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM"
     {
-        ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1405, 
+        ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1416, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39228,9 +39422,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2332 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM"
+    // Pos:2343 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM"
     {
-        ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1406, 
+        ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1417, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39246,9 +39440,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2333 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM"
+    // Pos:2344 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM"
     {
-        ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1407, 
+        ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1418, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39264,9 +39458,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2334 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI"
+    // Pos:2345 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1408, 
+        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1419, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39282,9 +39476,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2335 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM"
+    // Pos:2346 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1408, 
+        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1419, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39300,9 +39494,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2336 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI"
+    // Pos:2347 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1408, 
+        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1419, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39317,9 +39511,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2337 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM"
+    // Pos:2348 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1408, 
+        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1419, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39334,9 +39528,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2338 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI"
+    // Pos:2349 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1409, 
+        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1420, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39352,9 +39546,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2339 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM"
+    // Pos:2350 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1409, 
+        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1420, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39370,9 +39564,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2340 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI"
+    // Pos:2351 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1409, 
+        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1420, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39387,9 +39581,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2341 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM"
+    // Pos:2352 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1409, 
+        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1420, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39404,9 +39598,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2342 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI"
+    // Pos:2353 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI"
     {
-        ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1410, 
+        ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1421, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39421,9 +39615,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2343 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI"
+    // Pos:2354 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI"
     {
-        ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1410, 
+        ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1421, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39438,9 +39632,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2344 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI"
+    // Pos:2355 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1411, 
+        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1422, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39456,9 +39650,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2345 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM"
+    // Pos:2356 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1411, 
+        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1422, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39474,9 +39668,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2346 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI"
+    // Pos:2357 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1411, 
+        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1422, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39491,9 +39685,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2347 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM"
+    // Pos:2358 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1411, 
+        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1422, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39508,9 +39702,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2348 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM"
+    // Pos:2359 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM"
     {
-        ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1412, 
+        ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1423, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39526,9 +39720,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2349 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM"
+    // Pos:2360 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM"
     {
-        ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1412, 
+        ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1423, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39543,9 +39737,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2350 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM"
+    // Pos:2361 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM"
     {
-        ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1413, 
+        ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1424, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39561,9 +39755,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2351 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM"
+    // Pos:2362 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM"
     {
-        ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1413, 
+        ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1424, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39578,9 +39772,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2352 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM"
+    // Pos:2363 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM"
     {
-        ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1414, 
+        ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1425, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39596,9 +39790,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2353 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI"
+    // Pos:2364 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1415, 
+        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1426, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39614,9 +39808,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2354 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM"
+    // Pos:2365 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1415, 
+        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1426, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39632,9 +39826,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2355 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI"
+    // Pos:2366 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1415, 
+        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1426, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39649,9 +39843,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2356 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM"
+    // Pos:2367 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1415, 
+        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1426, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39666,9 +39860,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2357 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM"
+    // Pos:2368 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM"
     {
-        ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1416, 
+        ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1427, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39684,9 +39878,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2358 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM"
+    // Pos:2369 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM"
     {
-        ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1416, 
+        ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1427, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39701,9 +39895,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2359 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM"
+    // Pos:2370 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM"
     {
-        ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1417, 
+        ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1428, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39719,9 +39913,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2360 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM"
+    // Pos:2371 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM"
     {
-        ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1417, 
+        ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1428, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39736,9 +39930,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2361 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM"
+    // Pos:2372 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM"
     {
-        ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1418, 
+        ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1429, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39754,9 +39948,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2362 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM"
+    // Pos:2373 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM"
     {
-        ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1418, 
+        ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1429, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39771,9 +39965,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2363 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM"
+    // Pos:2374 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM"
     {
-        ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1419, 
+        ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1430, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39789,9 +39983,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2364 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM"
+    // Pos:2375 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM"
     {
-        ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1419, 
+        ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1430, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39806,9 +40000,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2365 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM"
+    // Pos:2376 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM"
     {
-        ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1420, 
+        ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1431, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39824,9 +40018,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2366 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM"
+    // Pos:2377 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM"
     {
-        ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1420, 
+        ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1431, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39841,9 +40035,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2367 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM"
+    // Pos:2378 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM"
     {
-        ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1421, 
+        ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1432, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39859,9 +40053,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2368 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM"
+    // Pos:2379 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM"
     {
-        ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1421, 
+        ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1432, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39876,9 +40070,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2369 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM"
+    // Pos:2380 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM"
     {
-        ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1422, 
+        ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1433, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39894,9 +40088,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2370 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM"
+    // Pos:2381 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM"
     {
-        ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1422, 
+        ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1433, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39911,9 +40105,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2371 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM"
+    // Pos:2382 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM"
     {
-        ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1423, 
+        ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1434, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39929,9 +40123,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2372 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM"
+    // Pos:2383 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM"
     {
-        ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1423, 
+        ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1434, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39946,9 +40140,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2373 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI"
+    // Pos:2384 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI"
     {
-        ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1424, 
+        ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1435, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39965,9 +40159,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2374 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI"
+    // Pos:2385 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI"
     {
-        ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1425, 
+        ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1436, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39984,9 +40178,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2375 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM"
+    // Pos:2386 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM"
     {
-        ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1426, 
+        ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1437, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40001,9 +40195,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2376 Instruction:"VPTESTMB rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM"
+    // Pos:2387 Instruction:"VPTESTMB rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1427, 
+        ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1438, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40019,9 +40213,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2377 Instruction:"VPTESTMD rKq{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM"
+    // Pos:2388 Instruction:"VPTESTMD rKq{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1428, 
+        ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1439, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40037,9 +40231,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2378 Instruction:"VPTESTMQ rKq{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM"
+    // Pos:2389 Instruction:"VPTESTMQ rKq{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1429, 
+        ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1440, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40055,9 +40249,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2379 Instruction:"VPTESTMW rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM"
+    // Pos:2390 Instruction:"VPTESTMW rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1430, 
+        ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1441, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40073,9 +40267,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2380 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM"
+    // Pos:2391 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1431, 
+        ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1442, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40091,9 +40285,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2381 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM"
+    // Pos:2392 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1432, 
+        ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1443, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40109,9 +40303,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2382 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM"
+    // Pos:2393 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1433, 
+        ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1444, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40127,9 +40321,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2383 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM"
+    // Pos:2394 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1434, 
+        ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1445, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40145,9 +40339,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2384 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM"
+    // Pos:2395 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1435, 
+        ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1446, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40163,9 +40357,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2385 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM"
+    // Pos:2396 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM"
     {
-        ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1435, 
+        ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1446, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40180,9 +40374,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2386 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM"
+    // Pos:2397 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1436, 
+        ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1447, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40198,9 +40392,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2387 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM"
+    // Pos:2398 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM"
     {
-        ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1436, 
+        ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1447, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40215,9 +40409,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2388 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM"
+    // Pos:2399 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1437, 
+        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1448, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40233,9 +40427,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2389 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM"
+    // Pos:2400 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM"
     {
-        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1437, 
+        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1448, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40250,9 +40444,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2390 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM"
+    // Pos:2401 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1438, 
+        ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1449, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40268,9 +40462,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2391 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM"
+    // Pos:2402 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM"
     {
-        ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1438, 
+        ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1449, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40285,9 +40479,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2392 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM"
+    // Pos:2403 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1439, 
+        ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1450, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40303,9 +40497,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2393 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM"
+    // Pos:2404 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM"
     {
-        ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1439, 
+        ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1450, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40320,9 +40514,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2394 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM"
+    // Pos:2405 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1440, 
+        ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1451, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40338,9 +40532,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2395 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM"
+    // Pos:2406 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM"
     {
-        ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1440, 
+        ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1451, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40355,9 +40549,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2396 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM"
+    // Pos:2407 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1441, 
+        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1452, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40373,9 +40567,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2397 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM"
+    // Pos:2408 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM"
     {
-        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1441, 
+        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1452, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40390,9 +40584,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2398 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM"
+    // Pos:2409 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1442, 
+        ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1453, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40408,9 +40602,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2399 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM"
+    // Pos:2410 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM"
     {
-        ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1442, 
+        ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1453, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40425,9 +40619,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2400 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM"
+    // Pos:2411 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM"
     {
-        ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1443, 
+        ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1454, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40442,9 +40636,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2401 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM"
+    // Pos:2412 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM"
     {
-        ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1444, 
+        ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1455, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40460,9 +40654,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2402 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM"
+    // Pos:2413 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM"
     {
-        ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1445, 
+        ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1456, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40478,9 +40672,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2403 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI"
+    // Pos:2414 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1446, 
+        ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1457, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40497,9 +40691,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2404 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI"
+    // Pos:2415 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1447, 
+        ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1458, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40516,9 +40710,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2405 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI"
+    // Pos:2416 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1448, 
+        ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1459, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40535,9 +40729,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2406 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI"
+    // Pos:2417 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1449, 
+        ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1460, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40554,9 +40748,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2407 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM"
+    // Pos:2418 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM"
     {
-        ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1450, 
+        ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1461, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40571,9 +40765,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2408 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM"
+    // Pos:2419 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM"
     {
-        ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1451, 
+        ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1462, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40588,9 +40782,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2409 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM"
+    // Pos:2420 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM"
     {
-        ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1452, 
+        ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1463, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40606,9 +40800,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2410 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM"
+    // Pos:2421 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM"
     {
-        ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1453, 
+        ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1464, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40624,9 +40818,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2411 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM"
+    // Pos:2422 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM"
     {
-        ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1454, 
+        ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1465, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -40641,9 +40835,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2412 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM"
+    // Pos:2423 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM"
     {
-        ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1455, 
+        ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1466, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -40658,9 +40852,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2413 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM"
+    // Pos:2424 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM"
     {
-        ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1456, 
+        ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1467, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -40676,9 +40870,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2414 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM"
+    // Pos:2425 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM"
     {
-        ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1457, 
+        ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1468, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -40694,9 +40888,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2415 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM"
+    // Pos:2426 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM"
     {
-        ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1458, 
+        ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1469, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40710,9 +40904,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2416 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM"
+    // Pos:2427 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM"
     {
-        ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1459, 
+        ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1470, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40727,9 +40921,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2417 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI"
+    // Pos:2428 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI"
     {
-        ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1460, 
+        ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1471, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40745,9 +40939,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2418 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI"
+    // Pos:2429 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI"
     {
-        ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1461, 
+        ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1472, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40763,9 +40957,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2419 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI"
+    // Pos:2430 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI"
     {
-        ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1462, 
+        ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1473, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40782,9 +40976,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2420 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI"
+    // Pos:2431 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI"
     {
-        ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1463, 
+        ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1474, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40801,9 +40995,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2421 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI"
+    // Pos:2432 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI"
     {
-        ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1464, 
+        ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1475, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40819,9 +41013,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2422 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI"
+    // Pos:2433 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI"
     {
-        ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1465, 
+        ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1476, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40837,9 +41031,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2423 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI"
+    // Pos:2434 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI"
     {
-        ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1466, 
+        ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1477, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40856,9 +41050,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2424 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI"
+    // Pos:2435 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI"
     {
-        ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1467, 
+        ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1478, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40875,9 +41069,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2425 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI"
+    // Pos:2436 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI"
     {
-        ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1468, 
+        ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1479, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40892,9 +41086,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2426 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI"
+    // Pos:2437 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI"
     {
-        ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1469, 
+        ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1480, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40909,9 +41103,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2427 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI"
+    // Pos:2438 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI"
     {
-        ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1470, 
+        ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1481, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40927,9 +41121,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2428 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI"
+    // Pos:2439 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI"
     {
-        ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1471, 
+        ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1482, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40945,9 +41139,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2429 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM"
+    // Pos:2440 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM"
     {
-        ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1472, 
+        ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1483, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40962,9 +41156,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2430 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM"
+    // Pos:2441 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM"
     {
-        ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1473, 
+        ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1484, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40979,9 +41173,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2431 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM"
+    // Pos:2442 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM"
     {
-        ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1474, 
+        ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1485, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40997,9 +41191,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2432 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM"
+    // Pos:2443 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM"
     {
-        ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1475, 
+        ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1486, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41015,9 +41209,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2433 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM"
+    // Pos:2444 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM"
     {
-        ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1476, 
+        ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1487, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -41032,9 +41226,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2434 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM"
+    // Pos:2445 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM"
     {
-        ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1477, 
+        ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1488, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -41049,9 +41243,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2435 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM"
+    // Pos:2446 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM"
     {
-        ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1478, 
+        ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1489, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -41067,9 +41261,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2436 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM"
+    // Pos:2447 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM"
     {
-        ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1479, 
+        ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1490, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -41085,9 +41279,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2437 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM"
+    // Pos:2448 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM"
     {
-        ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1480, 
+        ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1491, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41101,9 +41295,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2438 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM"
+    // Pos:2449 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM"
     {
-        ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1481, 
+        ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1492, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41118,9 +41312,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2439 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM"
+    // Pos:2450 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM"
     {
-        ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1482, 
+        ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1493, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41136,9 +41330,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2440 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM"
+    // Pos:2451 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM"
     {
-        ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1483, 
+        ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1494, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41154,9 +41348,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2441 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM"
+    // Pos:2452 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM"
     {
-        ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1484, 
+        ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1495, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41172,9 +41366,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2442 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM"
+    // Pos:2453 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM"
     {
-        ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1485, 
+        ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1496, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41190,9 +41384,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2443 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR"
+    // Pos:2454 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1486, 
+        ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1497, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41207,9 +41401,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2444 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR"
+    // Pos:2455 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1487, 
+        ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1498, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41224,9 +41418,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2445 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA"
+    // Pos:2456 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1488, 
+        ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1499, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41240,9 +41434,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2446 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA"
+    // Pos:2457 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1489, 
+        ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1500, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41256,9 +41450,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2447 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA"
+    // Pos:2458 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1490, 
+        ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1501, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41272,9 +41466,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2448 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA"
+    // Pos:2459 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1491, 
+        ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1502, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41288,9 +41482,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2449 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA"
+    // Pos:2460 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1492, 
+        ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1503, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41304,9 +41498,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2450 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA"
+    // Pos:2461 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1493, 
+        ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1504, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41320,9 +41514,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2451 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA"
+    // Pos:2462 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1494, 
+        ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1505, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41336,9 +41530,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2452 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA"
+    // Pos:2463 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1495, 
+        ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1506, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -41352,9 +41546,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2453 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR"
+    // Pos:2464 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1496, 
+        ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1507, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41369,9 +41563,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2454 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR"
+    // Pos:2465 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1497, 
+        ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1508, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41386,9 +41580,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2455 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI"
+    // Pos:2466 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1498, 
+        ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1509, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41405,9 +41599,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2456 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI"
+    // Pos:2467 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1499, 
+        ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1510, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41424,9 +41618,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2457 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI"
+    // Pos:2468 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1500, 
+        ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1511, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41443,9 +41637,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2458 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI"
+    // Pos:2469 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1501, 
+        ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1512, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41462,9 +41656,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2459 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI"
+    // Pos:2470 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1502, 
+        ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1513, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41481,9 +41675,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2460 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI"
+    // Pos:2471 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI"
     {
-        ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1502, 
+        ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1513, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41499,9 +41693,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2461 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI"
+    // Pos:2472 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1503, 
+        ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1514, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41518,9 +41712,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2462 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI"
+    // Pos:2473 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI"
     {
-        ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1503, 
+        ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1514, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41536,9 +41730,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2463 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM"
+    // Pos:2474 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM"
     {
-        ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1504, 
+        ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1515, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41553,9 +41747,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2464 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM"
+    // Pos:2475 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM"
     {
-        ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1504, 
+        ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1515, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41569,9 +41763,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2465 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM"
+    // Pos:2476 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM"
     {
-        ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1505, 
+        ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1516, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41586,9 +41780,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2466 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM"
+    // Pos:2477 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM"
     {
-        ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1505, 
+        ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1516, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41602,9 +41796,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2467 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM"
+    // Pos:2478 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM"
     {
-        ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1506, 
+        ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1517, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41620,9 +41814,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2468 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM"
+    // Pos:2479 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM"
     {
-        ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1506, 
+        ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1517, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41637,9 +41831,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2469 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM"
+    // Pos:2480 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM"
     {
-        ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1507, 
+        ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1518, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41655,9 +41849,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2470 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM"
+    // Pos:2481 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM"
     {
-        ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1507, 
+        ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1518, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41672,9 +41866,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2471 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M"
+    // Pos:2482 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M"
     {
-        ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1508, 
+        ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1519, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, 
@@ -41688,9 +41882,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2472 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM"
+    // Pos:2483 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1509, 
+        ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1520, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41706,9 +41900,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2473 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM"
+    // Pos:2484 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1509, 
+        ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1520, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41723,9 +41917,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2474 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM"
+    // Pos:2485 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1510, 
+        ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1521, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41741,9 +41935,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2475 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM"
+    // Pos:2486 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1510, 
+        ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1521, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41758,9 +41952,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2476 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM"
+    // Pos:2487 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1511, 
+        ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1522, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41776,9 +41970,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2477 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM"
+    // Pos:2488 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1511, 
+        ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1522, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41793,9 +41987,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2478 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM"
+    // Pos:2489 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1512, 
+        ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1523, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41811,9 +42005,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2479 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM"
+    // Pos:2490 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1512, 
+        ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1523, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41828,9 +42022,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2480 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM"
+    // Pos:2491 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM"
     {
-        ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1513, 
+        ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1524, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41845,9 +42039,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2481 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM"
+    // Pos:2492 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM"
     {
-        ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1514, 
+        ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1525, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41862,9 +42056,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2482 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM"
+    // Pos:2493 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1515, 
+        ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1526, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41879,9 +42073,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2483 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM"
+    // Pos:2494 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1515, 
+        ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1526, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41896,9 +42090,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2484 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM"
+    // Pos:2495 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1516, 
+        ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1527, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41913,9 +42107,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2485 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM"
+    // Pos:2496 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1516, 
+        ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1527, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41930,9 +42124,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2486 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM"
+    // Pos:2497 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM"
     {
-        ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1517, 
+        ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1528, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41948,9 +42142,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2487 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM"
+    // Pos:2498 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM"
     {
-        ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1517, 
+        ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1528, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41965,9 +42159,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2488 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM"
+    // Pos:2499 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM"
     {
-        ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1518, 
+        ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1529, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41983,9 +42177,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2489 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM"
+    // Pos:2500 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM"
     {
-        ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1518, 
+        ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1529, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42000,9 +42194,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2490 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM"
+    // Pos:2501 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM"
     {
-        ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1519, 
+        ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1530, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42018,9 +42212,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2491 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM"
+    // Pos:2502 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM"
     {
-        ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1519, 
+        ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1530, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42035,9 +42229,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2492 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM"
+    // Pos:2503 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM"
     {
-        ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1520, 
+        ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1531, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42053,9 +42247,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2493 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM"
+    // Pos:2504 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM"
     {
-        ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1520, 
+        ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1531, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42070,9 +42264,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2494 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM"
+    // Pos:2505 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM"
     {
-        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1521, 
+        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1532, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -42088,9 +42282,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2495 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM"
+    // Pos:2506 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM"
     {
-        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1521, 
+        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1532, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42105,9 +42299,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2496 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM"
+    // Pos:2507 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM"
     {
-        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1522, 
+        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1533, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -42123,9 +42317,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2497 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM"
+    // Pos:2508 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM"
     {
-        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1522, 
+        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1533, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42140,9 +42334,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2498 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/""
+    // Pos:2509 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/""
     {
-        ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1523, 
+        ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1534, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, 
@@ -42155,9 +42349,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2499 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/""
+    // Pos:2510 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/""
     {
-        ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1524, 
+        ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1535, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, 
@@ -42170,9 +42364,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2500 Instruction:"WAIT" Encoding:"0x9B"/""
+    // Pos:2511 Instruction:"WAIT" Encoding:"0x9B"/""
     {
-        ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1525, 
+        ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1536, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, 0, 0, 
@@ -42185,9 +42379,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2501 Instruction:"WBINVD" Encoding:"0x0F 0x09"/""
+    // Pos:2512 Instruction:"WBINVD" Encoding:"0x0F 0x09"/""
     {
-        ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1526, 
+        ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1537, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -42200,9 +42394,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2502 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/""
+    // Pos:2513 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/""
     {
-        ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1527, 
+        ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1538, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_WBNOINVD, 
@@ -42215,9 +42409,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2503 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M"
+    // Pos:2514 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M"
     {
-        ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1528, 
+        ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1539, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
@@ -42231,9 +42425,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2504 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M"
+    // Pos:2515 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M"
     {
-        ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1529, 
+        ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1540, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
@@ -42247,9 +42441,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2505 Instruction:"WRMSR" Encoding:"0x0F 0x30"/""
+    // Pos:2516 Instruction:"WRMSR" Encoding:"0x0F 0x30"/""
     {
-        ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1530, 
+        ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1541, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, ND_CFF_MSR, 
@@ -42265,9 +42459,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2506 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/""
+    // Pos:2517 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/""
     {
-        ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1531, 
+        ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1542, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, 
@@ -42283,9 +42477,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2507 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M"
+    // Pos:2518 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M"
     {
-        ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1532, 
+        ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1543, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42298,9 +42492,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2508 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR"
+    // Pos:2519 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR"
     {
-        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1533, 
+        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1544, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -42314,9 +42508,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2509 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR"
+    // Pos:2520 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR"
     {
-        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1534, 
+        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1545, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -42330,9 +42524,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2510 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
+    // Pos:2521 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
     {
-        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1535, 
+        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1546, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -42346,9 +42540,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2511 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
+    // Pos:2522 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
     {
-        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1536, 
+        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1547, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -42362,9 +42556,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2512 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I"
+    // Pos:2523 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I"
     {
-        ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1537, 
+        ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1548, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
@@ -42378,9 +42572,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2513 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR"
+    // Pos:2524 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR"
     {
-        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1538, 
+        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1549, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42395,9 +42589,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2514 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR"
+    // Pos:2525 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR"
     {
-        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1538, 
+        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1549, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42412,9 +42606,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2515 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D"
+    // Pos:2526 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D"
     {
-        ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1539, 
+        ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1550, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
@@ -42429,9 +42623,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2516 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR"
+    // Pos:2527 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1540, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, 
         ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42445,9 +42639,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2517 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR"
+    // Pos:2528 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1540, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, 
         ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42461,9 +42655,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2518 Instruction:"XCHG rAX,Zv" Encoding:"rex 0x90"/"O"
+    // Pos:2529 Instruction:"XCHG rAX,Zv" Encoding:"rex 0x90"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1540, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42477,9 +42671,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2519 Instruction:"XCHG rAX,Zv" Encoding:"0x91"/"O"
+    // Pos:2530 Instruction:"XCHG rAX,Zv" Encoding:"0x91"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1540, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42493,9 +42687,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2520 Instruction:"XCHG rAX,Zv" Encoding:"0x92"/"O"
+    // Pos:2531 Instruction:"XCHG rAX,Zv" Encoding:"0x92"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1540, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42509,9 +42703,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2521 Instruction:"XCHG rAX,Zv" Encoding:"0x93"/"O"
+    // Pos:2532 Instruction:"XCHG rAX,Zv" Encoding:"0x93"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1540, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42525,9 +42719,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2522 Instruction:"XCHG rAX,Zv" Encoding:"0x94"/"O"
+    // Pos:2533 Instruction:"XCHG rAX,Zv" Encoding:"0x94"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1540, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42541,9 +42735,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2523 Instruction:"XCHG rAX,Zv" Encoding:"0x95"/"O"
+    // Pos:2534 Instruction:"XCHG rAX,Zv" Encoding:"0x95"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1540, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42557,9 +42751,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2524 Instruction:"XCHG rAX,Zv" Encoding:"0x96"/"O"
+    // Pos:2535 Instruction:"XCHG rAX,Zv" Encoding:"0x96"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1540, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42573,9 +42767,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2525 Instruction:"XCHG rAX,Zv" Encoding:"0x97"/"O"
+    // Pos:2536 Instruction:"XCHG rAX,Zv" Encoding:"0x97"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1540, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42589,9 +42783,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2526 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/""
+    // Pos:2537 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/""
     {
-        ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1541, 
+        ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1552, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42604,9 +42798,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2527 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/""
+    // Pos:2538 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/""
     {
-        ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1542, 
+        ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1553, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42619,9 +42813,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2528 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/""
+    // Pos:2539 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/""
     {
-        ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1543, 
+        ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1554, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42634,9 +42828,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2529 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/""
+    // Pos:2540 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/""
     {
-        ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1544, 
+        ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1555, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42649,9 +42843,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2530 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/""
+    // Pos:2541 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/""
     {
-        ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1545, 
+        ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1556, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42664,9 +42858,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2531 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/""
+    // Pos:2542 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/""
     {
-        ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1546, 
+        ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1557, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
@@ -42679,9 +42873,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2532 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/""
+    // Pos:2543 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/""
     {
-        ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1547, 
+        ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -42697,9 +42891,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2533 Instruction:"XLATB" Encoding:"0xD7"/""
+    // Pos:2544 Instruction:"XLATB" Encoding:"0xD7"/""
     {
-        ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1548, 
+        ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1559, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42713,9 +42907,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2534 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR"
+    // Pos:2545 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1549, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42730,9 +42924,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2535 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR"
+    // Pos:2546 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1549, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42747,9 +42941,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2536 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM"
+    // Pos:2547 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1549, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42764,9 +42958,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2537 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM"
+    // Pos:2548 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1549, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42781,9 +42975,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2538 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I"
+    // Pos:2549 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1549, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42798,9 +42992,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2539 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I"
+    // Pos:2550 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1549, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -42815,9 +43009,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2540 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI"
+    // Pos:2551 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1549, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42832,9 +43026,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2541 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI"
+    // Pos:2552 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1549, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42849,9 +43043,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2542 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI"
+    // Pos:2553 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1549, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -42866,9 +43060,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2543 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI"
+    // Pos:2554 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1549, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1560, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -42883,9 +43077,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2544 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM"
+    // Pos:2555 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM"
     {
-        ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1550, 
+        ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1561, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -42899,9 +43093,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2545 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM"
+    // Pos:2556 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM"
     {
-        ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1551, 
+        ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1562, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -42915,9 +43109,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2546 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/""
+    // Pos:2557 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/""
     {
-        ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1552, 
+        ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1563, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, 
@@ -42930,9 +43124,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2547 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M"
+    // Pos:2558 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M"
     {
-        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1553, 
+        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1564, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -42949,9 +43143,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2548 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M"
+    // Pos:2559 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M"
     {
-        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1554, 
+        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1565, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -42968,9 +43162,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2549 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M"
+    // Pos:2560 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M"
     {
-        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1555, 
+        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1566, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
@@ -42987,9 +43181,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2550 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M"
+    // Pos:2561 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M"
     {
-        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1556, 
+        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1567, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
@@ -43006,9 +43200,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2551 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M"
+    // Pos:2562 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M"
     {
-        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1557, 
+        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1568, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43025,9 +43219,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2552 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M"
+    // Pos:2563 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M"
     {
-        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1558, 
+        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1569, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43044,9 +43238,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2553 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M"
+    // Pos:2564 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M"
     {
-        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1559, 
+        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1570, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, 
@@ -43063,9 +43257,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2554 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M"
+    // Pos:2565 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M"
     {
-        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1560, 
+        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1571, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, 
@@ -43082,9 +43276,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2555 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M"
+    // Pos:2566 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M"
     {
-        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1561, 
+        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1572, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43101,9 +43295,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2556 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M"
+    // Pos:2567 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M"
     {
-        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1562, 
+        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1573, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43120,9 +43314,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2557 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M"
+    // Pos:2568 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M"
     {
-        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1563, 
+        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1574, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
@@ -43139,9 +43333,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2558 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M"
+    // Pos:2569 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M"
     {
-        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1564, 
+        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1575, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
@@ -43158,9 +43352,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2559 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/""
+    // Pos:2570 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/""
     {
-        ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1565, 
+        ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1576, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -43176,9 +43370,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2560 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/""
+    // Pos:2571 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/""
     {
-        ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1566, 
+        ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1577, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43191,9 +43385,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2561 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/""
+    // Pos:2572 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/""
     {
-        ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1567, 
+        ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1578, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43206,9 +43400,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2562 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/""
+    // Pos:2573 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/""
     {
-        ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1568, 
+        ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1579, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -43221,9 +43415,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2563 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/""
+    // Pos:2574 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/""
     {
-        ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1569, 
+        ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1580, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, 
@@ -43236,9 +43430,9 @@ const ND_INSTRUCTION gInstructions[2565] =
         },
     }, 
 
-    // Pos:2564 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/""
+    // Pos:2575 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/""
     {
-        ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1570, 
+        ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1581, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
diff --git a/bddisasm/include/mnemonics.h b/bddisasm/include/mnemonics.h
index 85e0266..f2c6911 100644
--- a/bddisasm/include/mnemonics.h
+++ b/bddisasm/include/mnemonics.h
@@ -1,149 +1,151 @@
 #ifndef MNEMONICS_H
 #define MNEMONICS_H
 
-const char *gMnemonics[1571] = 
+const char *gMnemonics[1582] = 
 {
     "AAA", "AAD", "AAM", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS", 
-    "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", "AESDEC", "AESDECLAST", 
-    "AESENC", "AESENCLAST", "AESIMC", "AESKEYGENASSIST", "ALTINST", 
-    "AND", "ANDN", "ANDNPD", "ANDNPS", "ANDPD", "ANDPS", "ARPL", 
-    "BEXTR", "BLCFILL", "BLCI", "BLCIC", "BLCMSK", "BLCS", "BLENDPD", 
-    "BLENDPS", "BLENDVPD", "BLENDVPS", "BLSFILL", "BLSI", "BLSIC", 
-    "BLSMSK", "BLSR", "BNDCL", "BNDCN", "BNDCU", "BNDLDX", "BNDMK", 
-    "BNDMOV", "BNDSTX", "BOUND", "BSF", "BSR", "BSWAP", "BT", "BTC", 
-    "BTR", "BTS", "BZHI", "CALL", "CALLF", "CBW", "CDQ", "CDQE", 
-    "CL1INVMB", "CLAC", "CLC", "CLD", "CLDEMOTE", "CLEVICT0", "CLEVICT1", 
-    "CLFLUSH", "CLFLUSHOPT", "CLGI", "CLI", "CLRSSBSY", "CLTS", "CLWB", 
-    "CLZERO", "CMC", "CMOVBE", "CMOVC", "CMOVL", "CMOVLE", "CMOVNBE", 
-    "CMOVNC", "CMOVNL", "CMOVNLE", "CMOVNO", "CMOVNP", "CMOVNS", 
-    "CMOVNZ", "CMOVO", "CMOVP", "CMOVS", "CMOVZ", "CMP", "CMPPD", 
-    "CMPPS", "CMPSB", "CMPSD", "CMPSQ", "CMPSS", "CMPSW", "CMPXCHG", 
-    "CMPXCHG16B", "CMPXCHG8B", "COMISD", "COMISS", "CPUID", "CPU_READ", 
-    "CPU_WRITE", "CQO", "CRC32", "CVTDQ2PD", "CVTDQ2PS", "CVTPD2DQ", 
-    "CVTPD2PI", "CVTPD2PS", "CVTPI2PD", "CVTPI2PS", "CVTPS2DQ", "CVTPS2PD", 
-    "CVTPS2PI", "CVTSD2SI", "CVTSD2SS", "CVTSI2SD", "CVTSI2SS", "CVTSS2SD", 
-    "CVTSS2SI", "CVTTPD2DQ", "CVTTPD2PI", "CVTTPS2DQ", "CVTTPS2PI", 
-    "CVTTSD2SI", "CVTTSS2SI", "CWD", "CWDE", "DAA", "DAS", "DEC", 
-    "DELAY", "DIV", "DIVPD", "DIVPS", "DIVSD", "DIVSS", "DMINT", 
-    "DPPD", "DPPS", "EMMS", "ENCLS", "ENCLU", "ENCLV", "ENDBR32", 
-    "ENDBR64", "ENQCMD", "ENQCMDS", "ENTER", "EXTRACTPS", "EXTRQ", 
-    "F2XM1", "FABS", "FADD", "FADDP", "FBLD", "FBSTP", "FCHS", "FCMOVB", 
-    "FCMOVBE", "FCMOVE", "FCMOVNB", "FCMOVNBE", "FCMOVNE", "FCMOVNU", 
-    "FCMOVU", "FCOM", "FCOMI", "FCOMIP", "FCOMP", "FCOMPP", "FCOS", 
-    "FDECSTP", "FDIV", "FDIVP", "FDIVR", "FDIVRP", "FEMMS", "FFREE", 
-    "FFREEP", "FIADD", "FICOM", "FICOMP", "FIDIV", "FIDIVR", "FILD", 
-    "FIMUL", "FINCSTP", "FIST", "FISTP", "FISTTP", "FISUB", "FISUBR", 
-    "FLD", "FLD1", "FLDCW", "FLDENV", "FLDL2E", "FLDL2T", "FLDLG2", 
-    "FLDLN2", "FLDPI", "FLDZ", "FMUL", "FMULP", "FNCLEX", "FNDISI", 
-    "FNINIT", "FNOP", "FNSAVE", "FNSTCW", "FNSTENV", "FNSTSW", "FPATAN", 
-    "FPREM", "FPREM1", "FPTAN", "FRINEAR", "FRNDINT", "FRSTOR", "FSCALE", 
-    "FSIN", "FSINCOS", "FSQRT", "FST", "FSTDW", "FSTP", "FSTPNCE", 
-    "FSTSG", "FSUB", "FSUBP", "FSUBR", "FSUBRP", "FTST", "FUCOM", 
-    "FUCOMI", "FUCOMIP", "FUCOMP", "FUCOMPP", "FXAM", "FXCH", "FXRSTOR", 
-    "FXRSTOR64", "FXSAVE", "FXSAVE64", "FXTRACT", "FYL2X", "FYL2XP1", 
-    "GETSEC", "GF2P8AFFINEINVQB", "GF2P8AFFINEQB", "GF2P8MULB", "HADDPD", 
-    "HADDPS", "HLT", "HSUBPD", "HSUBPS", "IDIV", "IMUL", "IN", "INC", 
-    "INCSSPD", "INCSSPQ", "INSB", "INSD", "INSERTPS", "INSERTQ", 
-    "INSW", "INT", "INT1", "INT3", "INTO", "INVD", "INVEPT", "INVLPG", 
-    "INVLPGA", "INVLPGB", "INVPCID", "INVVPID", "IRETD", "IRETQ", 
-    "IRETW", "JBE", "JC", "JCXZ", "JECXZ", "JL", "JLE", "JMP", "JMPE", 
-    "JMPF", "JNBE", "JNC", "JNL", "JNLE", "JNO", "JNP", "JNS", "JNZ", 
-    "JO", "JP", "JRCXZ", "JS", "JZ", "KADDB", "KADDD", "KADDQ", "KADDW", 
-    "KANDB", "KANDD", "KANDNB", "KANDND", "KANDNQ", "KANDNW", "KANDQ", 
-    "KANDW", "KMERGE2L1H", "KMERGE2L1L", "KMOVB", "KMOVD", "KMOVQ", 
-    "KMOVW", "KNOTB", "KNOTD", "KNOTQ", "KNOTW", "KORB", "KORD", 
-    "KORQ", "KORTESTB", "KORTESTD", "KORTESTQ", "KORTESTW", "KORW", 
-    "KSHIFTLB", "KSHIFTLD", "KSHIFTLQ", "KSHIFTLW", "KSHIFTRB", "KSHIFTRD", 
-    "KSHIFTRQ", "KSHIFTRW", "KTESTB", "KTESTD", "KTESTQ", "KTESTW", 
-    "KUNPCKBW", "KUNPCKDQ", "KUNPCKWD", "KXNORB", "KXNORD", "KXNORQ", 
-    "KXNORW", "KXORB", "KXORD", "KXORQ", "KXORW", "LAHF", "LAR", 
-    "LDDQU", "LDMXCSR", "LDS", "LDTILECFG", "LEA", "LEAVE", "LES", 
-    "LFENCE", "LFS", "LGDT", "LGS", "LIDT", "LLDT", "LLWPCB", "LMSW", 
-    "LODSB", "LODSD", "LODSQ", "LODSW", "LOOP", "LOOPNZ", "LOOPZ", 
-    "LSL", "LSS", "LTR", "LWPINS", "LWPVAL", "LZCNT", "MASKMOVDQU", 
-    "MASKMOVQ", "MAXPD", "MAXPS", "MAXSD", "MAXSS", "MCOMMIT", "MFENCE", 
-    "MINPD", "MINPS", "MINSD", "MINSS", "MONITOR", "MONITORX", "MONTMUL", 
-    "MOV", "MOVAPD", "MOVAPS", "MOVBE", "MOVD", "MOVDDUP", "MOVDIR64B", 
-    "MOVDIRI", "MOVDQ2Q", "MOVDQA", "MOVDQU", "MOVHLPS", "MOVHPD", 
-    "MOVHPS", "MOVLHPS", "MOVLPD", "MOVLPS", "MOVMSKPD", "MOVMSKPS", 
-    "MOVNTDQ", "MOVNTDQA", "MOVNTI", "MOVNTPD", "MOVNTPS", "MOVNTQ", 
-    "MOVNTSD", "MOVNTSS", "MOVQ", "MOVQ2DQ", "MOVSB", "MOVSD", "MOVSHDUP", 
-    "MOVSLDUP", "MOVSQ", "MOVSS", "MOVSW", "MOVSX", "MOVSXD", "MOVUPD", 
-    "MOVUPS", "MOVZX", "MPSADBW", "MUL", "MULPD", "MULPS", "MULSD", 
-    "MULSS", "MULX", "MWAIT", "MWAITX", "NEG", "NOP", "NOT", "OR", 
-    "ORPD", "ORPS", "OUT", "OUTSB", "OUTSD", "OUTSW", "PABSB", "PABSD", 
-    "PABSW", "PACKSSDW", "PACKSSWB", "PACKUSDW", "PACKUSWB", "PADDB", 
-    "PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB", "PADDUSW", "PADDW", 
-    "PALIGNR", "PAND", "PANDN", "PAUSE", "PAVGB", "PAVGUSB", "PAVGW", 
-    "PBLENDVB", "PBLENDW", "PCLMULQDQ", "PCMPEQB", "PCMPEQD", "PCMPEQQ", 
-    "PCMPEQW", "PCMPESTRI", "PCMPESTRM", "PCMPGTB", "PCMPGTD", "PCMPGTQ", 
-    "PCMPGTW", "PCMPISTRI", "PCMPISTRM", "PCOMMIT", "PCONFIG", "PDEP", 
-    "PEXT", "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", "PF2ID", "PF2IW", 
-    "PFACC", "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", "PFMAX", "PFMIN", 
-    "PFMUL", "PFNACC", "PFPNACC", "PFRCP", "PFRCPIT1", "PFRCPIT2", 
-    "PFRCPV", "PFRSQIT1", "PFRSQRT", "PFRSQRTV", "PFSUB", "PFSUBR", 
-    "PHADDD", "PHADDSW", "PHADDW", "PHMINPOSUW", "PHSUBD", "PHSUBSW", 
-    "PHSUBW", "PI2FD", "PI2FW", "PINSRB", "PINSRD", "PINSRQ", "PINSRW", 
-    "PMADDUBSW", "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", "PMAXUB", 
-    "PMAXUD", "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", "PMINUD", 
-    "PMINUW", "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", "PMOVSXDQ", 
-    "PMOVSXWD", "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", "PMOVZXDQ", 
-    "PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", "PMULHUW", 
-    "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", "POPAD", 
-    "POPCNT", "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", "PREFETCHE", 
-    "PREFETCHM", "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", 
-    "PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", 
-    "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", 
-    "PSLLQ", "PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", 
-    "PSRLQ", "PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", 
-    "PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE", 
-    "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", 
-    "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSHA", "PUSHAD", 
-    "PUSHFD", "PUSHFQ", "PUSHFW", "PVALIDATE", "PXOR", "RCL", "RCPPS", 
-    "RCPSS", "RCR", "RDFSBASE", "RDGSBASE", "RDMSR", "RDPID", "RDPKRU", 
-    "RDPMC", "RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", 
-    "RDTSC", "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPUPDATE", 
-    "ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", 
-    "RSDC", "RSLDT", "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", 
-    "SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", 
-    "SCASD", "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", 
-    "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", "SETNC", 
-    "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", "SETO", 
-    "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", "SHA1MSG1", 
-    "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", 
-    "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", "SHRX", 
-    "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", "SMINT", 
-    "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", "STAC", 
-    "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", "STOSQ", 
-    "STOSW", "STR", "STTILECFG", "SUB", "SUBPD", "SUBPS", "SUBSD", 
-    "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", "SYSCALL", "SYSENTER", 
-    "SYSEXIT", "SYSRET", "T1MSKC", "TDCALL", "TDPBF16PS", "TDPBSSD", 
-    "TDPBSUD", "TDPBUSD", "TDPBUUD", "TEST", "TILELOADD", "TILELOADDT1", 
-    "TILERELEASE", "TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", 
-    "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", 
-    "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", 
-    "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", 
-    "VADDPS", "VADDSD", "VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", 
-    "VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", 
-    "VALIGND", "VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", 
-    "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", 
-    "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", 
-    "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", 
-    "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", 
-    "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", "VCMPPD", 
-    "VCMPPS", "VCMPSD", "VCMPSS", "VCOMISD", "VCOMISS", "VCOMPRESSPD", 
-    "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEPS2BF16", 
-    "VCVTPD2DQ", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", 
-    "VCVTPH2PS", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2QQ", 
-    "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PS", "VCVTSD2SI", 
-    "VCVTSD2SS", "VCVTSD2USI", "VCVTSI2SD", "VCVTSI2SS", "VCVTSS2SD", 
-    "VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", 
-    "VCVTTPD2UQQ", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", 
-    "VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSS2SI", "VCVTTSS2USI", "VCVTUDQ2PD", 
-    "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SS", 
-    "VDBPSADBW", "VDIVPD", "VDIVPS", "VDIVSD", "VDIVSS", "VDPBF16PS", 
-    "VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD", 
-    "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", 
+    "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", "AESDEC", "AESDEC128KL", 
+    "AESDEC256KL", "AESDECLAST", "AESDECWIDE128KL", "AESDECWIDE256KL", 
+    "AESENC", "AESENC128KL", "AESENC256KL", "AESENCLAST", "AESENCWIDE128KL", 
+    "AESENCWIDE256KL", "AESIMC", "AESKEYGENASSIST", "ALTINST", "AND", 
+    "ANDN", "ANDNPD", "ANDNPS", "ANDPD", "ANDPS", "ARPL", "BEXTR", 
+    "BLCFILL", "BLCI", "BLCIC", "BLCMSK", "BLCS", "BLENDPD", "BLENDPS", 
+    "BLENDVPD", "BLENDVPS", "BLSFILL", "BLSI", "BLSIC", "BLSMSK", 
+    "BLSR", "BNDCL", "BNDCN", "BNDCU", "BNDLDX", "BNDMK", "BNDMOV", 
+    "BNDSTX", "BOUND", "BSF", "BSR", "BSWAP", "BT", "BTC", "BTR", 
+    "BTS", "BZHI", "CALL", "CALLF", "CBW", "CDQ", "CDQE", "CL1INVMB", 
+    "CLAC", "CLC", "CLD", "CLDEMOTE", "CLEVICT0", "CLEVICT1", "CLFLUSH", 
+    "CLFLUSHOPT", "CLGI", "CLI", "CLRSSBSY", "CLTS", "CLWB", "CLZERO", 
+    "CMC", "CMOVBE", "CMOVC", "CMOVL", "CMOVLE", "CMOVNBE", "CMOVNC", 
+    "CMOVNL", "CMOVNLE", "CMOVNO", "CMOVNP", "CMOVNS", "CMOVNZ", 
+    "CMOVO", "CMOVP", "CMOVS", "CMOVZ", "CMP", "CMPPD", "CMPPS", 
+    "CMPSB", "CMPSD", "CMPSQ", "CMPSS", "CMPSW", "CMPXCHG", "CMPXCHG16B", 
+    "CMPXCHG8B", "COMISD", "COMISS", "CPUID", "CPU_READ", "CPU_WRITE", 
+    "CQO", "CRC32", "CVTDQ2PD", "CVTDQ2PS", "CVTPD2DQ", "CVTPD2PI", 
+    "CVTPD2PS", "CVTPI2PD", "CVTPI2PS", "CVTPS2DQ", "CVTPS2PD", "CVTPS2PI", 
+    "CVTSD2SI", "CVTSD2SS", "CVTSI2SD", "CVTSI2SS", "CVTSS2SD", "CVTSS2SI", 
+    "CVTTPD2DQ", "CVTTPD2PI", "CVTTPS2DQ", "CVTTPS2PI", "CVTTSD2SI", 
+    "CVTTSS2SI", "CWD", "CWDE", "DAA", "DAS", "DEC", "DELAY", "DIV", 
+    "DIVPD", "DIVPS", "DIVSD", "DIVSS", "DMINT", "DPPD", "DPPS", 
+    "EMMS", "ENCLS", "ENCLU", "ENCLV", "ENCODEKEY128", "ENCODEKEY256", 
+    "ENDBR32", "ENDBR64", "ENQCMD", "ENQCMDS", "ENTER", "EXTRACTPS", 
+    "EXTRQ", "F2XM1", "FABS", "FADD", "FADDP", "FBLD", "FBSTP", "FCHS", 
+    "FCMOVB", "FCMOVBE", "FCMOVE", "FCMOVNB", "FCMOVNBE", "FCMOVNE", 
+    "FCMOVNU", "FCMOVU", "FCOM", "FCOMI", "FCOMIP", "FCOMP", "FCOMPP", 
+    "FCOS", "FDECSTP", "FDIV", "FDIVP", "FDIVR", "FDIVRP", "FEMMS", 
+    "FFREE", "FFREEP", "FIADD", "FICOM", "FICOMP", "FIDIV", "FIDIVR", 
+    "FILD", "FIMUL", "FINCSTP", "FIST", "FISTP", "FISTTP", "FISUB", 
+    "FISUBR", "FLD", "FLD1", "FLDCW", "FLDENV", "FLDL2E", "FLDL2T", 
+    "FLDLG2", "FLDLN2", "FLDPI", "FLDZ", "FMUL", "FMULP", "FNCLEX", 
+    "FNDISI", "FNINIT", "FNOP", "FNSAVE", "FNSTCW", "FNSTENV", "FNSTSW", 
+    "FPATAN", "FPREM", "FPREM1", "FPTAN", "FRINEAR", "FRNDINT", "FRSTOR", 
+    "FSCALE", "FSIN", "FSINCOS", "FSQRT", "FST", "FSTDW", "FSTP", 
+    "FSTPNCE", "FSTSG", "FSUB", "FSUBP", "FSUBR", "FSUBRP", "FTST", 
+    "FUCOM", "FUCOMI", "FUCOMIP", "FUCOMP", "FUCOMPP", "FXAM", "FXCH", 
+    "FXRSTOR", "FXRSTOR64", "FXSAVE", "FXSAVE64", "FXTRACT", "FYL2X", 
+    "FYL2XP1", "GETSEC", "GF2P8AFFINEINVQB", "GF2P8AFFINEQB", "GF2P8MULB", 
+    "HADDPD", "HADDPS", "HLT", "HSUBPD", "HSUBPS", "IDIV", "IMUL", 
+    "IN", "INC", "INCSSPD", "INCSSPQ", "INSB", "INSD", "INSERTPS", 
+    "INSERTQ", "INSW", "INT", "INT1", "INT3", "INTO", "INVD", "INVEPT", 
+    "INVLPG", "INVLPGA", "INVLPGB", "INVPCID", "INVVPID", "IRETD", 
+    "IRETQ", "IRETW", "JBE", "JC", "JCXZ", "JECXZ", "JL", "JLE", 
+    "JMP", "JMPE", "JMPF", "JNBE", "JNC", "JNL", "JNLE", "JNO", "JNP", 
+    "JNS", "JNZ", "JO", "JP", "JRCXZ", "JS", "JZ", "KADDB", "KADDD", 
+    "KADDQ", "KADDW", "KANDB", "KANDD", "KANDNB", "KANDND", "KANDNQ", 
+    "KANDNW", "KANDQ", "KANDW", "KMERGE2L1H", "KMERGE2L1L", "KMOVB", 
+    "KMOVD", "KMOVQ", "KMOVW", "KNOTB", "KNOTD", "KNOTQ", "KNOTW", 
+    "KORB", "KORD", "KORQ", "KORTESTB", "KORTESTD", "KORTESTQ", "KORTESTW", 
+    "KORW", "KSHIFTLB", "KSHIFTLD", "KSHIFTLQ", "KSHIFTLW", "KSHIFTRB", 
+    "KSHIFTRD", "KSHIFTRQ", "KSHIFTRW", "KTESTB", "KTESTD", "KTESTQ", 
+    "KTESTW", "KUNPCKBW", "KUNPCKDQ", "KUNPCKWD", "KXNORB", "KXNORD", 
+    "KXNORQ", "KXNORW", "KXORB", "KXORD", "KXORQ", "KXORW", "LAHF", 
+    "LAR", "LDDQU", "LDMXCSR", "LDS", "LDTILECFG", "LEA", "LEAVE", 
+    "LES", "LFENCE", "LFS", "LGDT", "LGS", "LIDT", "LLDT", "LLWPCB", 
+    "LMSW", "LOADIWKEY", "LODSB", "LODSD", "LODSQ", "LODSW", "LOOP", 
+    "LOOPNZ", "LOOPZ", "LSL", "LSS", "LTR", "LWPINS", "LWPVAL", "LZCNT", 
+    "MASKMOVDQU", "MASKMOVQ", "MAXPD", "MAXPS", "MAXSD", "MAXSS", 
+    "MCOMMIT", "MFENCE", "MINPD", "MINPS", "MINSD", "MINSS", "MONITOR", 
+    "MONITORX", "MONTMUL", "MOV", "MOVAPD", "MOVAPS", "MOVBE", "MOVD", 
+    "MOVDDUP", "MOVDIR64B", "MOVDIRI", "MOVDQ2Q", "MOVDQA", "MOVDQU", 
+    "MOVHLPS", "MOVHPD", "MOVHPS", "MOVLHPS", "MOVLPD", "MOVLPS", 
+    "MOVMSKPD", "MOVMSKPS", "MOVNTDQ", "MOVNTDQA", "MOVNTI", "MOVNTPD", 
+    "MOVNTPS", "MOVNTQ", "MOVNTSD", "MOVNTSS", "MOVQ", "MOVQ2DQ", 
+    "MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP", "MOVSQ", "MOVSS", "MOVSW", 
+    "MOVSX", "MOVSXD", "MOVUPD", "MOVUPS", "MOVZX", "MPSADBW", "MUL", 
+    "MULPD", "MULPS", "MULSD", "MULSS", "MULX", "MWAIT", "MWAITX", 
+    "NEG", "NOP", "NOT", "OR", "ORPD", "ORPS", "OUT", "OUTSB", "OUTSD", 
+    "OUTSW", "PABSB", "PABSD", "PABSW", "PACKSSDW", "PACKSSWB", "PACKUSDW", 
+    "PACKUSWB", "PADDB", "PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB", 
+    "PADDUSW", "PADDW", "PALIGNR", "PAND", "PANDN", "PAUSE", "PAVGB", 
+    "PAVGUSB", "PAVGW", "PBLENDVB", "PBLENDW", "PCLMULQDQ", "PCMPEQB", 
+    "PCMPEQD", "PCMPEQQ", "PCMPEQW", "PCMPESTRI", "PCMPESTRM", "PCMPGTB", 
+    "PCMPGTD", "PCMPGTQ", "PCMPGTW", "PCMPISTRI", "PCMPISTRM", "PCOMMIT", 
+    "PCONFIG", "PDEP", "PEXT", "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", 
+    "PF2ID", "PF2IW", "PFACC", "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", 
+    "PFMAX", "PFMIN", "PFMUL", "PFNACC", "PFPNACC", "PFRCP", "PFRCPIT1", 
+    "PFRCPIT2", "PFRCPV", "PFRSQIT1", "PFRSQRT", "PFRSQRTV", "PFSUB", 
+    "PFSUBR", "PHADDD", "PHADDSW", "PHADDW", "PHMINPOSUW", "PHSUBD", 
+    "PHSUBSW", "PHSUBW", "PI2FD", "PI2FW", "PINSRB", "PINSRD", "PINSRQ", 
+    "PINSRW", "PMADDUBSW", "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", 
+    "PMAXUB", "PMAXUD", "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", 
+    "PMINUD", "PMINUW", "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", 
+    "PMOVSXDQ", "PMOVSXWD", "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", 
+    "PMOVZXDQ", "PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", 
+    "PMULHUW", "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", 
+    "POPAD", "POPCNT", "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", 
+    "PREFETCHE", "PREFETCHM", "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", 
+    "PREFETCHT2", "PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB", 
+    "PSHUFD", "PSHUFHW", "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", 
+    "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", "PSLLW", "PSMASH", "PSRAD", 
+    "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", "PSRLW", "PSUBB", "PSUBD", 
+    "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD", 
+    "PTEST", "PTWRITE", "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", 
+    "PUNPCKLBW", "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", 
+    "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW", "PVALIDATE", 
+    "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", "RDGSBASE", 
+    "RDMSR", "RDPID", "RDPKRU", "RDPMC", "RDPRU", "RDRAND", "RDSEED", 
+    "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC", "RDTSCP", "RETF", "RETN", 
+    "RMPADJUST", "RMPUPDATE", "ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", 
+    "ROUNDSD", "ROUNDSS", "RSDC", "RSLDT", "RSM", "RSQRTPS", "RSQRTSS", 
+    "RSTORSSP", "RSTS", "SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP", 
+    "SBB", "SCASB", "SCASD", "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", 
+    "SEAMRET", "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", 
+    "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", 
+    "SETO", "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", 
+    "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", 
+    "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", 
+    "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", 
+    "SMINT", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", 
+    "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", 
+    "STOSQ", "STOSW", "STR", "STTILECFG", "SUB", "SUBPD", "SUBPS", 
+    "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", "SYSCALL", 
+    "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TDCALL", "TDPBF16PS", 
+    "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TEST", "TILELOADD", 
+    "TILELOADDT1", "TILERELEASE", "TILESTORED", "TILEZERO", "TLBSYNC", 
+    "TPAUSE", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", "UD0", "UD1", 
+    "UD2", "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", 
+    "UNPCKLPS", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", 
+    "VADDPD", "VADDPS", "VADDSD", "VADDSS", "VADDSUBPD", "VADDSUBPS", 
+    "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC", 
+    "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", "VANDNPS", 
+    "VANDPD", "VANDPS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", 
+    "VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", 
+    "VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", 
+    "VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", 
+    "VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", 
+    "VCMPPD", "VCMPPS", "VCMPSD", "VCMPSS", "VCOMISD", "VCOMISS", 
+    "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PS", "VCVTNE2PS2BF16", 
+    "VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", 
+    "VCVTPD2UQQ", "VCVTPH2PS", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", 
+    "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PS", 
+    "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", "VCVTSI2SD", "VCVTSI2SS", 
+    "VCVTSS2SD", "VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", 
+    "VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", 
+    "VCVTTPS2UQQ", "VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSS2SI", "VCVTTSS2USI", 
+    "VCVTUDQ2PD", "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PS", "VCVTUSI2SD", 
+    "VCVTUSI2SS", "VDBPSADBW", "VDIVPD", "VDIVPS", "VDIVSD", "VDIVSS", 
+    "VDPBF16PS", "VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", 
+    "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", 
     "VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4", 
     "VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS", 
     "VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD", 
diff --git a/bddisasm/include/table_evex.h b/bddisasm/include/table_evex.h
index 044743c..04c2997 100644
--- a/bddisasm/include/table_evex.h
+++ b/bddisasm/include/table_evex.h
@@ -4,7 +4,7 @@
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1337]
+    (const void *)&gInstructions[1348]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9a_03_mem_02_w = 
@@ -39,13 +39,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9a_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1560]
+    (const void *)&gInstructions[1571]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1562]
+    (const void *)&gInstructions[1573]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9a_01_w = 
@@ -71,7 +71,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_03_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1338]
+    (const void *)&gInstructions[1349]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9b_03_mem_w = 
@@ -95,13 +95,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9b_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1564]
+    (const void *)&gInstructions[1575]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1566]
+    (const void *)&gInstructions[1577]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9b_01_w = 
@@ -127,7 +127,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1339]
+    (const void *)&gInstructions[1350]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_aa_03_mem_02_w = 
@@ -162,13 +162,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_aa_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1568]
+    (const void *)&gInstructions[1579]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1570]
+    (const void *)&gInstructions[1581]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_aa_01_w = 
@@ -194,7 +194,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_aa_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_03_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1340]
+    (const void *)&gInstructions[1351]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ab_03_mem_w = 
@@ -218,13 +218,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_ab_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1572]
+    (const void *)&gInstructions[1583]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1574]
+    (const void *)&gInstructions[1585]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ab_01_w = 
@@ -250,7 +250,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ab_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1351]
+    (const void *)&gInstructions[1362]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp = 
@@ -267,7 +267,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_df_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1353]
+    (const void *)&gInstructions[1364]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp = 
@@ -284,7 +284,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1355]
+    (const void *)&gInstructions[1366]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp = 
@@ -301,7 +301,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1357]
+    (const void *)&gInstructions[1368]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp = 
@@ -318,13 +318,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1371]
+    (const void *)&gInstructions[1382]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1372]
+    (const void *)&gInstructions[1383]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_65_01_w = 
@@ -350,13 +350,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_65_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1378]
+    (const void *)&gInstructions[1389]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1389]
+    (const void *)&gInstructions[1400]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_19_01_w = 
@@ -382,13 +382,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_19_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1379]
+    (const void *)&gInstructions[1390]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1381]
+    (const void *)&gInstructions[1392]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1a_01_mem_w = 
@@ -423,13 +423,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1380]
+    (const void *)&gInstructions[1391]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1382]
+    (const void *)&gInstructions[1393]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1b_01_mem_02_w = 
@@ -475,13 +475,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1384]
+    (const void *)&gInstructions[1395]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1943]
+    (const void *)&gInstructions[1954]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_59_01_w = 
@@ -507,13 +507,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_59_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1385]
+    (const void *)&gInstructions[1396]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1387]
+    (const void *)&gInstructions[1398]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_5a_01_mem_w = 
@@ -548,13 +548,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1386]
+    (const void *)&gInstructions[1397]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1388]
+    (const void *)&gInstructions[1399]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_5b_01_mem_02_w = 
@@ -600,7 +600,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_18_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1391]
+    (const void *)&gInstructions[1402]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_18_01_w = 
@@ -626,13 +626,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_18_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1405]
+    (const void *)&gInstructions[1416]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1406]
+    (const void *)&gInstructions[1417]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8a_01_w = 
@@ -658,7 +658,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1412]
+    (const void *)&gInstructions[1423]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w = 
@@ -673,7 +673,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1413]
+    (const void *)&gInstructions[1424]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w = 
@@ -688,7 +688,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2291]
+    (const void *)&gInstructions[2302]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_72_01_w = 
@@ -714,7 +714,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_72_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1422]
+    (const void *)&gInstructions[1433]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w = 
@@ -729,7 +729,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2189]
+    (const void *)&gInstructions[2200]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_13_02_w = 
@@ -755,7 +755,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_13_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1485]
+    (const void *)&gInstructions[1496]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w = 
@@ -770,7 +770,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1883]
+    (const void *)&gInstructions[1894]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_52_03_mem_02_w = 
@@ -805,7 +805,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_52_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1997]
+    (const void *)&gInstructions[2008]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_52_01_w = 
@@ -831,13 +831,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_52_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1490]
+    (const void *)&gInstructions[1501]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1491]
+    (const void *)&gInstructions[1502]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c8_01_02_w = 
@@ -874,13 +874,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1492]
+    (const void *)&gInstructions[1503]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1493]
+    (const void *)&gInstructions[1504]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_88_01_w = 
@@ -906,13 +906,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_88_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1512]
+    (const void *)&gInstructions[1523]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1514]
+    (const void *)&gInstructions[1525]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_98_01_w = 
@@ -938,13 +938,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_98_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1516]
+    (const void *)&gInstructions[1527]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1518]
+    (const void *)&gInstructions[1529]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_99_01_w = 
@@ -970,13 +970,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_99_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1520]
+    (const void *)&gInstructions[1531]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1522]
+    (const void *)&gInstructions[1533]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a8_01_w = 
@@ -1002,13 +1002,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1524]
+    (const void *)&gInstructions[1535]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1526]
+    (const void *)&gInstructions[1537]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a9_01_w = 
@@ -1034,13 +1034,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1528]
+    (const void *)&gInstructions[1539]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1530]
+    (const void *)&gInstructions[1541]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b8_01_w = 
@@ -1066,13 +1066,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1532]
+    (const void *)&gInstructions[1543]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1534]
+    (const void *)&gInstructions[1545]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b9_01_w = 
@@ -1098,13 +1098,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1544]
+    (const void *)&gInstructions[1555]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1546]
+    (const void *)&gInstructions[1557]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_96_01_w = 
@@ -1130,13 +1130,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_96_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1548]
+    (const void *)&gInstructions[1559]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1550]
+    (const void *)&gInstructions[1561]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a6_01_w = 
@@ -1162,13 +1162,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1552]
+    (const void *)&gInstructions[1563]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1554]
+    (const void *)&gInstructions[1565]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b6_01_w = 
@@ -1194,13 +1194,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1576]
+    (const void *)&gInstructions[1587]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1578]
+    (const void *)&gInstructions[1589]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ba_01_w = 
@@ -1226,13 +1226,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ba_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1580]
+    (const void *)&gInstructions[1591]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1582]
+    (const void *)&gInstructions[1593]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bb_01_w = 
@@ -1258,13 +1258,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1584]
+    (const void *)&gInstructions[1595]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1586]
+    (const void *)&gInstructions[1597]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_97_01_w = 
@@ -1290,13 +1290,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_97_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1588]
+    (const void *)&gInstructions[1599]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1590]
+    (const void *)&gInstructions[1601]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a7_01_w = 
@@ -1322,13 +1322,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1592]
+    (const void *)&gInstructions[1603]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1594]
+    (const void *)&gInstructions[1605]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b7_01_w = 
@@ -1354,13 +1354,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1608]
+    (const void *)&gInstructions[1619]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1610]
+    (const void *)&gInstructions[1621]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9c_01_w = 
@@ -1386,13 +1386,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1612]
+    (const void *)&gInstructions[1623]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1614]
+    (const void *)&gInstructions[1625]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9d_01_w = 
@@ -1418,13 +1418,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1616]
+    (const void *)&gInstructions[1627]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1618]
+    (const void *)&gInstructions[1629]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ac_01_w = 
@@ -1450,13 +1450,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ac_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1620]
+    (const void *)&gInstructions[1631]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1622]
+    (const void *)&gInstructions[1633]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ad_01_w = 
@@ -1482,13 +1482,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ad_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1624]
+    (const void *)&gInstructions[1635]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1626]
+    (const void *)&gInstructions[1637]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bc_01_w = 
@@ -1514,13 +1514,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1628]
+    (const void *)&gInstructions[1639]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1630]
+    (const void *)&gInstructions[1641]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bd_01_w = 
@@ -1546,13 +1546,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1640]
+    (const void *)&gInstructions[1651]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1642]
+    (const void *)&gInstructions[1653]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9e_01_w = 
@@ -1578,13 +1578,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1644]
+    (const void *)&gInstructions[1655]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1646]
+    (const void *)&gInstructions[1657]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9f_01_w = 
@@ -1610,13 +1610,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1648]
+    (const void *)&gInstructions[1659]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1650]
+    (const void *)&gInstructions[1661]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ae_01_w = 
@@ -1642,13 +1642,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ae_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1652]
+    (const void *)&gInstructions[1663]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1654]
+    (const void *)&gInstructions[1665]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_af_01_w = 
@@ -1674,13 +1674,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_af_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1656]
+    (const void *)&gInstructions[1667]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1658]
+    (const void *)&gInstructions[1669]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_be_01_w = 
@@ -1706,13 +1706,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_be_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1660]
+    (const void *)&gInstructions[1671]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1662]
+    (const void *)&gInstructions[1673]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bf_01_w = 
@@ -1738,13 +1738,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1680]
+    (const void *)&gInstructions[1691]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1682]
+    (const void *)&gInstructions[1693]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_92_01_mem_w = 
@@ -1779,13 +1779,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_92_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1684]
+    (const void *)&gInstructions[1695]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1685]
+    (const void *)&gInstructions[1696]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_01_02_w = 
@@ -1811,13 +1811,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_01_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1688]
+    (const void *)&gInstructions[1699]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1689]
+    (const void *)&gInstructions[1700]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_02_02_w = 
@@ -1843,13 +1843,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_02_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2445]
+    (const void *)&gInstructions[2456]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2446]
+    (const void *)&gInstructions[2457]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_05_02_w = 
@@ -1875,13 +1875,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_05_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2449]
+    (const void *)&gInstructions[2460]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2450]
+    (const void *)&gInstructions[2461]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_06_02_w = 
@@ -1942,13 +1942,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1686]
+    (const void *)&gInstructions[1697]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1687]
+    (const void *)&gInstructions[1698]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_01_02_w = 
@@ -1974,13 +1974,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_01_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1690]
+    (const void *)&gInstructions[1701]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1691]
+    (const void *)&gInstructions[1702]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_02_02_w = 
@@ -2006,13 +2006,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_02_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2447]
+    (const void *)&gInstructions[2458]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2448]
+    (const void *)&gInstructions[2459]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_05_02_w = 
@@ -2038,13 +2038,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_05_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2451]
+    (const void *)&gInstructions[2462]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2452]
+    (const void *)&gInstructions[2463]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_06_02_w = 
@@ -2105,13 +2105,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1692]
+    (const void *)&gInstructions[1703]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1694]
+    (const void *)&gInstructions[1705]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_93_01_mem_w = 
@@ -2146,13 +2146,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_93_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1696]
+    (const void *)&gInstructions[1707]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1697]
+    (const void *)&gInstructions[1708]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_42_01_w = 
@@ -2178,13 +2178,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_42_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1698]
+    (const void *)&gInstructions[1709]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1699]
+    (const void *)&gInstructions[1710]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_43_01_w = 
@@ -2210,7 +2210,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_43_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1708]
+    (const void *)&gInstructions[1719]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cf_01_w = 
@@ -2236,7 +2236,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1817]
+    (const void *)&gInstructions[1828]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2a_01_mem_w = 
@@ -2260,7 +2260,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1941]
+    (const void *)&gInstructions[1952]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2a_02_reg_w = 
@@ -2295,13 +2295,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1881]
+    (const void *)&gInstructions[1892]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1882]
+    (const void *)&gInstructions[1893]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_68_03_w = 
@@ -2327,7 +2327,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_68_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1884]
+    (const void *)&gInstructions[1895]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_53_03_mem_02_w = 
@@ -2362,7 +2362,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_53_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1998]
+    (const void *)&gInstructions[2009]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_53_01_w = 
@@ -2388,7 +2388,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_53_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1885]
+    (const void *)&gInstructions[1896]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp = 
@@ -2405,7 +2405,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1887]
+    (const void *)&gInstructions[1898]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1e_01_w = 
@@ -2431,7 +2431,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1889]
+    (const void *)&gInstructions[1900]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1f_01_w = 
@@ -2457,7 +2457,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1890]
+    (const void *)&gInstructions[1901]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp = 
@@ -2474,7 +2474,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1896]
+    (const void *)&gInstructions[1907]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2b_01_w = 
@@ -2500,13 +2500,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1929]
+    (const void *)&gInstructions[1940]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1932]
+    (const void *)&gInstructions[1943]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_66_01_w = 
@@ -2532,13 +2532,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_66_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1930]
+    (const void *)&gInstructions[1941]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1931]
+    (const void *)&gInstructions[1942]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_64_01_w = 
@@ -2564,7 +2564,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_64_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1935]
+    (const void *)&gInstructions[1946]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_78_01_w = 
@@ -2590,7 +2590,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_78_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7a_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1936]
+    (const void *)&gInstructions[1947]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7a_01_reg_w = 
@@ -2625,7 +2625,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_58_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1938]
+    (const void *)&gInstructions[1949]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_58_01_w = 
@@ -2651,13 +2651,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_58_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1939]
+    (const void *)&gInstructions[1950]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1944]
+    (const void *)&gInstructions[1955]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7c_01_reg_w = 
@@ -2692,7 +2692,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1942]
+    (const void *)&gInstructions[1953]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3a_02_reg_w = 
@@ -2716,7 +2716,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_3a_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2149]
+    (const void *)&gInstructions[2160]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp = 
@@ -2733,7 +2733,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1946]
+    (const void *)&gInstructions[1957]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_79_01_w = 
@@ -2759,7 +2759,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_79_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7b_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1947]
+    (const void *)&gInstructions[1958]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7b_01_reg_w = 
@@ -2794,7 +2794,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1959]
+    (const void *)&gInstructions[1970]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w = 
@@ -2809,13 +2809,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2151]
+    (const void *)&gInstructions[2162]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2194]
+    (const void *)&gInstructions[2205]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_29_02_reg_w = 
@@ -2850,7 +2850,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_29_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_37_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1969]
+    (const void *)&gInstructions[1980]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_37_01_w = 
@@ -2876,13 +2876,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_37_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1983]
+    (const void *)&gInstructions[1994]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1986]
+    (const void *)&gInstructions[1997]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_63_01_w = 
@@ -2908,13 +2908,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_63_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1984]
+    (const void *)&gInstructions[1995]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1985]
+    (const void *)&gInstructions[1996]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8b_01_w = 
@@ -2940,13 +2940,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1993]
+    (const void *)&gInstructions[2004]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1994]
+    (const void *)&gInstructions[2005]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c4_01_w = 
@@ -2972,7 +2972,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_50_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1995]
+    (const void *)&gInstructions[2006]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_50_01_w = 
@@ -2998,7 +2998,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_50_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_51_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1996]
+    (const void *)&gInstructions[2007]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_51_01_w = 
@@ -3024,13 +3024,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2001]
+    (const void *)&gInstructions[2012]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2038]
+    (const void *)&gInstructions[2049]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8d_01_w = 
@@ -3056,13 +3056,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2002]
+    (const void *)&gInstructions[2013]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2029]
+    (const void *)&gInstructions[2040]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_36_01_w = 
@@ -3088,13 +3088,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_36_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2004]
+    (const void *)&gInstructions[2015]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2009]
+    (const void *)&gInstructions[2020]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_75_01_w = 
@@ -3120,13 +3120,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_75_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2005]
+    (const void *)&gInstructions[2016]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2008]
+    (const void *)&gInstructions[2019]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_76_01_w = 
@@ -3152,13 +3152,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_76_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2006]
+    (const void *)&gInstructions[2017]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2007]
+    (const void *)&gInstructions[2018]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_77_01_w = 
@@ -3184,7 +3184,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_77_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_0d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2014]
+    (const void *)&gInstructions[2025]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_0d_01_w = 
@@ -3210,7 +3210,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_0c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2018]
+    (const void *)&gInstructions[2029]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_0c_01_w = 
@@ -3236,13 +3236,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2022]
+    (const void *)&gInstructions[2033]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2026]
+    (const void *)&gInstructions[2037]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w = 
@@ -3257,13 +3257,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2023]
+    (const void *)&gInstructions[2034]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2027]
+    (const void *)&gInstructions[2038]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_16_01_02_w = 
@@ -3300,13 +3300,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_16_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2032]
+    (const void *)&gInstructions[2043]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2037]
+    (const void *)&gInstructions[2048]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7d_01_w = 
@@ -3332,13 +3332,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2033]
+    (const void *)&gInstructions[2044]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2036]
+    (const void *)&gInstructions[2047]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7e_01_w = 
@@ -3364,13 +3364,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2034]
+    (const void *)&gInstructions[2045]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2035]
+    (const void *)&gInstructions[2046]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7f_01_w = 
@@ -3396,13 +3396,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2039]
+    (const void *)&gInstructions[2050]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2042]
+    (const void *)&gInstructions[2053]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_62_01_w = 
@@ -3428,13 +3428,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_62_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2040]
+    (const void *)&gInstructions[2051]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2041]
+    (const void *)&gInstructions[2052]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_89_01_w = 
@@ -3460,13 +3460,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_89_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2057]
+    (const void *)&gInstructions[2068]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2059]
+    (const void *)&gInstructions[2070]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_90_01_mem_w = 
@@ -3501,13 +3501,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_90_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2061]
+    (const void *)&gInstructions[2072]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2063]
+    (const void *)&gInstructions[2074]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_91_01_mem_w = 
@@ -3542,13 +3542,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_91_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2099]
+    (const void *)&gInstructions[2110]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2100]
+    (const void *)&gInstructions[2111]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_44_01_w = 
@@ -3574,7 +3574,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_44_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b5_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2113]
+    (const void *)&gInstructions[2124]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b5_01_w = 
@@ -3600,7 +3600,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2114]
+    (const void *)&gInstructions[2125]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b4_01_w = 
@@ -3626,7 +3626,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2115]
+    (const void *)&gInstructions[2126]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp = 
@@ -3643,7 +3643,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2123]
+    (const void *)&gInstructions[2134]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp = 
@@ -3660,13 +3660,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2125]
+    (const void *)&gInstructions[2136]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2127]
+    (const void *)&gInstructions[2138]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3d_01_w = 
@@ -3692,13 +3692,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2132]
+    (const void *)&gInstructions[2143]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2134]
+    (const void *)&gInstructions[2145]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3f_01_w = 
@@ -3724,7 +3724,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2135]
+    (const void *)&gInstructions[2146]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp = 
@@ -3741,19 +3741,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2137]
+    (const void *)&gInstructions[2148]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2156]
+    (const void *)&gInstructions[2167]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2157]
+    (const void *)&gInstructions[2168]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_38_02_reg_w = 
@@ -3788,13 +3788,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_38_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2139]
+    (const void *)&gInstructions[2150]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2141]
+    (const void *)&gInstructions[2152]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w = 
@@ -3809,13 +3809,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2152]
+    (const void *)&gInstructions[2163]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2160]
+    (const void *)&gInstructions[2171]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_39_02_reg_w = 
@@ -3850,13 +3850,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_39_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2146]
+    (const void *)&gInstructions[2157]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2148]
+    (const void *)&gInstructions[2159]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3b_01_w = 
@@ -3882,7 +3882,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2153]
+    (const void *)&gInstructions[2164]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w = 
@@ -3897,7 +3897,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2196]
+    (const void *)&gInstructions[2207]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp = 
@@ -3914,7 +3914,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2154]
+    (const void *)&gInstructions[2165]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w = 
@@ -3929,7 +3929,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2208]
+    (const void *)&gInstructions[2219]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp = 
@@ -3946,13 +3946,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2155]
+    (const void *)&gInstructions[2166]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2158]
+    (const void *)&gInstructions[2169]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_28_02_reg_w = 
@@ -3976,7 +3976,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_28_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2214]
+    (const void *)&gInstructions[2225]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_28_01_w = 
@@ -4002,7 +4002,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_28_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2161]
+    (const void *)&gInstructions[2172]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w = 
@@ -4017,7 +4017,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2199]
+    (const void *)&gInstructions[2210]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp = 
@@ -4034,7 +4034,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2162]
+    (const void *)&gInstructions[2173]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w = 
@@ -4049,7 +4049,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2205]
+    (const void *)&gInstructions[2216]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_35_01_w = 
@@ -4075,7 +4075,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_35_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2163]
+    (const void *)&gInstructions[2174]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w = 
@@ -4090,7 +4090,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2211]
+    (const void *)&gInstructions[2222]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp = 
@@ -4107,7 +4107,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2164]
+    (const void *)&gInstructions[2175]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w = 
@@ -4122,7 +4122,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2170]
+    (const void *)&gInstructions[2181]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp = 
@@ -4139,7 +4139,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2165]
+    (const void *)&gInstructions[2176]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w = 
@@ -4154,7 +4154,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2182]
+    (const void *)&gInstructions[2193]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp = 
@@ -4171,7 +4171,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2166]
+    (const void *)&gInstructions[2177]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w = 
@@ -4186,7 +4186,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2173]
+    (const void *)&gInstructions[2184]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp = 
@@ -4203,7 +4203,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2167]
+    (const void *)&gInstructions[2178]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w = 
@@ -4218,7 +4218,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2179]
+    (const void *)&gInstructions[2190]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_25_01_w = 
@@ -4244,7 +4244,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_25_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2168]
+    (const void *)&gInstructions[2179]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w = 
@@ -4259,7 +4259,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2185]
+    (const void *)&gInstructions[2196]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp = 
@@ -4276,7 +4276,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2169]
+    (const void *)&gInstructions[2180]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w = 
@@ -4291,7 +4291,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2176]
+    (const void *)&gInstructions[2187]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp = 
@@ -4308,7 +4308,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2188]
+    (const void *)&gInstructions[2199]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w = 
@@ -4323,7 +4323,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2333]
+    (const void *)&gInstructions[2344]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_11_01_w = 
@@ -4349,7 +4349,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_11_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2190]
+    (const void *)&gInstructions[2201]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w = 
@@ -4364,7 +4364,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2319]
+    (const void *)&gInstructions[2330]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_12_01_w = 
@@ -4390,7 +4390,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_12_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2191]
+    (const void *)&gInstructions[2202]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w = 
@@ -4405,13 +4405,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2241]
+    (const void *)&gInstructions[2252]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2242]
+    (const void *)&gInstructions[2253]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_15_01_w = 
@@ -4437,7 +4437,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_15_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2192]
+    (const void *)&gInstructions[2203]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w = 
@@ -4452,13 +4452,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2245]
+    (const void *)&gInstructions[2256]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2246]
+    (const void *)&gInstructions[2257]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_14_01_w = 
@@ -4484,7 +4484,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_14_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2193]
+    (const void *)&gInstructions[2204]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w = 
@@ -4499,7 +4499,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2352]
+    (const void *)&gInstructions[2363]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_10_01_w = 
@@ -4525,7 +4525,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_10_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2195]
+    (const void *)&gInstructions[2206]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w = 
@@ -4540,7 +4540,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2202]
+    (const void *)&gInstructions[2213]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp = 
@@ -4557,7 +4557,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_0b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2216]
+    (const void *)&gInstructions[2227]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp = 
@@ -4574,13 +4574,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2222]
+    (const void *)&gInstructions[2233]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2224]
+    (const void *)&gInstructions[2235]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_40_01_w = 
@@ -4606,7 +4606,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_40_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_83_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2227]
+    (const void *)&gInstructions[2238]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_83_01_w = 
@@ -4632,13 +4632,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_83_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2230]
+    (const void *)&gInstructions[2241]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2233]
+    (const void *)&gInstructions[2244]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_54_01_w = 
@@ -4664,13 +4664,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_54_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2231]
+    (const void *)&gInstructions[2242]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2232]
+    (const void *)&gInstructions[2243]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_55_01_w = 
@@ -4696,13 +4696,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_55_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2261]
+    (const void *)&gInstructions[2272]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2262]
+    (const void *)&gInstructions[2273]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a0_01_mem_w = 
@@ -4737,13 +4737,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a0_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2263]
+    (const void *)&gInstructions[2274]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2264]
+    (const void *)&gInstructions[2275]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a1_01_mem_w = 
@@ -4778,13 +4778,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2280]
+    (const void *)&gInstructions[2291]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2281]
+    (const void *)&gInstructions[2292]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_71_01_w = 
@@ -4810,7 +4810,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_71_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_70_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2282]
+    (const void *)&gInstructions[2293]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_70_01_w = 
@@ -4836,13 +4836,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_70_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2289]
+    (const void *)&gInstructions[2300]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2290]
+    (const void *)&gInstructions[2301]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_73_01_w = 
@@ -4868,7 +4868,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_73_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2293]
+    (const void *)&gInstructions[2304]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp = 
@@ -4885,7 +4885,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2295]
+    (const void *)&gInstructions[2306]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8f_01_w = 
@@ -4911,13 +4911,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2315]
+    (const void *)&gInstructions[2326]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2317]
+    (const void *)&gInstructions[2328]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_47_01_w = 
@@ -4943,13 +4943,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_47_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2330]
+    (const void *)&gInstructions[2341]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2332]
+    (const void *)&gInstructions[2343]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_46_01_w = 
@@ -4975,13 +4975,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_46_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2348]
+    (const void *)&gInstructions[2359]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2350]
+    (const void *)&gInstructions[2361]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_45_01_w = 
@@ -5007,13 +5007,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_45_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2376]
+    (const void *)&gInstructions[2387]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2379]
+    (const void *)&gInstructions[2390]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w = 
@@ -5028,13 +5028,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2380]
+    (const void *)&gInstructions[2391]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2383]
+    (const void *)&gInstructions[2394]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_26_02_w = 
@@ -5060,13 +5060,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_26_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2377]
+    (const void *)&gInstructions[2388]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2378]
+    (const void *)&gInstructions[2389]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w = 
@@ -5081,13 +5081,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2381]
+    (const void *)&gInstructions[2392]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2382]
+    (const void *)&gInstructions[2393]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_27_02_w = 
@@ -5113,13 +5113,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_27_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2407]
+    (const void *)&gInstructions[2418]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2408]
+    (const void *)&gInstructions[2419]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4c_01_w = 
@@ -5145,13 +5145,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2409]
+    (const void *)&gInstructions[2420]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2410]
+    (const void *)&gInstructions[2421]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4d_01_w = 
@@ -5177,13 +5177,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2411]
+    (const void *)&gInstructions[2422]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2412]
+    (const void *)&gInstructions[2423]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ca_01_02_w = 
@@ -5220,13 +5220,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ca_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2413]
+    (const void *)&gInstructions[2424]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2414]
+    (const void *)&gInstructions[2425]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cb_01_w = 
@@ -5252,13 +5252,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2429]
+    (const void *)&gInstructions[2440]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2430]
+    (const void *)&gInstructions[2441]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4e_01_w = 
@@ -5284,13 +5284,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2431]
+    (const void *)&gInstructions[2442]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2432]
+    (const void *)&gInstructions[2443]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4f_01_w = 
@@ -5316,13 +5316,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2433]
+    (const void *)&gInstructions[2444]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2434]
+    (const void *)&gInstructions[2445]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cc_01_02_w = 
@@ -5359,13 +5359,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2435]
+    (const void *)&gInstructions[2446]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2436]
+    (const void *)&gInstructions[2447]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cd_01_w = 
@@ -5391,13 +5391,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2439]
+    (const void *)&gInstructions[2450]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2440]
+    (const void *)&gInstructions[2451]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2c_01_w = 
@@ -5423,13 +5423,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2441]
+    (const void *)&gInstructions[2452]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2442]
+    (const void *)&gInstructions[2453]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2d_01_w = 
@@ -5455,13 +5455,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2443]
+    (const void *)&gInstructions[2454]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2444]
+    (const void *)&gInstructions[2455]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a2_01_mem_w = 
@@ -5496,13 +5496,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2453]
+    (const void *)&gInstructions[2464]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2454]
+    (const void *)&gInstructions[2465]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a3_01_mem_w = 
@@ -5800,7 +5800,7 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1341]
+    (const void *)&gInstructions[1352]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w = 
@@ -5815,7 +5815,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1343]
+    (const void *)&gInstructions[1354]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w = 
@@ -5830,7 +5830,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1345]
+    (const void *)&gInstructions[1356]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w = 
@@ -5845,7 +5845,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1347]
+    (const void *)&gInstructions[1358]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_02_w = 
@@ -5871,7 +5871,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_58_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1363]
+    (const void *)&gInstructions[1374]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w = 
@@ -5886,7 +5886,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1365]
+    (const void *)&gInstructions[1376]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_55_00_w = 
@@ -5912,7 +5912,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_55_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1367]
+    (const void *)&gInstructions[1378]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w = 
@@ -5927,7 +5927,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1369]
+    (const void *)&gInstructions[1380]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_54_00_w = 
@@ -5953,7 +5953,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_54_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1393]
+    (const void *)&gInstructions[1404]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w = 
@@ -5968,7 +5968,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1395]
+    (const void *)&gInstructions[1406]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w = 
@@ -5983,7 +5983,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1397]
+    (const void *)&gInstructions[1408]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w = 
@@ -5998,7 +5998,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1399]
+    (const void *)&gInstructions[1410]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_02_w = 
@@ -6024,7 +6024,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1401]
+    (const void *)&gInstructions[1412]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w = 
@@ -6039,7 +6039,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1403]
+    (const void *)&gInstructions[1414]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2f_00_w = 
@@ -6065,13 +6065,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1407]
+    (const void *)&gInstructions[1418]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1436]
+    (const void *)&gInstructions[1447]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w = 
@@ -6086,7 +6086,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1414]
+    (const void *)&gInstructions[1425]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w = 
@@ -6101,7 +6101,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1453]
+    (const void *)&gInstructions[1464]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e6_01_w = 
@@ -6127,13 +6127,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1410]
+    (const void *)&gInstructions[1421]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1437]
+    (const void *)&gInstructions[1448]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w = 
@@ -6148,7 +6148,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1425]
+    (const void *)&gInstructions[1436]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w = 
@@ -6163,7 +6163,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1458]
+    (const void *)&gInstructions[1469]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5b_02_w = 
@@ -6189,7 +6189,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1416]
+    (const void *)&gInstructions[1427]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w = 
@@ -6204,7 +6204,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1427]
+    (const void *)&gInstructions[1438]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w = 
@@ -6219,7 +6219,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1440]
+    (const void *)&gInstructions[1451]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w = 
@@ -6234,7 +6234,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1448]
+    (const void *)&gInstructions[1459]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_02_w = 
@@ -6260,13 +6260,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1419]
+    (const void *)&gInstructions[1430]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1433]
+    (const void *)&gInstructions[1444]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w = 
@@ -6281,13 +6281,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1473]
+    (const void *)&gInstructions[1484]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1474]
+    (const void *)&gInstructions[1485]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_w = 
@@ -6302,7 +6302,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1475]
+    (const void *)&gInstructions[1486]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp = 
@@ -6319,13 +6319,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1420]
+    (const void *)&gInstructions[1431]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1434]
+    (const void *)&gInstructions[1445]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w = 
@@ -6340,13 +6340,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1421]
+    (const void *)&gInstructions[1432]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1435]
+    (const void *)&gInstructions[1446]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w = 
@@ -6361,13 +6361,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1442]
+    (const void *)&gInstructions[1453]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1452]
+    (const void *)&gInstructions[1463]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp = 
@@ -6384,13 +6384,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1438]
+    (const void *)&gInstructions[1449]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1450]
+    (const void *)&gInstructions[1461]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp = 
@@ -6407,13 +6407,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1443]
+    (const void *)&gInstructions[1454]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1444]
+    (const void *)&gInstructions[1455]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_w = 
@@ -6428,7 +6428,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1446]
+    (const void *)&gInstructions[1457]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp = 
@@ -6445,13 +6445,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1455]
+    (const void *)&gInstructions[1466]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1460]
+    (const void *)&gInstructions[1471]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w = 
@@ -6466,13 +6466,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1469]
+    (const void *)&gInstructions[1480]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1471]
+    (const void *)&gInstructions[1482]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w = 
@@ -6487,13 +6487,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1470]
+    (const void *)&gInstructions[1481]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1472]
+    (const void *)&gInstructions[1483]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7a_03_w = 
@@ -6519,13 +6519,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1456]
+    (const void *)&gInstructions[1467]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1461]
+    (const void *)&gInstructions[1472]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w = 
@@ -6540,13 +6540,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1457]
+    (const void *)&gInstructions[1468]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1462]
+    (const void *)&gInstructions[1473]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w = 
@@ -6561,13 +6561,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1465]
+    (const void *)&gInstructions[1476]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1468]
+    (const void *)&gInstructions[1479]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp = 
@@ -6584,13 +6584,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1463]
+    (const void *)&gInstructions[1474]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1466]
+    (const void *)&gInstructions[1477]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp = 
@@ -6607,7 +6607,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1477]
+    (const void *)&gInstructions[1488]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w = 
@@ -6622,7 +6622,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1479]
+    (const void *)&gInstructions[1490]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w = 
@@ -6637,7 +6637,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1481]
+    (const void *)&gInstructions[1492]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w = 
@@ -6652,7 +6652,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1483]
+    (const void *)&gInstructions[1494]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_02_w = 
@@ -6678,7 +6678,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1735]
+    (const void *)&gInstructions[1746]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w = 
@@ -6693,7 +6693,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1737]
+    (const void *)&gInstructions[1748]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w = 
@@ -6708,7 +6708,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1739]
+    (const void *)&gInstructions[1750]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w = 
@@ -6723,7 +6723,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1741]
+    (const void *)&gInstructions[1752]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_02_w = 
@@ -6749,7 +6749,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1748]
+    (const void *)&gInstructions[1759]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w = 
@@ -6764,7 +6764,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1750]
+    (const void *)&gInstructions[1761]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w = 
@@ -6779,7 +6779,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1752]
+    (const void *)&gInstructions[1763]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w = 
@@ -6794,7 +6794,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1754]
+    (const void *)&gInstructions[1765]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_02_w = 
@@ -6820,7 +6820,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1760]
+    (const void *)&gInstructions[1771]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w = 
@@ -6835,7 +6835,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1764]
+    (const void *)&gInstructions[1775]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_28_00_w = 
@@ -6861,7 +6861,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_28_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1761]
+    (const void *)&gInstructions[1772]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w = 
@@ -6876,7 +6876,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1765]
+    (const void *)&gInstructions[1776]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_29_00_w = 
@@ -6902,13 +6902,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_29_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1768]
+    (const void *)&gInstructions[1779]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1823]
+    (const void *)&gInstructions[1834]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6e_01_00_w = 
@@ -6945,13 +6945,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1769]
+    (const void *)&gInstructions[1780]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1824]
+    (const void *)&gInstructions[1835]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7e_01_00_w = 
@@ -6977,7 +6977,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_7e_01_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_02_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1825]
+    (const void *)&gInstructions[1836]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7e_02_00_w = 
@@ -7014,7 +7014,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1772]
+    (const void *)&gInstructions[1783]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w = 
@@ -7029,7 +7029,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1773]
+    (const void *)&gInstructions[1784]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w = 
@@ -7044,7 +7044,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1774]
+    (const void *)&gInstructions[1785]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_03_02_w = 
@@ -7070,7 +7070,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_03_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1793]
+    (const void *)&gInstructions[1804]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_00_reg_00_w = 
@@ -7096,7 +7096,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_00_reg_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1809]
+    (const void *)&gInstructions[1820]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_00_mem_00_w = 
@@ -7131,7 +7131,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_00_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1805]
+    (const void *)&gInstructions[1816]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_01_mem_00_w = 
@@ -7166,7 +7166,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1841]
+    (const void *)&gInstructions[1852]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_02_w = 
@@ -7192,13 +7192,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_12_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1779]
+    (const void *)&gInstructions[1790]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1781]
+    (const void *)&gInstructions[1792]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w = 
@@ -7213,13 +7213,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1785]
+    (const void *)&gInstructions[1796]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1791]
+    (const void *)&gInstructions[1802]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w = 
@@ -7234,13 +7234,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1787]
+    (const void *)&gInstructions[1798]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1789]
+    (const void *)&gInstructions[1800]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6f_02_w = 
@@ -7266,13 +7266,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1780]
+    (const void *)&gInstructions[1791]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1782]
+    (const void *)&gInstructions[1793]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w = 
@@ -7287,13 +7287,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1786]
+    (const void *)&gInstructions[1797]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1792]
+    (const void *)&gInstructions[1803]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w = 
@@ -7308,13 +7308,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1788]
+    (const void *)&gInstructions[1799]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1790]
+    (const void *)&gInstructions[1801]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7f_02_w = 
@@ -7340,7 +7340,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1795]
+    (const void *)&gInstructions[1806]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_01_mem_00_w = 
@@ -7375,7 +7375,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1799]
+    (const void *)&gInstructions[1810]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_00_mem_00_w = 
@@ -7401,7 +7401,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_16_00_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1803]
+    (const void *)&gInstructions[1814]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_00_reg_00_w = 
@@ -7436,7 +7436,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_00_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1839]
+    (const void *)&gInstructions[1850]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_02_w = 
@@ -7462,7 +7462,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_16_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1796]
+    (const void *)&gInstructions[1807]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_17_01_mem_00_w = 
@@ -7497,7 +7497,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1800]
+    (const void *)&gInstructions[1811]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_17_00_mem_00_w = 
@@ -7543,7 +7543,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_17_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1806]
+    (const void *)&gInstructions[1817]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_13_01_mem_00_w = 
@@ -7578,7 +7578,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1810]
+    (const void *)&gInstructions[1821]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_13_00_mem_00_w = 
@@ -7624,7 +7624,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_13_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e7_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1815]
+    (const void *)&gInstructions[1826]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e7_01_mem_w = 
@@ -7659,7 +7659,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1819]
+    (const void *)&gInstructions[1830]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2b_01_mem_w = 
@@ -7683,7 +7683,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1821]
+    (const void *)&gInstructions[1832]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2b_00_mem_w = 
@@ -7718,7 +7718,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d6_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1826]
+    (const void *)&gInstructions[1837]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d6_01_00_w = 
@@ -7755,7 +7755,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1831]
+    (const void *)&gInstructions[1842]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w = 
@@ -7770,7 +7770,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1832]
+    (const void *)&gInstructions[1843]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_03_reg_w = 
@@ -7794,7 +7794,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1843]
+    (const void *)&gInstructions[1854]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w = 
@@ -7809,7 +7809,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1844]
+    (const void *)&gInstructions[1855]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_02_reg_w = 
@@ -7833,7 +7833,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1851]
+    (const void *)&gInstructions[1862]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w = 
@@ -7848,7 +7848,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1855]
+    (const void *)&gInstructions[1866]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_00_w = 
@@ -7874,7 +7874,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_10_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1833]
+    (const void *)&gInstructions[1844]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w = 
@@ -7889,7 +7889,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1834]
+    (const void *)&gInstructions[1845]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_03_reg_w = 
@@ -7913,7 +7913,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1845]
+    (const void *)&gInstructions[1856]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w = 
@@ -7928,7 +7928,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1846]
+    (const void *)&gInstructions[1857]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_02_reg_w = 
@@ -7952,7 +7952,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1852]
+    (const void *)&gInstructions[1863]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w = 
@@ -7967,7 +7967,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1856]
+    (const void *)&gInstructions[1867]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_00_w = 
@@ -7993,7 +7993,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_11_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1866]
+    (const void *)&gInstructions[1877]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w = 
@@ -8008,7 +8008,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1868]
+    (const void *)&gInstructions[1879]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w = 
@@ -8023,7 +8023,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1870]
+    (const void *)&gInstructions[1881]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w = 
@@ -8038,7 +8038,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1872]
+    (const void *)&gInstructions[1883]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_02_w = 
@@ -8064,7 +8064,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_59_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1877]
+    (const void *)&gInstructions[1888]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w = 
@@ -8079,7 +8079,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1879]
+    (const void *)&gInstructions[1890]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_56_00_w = 
@@ -8105,7 +8105,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_56_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1892]
+    (const void *)&gInstructions[1903]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6b_01_w = 
@@ -8131,7 +8131,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_63_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1894]
+    (const void *)&gInstructions[1905]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp = 
@@ -8148,7 +8148,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_67_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1898]
+    (const void *)&gInstructions[1909]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp = 
@@ -8165,7 +8165,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1900]
+    (const void *)&gInstructions[1911]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp = 
@@ -8182,7 +8182,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fe_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1902]
+    (const void *)&gInstructions[1913]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_fe_01_w = 
@@ -8208,7 +8208,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fe_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1904]
+    (const void *)&gInstructions[1915]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d4_01_w = 
@@ -8234,7 +8234,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ec_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1906]
+    (const void *)&gInstructions[1917]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp = 
@@ -8251,7 +8251,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ed_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1908]
+    (const void *)&gInstructions[1919]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp = 
@@ -8268,7 +8268,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1910]
+    (const void *)&gInstructions[1921]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp = 
@@ -8285,7 +8285,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1912]
+    (const void *)&gInstructions[1923]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp = 
@@ -8302,7 +8302,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1914]
+    (const void *)&gInstructions[1925]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp = 
@@ -8319,13 +8319,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1919]
+    (const void *)&gInstructions[1930]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1923]
+    (const void *)&gInstructions[1934]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_db_01_w = 
@@ -8351,13 +8351,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_db_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1921]
+    (const void *)&gInstructions[1932]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1922]
+    (const void *)&gInstructions[1933]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_df_01_w = 
@@ -8383,7 +8383,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_df_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1924]
+    (const void *)&gInstructions[1935]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp = 
@@ -8400,7 +8400,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1926]
+    (const void *)&gInstructions[1937]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp = 
@@ -8417,7 +8417,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_74_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1955]
+    (const void *)&gInstructions[1966]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp = 
@@ -8434,7 +8434,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_76_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1957]
+    (const void *)&gInstructions[1968]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp = 
@@ -8451,7 +8451,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_75_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1961]
+    (const void *)&gInstructions[1972]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp = 
@@ -8468,7 +8468,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_64_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1965]
+    (const void *)&gInstructions[1976]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp = 
@@ -8485,7 +8485,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_66_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1967]
+    (const void *)&gInstructions[1978]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_66_01_w = 
@@ -8511,7 +8511,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_66_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_65_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1971]
+    (const void *)&gInstructions[1982]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp = 
@@ -8528,7 +8528,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c5_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2051]
+    (const void *)&gInstructions[2062]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_01_c5_01_reg_l = 
@@ -8565,7 +8565,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2095]
+    (const void *)&gInstructions[2106]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l = 
@@ -8582,7 +8582,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2096]
+    (const void *)&gInstructions[2107]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_reg_l = 
@@ -8619,7 +8619,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2117]
+    (const void *)&gInstructions[2128]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp = 
@@ -8636,7 +8636,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ee_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2128]
+    (const void *)&gInstructions[2139]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp = 
@@ -8653,7 +8653,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2130]
+    (const void *)&gInstructions[2141]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp = 
@@ -8670,7 +8670,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ea_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2142]
+    (const void *)&gInstructions[2153]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp = 
@@ -8687,7 +8687,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_da_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2144]
+    (const void *)&gInstructions[2155]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp = 
@@ -8704,7 +8704,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2218]
+    (const void *)&gInstructions[2229]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp = 
@@ -8721,7 +8721,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2220]
+    (const void *)&gInstructions[2231]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp = 
@@ -8738,7 +8738,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2225]
+    (const void *)&gInstructions[2236]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp = 
@@ -8755,7 +8755,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2228]
+    (const void *)&gInstructions[2239]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_f4_01_w = 
@@ -8781,13 +8781,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2235]
+    (const void *)&gInstructions[2246]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2236]
+    (const void *)&gInstructions[2247]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_eb_01_w = 
@@ -8813,13 +8813,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_eb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2239]
+    (const void *)&gInstructions[2250]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2240]
+    (const void *)&gInstructions[2251]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w = 
@@ -8834,13 +8834,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2243]
+    (const void *)&gInstructions[2254]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2244]
+    (const void *)&gInstructions[2255]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w = 
@@ -8855,7 +8855,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_06_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2305]
+    (const void *)&gInstructions[2316]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w = 
@@ -8870,13 +8870,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2324]
+    (const void *)&gInstructions[2335]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2328]
+    (const void *)&gInstructions[2339]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w = 
@@ -8891,7 +8891,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2338]
+    (const void *)&gInstructions[2349]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_02_w = 
@@ -8932,7 +8932,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_72_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2259]
+    (const void *)&gInstructions[2270]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp = 
@@ -8949,7 +8949,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2296]
+    (const void *)&gInstructions[2307]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w = 
@@ -8964,13 +8964,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2298]
+    (const void *)&gInstructions[2309]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2300]
+    (const void *)&gInstructions[2311]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp = 
@@ -8987,7 +8987,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f2_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2306]
+    (const void *)&gInstructions[2317]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_f2_01_w = 
@@ -9013,13 +9013,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2309]
+    (const void *)&gInstructions[2320]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_06_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2311]
+    (const void *)&gInstructions[2322]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w = 
@@ -9034,13 +9034,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2342]
+    (const void *)&gInstructions[2353]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2344]
+    (const void *)&gInstructions[2355]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_73_01_02_w = 
@@ -9081,7 +9081,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_73_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f3_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2312]
+    (const void *)&gInstructions[2323]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_f3_01_w = 
@@ -9107,19 +9107,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f3_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2320]
+    (const void *)&gInstructions[2331]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2334]
+    (const void *)&gInstructions[2345]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2353]
+    (const void *)&gInstructions[2364]
 };
 
 const ND_TABLE_MODRM_REG gEvexTable_root_01_71_01_modrmreg = 
@@ -9151,7 +9151,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_71_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2321]
+    (const void *)&gInstructions[2332]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp = 
@@ -9168,13 +9168,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2325]
+    (const void *)&gInstructions[2336]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2329]
+    (const void *)&gInstructions[2340]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e2_01_w = 
@@ -9200,7 +9200,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2335]
+    (const void *)&gInstructions[2346]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp = 
@@ -9217,7 +9217,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d2_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2339]
+    (const void *)&gInstructions[2350]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d2_01_w = 
@@ -9243,7 +9243,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d3_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2345]
+    (const void *)&gInstructions[2356]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d3_01_w = 
@@ -9269,7 +9269,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d3_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2354]
+    (const void *)&gInstructions[2365]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp = 
@@ -9286,7 +9286,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2357]
+    (const void *)&gInstructions[2368]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp = 
@@ -9303,7 +9303,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2359]
+    (const void *)&gInstructions[2370]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_fa_01_w = 
@@ -9329,7 +9329,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fa_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2361]
+    (const void *)&gInstructions[2372]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_fb_01_w = 
@@ -9355,7 +9355,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2363]
+    (const void *)&gInstructions[2374]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp = 
@@ -9372,7 +9372,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2365]
+    (const void *)&gInstructions[2376]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp = 
@@ -9389,7 +9389,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2367]
+    (const void *)&gInstructions[2378]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp = 
@@ -9406,7 +9406,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2369]
+    (const void *)&gInstructions[2380]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp = 
@@ -9423,7 +9423,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2371]
+    (const void *)&gInstructions[2382]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp = 
@@ -9440,7 +9440,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_68_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2384]
+    (const void *)&gInstructions[2395]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp = 
@@ -9457,7 +9457,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2386]
+    (const void *)&gInstructions[2397]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6a_01_w = 
@@ -9483,7 +9483,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2388]
+    (const void *)&gInstructions[2399]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6d_01_w = 
@@ -9509,7 +9509,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_69_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2390]
+    (const void *)&gInstructions[2401]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp = 
@@ -9526,7 +9526,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_60_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2392]
+    (const void *)&gInstructions[2403]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp = 
@@ -9543,7 +9543,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_62_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2394]
+    (const void *)&gInstructions[2405]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_62_01_w = 
@@ -9569,7 +9569,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_62_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2396]
+    (const void *)&gInstructions[2407]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6c_01_w = 
@@ -9595,7 +9595,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_61_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2398]
+    (const void *)&gInstructions[2409]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp = 
@@ -9612,13 +9612,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2401]
+    (const void *)&gInstructions[2412]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2402]
+    (const void *)&gInstructions[2413]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_ef_01_w = 
@@ -9644,7 +9644,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ef_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2459]
+    (const void *)&gInstructions[2470]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w = 
@@ -9659,7 +9659,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2461]
+    (const void *)&gInstructions[2472]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c6_00_w = 
@@ -9685,7 +9685,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2463]
+    (const void *)&gInstructions[2474]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w = 
@@ -9700,7 +9700,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2465]
+    (const void *)&gInstructions[2476]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w = 
@@ -9715,7 +9715,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2467]
+    (const void *)&gInstructions[2478]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w = 
@@ -9730,7 +9730,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2469]
+    (const void *)&gInstructions[2480]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_02_w = 
@@ -9756,7 +9756,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2472]
+    (const void *)&gInstructions[2483]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w = 
@@ -9771,7 +9771,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2474]
+    (const void *)&gInstructions[2485]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w = 
@@ -9786,7 +9786,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2476]
+    (const void *)&gInstructions[2487]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w = 
@@ -9801,7 +9801,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2478]
+    (const void *)&gInstructions[2489]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_02_w = 
@@ -9827,7 +9827,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2482]
+    (const void *)&gInstructions[2493]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w = 
@@ -9842,7 +9842,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2484]
+    (const void *)&gInstructions[2495]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2e_00_w = 
@@ -9868,7 +9868,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2486]
+    (const void *)&gInstructions[2497]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w = 
@@ -9883,7 +9883,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2488]
+    (const void *)&gInstructions[2499]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_15_00_w = 
@@ -9909,7 +9909,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_15_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2490]
+    (const void *)&gInstructions[2501]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w = 
@@ -9924,7 +9924,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2492]
+    (const void *)&gInstructions[2503]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_14_00_w = 
@@ -9950,7 +9950,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_14_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2494]
+    (const void *)&gInstructions[2505]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w = 
@@ -9965,7 +9965,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2496]
+    (const void *)&gInstructions[2507]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_57_00_w = 
@@ -10254,13 +10254,13 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1361]
+    (const void *)&gInstructions[1372]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1362]
+    (const void *)&gInstructions[1373]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_03_01_w = 
@@ -10286,7 +10286,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_03_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1430]
+    (const void *)&gInstructions[1441]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1d_01_w = 
@@ -10312,7 +10312,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_42_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1476]
+    (const void *)&gInstructions[1487]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_42_01_w = 
@@ -10338,13 +10338,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_42_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1495]
+    (const void *)&gInstructions[1506]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1497]
+    (const void *)&gInstructions[1508]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_19_01_w = 
@@ -10370,13 +10370,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_19_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1496]
+    (const void *)&gInstructions[1507]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1498]
+    (const void *)&gInstructions[1509]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1b_01_02_w = 
@@ -10413,13 +10413,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1500]
+    (const void *)&gInstructions[1511]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1502]
+    (const void *)&gInstructions[1513]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_39_01_w = 
@@ -10445,13 +10445,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_39_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1501]
+    (const void *)&gInstructions[1512]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1503]
+    (const void *)&gInstructions[1514]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3b_01_02_w = 
@@ -10488,7 +10488,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1504]
+    (const void *)&gInstructions[1515]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l = 
@@ -10505,7 +10505,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1505]
+    (const void *)&gInstructions[1516]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_17_01_reg_l = 
@@ -10542,13 +10542,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_17_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1508]
+    (const void *)&gInstructions[1519]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1509]
+    (const void *)&gInstructions[1520]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_54_01_w = 
@@ -10574,13 +10574,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_54_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1510]
+    (const void *)&gInstructions[1521]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1511]
+    (const void *)&gInstructions[1522]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_55_01_w = 
@@ -10606,13 +10606,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_55_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1672]
+    (const void *)&gInstructions[1683]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1673]
+    (const void *)&gInstructions[1684]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_66_01_w = 
@@ -10638,13 +10638,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_66_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1674]
+    (const void *)&gInstructions[1685]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1675]
+    (const void *)&gInstructions[1686]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_67_01_w = 
@@ -10670,13 +10670,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_67_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1700]
+    (const void *)&gInstructions[1711]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1701]
+    (const void *)&gInstructions[1712]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_26_01_w = 
@@ -10702,13 +10702,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_26_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1702]
+    (const void *)&gInstructions[1713]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1703]
+    (const void *)&gInstructions[1714]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_27_01_w = 
@@ -10734,7 +10734,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_27_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_cf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1704]
+    (const void *)&gInstructions[1715]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_cf_01_w = 
@@ -10760,7 +10760,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_cf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_ce_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1706]
+    (const void *)&gInstructions[1717]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_ce_01_w = 
@@ -10786,13 +10786,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_ce_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1715]
+    (const void *)&gInstructions[1726]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1717]
+    (const void *)&gInstructions[1728]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_18_01_w = 
@@ -10818,13 +10818,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_18_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1716]
+    (const void *)&gInstructions[1727]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1718]
+    (const void *)&gInstructions[1729]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1a_01_02_w = 
@@ -10861,13 +10861,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1720]
+    (const void *)&gInstructions[1731]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1722]
+    (const void *)&gInstructions[1733]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_38_01_w = 
@@ -10893,13 +10893,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_38_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1721]
+    (const void *)&gInstructions[1732]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1723]
+    (const void *)&gInstructions[1734]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3a_01_02_w = 
@@ -10936,7 +10936,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1724]
+    (const void *)&gInstructions[1735]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l = 
@@ -10953,7 +10953,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1725]
+    (const void *)&gInstructions[1736]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_21_01_reg_l = 
@@ -10990,7 +10990,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_21_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1916]
+    (const void *)&gInstructions[1927]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp = 
@@ -11007,7 +11007,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_44_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1949]
+    (const void *)&gInstructions[1960]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp = 
@@ -11024,13 +11024,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1953]
+    (const void *)&gInstructions[1964]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1980]
+    (const void *)&gInstructions[1991]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3f_01_w = 
@@ -11056,13 +11056,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1954]
+    (const void *)&gInstructions[1965]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1975]
+    (const void *)&gInstructions[1986]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1f_01_w = 
@@ -11088,13 +11088,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1976]
+    (const void *)&gInstructions[1987]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1979]
+    (const void *)&gInstructions[1990]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3e_01_w = 
@@ -11120,13 +11120,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1977]
+    (const void *)&gInstructions[1988]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1978]
+    (const void *)&gInstructions[1989]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1e_01_w = 
@@ -11152,7 +11152,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_05_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2015]
+    (const void *)&gInstructions[2026]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_05_01_w = 
@@ -11178,7 +11178,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_05_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_04_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2019]
+    (const void *)&gInstructions[2030]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_04_01_w = 
@@ -11204,7 +11204,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_04_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2024]
+    (const void *)&gInstructions[2035]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_01_01_w = 
@@ -11230,7 +11230,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_01_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_00_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2030]
+    (const void *)&gInstructions[2041]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_00_01_w = 
@@ -11256,7 +11256,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_00_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2043]
+    (const void *)&gInstructions[2054]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l = 
@@ -11273,7 +11273,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2044]
+    (const void *)&gInstructions[2055]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_14_01_reg_l = 
@@ -11310,13 +11310,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_14_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2047]
+    (const void *)&gInstructions[2058]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2049]
+    (const void *)&gInstructions[2060]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_16_01_00_w = 
@@ -11353,7 +11353,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_16_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2052]
+    (const void *)&gInstructions[2063]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l = 
@@ -11370,7 +11370,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2053]
+    (const void *)&gInstructions[2064]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_15_01_reg_l = 
@@ -11407,7 +11407,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_15_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2087]
+    (const void *)&gInstructions[2098]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l = 
@@ -11424,7 +11424,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2088]
+    (const void *)&gInstructions[2099]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_20_01_reg_l = 
@@ -11461,13 +11461,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_20_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2091]
+    (const void *)&gInstructions[2102]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2093]
+    (const void *)&gInstructions[2104]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_22_01_00_w = 
@@ -11504,13 +11504,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_22_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2278]
+    (const void *)&gInstructions[2289]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2279]
+    (const void *)&gInstructions[2290]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_71_01_w = 
@@ -11536,7 +11536,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_71_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_70_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2283]
+    (const void *)&gInstructions[2294]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_70_01_w = 
@@ -11562,13 +11562,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_70_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2287]
+    (const void *)&gInstructions[2298]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2288]
+    (const void *)&gInstructions[2299]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_73_01_w = 
@@ -11594,7 +11594,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_73_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_72_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2292]
+    (const void *)&gInstructions[2303]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_72_01_w = 
@@ -11620,13 +11620,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_72_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2373]
+    (const void *)&gInstructions[2384]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2374]
+    (const void *)&gInstructions[2385]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_25_01_w = 
@@ -11652,13 +11652,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_25_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2403]
+    (const void *)&gInstructions[2414]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2404]
+    (const void *)&gInstructions[2415]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_50_01_w = 
@@ -11684,13 +11684,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_50_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2405]
+    (const void *)&gInstructions[2416]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2406]
+    (const void *)&gInstructions[2417]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_51_01_w = 
@@ -11716,13 +11716,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2417]
+    (const void *)&gInstructions[2428]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2418]
+    (const void *)&gInstructions[2429]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_56_01_w = 
@@ -11748,13 +11748,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_56_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2419]
+    (const void *)&gInstructions[2430]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2420]
+    (const void *)&gInstructions[2431]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_57_01_w = 
@@ -11780,7 +11780,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_57_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_09_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2421]
+    (const void *)&gInstructions[2432]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_09_01_w = 
@@ -11806,7 +11806,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_09_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2422]
+    (const void *)&gInstructions[2433]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_08_01_w = 
@@ -11832,7 +11832,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_08_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2423]
+    (const void *)&gInstructions[2434]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_0b_01_w = 
@@ -11858,7 +11858,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2424]
+    (const void *)&gInstructions[2435]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_0a_01_w = 
@@ -11884,13 +11884,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2455]
+    (const void *)&gInstructions[2466]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2456]
+    (const void *)&gInstructions[2467]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_23_01_w = 
@@ -11916,13 +11916,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_23_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2457]
+    (const void *)&gInstructions[2468]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2458]
+    (const void *)&gInstructions[2469]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_43_01_w = 
diff --git a/bddisasm/include/table_root.h b/bddisasm/include/table_root.h
index e2f2a2f..bbbac93 100644
--- a/bddisasm/include/table_root.h
+++ b/bddisasm/include/table_root.h
@@ -76,37 +76,37 @@ const ND_TABLE_INSTRUCTION gRootTable_root_80_00_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_80_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[45]
+    (const void *)&gInstructions[53]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_80_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[144]
+    (const void *)&gInstructions[152]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_80_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[784]
+    (const void *)&gInstructions[795]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_80_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1188]
+    (const void *)&gInstructions[1199]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1286]
+    (const void *)&gInstructions[1297]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2540]
+    (const void *)&gInstructions[2551]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg = 
@@ -139,37 +139,37 @@ const ND_TABLE_INSTRUCTION gRootTable_root_81_00_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_81_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[46]
+    (const void *)&gInstructions[54]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_81_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[145]
+    (const void *)&gInstructions[153]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_81_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[785]
+    (const void *)&gInstructions[796]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_81_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1189]
+    (const void *)&gInstructions[1200]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1287]
+    (const void *)&gInstructions[1298]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2541]
+    (const void *)&gInstructions[2552]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg = 
@@ -202,37 +202,37 @@ const ND_TABLE_INSTRUCTION gRootTable_root_82_00_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_82_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[47]
+    (const void *)&gInstructions[55]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_82_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[146]
+    (const void *)&gInstructions[154]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_82_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[786]
+    (const void *)&gInstructions[797]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_82_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1190]
+    (const void *)&gInstructions[1201]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1288]
+    (const void *)&gInstructions[1299]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2542]
+    (const void *)&gInstructions[2553]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg = 
@@ -265,37 +265,37 @@ const ND_TABLE_INSTRUCTION gRootTable_root_83_00_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_83_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[48]
+    (const void *)&gInstructions[56]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_83_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[147]
+    (const void *)&gInstructions[155]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_83_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[787]
+    (const void *)&gInstructions[798]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_83_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1191]
+    (const void *)&gInstructions[1202]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1289]
+    (const void *)&gInstructions[1300]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2543]
+    (const void *)&gInstructions[2554]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg = 
@@ -328,13 +328,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_F3_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2508]
+    (const void *)&gInstructions[2519]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2509]
+    (const void *)&gInstructions[2520]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary = 
@@ -393,80 +393,306 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f6_modrmmod =
     }
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_de_66_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_de_mem_66_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[32]
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_de_mem_F3_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[40]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_de_mem_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_de_mem_66_leaf,
+        /* 02 */ (const void *)&gRootTable_root_0f_38_de_mem_F3_leaf,
+        /* 03 */ NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_de_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[32]
 };
 
-const ND_TABLE_MPREFIX gRootTable_root_0f_38_de_mprefix = 
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_de_reg_mprefix = 
 {
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gRootTable_root_0f_38_de_66_leaf,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_de_reg_66_leaf,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_df_66_leaf = 
+const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_de_modrmmod = 
+{
+    ND_ILUT_MODRM_MOD,
+    { 
+        /* 00 */ (const void *)&gRootTable_root_0f_38_de_mem_mprefix,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_de_reg_mprefix,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dd_mem_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[33]
 };
 
-const ND_TABLE_MPREFIX gRootTable_root_0f_38_df_mprefix = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dd_mem_66_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[41]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_dd_mem_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_dd_mem_66_leaf,
+        /* 02 */ (const void *)&gRootTable_root_0f_38_dd_mem_F3_leaf,
+        /* 03 */ NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dd_reg_66_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[41]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_dd_reg_mprefix = 
 {
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gRootTable_root_0f_38_df_66_leaf,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_dd_reg_66_leaf,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_66_leaf = 
+const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_dd_modrmmod = 
+{
+    ND_ILUT_MODRM_MOD,
+    { 
+        /* 00 */ (const void *)&gRootTable_root_0f_38_dd_mem_mprefix,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_dd_reg_mprefix,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_df_mem_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[34]
 };
 
-const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_mprefix = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_df_mem_66_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[35]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_df_mem_mprefix = 
 {
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gRootTable_root_0f_38_dc_66_leaf,
-        /* 02 */ NULL,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_df_mem_66_leaf,
+        /* 02 */ (const void *)&gRootTable_root_0f_38_df_mem_F3_leaf,
         /* 03 */ NULL,
     }
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dd_66_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_df_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[35]
 };
 
-const ND_TABLE_MPREFIX gRootTable_root_0f_38_dd_mprefix = 
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_df_reg_mprefix = 
 {
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gRootTable_root_0f_38_dd_66_leaf,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_df_reg_66_leaf,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_db_66_leaf = 
+const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_df_modrmmod = 
+{
+    ND_ILUT_MODRM_MOD,
+    { 
+        /* 00 */ (const void *)&gRootTable_root_0f_38_df_mem_mprefix,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_df_reg_mprefix,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_d8_mem_01_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[36]
 };
 
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_01_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ NULL,
+        /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_01_F3_leaf,
+        /* 03 */ NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_d8_mem_03_F3_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[37]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_03_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ NULL,
+        /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_03_F3_leaf,
+        /* 03 */ NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_d8_mem_00_F3_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[42]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_00_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ NULL,
+        /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_00_F3_leaf,
+        /* 03 */ NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_d8_mem_02_F3_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[43]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_02_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ NULL,
+        /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_02_F3_leaf,
+        /* 03 */ NULL,
+    }
+};
+
+const ND_TABLE_MODRM_REG gRootTable_root_0f_38_d8_mem_modrmreg = 
+{
+    ND_ILUT_MODRM_REG,
+    { 
+        /* 00 */ (const void *)&gRootTable_root_0f_38_d8_mem_00_mprefix,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_d8_mem_01_mprefix,
+        /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_02_mprefix,
+        /* 03 */ (const void *)&gRootTable_root_0f_38_d8_mem_03_mprefix,
+        /* 04 */ NULL,
+        /* 05 */ NULL,
+        /* 06 */ NULL,
+        /* 07 */ NULL,
+    }
+};
+
+const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_d8_modrmmod = 
+{
+    ND_ILUT_MODRM_MOD,
+    { 
+        /* 00 */ (const void *)&gRootTable_root_0f_38_d8_mem_modrmreg,
+        /* 01 */ NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_mem_66_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[38]
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_mem_F3_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[39]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_mem_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_dc_mem_66_leaf,
+        /* 02 */ (const void *)&gRootTable_root_0f_38_dc_mem_F3_leaf,
+        /* 03 */ NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_reg_66_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[38]
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_reg_F3_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[579]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_reg_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_dc_reg_66_leaf,
+        /* 02 */ (const void *)&gRootTable_root_0f_38_dc_reg_F3_leaf,
+        /* 03 */ NULL,
+    }
+};
+
+const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_dc_modrmmod = 
+{
+    ND_ILUT_MODRM_MOD,
+    { 
+        /* 00 */ (const void *)&gRootTable_root_0f_38_dc_mem_mprefix,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_dc_reg_mprefix,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_db_66_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[44]
+};
+
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_db_mprefix = 
 {
     ND_ILUT_MAN_PREFIX,
@@ -481,7 +707,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_db_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_15_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[64]
+    (const void *)&gInstructions[72]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_15_mprefix = 
@@ -498,7 +724,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_15_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_14_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[65]
+    (const void *)&gInstructions[73]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_14_mprefix = 
@@ -515,13 +741,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_14_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_F2_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[170]
+    (const void *)&gInstructions[178]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_F2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[171]
+    (const void *)&gInstructions[179]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_F2_mprefix = 
@@ -538,13 +764,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_F2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[642]
+    (const void *)&gInstructions[653]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[643]
+    (const void *)&gInstructions[654]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_mprefix = 
@@ -561,13 +787,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_reg_F2_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[170]
+    (const void *)&gInstructions[178]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_reg_F2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[171]
+    (const void *)&gInstructions[179]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_reg_F2_mprefix = 
@@ -604,13 +830,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f0_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_F2_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[172]
+    (const void *)&gInstructions[180]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_F2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[173]
+    (const void *)&gInstructions[181]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_F2_mprefix = 
@@ -627,13 +853,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_F2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[644]
+    (const void *)&gInstructions[655]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[645]
+    (const void *)&gInstructions[656]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_mprefix = 
@@ -650,13 +876,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_reg_F2_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[172]
+    (const void *)&gInstructions[180]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_reg_F2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[173]
+    (const void *)&gInstructions[181]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_reg_F2_mprefix = 
@@ -690,22 +916,74 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f1_modrmmod =
     }
 };
 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fa_reg_F3_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[232]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_fa_reg_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ NULL,
+        /* 02 */ (const void *)&gRootTable_root_0f_38_fa_reg_F3_leaf,
+        /* 03 */ NULL,
+    }
+};
+
+const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_fa_modrmmod = 
+{
+    ND_ILUT_MODRM_MOD,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_fa_reg_mprefix,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fb_reg_F3_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[233]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_38_fb_reg_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ NULL,
+        /* 02 */ (const void *)&gRootTable_root_0f_38_fb_reg_F3_leaf,
+        /* 03 */ NULL,
+    }
+};
+
+const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_fb_modrmmod = 
+{
+    ND_ILUT_MODRM_MOD,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ (const void *)&gRootTable_root_0f_38_fb_reg_mprefix,
+    }
+};
+
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[226]
+    (const void *)&gInstructions[236]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[227]
+    (const void *)&gInstructions[237]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[651]
+    (const void *)&gInstructions[662]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_f8_mem_mprefix = 
@@ -731,7 +1009,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f8_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cf_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[387]
+    (const void *)&gInstructions[397]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix = 
@@ -748,7 +1026,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_80_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[431]
+    (const void *)&gInstructions[441]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_80_mem_mprefix = 
@@ -774,7 +1052,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_80_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_82_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[435]
+    (const void *)&gInstructions[445]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_82_mem_mprefix = 
@@ -800,7 +1078,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_82_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_81_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[436]
+    (const void *)&gInstructions[446]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_81_mem_mprefix = 
@@ -826,7 +1104,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_81_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f9_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[652]
+    (const void *)&gInstructions[663]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_f9_mem_mprefix = 
@@ -852,7 +1130,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f9_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_2a_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[670]
+    (const void *)&gInstructions[681]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_2a_mem_mprefix = 
@@ -878,13 +1156,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_2a_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1c_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[800]
+    (const void *)&gInstructions[811]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[801]
+    (const void *)&gInstructions[812]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_1c_mprefix = 
@@ -901,13 +1179,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1e_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[802]
+    (const void *)&gInstructions[813]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1e_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[803]
+    (const void *)&gInstructions[814]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_1e_mprefix = 
@@ -924,13 +1202,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1d_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[804]
+    (const void *)&gInstructions[815]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[805]
+    (const void *)&gInstructions[816]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_1d_mprefix = 
@@ -947,7 +1225,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_1d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_2b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[810]
+    (const void *)&gInstructions[821]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_2b_mprefix = 
@@ -964,7 +1242,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_2b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_10_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[841]
+    (const void *)&gInstructions[852]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_10_mprefix = 
@@ -981,7 +1259,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_10_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_29_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[848]
+    (const void *)&gInstructions[859]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix = 
@@ -998,7 +1276,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_37_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[857]
+    (const void *)&gInstructions[868]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix = 
@@ -1015,13 +1293,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[895]
+    (const void *)&gInstructions[906]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[896]
+    (const void *)&gInstructions[907]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix = 
@@ -1038,13 +1316,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[897]
+    (const void *)&gInstructions[908]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[898]
+    (const void *)&gInstructions[909]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix = 
@@ -1061,13 +1339,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[899]
+    (const void *)&gInstructions[910]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[900]
+    (const void *)&gInstructions[911]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix = 
@@ -1084,7 +1362,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_41_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[901]
+    (const void *)&gInstructions[912]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix = 
@@ -1101,13 +1379,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[902]
+    (const void *)&gInstructions[913]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[903]
+    (const void *)&gInstructions[914]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix = 
@@ -1124,13 +1402,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[904]
+    (const void *)&gInstructions[915]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[905]
+    (const void *)&gInstructions[916]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix = 
@@ -1147,13 +1425,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[906]
+    (const void *)&gInstructions[917]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[907]
+    (const void *)&gInstructions[918]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix = 
@@ -1170,13 +1448,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[918]
+    (const void *)&gInstructions[929]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[919]
+    (const void *)&gInstructions[930]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix = 
@@ -1193,7 +1471,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[922]
+    (const void *)&gInstructions[933]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix = 
@@ -1210,7 +1488,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[923]
+    (const void *)&gInstructions[934]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix = 
@@ -1227,7 +1505,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3f_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[928]
+    (const void *)&gInstructions[939]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix = 
@@ -1244,7 +1522,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3e_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[929]
+    (const void *)&gInstructions[940]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix = 
@@ -1261,7 +1539,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_38_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[930]
+    (const void *)&gInstructions[941]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix = 
@@ -1278,7 +1556,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_39_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[931]
+    (const void *)&gInstructions[942]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix = 
@@ -1295,7 +1573,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[936]
+    (const void *)&gInstructions[947]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix = 
@@ -1312,7 +1590,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[937]
+    (const void *)&gInstructions[948]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix = 
@@ -1329,7 +1607,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_21_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[940]
+    (const void *)&gInstructions[951]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix = 
@@ -1346,7 +1624,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_22_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[941]
+    (const void *)&gInstructions[952]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix = 
@@ -1363,7 +1641,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_20_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[942]
+    (const void *)&gInstructions[953]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix = 
@@ -1380,7 +1658,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_25_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[943]
+    (const void *)&gInstructions[954]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix = 
@@ -1397,7 +1675,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_23_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[944]
+    (const void *)&gInstructions[955]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix = 
@@ -1414,7 +1692,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_24_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[945]
+    (const void *)&gInstructions[956]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix = 
@@ -1431,7 +1709,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_31_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[946]
+    (const void *)&gInstructions[957]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix = 
@@ -1448,7 +1726,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_32_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[947]
+    (const void *)&gInstructions[958]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix = 
@@ -1465,7 +1743,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_30_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[948]
+    (const void *)&gInstructions[959]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix = 
@@ -1482,7 +1760,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_35_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[949]
+    (const void *)&gInstructions[960]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix = 
@@ -1499,7 +1777,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_33_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[950]
+    (const void *)&gInstructions[961]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix = 
@@ -1516,7 +1794,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_34_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[951]
+    (const void *)&gInstructions[962]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix = 
@@ -1533,7 +1811,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_28_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[952]
+    (const void *)&gInstructions[963]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix = 
@@ -1550,13 +1828,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[953]
+    (const void *)&gInstructions[964]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[954]
+    (const void *)&gInstructions[965]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix = 
@@ -1573,7 +1851,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_40_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[960]
+    (const void *)&gInstructions[971]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix = 
@@ -1590,13 +1868,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1001]
+    (const void *)&gInstructions[1012]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1002]
+    (const void *)&gInstructions[1013]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix = 
@@ -1613,13 +1891,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1007]
+    (const void *)&gInstructions[1018]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1008]
+    (const void *)&gInstructions[1019]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix = 
@@ -1636,13 +1914,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1009]
+    (const void *)&gInstructions[1020]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1010]
+    (const void *)&gInstructions[1021]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix = 
@@ -1659,13 +1937,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1011]
+    (const void *)&gInstructions[1022]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1012]
+    (const void *)&gInstructions[1023]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix = 
@@ -1682,7 +1960,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_17_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1065]
+    (const void *)&gInstructions[1076]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix = 
@@ -1699,7 +1977,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1223]
+    (const void *)&gInstructions[1234]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix = 
@@ -1716,7 +1994,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_ca_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1224]
+    (const void *)&gInstructions[1235]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix = 
@@ -1733,7 +2011,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1225]
+    (const void *)&gInstructions[1236]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix = 
@@ -1750,7 +2028,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cc_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1227]
+    (const void *)&gInstructions[1238]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix = 
@@ -1767,7 +2045,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cd_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1228]
+    (const void *)&gInstructions[1239]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix = 
@@ -1784,7 +2062,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cb_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1229]
+    (const void *)&gInstructions[1240]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix = 
@@ -1801,13 +2079,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2510]
+    (const void *)&gInstructions[2521]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2511]
+    (const void *)&gInstructions[2522]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary = 
@@ -2063,14 +2341,14 @@ const ND_TABLE_OPCODE gRootTable_root_0f_38_opcode =
         /* d5 */ NULL,
         /* d6 */ NULL,
         /* d7 */ NULL,
-        /* d8 */ NULL,
+        /* d8 */ (const void *)&gRootTable_root_0f_38_d8_modrmmod,
         /* d9 */ NULL,
         /* da */ NULL,
         /* db */ (const void *)&gRootTable_root_0f_38_db_mprefix,
-        /* dc */ (const void *)&gRootTable_root_0f_38_dc_mprefix,
-        /* dd */ (const void *)&gRootTable_root_0f_38_dd_mprefix,
-        /* de */ (const void *)&gRootTable_root_0f_38_de_mprefix,
-        /* df */ (const void *)&gRootTable_root_0f_38_df_mprefix,
+        /* dc */ (const void *)&gRootTable_root_0f_38_dc_modrmmod,
+        /* dd */ (const void *)&gRootTable_root_0f_38_dd_modrmmod,
+        /* de */ (const void *)&gRootTable_root_0f_38_de_modrmmod,
+        /* df */ (const void *)&gRootTable_root_0f_38_df_modrmmod,
         /* e0 */ NULL,
         /* e1 */ NULL,
         /* e2 */ NULL,
@@ -2097,8 +2375,8 @@ const ND_TABLE_OPCODE gRootTable_root_0f_38_opcode =
         /* f7 */ NULL,
         /* f8 */ (const void *)&gRootTable_root_0f_38_f8_modrmmod,
         /* f9 */ (const void *)&gRootTable_root_0f_38_f9_modrmmod,
-        /* fa */ NULL,
-        /* fb */ NULL,
+        /* fa */ (const void *)&gRootTable_root_0f_38_fa_modrmmod,
+        /* fb */ (const void *)&gRootTable_root_0f_38_fb_modrmmod,
         /* fc */ NULL,
         /* fd */ NULL,
         /* fe */ NULL,
@@ -2167,7 +2445,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d0_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_df_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[37]
+    (const void *)&gInstructions[45]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_df_mprefix = 
@@ -2184,7 +2462,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_df_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[62]
+    (const void *)&gInstructions[70]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0d_mprefix = 
@@ -2201,7 +2479,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[63]
+    (const void *)&gInstructions[71]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0c_mprefix = 
@@ -2218,7 +2496,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_41_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[218]
+    (const void *)&gInstructions[226]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_41_mprefix = 
@@ -2235,7 +2513,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_41_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_40_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[219]
+    (const void *)&gInstructions[227]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_40_mprefix = 
@@ -2252,7 +2530,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_40_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_17_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[229]
+    (const void *)&gInstructions[239]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_17_mprefix = 
@@ -2269,7 +2547,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_17_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cf_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[385]
+    (const void *)&gInstructions[395]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix = 
@@ -2286,7 +2564,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_ce_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[386]
+    (const void *)&gInstructions[396]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix = 
@@ -2303,7 +2581,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[420]
+    (const void *)&gInstructions[430]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix = 
@@ -2320,7 +2598,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[421]
+    (const void *)&gInstructions[431]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_reg_mprefix = 
@@ -2346,7 +2624,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_21_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_42_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[709]
+    (const void *)&gInstructions[720]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_42_mprefix = 
@@ -2363,13 +2641,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_42_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0f_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[829]
+    (const void *)&gInstructions[840]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0f_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[830]
+    (const void *)&gInstructions[841]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0f_mprefix = 
@@ -2386,7 +2664,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0e_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[842]
+    (const void *)&gInstructions[853]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0e_mprefix = 
@@ -2403,7 +2681,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_44_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[843]
+    (const void *)&gInstructions[854]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix = 
@@ -2420,7 +2698,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_61_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[851]
+    (const void *)&gInstructions[862]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix = 
@@ -2437,7 +2715,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_60_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[852]
+    (const void *)&gInstructions[863]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix = 
@@ -2454,7 +2732,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_63_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[860]
+    (const void *)&gInstructions[871]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix = 
@@ -2471,7 +2749,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_62_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[861]
+    (const void *)&gInstructions[872]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix = 
@@ -2488,7 +2766,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[866]
+    (const void *)&gInstructions[877]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix = 
@@ -2505,7 +2783,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[867]
+    (const void *)&gInstructions[878]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_reg_mprefix = 
@@ -2531,13 +2809,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_14_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[868]
+    (const void *)&gInstructions[879]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[869]
+    (const void *)&gInstructions[880]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_16_66_auxiliary = 
@@ -2567,7 +2845,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_16_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[872]
+    (const void *)&gInstructions[883]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix = 
@@ -2584,7 +2862,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[873]
+    (const void *)&gInstructions[884]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_reg_mprefix = 
@@ -2610,7 +2888,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_15_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[910]
+    (const void *)&gInstructions[921]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix = 
@@ -2627,7 +2905,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[911]
+    (const void *)&gInstructions[922]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_reg_mprefix = 
@@ -2653,13 +2931,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_20_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[912]
+    (const void *)&gInstructions[923]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[913]
+    (const void *)&gInstructions[924]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_22_66_auxiliary = 
@@ -2689,7 +2967,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_22_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_09_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1155]
+    (const void *)&gInstructions[1166]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix = 
@@ -2706,7 +2984,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_08_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1156]
+    (const void *)&gInstructions[1167]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix = 
@@ -2723,7 +3001,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1157]
+    (const void *)&gInstructions[1168]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix = 
@@ -2740,7 +3018,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1158]
+    (const void *)&gInstructions[1169]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix = 
@@ -2757,7 +3035,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cc_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1226]
+    (const void *)&gInstructions[1237]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cc_mprefix = 
@@ -3037,19 +3315,19 @@ const ND_TABLE_OPCODE gRootTable_root_0f_3a_opcode =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[38]
+    (const void *)&gInstructions[46]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_55_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[50]
+    (const void *)&gInstructions[58]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_55_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[51]
+    (const void *)&gInstructions[59]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_55_mprefix = 
@@ -3066,13 +3344,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_55_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_54_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[52]
+    (const void *)&gInstructions[60]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_54_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[53]
+    (const void *)&gInstructions[61]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_54_mprefix = 
@@ -3089,25 +3367,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_54_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_mem_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[71]
+    (const void *)&gInstructions[79]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_mem_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[73]
+    (const void *)&gInstructions[81]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_mem_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[74]
+    (const void *)&gInstructions[82]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[76]
+    (const void *)&gInstructions[84]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_1a_mpx_mem_mprefix = 
@@ -3124,25 +3402,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_1a_mpx_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[71]
+    (const void *)&gInstructions[79]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[73]
+    (const void *)&gInstructions[81]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[76]
+    (const void *)&gInstructions[84]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[744]
+    (const void *)&gInstructions[755]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_1a_mpx_reg_mprefix = 
@@ -3168,7 +3446,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1a_mpx_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[738]
+    (const void *)&gInstructions[749]
 };
 
 const ND_TABLE_FEATURE gRootTable_root_0f_1a_feature = 
@@ -3185,25 +3463,25 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1a_feature =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_mem_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[72]
+    (const void *)&gInstructions[80]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_mem_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[75]
+    (const void *)&gInstructions[83]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[77]
+    (const void *)&gInstructions[85]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_mem_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[78]
+    (const void *)&gInstructions[86]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_1b_mpx_mem_mprefix = 
@@ -3220,25 +3498,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_1b_mpx_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[72]
+    (const void *)&gInstructions[80]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[77]
+    (const void *)&gInstructions[85]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[745]
+    (const void *)&gInstructions[756]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[746]
+    (const void *)&gInstructions[757]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_1b_mpx_reg_mprefix = 
@@ -3264,7 +3542,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1b_mpx_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[739]
+    (const void *)&gInstructions[750]
 };
 
 const ND_TABLE_FEATURE gRootTable_root_0f_1b_feature = 
@@ -3281,13 +3559,13 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1b_feature =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[80]
+    (const void *)&gInstructions[88]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1324]
+    (const void *)&gInstructions[1335]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary = 
@@ -3306,13 +3584,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_bd_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[81]
+    (const void *)&gInstructions[89]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_bd_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[586]
+    (const void *)&gInstructions[597]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_bd_auxiliary = 
@@ -3331,79 +3609,79 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_bd_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[82]
+    (const void *)&gInstructions[90]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[83]
+    (const void *)&gInstructions[91]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ca_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[84]
+    (const void *)&gInstructions[92]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_cb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[85]
+    (const void *)&gInstructions[93]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_cc_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[86]
+    (const void *)&gInstructions[94]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_cd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[87]
+    (const void *)&gInstructions[95]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ce_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[88]
+    (const void *)&gInstructions[96]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_cf_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[89]
+    (const void *)&gInstructions[97]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[90]
+    (const void *)&gInstructions[98]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[91]
+    (const void *)&gInstructions[99]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[92]
+    (const void *)&gInstructions[100]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[95]
+    (const void *)&gInstructions[103]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[97]
+    (const void *)&gInstructions[105]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_ba_modrmreg = 
@@ -3424,31 +3702,31 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_ba_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_bb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[93]
+    (const void *)&gInstructions[101]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[94]
+    (const void *)&gInstructions[102]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ab_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[96]
+    (const void *)&gInstructions[104]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[106]
+    (const void *)&gInstructions[114]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[107]
+    (const void *)&gInstructions[115]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_02_mprefix = 
@@ -3465,13 +3743,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[221]
+    (const void *)&gInstructions[229]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1200]
+    (const void *)&gInstructions[1211]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix = 
@@ -3488,7 +3766,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[599]
+    (const void *)&gInstructions[610]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_00_mprefix = 
@@ -3505,7 +3783,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_01_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[717]
+    (const void *)&gInstructions[728]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix = 
@@ -3522,7 +3800,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1201]
+    (const void *)&gInstructions[1212]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix = 
@@ -3539,7 +3817,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_05_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1202]
+    (const void *)&gInstructions[1213]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix = 
@@ -3556,7 +3834,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1263]
+    (const void *)&gInstructions[1274]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix = 
@@ -3573,7 +3851,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1303]
+    (const void *)&gInstructions[1314]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_04_mprefix = 
@@ -3605,49 +3883,49 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_01_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[115]
+    (const void *)&gInstructions[123]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[433]
+    (const void *)&gInstructions[443]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1251]
+    (const void *)&gInstructions[1262]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1266]
+    (const void *)&gInstructions[1277]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1746]
+    (const void *)&gInstructions[1757]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1747]
+    (const void *)&gInstructions[1758]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1758]
+    (const void *)&gInstructions[1769]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1759]
+    (const void *)&gInstructions[1770]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix = 
@@ -3664,19 +3942,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1757]
+    (const void *)&gInstructions[1768]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1864]
+    (const void *)&gInstructions[1875]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1865]
+    (const void *)&gInstructions[1876]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm = 
@@ -3697,25 +3975,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[120]
+    (const void *)&gInstructions[128]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[434]
+    (const void *)&gInstructions[444]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1140]
+    (const void *)&gInstructions[1151]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1141]
+    (const void *)&gInstructions[1152]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix = 
@@ -3732,13 +4010,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[593]
+    (const void *)&gInstructions[604]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[600]
+    (const void *)&gInstructions[611]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_02_mprefix = 
@@ -3755,7 +4033,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[718]
+    (const void *)&gInstructions[729]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix = 
@@ -3772,19 +4050,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1026]
+    (const void *)&gInstructions[1037]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1103]
+    (const void *)&gInstructions[1114]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1322]
+    (const void *)&gInstructions[1333]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix = 
@@ -3801,19 +4079,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1126]
+    (const void *)&gInstructions[1137]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1135]
+    (const void *)&gInstructions[1146]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1297]
+    (const void *)&gInstructions[1308]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm = 
@@ -3834,7 +4112,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[222]
+    (const void *)&gInstructions[230]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix = 
@@ -3851,7 +4129,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1745]
+    (const void *)&gInstructions[1756]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix = 
@@ -3868,7 +4146,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2531]
+    (const void *)&gInstructions[2542]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix = 
@@ -3885,7 +4163,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2532]
+    (const void *)&gInstructions[2543]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix = 
@@ -3902,7 +4180,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2559]
+    (const void *)&gInstructions[2570]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix = 
@@ -3919,7 +4197,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2564]
+    (const void *)&gInstructions[2575]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix = 
@@ -3951,7 +4229,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_02_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[223]
+    (const void *)&gInstructions[231]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_00_mprefix = 
@@ -3968,7 +4246,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[863]
+    (const void *)&gInstructions[874]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix = 
@@ -3985,25 +4263,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1743]
+    (const void *)&gInstructions[1754]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1756]
+    (const void *)&gInstructions[1767]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1863]
+    (const void *)&gInstructions[1874]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1875]
+    (const void *)&gInstructions[1886]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm = 
@@ -4024,13 +4302,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[568]
+    (const void *)&gInstructions[578]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1124]
+    (const void *)&gInstructions[1135]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix = 
@@ -4047,7 +4325,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_02_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1181]
+    (const void *)&gInstructions[1192]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix = 
@@ -4064,19 +4342,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1203]
+    (const void *)&gInstructions[1214]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1219]
+    (const void *)&gInstructions[1230]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2563]
+    (const void *)&gInstructions[2574]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix = 
@@ -4093,7 +4371,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2506]
+    (const void *)&gInstructions[2517]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix = 
@@ -4110,7 +4388,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2546]
+    (const void *)&gInstructions[2557]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix = 
@@ -4142,7 +4420,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_05_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1257]
+    (const void *)&gInstructions[1268]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg = 
@@ -4163,31 +4441,31 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[432]
+    (const void *)&gInstructions[442]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[563]
+    (const void *)&gInstructions[573]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[565]
+    (const void *)&gInstructions[575]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[568]
+    (const void *)&gInstructions[578]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_05_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1164]
+    (const void *)&gInstructions[1175]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix = 
@@ -4204,19 +4482,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1222]
+    (const void *)&gInstructions[1233]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1250]
+    (const void *)&gInstructions[1261]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1256]
+    (const void *)&gInstructions[1267]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_01_mem_modrmreg = 
@@ -4246,25 +4524,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_01_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[110]
+    (const void *)&gInstructions[118]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[747]
+    (const void *)&gInstructions[758]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[748]
+    (const void *)&gInstructions[759]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[749]
+    (const void *)&gInstructions[760]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_1c_cldm_mem_00_mprefix = 
@@ -4281,43 +4559,43 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_1c_cldm_mem_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[751]
+    (const void *)&gInstructions[762]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[752]
+    (const void *)&gInstructions[763]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[753]
+    (const void *)&gInstructions[764]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[754]
+    (const void *)&gInstructions[765]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[755]
+    (const void *)&gInstructions[766]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[756]
+    (const void *)&gInstructions[767]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[757]
+    (const void *)&gInstructions[768]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_mem_modrmreg = 
@@ -4338,49 +4616,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[750]
+    (const void *)&gInstructions[761]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[751]
+    (const void *)&gInstructions[762]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[752]
+    (const void *)&gInstructions[763]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[753]
+    (const void *)&gInstructions[764]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[754]
+    (const void *)&gInstructions[765]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[755]
+    (const void *)&gInstructions[766]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[756]
+    (const void *)&gInstructions[767]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[757]
+    (const void *)&gInstructions[768]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_reg_modrmreg = 
@@ -4410,7 +4688,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1c_cldm_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[740]
+    (const void *)&gInstructions[751]
 };
 
 const ND_TABLE_FEATURE gRootTable_root_0f_1c_feature = 
@@ -4427,13 +4705,13 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1c_feature =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[113]
+    (const void *)&gInstructions[121]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[114]
+    (const void *)&gInstructions[122]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_07_mprefix = 
@@ -4450,25 +4728,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[117]
+    (const void *)&gInstructions[125]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[119]
+    (const void *)&gInstructions[127]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2555]
+    (const void *)&gInstructions[2566]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2556]
+    (const void *)&gInstructions[2567]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary = 
@@ -4498,13 +4776,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[377]
+    (const void *)&gInstructions[387]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[378]
+    (const void *)&gInstructions[388]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_01_NP_auxiliary = 
@@ -4534,13 +4812,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[379]
+    (const void *)&gInstructions[389]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[380]
+    (const void *)&gInstructions[390]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_00_NP_auxiliary = 
@@ -4570,7 +4848,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[555]
+    (const void *)&gInstructions[565]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix = 
@@ -4587,19 +4865,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1066]
+    (const void *)&gInstructions[1077]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2551]
+    (const void *)&gInstructions[2562]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2552]
+    (const void *)&gInstructions[2563]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary = 
@@ -4629,7 +4907,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1268]
+    (const void *)&gInstructions[1279]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix = 
@@ -4646,13 +4924,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2547]
+    (const void *)&gInstructions[2558]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2548]
+    (const void *)&gInstructions[2559]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary = 
@@ -4697,13 +4975,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_ae_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[414]
+    (const void *)&gInstructions[424]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[415]
+    (const void *)&gInstructions[425]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary = 
@@ -4722,7 +5000,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[561]
+    (const void *)&gInstructions[571]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_05_mprefix = 
@@ -4739,25 +5017,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[594]
+    (const void *)&gInstructions[605]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1323]
+    (const void *)&gInstructions[1334]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1331]
+    (const void *)&gInstructions[1342]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1332]
+    (const void *)&gInstructions[1343]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix = 
@@ -4774,13 +5052,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[862]
+    (const void *)&gInstructions[873]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1221]
+    (const void *)&gInstructions[1232]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix = 
@@ -4797,7 +5075,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_04_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1066]
+    (const void *)&gInstructions[1077]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix = 
@@ -4814,7 +5092,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_00_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1120]
+    (const void *)&gInstructions[1131]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_00_F3_auxiliary = 
@@ -4844,7 +5122,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_01_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1121]
+    (const void *)&gInstructions[1132]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_01_F3_auxiliary = 
@@ -4874,7 +5152,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_02_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2503]
+    (const void *)&gInstructions[2514]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary = 
@@ -4904,7 +5182,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_03_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2504]
+    (const void *)&gInstructions[2515]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary = 
@@ -4958,127 +5236,127 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_ae_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[118]
+    (const void *)&gInstructions[126]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_46_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[122]
+    (const void *)&gInstructions[130]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_42_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[123]
+    (const void *)&gInstructions[131]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_4c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[124]
+    (const void *)&gInstructions[132]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_4e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[125]
+    (const void *)&gInstructions[133]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_47_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[126]
+    (const void *)&gInstructions[134]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_43_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[127]
+    (const void *)&gInstructions[135]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_4d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[128]
+    (const void *)&gInstructions[136]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_4f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[129]
+    (const void *)&gInstructions[137]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_41_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[130]
+    (const void *)&gInstructions[138]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_4b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[131]
+    (const void *)&gInstructions[139]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_49_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[132]
+    (const void *)&gInstructions[140]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_45_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[133]
+    (const void *)&gInstructions[141]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_40_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[134]
+    (const void *)&gInstructions[142]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_4a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[135]
+    (const void *)&gInstructions[143]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_48_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[136]
+    (const void *)&gInstructions[144]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_44_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[137]
+    (const void *)&gInstructions[145]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[148]
+    (const void *)&gInstructions[156]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[149]
+    (const void *)&gInstructions[157]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[152]
+    (const void *)&gInstructions[160]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[157]
+    (const void *)&gInstructions[165]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c2_mprefix = 
@@ -5095,25 +5373,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[160]
+    (const void *)&gInstructions[168]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[161]
+    (const void *)&gInstructions[169]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_01_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[162]
+    (const void *)&gInstructions[170]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_01_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[163]
+    (const void *)&gInstructions[171]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary = 
@@ -5132,19 +5410,19 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1744]
+    (const void *)&gInstructions[1755]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1860]
+    (const void *)&gInstructions[1871]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1876]
+    (const void *)&gInstructions[1887]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix = 
@@ -5161,7 +5439,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1861]
+    (const void *)&gInstructions[1872]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix = 
@@ -5178,13 +5456,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2549]
+    (const void *)&gInstructions[2560]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2550]
+    (const void *)&gInstructions[2561]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary = 
@@ -5214,13 +5492,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2553]
+    (const void *)&gInstructions[2564]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2554]
+    (const void *)&gInstructions[2565]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary = 
@@ -5250,13 +5528,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2557]
+    (const void *)&gInstructions[2568]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2558]
+    (const void *)&gInstructions[2569]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary = 
@@ -5301,19 +5579,19 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_c7_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1123]
+    (const void *)&gInstructions[1134]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1129]
+    (const void *)&gInstructions[1140]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1130]
+    (const void *)&gInstructions[1141]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix = 
@@ -5330,13 +5608,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1127]
+    (const void *)&gInstructions[1138]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1128]
+    (const void *)&gInstructions[1139]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_06_mprefix = 
@@ -5377,13 +5655,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2f_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[164]
+    (const void *)&gInstructions[172]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2f_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[165]
+    (const void *)&gInstructions[173]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_2f_mprefix = 
@@ -5400,37 +5678,37 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[166]
+    (const void *)&gInstructions[174]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[167]
+    (const void *)&gInstructions[175]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[168]
+    (const void *)&gInstructions[176]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[174]
+    (const void *)&gInstructions[182]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[176]
+    (const void *)&gInstructions[184]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[190]
+    (const void *)&gInstructions[198]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e6_mprefix = 
@@ -5447,19 +5725,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e6_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[175]
+    (const void *)&gInstructions[183]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[181]
+    (const void *)&gInstructions[189]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[192]
+    (const void *)&gInstructions[200]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_5b_mprefix = 
@@ -5476,25 +5754,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[177]
+    (const void *)&gInstructions[185]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[183]
+    (const void *)&gInstructions[191]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[184]
+    (const void *)&gInstructions[192]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[189]
+    (const void *)&gInstructions[197]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_2d_mprefix = 
@@ -5511,25 +5789,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[178]
+    (const void *)&gInstructions[186]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[182]
+    (const void *)&gInstructions[190]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[185]
+    (const void *)&gInstructions[193]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[188]
+    (const void *)&gInstructions[196]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_5a_mprefix = 
@@ -5546,25 +5824,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[179]
+    (const void *)&gInstructions[187]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[180]
+    (const void *)&gInstructions[188]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[186]
+    (const void *)&gInstructions[194]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[187]
+    (const void *)&gInstructions[195]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_2a_mprefix = 
@@ -5581,25 +5859,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[191]
+    (const void *)&gInstructions[199]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[193]
+    (const void *)&gInstructions[201]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[194]
+    (const void *)&gInstructions[202]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[195]
+    (const void *)&gInstructions[203]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_2c_mprefix = 
@@ -5616,25 +5894,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[213]
+    (const void *)&gInstructions[221]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[214]
+    (const void *)&gInstructions[222]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[215]
+    (const void *)&gInstructions[223]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[216]
+    (const void *)&gInstructions[224]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_5e_mprefix = 
@@ -5651,13 +5929,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_39_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[217]
+    (const void *)&gInstructions[225]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_77_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[220]
+    (const void *)&gInstructions[228]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_77_mprefix = 
@@ -5674,13 +5952,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_77_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_03_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[224]
+    (const void *)&gInstructions[234]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_03_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[770]
+    (const void *)&gInstructions[781]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_03_auxiliary = 
@@ -5699,13 +5977,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_03_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_02_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[225]
+    (const void *)&gInstructions[235]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_02_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[769]
+    (const void *)&gInstructions[780]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_02_auxiliary = 
@@ -5724,37 +6002,37 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_02_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[767]
+    (const void *)&gInstructions[778]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[768]
+    (const void *)&gInstructions[779]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[771]
+    (const void *)&gInstructions[782]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[772]
+    (const void *)&gInstructions[783]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[773]
+    (const void *)&gInstructions[784]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[774]
+    (const void *)&gInstructions[785]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_1e_cet_reg_07_modrmrm = 
@@ -5775,25 +6053,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_1e_cet_reg_07_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[759]
+    (const void *)&gInstructions[770]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[760]
+    (const void *)&gInstructions[771]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_rexw_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[761]
+    (const void *)&gInstructions[772]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_rexw_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1133]
+    (const void *)&gInstructions[1144]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary = 
@@ -5812,7 +6090,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1132]
+    (const void *)&gInstructions[1143]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_auxiliary = 
@@ -5831,31 +6109,31 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[762]
+    (const void *)&gInstructions[773]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[763]
+    (const void *)&gInstructions[774]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[764]
+    (const void *)&gInstructions[775]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[765]
+    (const void *)&gInstructions[776]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[766]
+    (const void *)&gInstructions[777]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_1e_cet_reg_modrmreg = 
@@ -5876,7 +6154,7 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_1e_cet_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[758]
+    (const void *)&gInstructions[769]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_1e_cet_modrmmod = 
@@ -5891,7 +6169,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_1e_cet_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[742]
+    (const void *)&gInstructions[753]
 };
 
 const ND_TABLE_FEATURE gRootTable_root_0f_1e_feature = 
@@ -5908,7 +6186,7 @@ const ND_TABLE_FEATURE gRootTable_root_0f_1e_feature =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_66_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[230]
+    (const void *)&gInstructions[240]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_78_None_66_modrmreg = 
@@ -5929,13 +6207,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_78_None_66_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[422]
+    (const void *)&gInstructions[432]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1862]
+    (const void *)&gInstructions[1873]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix = 
@@ -5952,7 +6230,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1294]
+    (const void *)&gInstructions[1305]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_78_cyrix_modrmmod = 
@@ -5980,19 +6258,19 @@ const ND_TABLE_VENDOR gRootTable_root_0f_78_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[231]
+    (const void *)&gInstructions[241]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[423]
+    (const void *)&gInstructions[433]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1874]
+    (const void *)&gInstructions[1885]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix = 
@@ -6009,7 +6287,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1874]
+    (const void *)&gInstructions[1885]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_mem_mprefix = 
@@ -6035,7 +6313,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_None_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1159]
+    (const void *)&gInstructions[1170]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_cyrix_modrmmod = 
@@ -6063,13 +6341,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_79_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[274]
+    (const void *)&gInstructions[284]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_None_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[384]
+    (const void *)&gInstructions[394]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix = 
@@ -6086,7 +6364,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_cyrix_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2507]
+    (const void *)&gInstructions[2518]
 };
 
 const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor = 
@@ -6105,13 +6383,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[388]
+    (const void *)&gInstructions[398]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[389]
+    (const void *)&gInstructions[399]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix = 
@@ -6128,7 +6406,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1296]
+    (const void *)&gInstructions[1307]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7c_cyrix_modrmmod = 
@@ -6156,13 +6434,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7c_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[391]
+    (const void *)&gInstructions[401]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[392]
+    (const void *)&gInstructions[402]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix = 
@@ -6179,7 +6457,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1165]
+    (const void *)&gInstructions[1176]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7d_cyrix_modrmmod = 
@@ -6207,79 +6485,79 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7d_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_af_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[395]
+    (const void *)&gInstructions[405]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_08_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[430]
+    (const void *)&gInstructions[440]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[440]
+    (const void *)&gInstructions[450]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_82_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[442]
+    (const void *)&gInstructions[452]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[446]
+    (const void *)&gInstructions[456]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[448]
+    (const void *)&gInstructions[458]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[453]
+    (const void *)&gInstructions[463]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[566]
+    (const void *)&gInstructions[576]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[583]
+    (const void *)&gInstructions[594]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1252]
+    (const void *)&gInstructions[1263]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1277]
+    (const void *)&gInstructions[1288]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1488]
+    (const void *)&gInstructions[1499]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1489]
+    (const void *)&gInstructions[1500]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg = 
@@ -6300,43 +6578,43 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[453]
+    (const void *)&gInstructions[463]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[566]
+    (const void *)&gInstructions[576]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[583]
+    (const void *)&gInstructions[594]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1253]
+    (const void *)&gInstructions[1264]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1278]
+    (const void *)&gInstructions[1289]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1488]
+    (const void *)&gInstructions[1499]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1489]
+    (const void *)&gInstructions[1500]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg = 
@@ -6366,13 +6644,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_00_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[454]
+    (const void *)&gInstructions[464]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[981]
+    (const void *)&gInstructions[992]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary = 
@@ -6391,85 +6669,85 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[457]
+    (const void *)&gInstructions[467]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_83_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[459]
+    (const void *)&gInstructions[469]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[461]
+    (const void *)&gInstructions[471]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[463]
+    (const void *)&gInstructions[473]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_81_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[465]
+    (const void *)&gInstructions[475]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[467]
+    (const void *)&gInstructions[477]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_89_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[469]
+    (const void *)&gInstructions[479]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_85_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[471]
+    (const void *)&gInstructions[481]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_80_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[473]
+    (const void *)&gInstructions[483]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[475]
+    (const void *)&gInstructions[485]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_88_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[478]
+    (const void *)&gInstructions[488]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_84_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[480]
+    (const void *)&gInstructions[490]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[552]
+    (const void *)&gInstructions[562]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[553]
+    (const void *)&gInstructions[563]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_02_modrmmod = 
@@ -6484,7 +6762,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_02_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f0_mem_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[554]
+    (const void *)&gInstructions[564]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f0_mem_mprefix = 
@@ -6510,7 +6788,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_f0_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b4_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[562]
+    (const void *)&gInstructions[572]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod = 
@@ -6525,7 +6803,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b5_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[564]
+    (const void *)&gInstructions[574]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod = 
@@ -6540,13 +6818,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[580]
+    (const void *)&gInstructions[591]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[581]
+    (const void *)&gInstructions[592]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_03_modrmmod = 
@@ -6561,7 +6839,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_03_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b2_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[582]
+    (const void *)&gInstructions[593]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_b2_modrmmod = 
@@ -6576,13 +6854,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b2_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f7_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[587]
+    (const void *)&gInstructions[598]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f7_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[588]
+    (const void *)&gInstructions[599]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f7_reg_mprefix = 
@@ -6608,25 +6886,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_f7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[589]
+    (const void *)&gInstructions[600]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[590]
+    (const void *)&gInstructions[601]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[591]
+    (const void *)&gInstructions[602]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[592]
+    (const void *)&gInstructions[603]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_5f_mprefix = 
@@ -6643,25 +6921,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[595]
+    (const void *)&gInstructions[606]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[596]
+    (const void *)&gInstructions[607]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[597]
+    (const void *)&gInstructions[608]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[598]
+    (const void *)&gInstructions[609]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_5d_mprefix = 
@@ -6678,7 +6956,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_00_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[601]
+    (const void *)&gInstructions[612]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_00_00_mprefix = 
@@ -6710,7 +6988,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_00_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_01_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2560]
+    (const void *)&gInstructions[2571]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_01_00_mprefix = 
@@ -6742,7 +7020,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_01_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_02_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2561]
+    (const void *)&gInstructions[2572]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_02_00_mprefix = 
@@ -6798,49 +7076,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a6_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_20_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[602]
+    (const void *)&gInstructions[613]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_21_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[603]
+    (const void *)&gInstructions[614]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_22_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[604]
+    (const void *)&gInstructions[615]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_23_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[605]
+    (const void *)&gInstructions[616]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_24_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[606]
+    (const void *)&gInstructions[617]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_26_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[607]
+    (const void *)&gInstructions[618]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_28_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[638]
+    (const void *)&gInstructions[649]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_28_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[640]
+    (const void *)&gInstructions[651]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_28_mprefix = 
@@ -6857,13 +7135,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_28_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_29_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[639]
+    (const void *)&gInstructions[650]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_29_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[641]
+    (const void *)&gInstructions[652]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_29_mprefix = 
@@ -6880,13 +7158,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_29_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[646]
+    (const void *)&gInstructions[657]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[677]
+    (const void *)&gInstructions[688]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_NP_auxiliary = 
@@ -6905,13 +7183,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_NP_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[647]
+    (const void *)&gInstructions[658]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[678]
+    (const void *)&gInstructions[689]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_66_auxiliary = 
@@ -6941,13 +7219,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[648]
+    (const void *)&gInstructions[659]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[680]
+    (const void *)&gInstructions[691]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_NP_auxiliary = 
@@ -6966,13 +7244,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_NP_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[649]
+    (const void *)&gInstructions[660]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[681]
+    (const void *)&gInstructions[692]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_66_auxiliary = 
@@ -6991,7 +7269,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_66_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[682]
+    (const void *)&gInstructions[693]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix = 
@@ -7008,7 +7286,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_cyrix_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1255]
+    (const void *)&gInstructions[1266]
 };
 
 const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor = 
@@ -7027,25 +7305,25 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[650]
+    (const void *)&gInstructions[661]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[658]
+    (const void *)&gInstructions[669]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[664]
+    (const void *)&gInstructions[675]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[693]
+    (const void *)&gInstructions[704]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_12_mem_mprefix = 
@@ -7062,19 +7340,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_12_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[650]
+    (const void *)&gInstructions[661]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[658]
+    (const void *)&gInstructions[669]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[693]
+    (const void *)&gInstructions[704]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_12_reg_mprefix = 
@@ -7100,19 +7378,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_12_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[653]
+    (const void *)&gInstructions[664]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[684]
+    (const void *)&gInstructions[695]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[685]
+    (const void *)&gInstructions[696]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d6_reg_mprefix = 
@@ -7129,7 +7407,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d6_reg_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[684]
+    (const void *)&gInstructions[695]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d6_mem_mprefix = 
@@ -7155,19 +7433,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_d6_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[654]
+    (const void *)&gInstructions[665]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[656]
+    (const void *)&gInstructions[667]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[679]
+    (const void *)&gInstructions[690]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6f_mprefix = 
@@ -7184,19 +7462,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[655]
+    (const void *)&gInstructions[666]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[657]
+    (const void *)&gInstructions[668]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[683]
+    (const void *)&gInstructions[694]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_7f_mprefix = 
@@ -7213,19 +7491,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[659]
+    (const void *)&gInstructions[670]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[661]
+    (const void *)&gInstructions[672]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[692]
+    (const void *)&gInstructions[703]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_16_mem_mprefix = 
@@ -7242,13 +7520,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_16_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[663]
+    (const void *)&gInstructions[674]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[692]
+    (const void *)&gInstructions[703]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_16_reg_mprefix = 
@@ -7274,13 +7552,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_16_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[660]
+    (const void *)&gInstructions[671]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[662]
+    (const void *)&gInstructions[673]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_17_mem_mprefix = 
@@ -7306,13 +7584,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_17_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[665]
+    (const void *)&gInstructions[676]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[666]
+    (const void *)&gInstructions[677]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_13_mem_mprefix = 
@@ -7338,13 +7616,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_13_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_50_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[667]
+    (const void *)&gInstructions[678]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_50_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[668]
+    (const void *)&gInstructions[679]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_50_reg_mprefix = 
@@ -7370,13 +7648,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_50_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e7_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[669]
+    (const void *)&gInstructions[680]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e7_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[674]
+    (const void *)&gInstructions[685]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e7_mem_mprefix = 
@@ -7402,7 +7680,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_e7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c3_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[671]
+    (const void *)&gInstructions[682]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c3_mem_mprefix = 
@@ -7428,25 +7706,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c3_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[672]
+    (const void *)&gInstructions[683]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[673]
+    (const void *)&gInstructions[684]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[675]
+    (const void *)&gInstructions[686]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[676]
+    (const void *)&gInstructions[687]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_2b_mem_mprefix = 
@@ -7472,25 +7750,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_2b_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[688]
+    (const void *)&gInstructions[699]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[696]
+    (const void *)&gInstructions[707]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[703]
+    (const void *)&gInstructions[714]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[705]
+    (const void *)&gInstructions[716]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_10_mprefix = 
@@ -7507,25 +7785,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_10_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[689]
+    (const void *)&gInstructions[700]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[697]
+    (const void *)&gInstructions[708]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[704]
+    (const void *)&gInstructions[715]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[706]
+    (const void *)&gInstructions[717]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_11_mprefix = 
@@ -7542,49 +7820,49 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_11_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_be_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[700]
+    (const void *)&gInstructions[711]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_bf_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[701]
+    (const void *)&gInstructions[712]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[707]
+    (const void *)&gInstructions[718]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[708]
+    (const void *)&gInstructions[719]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[712]
+    (const void *)&gInstructions[723]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[713]
+    (const void *)&gInstructions[724]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[714]
+    (const void *)&gInstructions[725]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[715]
+    (const void *)&gInstructions[726]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_59_mprefix = 
@@ -7601,49 +7879,49 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_59_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[721]
+    (const void *)&gInstructions[732]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[722]
+    (const void *)&gInstructions[733]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[723]
+    (const void *)&gInstructions[734]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[724]
+    (const void *)&gInstructions[735]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[725]
+    (const void *)&gInstructions[736]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[726]
+    (const void *)&gInstructions[737]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[727]
+    (const void *)&gInstructions[738]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[728]
+    (const void *)&gInstructions[739]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_reg_modrmreg = 
@@ -7664,49 +7942,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[987]
+    (const void *)&gInstructions[998]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[988]
+    (const void *)&gInstructions[999]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[989]
+    (const void *)&gInstructions[1000]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[990]
+    (const void *)&gInstructions[1001]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[991]
+    (const void *)&gInstructions[1002]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[992]
+    (const void *)&gInstructions[1003]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[997]
+    (const void *)&gInstructions[1008]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[998]
+    (const void *)&gInstructions[1009]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_mem_modrmreg = 
@@ -7736,49 +8014,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_0d_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[729]
+    (const void *)&gInstructions[740]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[730]
+    (const void *)&gInstructions[741]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[731]
+    (const void *)&gInstructions[742]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[732]
+    (const void *)&gInstructions[743]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[733]
+    (const void *)&gInstructions[744]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[734]
+    (const void *)&gInstructions[745]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[735]
+    (const void *)&gInstructions[746]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[736]
+    (const void *)&gInstructions[747]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_18_reg_modrmreg = 
@@ -7799,49 +8077,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_18_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[733]
+    (const void *)&gInstructions[744]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[734]
+    (const void *)&gInstructions[745]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[735]
+    (const void *)&gInstructions[746]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[736]
+    (const void *)&gInstructions[747]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[993]
+    (const void *)&gInstructions[1004]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[994]
+    (const void *)&gInstructions[1005]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[995]
+    (const void *)&gInstructions[1006]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[996]
+    (const void *)&gInstructions[1007]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_18_mem_modrmreg = 
@@ -7871,31 +8149,31 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_18_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_19_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[737]
+    (const void *)&gInstructions[748]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[741]
+    (const void *)&gInstructions[752]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[743]
+    (const void *)&gInstructions[754]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_56_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[788]
+    (const void *)&gInstructions[799]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_56_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[789]
+    (const void *)&gInstructions[800]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_56_mprefix = 
@@ -7912,13 +8190,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_56_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6b_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[806]
+    (const void *)&gInstructions[817]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[807]
+    (const void *)&gInstructions[818]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6b_mprefix = 
@@ -7935,13 +8213,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_63_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[808]
+    (const void *)&gInstructions[819]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_63_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[809]
+    (const void *)&gInstructions[820]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_63_mprefix = 
@@ -7958,13 +8236,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_63_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_67_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[811]
+    (const void *)&gInstructions[822]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_67_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[812]
+    (const void *)&gInstructions[823]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_67_mprefix = 
@@ -7981,13 +8259,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_67_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fc_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[813]
+    (const void *)&gInstructions[824]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fc_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[814]
+    (const void *)&gInstructions[825]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fc_mprefix = 
@@ -8004,13 +8282,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fc_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fe_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[815]
+    (const void *)&gInstructions[826]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fe_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[816]
+    (const void *)&gInstructions[827]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fe_mprefix = 
@@ -8027,13 +8305,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fe_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d4_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[817]
+    (const void *)&gInstructions[828]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d4_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[818]
+    (const void *)&gInstructions[829]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d4_mprefix = 
@@ -8050,13 +8328,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d4_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ec_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[819]
+    (const void *)&gInstructions[830]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ec_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[820]
+    (const void *)&gInstructions[831]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ec_mprefix = 
@@ -8073,13 +8351,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ec_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ed_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[821]
+    (const void *)&gInstructions[832]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ed_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[822]
+    (const void *)&gInstructions[833]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ed_mprefix = 
@@ -8096,13 +8374,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ed_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_dc_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[823]
+    (const void *)&gInstructions[834]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_dc_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[824]
+    (const void *)&gInstructions[835]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_dc_mprefix = 
@@ -8119,13 +8397,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_dc_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_dd_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[825]
+    (const void *)&gInstructions[836]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_dd_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[826]
+    (const void *)&gInstructions[837]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_dd_mprefix = 
@@ -8142,13 +8420,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_dd_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fd_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[827]
+    (const void *)&gInstructions[838]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fd_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[828]
+    (const void *)&gInstructions[839]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fd_mprefix = 
@@ -8165,13 +8443,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fd_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_db_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[831]
+    (const void *)&gInstructions[842]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_db_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[832]
+    (const void *)&gInstructions[843]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_db_mprefix = 
@@ -8188,13 +8466,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_db_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_df_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[833]
+    (const void *)&gInstructions[844]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_df_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[834]
+    (const void *)&gInstructions[845]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_df_mprefix = 
@@ -8211,13 +8489,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_df_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e0_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[836]
+    (const void *)&gInstructions[847]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e0_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[837]
+    (const void *)&gInstructions[848]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e0_mprefix = 
@@ -8234,157 +8512,157 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e0_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bf_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[838]
+    (const void *)&gInstructions[849]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[874]
+    (const void *)&gInstructions[885]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[875]
+    (const void *)&gInstructions[886]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_ae_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[876]
+    (const void *)&gInstructions[887]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[877]
+    (const void *)&gInstructions[888]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[878]
+    (const void *)&gInstructions[889]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_90_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[879]
+    (const void *)&gInstructions[890]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[880]
+    (const void *)&gInstructions[891]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[881]
+    (const void *)&gInstructions[892]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_94_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[882]
+    (const void *)&gInstructions[893]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[883]
+    (const void *)&gInstructions[894]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[884]
+    (const void *)&gInstructions[895]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[885]
+    (const void *)&gInstructions[896]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[886]
+    (const void *)&gInstructions[897]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[887]
+    (const void *)&gInstructions[898]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[888]
+    (const void *)&gInstructions[899]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[889]
+    (const void *)&gInstructions[900]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[890]
+    (const void *)&gInstructions[901]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[891]
+    (const void *)&gInstructions[902]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[892]
+    (const void *)&gInstructions[903]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[893]
+    (const void *)&gInstructions[904]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_aa_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[894]
+    (const void *)&gInstructions[905]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[908]
+    (const void *)&gInstructions[919]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[909]
+    (const void *)&gInstructions[920]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[955]
+    (const void *)&gInstructions[966]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1064]
+    (const void *)&gInstructions[1075]
 };
 
 const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow = 
@@ -8653,13 +8931,13 @@ const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e3_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[839]
+    (const void *)&gInstructions[850]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e3_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[840]
+    (const void *)&gInstructions[851]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e3_mprefix = 
@@ -8676,13 +8954,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e3_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[844]
+    (const void *)&gInstructions[855]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[845]
+    (const void *)&gInstructions[856]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix = 
@@ -8699,13 +8977,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[846]
+    (const void *)&gInstructions[857]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[847]
+    (const void *)&gInstructions[858]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix = 
@@ -8722,13 +9000,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[849]
+    (const void *)&gInstructions[860]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[850]
+    (const void *)&gInstructions[861]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix = 
@@ -8745,13 +9023,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[853]
+    (const void *)&gInstructions[864]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[854]
+    (const void *)&gInstructions[865]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix = 
@@ -8768,13 +9046,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[855]
+    (const void *)&gInstructions[866]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[856]
+    (const void *)&gInstructions[867]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix = 
@@ -8791,13 +9069,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[858]
+    (const void *)&gInstructions[869]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[859]
+    (const void *)&gInstructions[870]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix = 
@@ -8814,13 +9092,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[870]
+    (const void *)&gInstructions[881]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[871]
+    (const void *)&gInstructions[882]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c5_reg_mprefix = 
@@ -8846,13 +9124,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c5_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[914]
+    (const void *)&gInstructions[925]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[916]
+    (const void *)&gInstructions[927]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix = 
@@ -8869,13 +9147,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[915]
+    (const void *)&gInstructions[926]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[917]
+    (const void *)&gInstructions[928]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c4_mem_mprefix = 
@@ -8901,13 +9179,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c4_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[920]
+    (const void *)&gInstructions[931]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[921]
+    (const void *)&gInstructions[932]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix = 
@@ -8924,13 +9202,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[924]
+    (const void *)&gInstructions[935]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[925]
+    (const void *)&gInstructions[936]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix = 
@@ -8947,13 +9225,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[926]
+    (const void *)&gInstructions[937]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[927]
+    (const void *)&gInstructions[938]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix = 
@@ -8970,13 +9248,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[932]
+    (const void *)&gInstructions[943]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[933]
+    (const void *)&gInstructions[944]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix = 
@@ -8993,13 +9271,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[934]
+    (const void *)&gInstructions[945]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[935]
+    (const void *)&gInstructions[946]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix = 
@@ -9016,13 +9294,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[938]
+    (const void *)&gInstructions[949]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[939]
+    (const void *)&gInstructions[950]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d7_reg_mprefix = 
@@ -9048,13 +9326,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_d7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[956]
+    (const void *)&gInstructions[967]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[957]
+    (const void *)&gInstructions[968]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix = 
@@ -9071,13 +9349,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[958]
+    (const void *)&gInstructions[969]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[959]
+    (const void *)&gInstructions[970]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix = 
@@ -9094,13 +9372,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[961]
+    (const void *)&gInstructions[972]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[962]
+    (const void *)&gInstructions[973]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix = 
@@ -9117,13 +9395,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[963]
+    (const void *)&gInstructions[974]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[964]
+    (const void *)&gInstructions[975]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix = 
@@ -9140,25 +9418,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[965]
+    (const void *)&gInstructions[976]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[966]
+    (const void *)&gInstructions[977]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[985]
+    (const void *)&gInstructions[996]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[986]
+    (const void *)&gInstructions[997]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix = 
@@ -9175,13 +9453,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[999]
+    (const void *)&gInstructions[1010]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1000]
+    (const void *)&gInstructions[1011]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix = 
@@ -9198,25 +9476,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1003]
+    (const void *)&gInstructions[1014]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1004]
+    (const void *)&gInstructions[1015]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1005]
+    (const void *)&gInstructions[1016]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1006]
+    (const void *)&gInstructions[1017]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix = 
@@ -9233,13 +9511,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1013]
+    (const void *)&gInstructions[1024]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1014]
+    (const void *)&gInstructions[1025]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix = 
@@ -9256,13 +9534,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1027]
+    (const void *)&gInstructions[1038]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1028]
+    (const void *)&gInstructions[1039]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix = 
@@ -9279,13 +9557,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1035]
+    (const void *)&gInstructions[1046]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1036]
+    (const void *)&gInstructions[1047]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_02_mprefix = 
@@ -9326,13 +9604,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_72_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1015]
+    (const void *)&gInstructions[1026]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1016]
+    (const void *)&gInstructions[1027]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix = 
@@ -9349,7 +9627,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1017]
+    (const void *)&gInstructions[1028]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix = 
@@ -9366,13 +9644,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1018]
+    (const void *)&gInstructions[1029]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1019]
+    (const void *)&gInstructions[1030]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix = 
@@ -9389,7 +9667,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_03_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1039]
+    (const void *)&gInstructions[1050]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix = 
@@ -9406,13 +9684,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1040]
+    (const void *)&gInstructions[1051]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1041]
+    (const void *)&gInstructions[1052]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_02_mprefix = 
@@ -9453,13 +9731,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_73_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1020]
+    (const void *)&gInstructions[1031]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1021]
+    (const void *)&gInstructions[1032]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix = 
@@ -9476,13 +9754,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1022]
+    (const void *)&gInstructions[1033]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1023]
+    (const void *)&gInstructions[1034]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix = 
@@ -9499,13 +9777,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1031]
+    (const void *)&gInstructions[1042]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1032]
+    (const void *)&gInstructions[1043]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix = 
@@ -9522,13 +9800,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1044]
+    (const void *)&gInstructions[1055]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1045]
+    (const void *)&gInstructions[1056]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_02_mprefix = 
@@ -9569,13 +9847,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_71_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1024]
+    (const void *)&gInstructions[1035]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1025]
+    (const void *)&gInstructions[1036]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix = 
@@ -9592,13 +9870,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1029]
+    (const void *)&gInstructions[1040]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1030]
+    (const void *)&gInstructions[1041]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix = 
@@ -9615,13 +9893,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1033]
+    (const void *)&gInstructions[1044]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1034]
+    (const void *)&gInstructions[1045]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix = 
@@ -9638,13 +9916,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1037]
+    (const void *)&gInstructions[1048]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1038]
+    (const void *)&gInstructions[1049]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix = 
@@ -9661,13 +9939,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1042]
+    (const void *)&gInstructions[1053]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1043]
+    (const void *)&gInstructions[1054]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix = 
@@ -9684,13 +9962,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1046]
+    (const void *)&gInstructions[1057]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1047]
+    (const void *)&gInstructions[1058]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix = 
@@ -9707,13 +9985,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1048]
+    (const void *)&gInstructions[1059]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1049]
+    (const void *)&gInstructions[1060]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix = 
@@ -9730,13 +10008,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1050]
+    (const void *)&gInstructions[1061]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1051]
+    (const void *)&gInstructions[1062]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix = 
@@ -9753,13 +10031,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1052]
+    (const void *)&gInstructions[1063]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1053]
+    (const void *)&gInstructions[1064]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix = 
@@ -9776,13 +10054,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1054]
+    (const void *)&gInstructions[1065]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1055]
+    (const void *)&gInstructions[1066]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix = 
@@ -9799,13 +10077,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1056]
+    (const void *)&gInstructions[1067]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1057]
+    (const void *)&gInstructions[1068]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix = 
@@ -9822,13 +10100,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1058]
+    (const void *)&gInstructions[1069]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1059]
+    (const void *)&gInstructions[1070]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix = 
@@ -9845,13 +10123,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1060]
+    (const void *)&gInstructions[1071]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1061]
+    (const void *)&gInstructions[1072]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix = 
@@ -9868,13 +10146,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1062]
+    (const void *)&gInstructions[1073]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1063]
+    (const void *)&gInstructions[1074]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix = 
@@ -9891,13 +10169,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1067]
+    (const void *)&gInstructions[1078]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1068]
+    (const void *)&gInstructions[1079]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix = 
@@ -9914,13 +10192,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1069]
+    (const void *)&gInstructions[1080]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1070]
+    (const void *)&gInstructions[1081]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix = 
@@ -9937,7 +10215,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1071]
+    (const void *)&gInstructions[1082]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix = 
@@ -9954,13 +10232,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1072]
+    (const void *)&gInstructions[1083]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1073]
+    (const void *)&gInstructions[1084]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix = 
@@ -9977,13 +10255,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1074]
+    (const void *)&gInstructions[1085]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1075]
+    (const void *)&gInstructions[1086]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix = 
@@ -10000,13 +10278,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1076]
+    (const void *)&gInstructions[1087]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1077]
+    (const void *)&gInstructions[1088]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix = 
@@ -10023,7 +10301,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1078]
+    (const void *)&gInstructions[1089]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix = 
@@ -10040,13 +10318,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1079]
+    (const void *)&gInstructions[1090]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1080]
+    (const void *)&gInstructions[1091]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix = 
@@ -10063,25 +10341,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1081]
+    (const void *)&gInstructions[1092]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1082]
+    (const void *)&gInstructions[1093]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1104]
+    (const void *)&gInstructions[1115]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1105]
+    (const void *)&gInstructions[1116]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix = 
@@ -10098,13 +10376,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1112]
+    (const void *)&gInstructions[1123]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1113]
+    (const void *)&gInstructions[1124]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix = 
@@ -10121,19 +10399,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1122]
+    (const void *)&gInstructions[1133]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_33_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1125]
+    (const void *)&gInstructions[1136]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_36_cyrix_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1131]
+    (const void *)&gInstructions[1142]
 };
 
 const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor = 
@@ -10152,13 +10430,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_31_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1134]
+    (const void *)&gInstructions[1145]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7b_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1160]
+    (const void *)&gInstructions[1171]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7b_cyrix_modrmmod = 
@@ -10186,19 +10464,19 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7b_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_aa_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1161]
+    (const void *)&gInstructions[1172]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1162]
+    (const void *)&gInstructions[1173]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1163]
+    (const void *)&gInstructions[1174]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix = 
@@ -10215,133 +10493,133 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1204]
+    (const void *)&gInstructions[1215]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_92_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1205]
+    (const void *)&gInstructions[1216]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1206]
+    (const void *)&gInstructions[1217]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1207]
+    (const void *)&gInstructions[1218]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1208]
+    (const void *)&gInstructions[1219]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_93_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1209]
+    (const void *)&gInstructions[1220]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1210]
+    (const void *)&gInstructions[1221]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1211]
+    (const void *)&gInstructions[1222]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_91_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1212]
+    (const void *)&gInstructions[1223]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1213]
+    (const void *)&gInstructions[1224]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_99_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1214]
+    (const void *)&gInstructions[1225]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_95_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1215]
+    (const void *)&gInstructions[1226]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_90_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1216]
+    (const void *)&gInstructions[1227]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1217]
+    (const void *)&gInstructions[1228]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_98_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1218]
+    (const void *)&gInstructions[1229]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_94_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1220]
+    (const void *)&gInstructions[1231]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1236]
+    (const void *)&gInstructions[1247]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a5_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1237]
+    (const void *)&gInstructions[1248]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ac_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1245]
+    (const void *)&gInstructions[1256]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ad_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1246]
+    (const void *)&gInstructions[1257]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1248]
+    (const void *)&gInstructions[1259]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1249]
+    (const void *)&gInstructions[1260]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix = 
@@ -10358,25 +10636,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1259]
+    (const void *)&gInstructions[1270]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1260]
+    (const void *)&gInstructions[1271]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1261]
+    (const void *)&gInstructions[1272]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1262]
+    (const void *)&gInstructions[1273]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix = 
@@ -10393,25 +10671,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1290]
+    (const void *)&gInstructions[1301]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1291]
+    (const void *)&gInstructions[1302]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1292]
+    (const void *)&gInstructions[1303]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1293]
+    (const void *)&gInstructions[1304]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix = 
@@ -10428,7 +10706,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7a_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1295]
+    (const void *)&gInstructions[1306]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7a_cyrix_modrmmod = 
@@ -10456,37 +10734,37 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7a_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1298]
+    (const void *)&gInstructions[1309]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_34_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1299]
+    (const void *)&gInstructions[1310]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_35_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1300]
+    (const void *)&gInstructions[1311]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1301]
+    (const void *)&gInstructions[1312]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1326]
+    (const void *)&gInstructions[1337]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1327]
+    (const void *)&gInstructions[1338]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix = 
@@ -10503,31 +10781,31 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ff_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1328]
+    (const void *)&gInstructions[1339]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1329]
+    (const void *)&gInstructions[1340]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1330]
+    (const void *)&gInstructions[1341]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1333]
+    (const void *)&gInstructions[1344]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1334]
+    (const void *)&gInstructions[1345]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix = 
@@ -10544,13 +10822,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1335]
+    (const void *)&gInstructions[1346]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1336]
+    (const void *)&gInstructions[1347]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix = 
@@ -10567,13 +10845,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2501]
+    (const void *)&gInstructions[2512]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2502]
+    (const void *)&gInstructions[2513]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary = 
@@ -10592,25 +10870,25 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_30_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2505]
+    (const void *)&gInstructions[2516]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2513]
+    (const void *)&gInstructions[2524]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2514]
+    (const void *)&gInstructions[2525]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_02_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2526]
+    (const void *)&gInstructions[2537]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_02_00_mprefix = 
@@ -10642,7 +10920,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_02_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_04_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2527]
+    (const void *)&gInstructions[2538]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_04_00_mprefix = 
@@ -10674,7 +10952,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_04_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_03_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2528]
+    (const void *)&gInstructions[2539]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_03_00_mprefix = 
@@ -10706,7 +10984,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_03_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_01_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2529]
+    (const void *)&gInstructions[2540]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_01_00_mprefix = 
@@ -10738,7 +11016,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_01_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_05_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2530]
+    (const void *)&gInstructions[2541]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_05_00_mprefix = 
@@ -10770,7 +11048,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_05_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2562]
+    (const void *)&gInstructions[2573]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_00_modrmrm = 
@@ -10815,13 +11093,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2544]
+    (const void *)&gInstructions[2555]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2545]
+    (const void *)&gInstructions[2556]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_57_mprefix = 
@@ -11137,49 +11415,49 @@ const ND_TABLE_INSTRUCTION gRootTable_root_05_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_20_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[39]
+    (const void *)&gInstructions[47]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_21_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[40]
+    (const void *)&gInstructions[48]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_22_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[41]
+    (const void *)&gInstructions[49]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_23_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[42]
+    (const void *)&gInstructions[50]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_24_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[43]
+    (const void *)&gInstructions[51]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_25_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[44]
+    (const void *)&gInstructions[52]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_63_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[54]
+    (const void *)&gInstructions[62]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_63_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[702]
+    (const void *)&gInstructions[713]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_63_auxiliary = 
@@ -11198,7 +11476,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_63_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_62_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[79]
+    (const void *)&gInstructions[87]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_62_modrmmod = 
@@ -11213,49 +11491,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_62_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_e8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[99]
+    (const void *)&gInstructions[107]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[100]
+    (const void *)&gInstructions[108]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[102]
+    (const void *)&gInstructions[110]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[209]
+    (const void *)&gInstructions[217]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[413]
+    (const void *)&gInstructions[423]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[452]
+    (const void *)&gInstructions[462]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[456]
+    (const void *)&gInstructions[466]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1097]
+    (const void *)&gInstructions[1108]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_ff_mem_modrmreg = 
@@ -11276,31 +11554,31 @@ const ND_TABLE_MODRM_REG gRootTable_root_ff_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[100]
+    (const void *)&gInstructions[108]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[209]
+    (const void *)&gInstructions[217]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[413]
+    (const void *)&gInstructions[423]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[452]
+    (const void *)&gInstructions[462]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1097]
+    (const void *)&gInstructions[1108]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_ff_reg_modrmreg = 
@@ -11330,25 +11608,25 @@ const ND_TABLE_MODRM_MOD gRootTable_root_ff_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_9a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[101]
+    (const void *)&gInstructions[109]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_98_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[103]
+    (const void *)&gInstructions[111]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_98_ds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[105]
+    (const void *)&gInstructions[113]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_98_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[197]
+    (const void *)&gInstructions[205]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_98_dsize = 
@@ -11367,19 +11645,19 @@ const ND_TABLE_DSIZE gRootTable_root_98_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_99_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[104]
+    (const void *)&gInstructions[112]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_99_ds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[169]
+    (const void *)&gInstructions[177]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_99_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[196]
+    (const void *)&gInstructions[204]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_99_dsize = 
@@ -11398,73 +11676,73 @@ const ND_TABLE_DSIZE gRootTable_root_99_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_f8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[108]
+    (const void *)&gInstructions[116]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_fc_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[109]
+    (const void *)&gInstructions[117]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_fa_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[116]
+    (const void *)&gInstructions[124]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f5_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[121]
+    (const void *)&gInstructions[129]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_38_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[138]
+    (const void *)&gInstructions[146]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_39_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[139]
+    (const void *)&gInstructions[147]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_3a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[140]
+    (const void *)&gInstructions[148]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_3b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[141]
+    (const void *)&gInstructions[149]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_3c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[142]
+    (const void *)&gInstructions[150]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_3d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[143]
+    (const void *)&gInstructions[151]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a6_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[150]
+    (const void *)&gInstructions[158]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a6_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[151]
+    (const void *)&gInstructions[159]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_a6_auxiliary = 
@@ -11483,13 +11761,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a6_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[153]
+    (const void *)&gInstructions[161]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[154]
+    (const void *)&gInstructions[162]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_a7_ds32_auxiliary = 
@@ -11508,13 +11786,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a7_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[155]
+    (const void *)&gInstructions[163]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[156]
+    (const void *)&gInstructions[164]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_a7_ds64_auxiliary = 
@@ -11533,13 +11811,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a7_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[158]
+    (const void *)&gInstructions[166]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[159]
+    (const void *)&gInstructions[167]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_a7_ds16_auxiliary = 
@@ -11571,73 +11849,73 @@ const ND_TABLE_DSIZE gRootTable_root_a7_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_27_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[198]
+    (const void *)&gInstructions[206]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[199]
+    (const void *)&gInstructions[207]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_48_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[200]
+    (const void *)&gInstructions[208]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_49_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[201]
+    (const void *)&gInstructions[209]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_4a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[202]
+    (const void *)&gInstructions[210]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_4b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[203]
+    (const void *)&gInstructions[211]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_4c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[204]
+    (const void *)&gInstructions[212]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_4d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[205]
+    (const void *)&gInstructions[213]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_4e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[206]
+    (const void *)&gInstructions[214]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_4f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[207]
+    (const void *)&gInstructions[215]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_fe_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[208]
+    (const void *)&gInstructions[216]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_fe_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[412]
+    (const void *)&gInstructions[422]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_fe_modrmreg = 
@@ -11658,49 +11936,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_fe_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[211]
+    (const void *)&gInstructions[219]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[393]
+    (const void *)&gInstructions[403]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[398]
+    (const void *)&gInstructions[408]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[710]
+    (const void *)&gInstructions[721]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[719]
+    (const void *)&gInstructions[730]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[776]
+    (const void *)&gInstructions[787]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1313]
+    (const void *)&gInstructions[1324]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1314]
+    (const void *)&gInstructions[1325]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg = 
@@ -11721,49 +11999,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[212]
+    (const void *)&gInstructions[220]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[394]
+    (const void *)&gInstructions[404]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[399]
+    (const void *)&gInstructions[409]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[711]
+    (const void *)&gInstructions[722]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[720]
+    (const void *)&gInstructions[731]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[777]
+    (const void *)&gInstructions[788]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1315]
+    (const void *)&gInstructions[1326]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1316]
+    (const void *)&gInstructions[1327]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg = 
@@ -11784,55 +12062,55 @@ const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_c8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[228]
+    (const void *)&gInstructions[238]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[232]
+    (const void *)&gInstructions[242]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[263]
+    (const void *)&gInstructions[273]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[292]
+    (const void *)&gInstructions[302]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[334]
+    (const void *)&gInstructions[344]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[336]
+    (const void *)&gInstructions[346]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[337]
+    (const void *)&gInstructions[347]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[381]
+    (const void *)&gInstructions[391]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[382]
+    (const void *)&gInstructions[392]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_06_modrmrm = 
@@ -11853,25 +12131,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_06_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[233]
+    (const void *)&gInstructions[243]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[241]
+    (const void *)&gInstructions[251]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[367]
+    (const void *)&gInstructions[377]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[373]
+    (const void *)&gInstructions[383]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_04_modrmrm = 
@@ -11892,49 +12170,49 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_04_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[262]
+    (const void *)&gInstructions[272]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[335]
+    (const void *)&gInstructions[345]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[339]
+    (const void *)&gInstructions[349]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[341]
+    (const void *)&gInstructions[351]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[342]
+    (const void *)&gInstructions[352]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[343]
+    (const void *)&gInstructions[353]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[344]
+    (const void *)&gInstructions[354]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[383]
+    (const void *)&gInstructions[393]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_07_modrmrm = 
@@ -11955,49 +12233,49 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_07_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[306]
+    (const void *)&gInstructions[316]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[309]
+    (const void *)&gInstructions[319]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[312]
+    (const void *)&gInstructions[322]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[313]
+    (const void *)&gInstructions[323]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[314]
+    (const void *)&gInstructions[324]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[315]
+    (const void *)&gInstructions[325]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[316]
+    (const void *)&gInstructions[326]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[317]
+    (const void *)&gInstructions[327]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_05_modrmrm = 
@@ -12018,7 +12296,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_05_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[326]
+    (const void *)&gInstructions[336]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_02_modrmrm = 
@@ -12039,13 +12317,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_02_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[355]
+    (const void *)&gInstructions[365]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[374]
+    (const void *)&gInstructions[384]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d9_reg_modrmreg = 
@@ -12066,43 +12344,43 @@ const ND_TABLE_MODRM_REG gRootTable_root_d9_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[305]
+    (const void *)&gInstructions[315]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[310]
+    (const void *)&gInstructions[320]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[311]
+    (const void *)&gInstructions[321]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[330]
+    (const void *)&gInstructions[340]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[331]
+    (const void *)&gInstructions[341]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[345]
+    (const void *)&gInstructions[355]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[349]
+    (const void *)&gInstructions[359]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d9_mem_modrmreg = 
@@ -12132,49 +12410,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_d9_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[234]
+    (const void *)&gInstructions[244]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[250]
+    (const void *)&gInstructions[260]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[256]
+    (const void *)&gInstructions[266]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[264]
+    (const void *)&gInstructions[274]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[269]
+    (const void *)&gInstructions[279]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[318]
+    (const void *)&gInstructions[328]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[357]
+    (const void *)&gInstructions[367]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[362]
+    (const void *)&gInstructions[372]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d8_mem_modrmreg = 
@@ -12195,49 +12473,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d8_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[235]
+    (const void *)&gInstructions[245]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[251]
+    (const void *)&gInstructions[261]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[257]
+    (const void *)&gInstructions[267]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[265]
+    (const void *)&gInstructions[275]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[270]
+    (const void *)&gInstructions[280]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[319]
+    (const void *)&gInstructions[329]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[358]
+    (const void *)&gInstructions[368]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[363]
+    (const void *)&gInstructions[373]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d8_reg_modrmreg = 
@@ -12267,49 +12545,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_d8_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[236]
+    (const void *)&gInstructions[246]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[252]
+    (const void *)&gInstructions[262]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[258]
+    (const void *)&gInstructions[268]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[266]
+    (const void *)&gInstructions[276]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[271]
+    (const void *)&gInstructions[281]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[320]
+    (const void *)&gInstructions[330]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[359]
+    (const void *)&gInstructions[369]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[364]
+    (const void *)&gInstructions[374]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_dc_mem_modrmreg = 
@@ -12330,49 +12608,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_dc_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[237]
+    (const void *)&gInstructions[247]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[253]
+    (const void *)&gInstructions[263]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[259]
+    (const void *)&gInstructions[269]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[267]
+    (const void *)&gInstructions[277]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[272]
+    (const void *)&gInstructions[282]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[321]
+    (const void *)&gInstructions[331]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[360]
+    (const void *)&gInstructions[370]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[365]
+    (const void *)&gInstructions[375]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_dc_reg_modrmreg = 
@@ -12402,19 +12680,19 @@ const ND_TABLE_MODRM_MOD gRootTable_root_dc_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[238]
+    (const void *)&gInstructions[248]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[260]
+    (const void *)&gInstructions[270]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[261]
+    (const void *)&gInstructions[271]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_de_reg_03_modrmrm = 
@@ -12435,31 +12713,31 @@ const ND_TABLE_MODRM_RM gRootTable_root_de_reg_03_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[268]
+    (const void *)&gInstructions[278]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[273]
+    (const void *)&gInstructions[283]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[322]
+    (const void *)&gInstructions[332]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[361]
+    (const void *)&gInstructions[371]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[366]
+    (const void *)&gInstructions[376]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_de_reg_modrmreg = 
@@ -12480,49 +12758,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_de_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[278]
+    (const void *)&gInstructions[288]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[280]
+    (const void *)&gInstructions[290]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[282]
+    (const void *)&gInstructions[292]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[284]
+    (const void *)&gInstructions[294]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[286]
+    (const void *)&gInstructions[296]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[291]
+    (const void *)&gInstructions[301]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[302]
+    (const void *)&gInstructions[312]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[304]
+    (const void *)&gInstructions[314]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_de_mem_modrmreg = 
@@ -12552,49 +12830,49 @@ const ND_TABLE_MODRM_MOD gRootTable_root_de_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[239]
+    (const void *)&gInstructions[249]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[240]
+    (const void *)&gInstructions[250]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[288]
+    (const void *)&gInstructions[298]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[289]
+    (const void *)&gInstructions[299]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[294]
+    (const void *)&gInstructions[304]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[296]
+    (const void *)&gInstructions[306]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[297]
+    (const void *)&gInstructions[307]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[300]
+    (const void *)&gInstructions[310]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_df_mem_modrmreg = 
@@ -12615,31 +12893,31 @@ const ND_TABLE_MODRM_REG gRootTable_root_df_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[255]
+    (const void *)&gInstructions[265]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[276]
+    (const void *)&gInstructions[286]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[333]
+    (const void *)&gInstructions[343]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[348]
+    (const void *)&gInstructions[358]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[356]
+    (const void *)&gInstructions[366]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_df_reg_04_modrmrm = 
@@ -12660,7 +12938,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_df_reg_04_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_07_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[338]
+    (const void *)&gInstructions[348]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_df_reg_07_modrmrm = 
@@ -12681,25 +12959,25 @@ const ND_TABLE_MODRM_RM gRootTable_root_df_reg_07_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[353]
+    (const void *)&gInstructions[363]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[354]
+    (const void *)&gInstructions[364]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[370]
+    (const void *)&gInstructions[380]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[376]
+    (const void *)&gInstructions[386]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_df_reg_modrmreg = 
@@ -12729,31 +13007,31 @@ const ND_TABLE_MODRM_MOD gRootTable_root_df_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[242]
+    (const void *)&gInstructions[252]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[243]
+    (const void *)&gInstructions[253]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[244]
+    (const void *)&gInstructions[254]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[249]
+    (const void *)&gInstructions[259]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_05_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[372]
+    (const void *)&gInstructions[382]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_da_reg_05_modrmrm = 
@@ -12789,49 +13067,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_da_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[277]
+    (const void *)&gInstructions[287]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[279]
+    (const void *)&gInstructions[289]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[281]
+    (const void *)&gInstructions[291]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[283]
+    (const void *)&gInstructions[293]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[285]
+    (const void *)&gInstructions[295]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[290]
+    (const void *)&gInstructions[300]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[301]
+    (const void *)&gInstructions[311]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[303]
+    (const void *)&gInstructions[313]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_da_mem_modrmreg = 
@@ -12861,61 +13139,61 @@ const ND_TABLE_MODRM_MOD gRootTable_root_da_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[245]
+    (const void *)&gInstructions[255]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[246]
+    (const void *)&gInstructions[256]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[247]
+    (const void *)&gInstructions[257]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[248]
+    (const void *)&gInstructions[258]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[254]
+    (const void *)&gInstructions[264]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[323]
+    (const void *)&gInstructions[333]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[324]
+    (const void *)&gInstructions[334]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[325]
+    (const void *)&gInstructions[335]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[327]
+    (const void *)&gInstructions[337]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[328]
+    (const void *)&gInstructions[338]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_db_reg_04_modrmrm = 
@@ -12936,7 +13214,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_db_reg_04_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[369]
+    (const void *)&gInstructions[379]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_db_reg_modrmreg = 
@@ -12957,37 +13235,37 @@ const ND_TABLE_MODRM_REG gRootTable_root_db_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[287]
+    (const void *)&gInstructions[297]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[293]
+    (const void *)&gInstructions[303]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[295]
+    (const void *)&gInstructions[305]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[298]
+    (const void *)&gInstructions[308]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[307]
+    (const void *)&gInstructions[317]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[350]
+    (const void *)&gInstructions[360]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_db_mem_modrmreg = 
@@ -13017,37 +13295,37 @@ const ND_TABLE_MODRM_MOD gRootTable_root_db_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[275]
+    (const void *)&gInstructions[285]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[347]
+    (const void *)&gInstructions[357]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[352]
+    (const void *)&gInstructions[362]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[368]
+    (const void *)&gInstructions[378]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[371]
+    (const void *)&gInstructions[381]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[375]
+    (const void *)&gInstructions[385]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_dd_reg_modrmreg = 
@@ -13068,43 +13346,43 @@ const ND_TABLE_MODRM_REG gRootTable_root_dd_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[299]
+    (const void *)&gInstructions[309]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[308]
+    (const void *)&gInstructions[318]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[329]
+    (const void *)&gInstructions[339]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[332]
+    (const void *)&gInstructions[342]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[340]
+    (const void *)&gInstructions[350]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[346]
+    (const void *)&gInstructions[356]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[351]
+    (const void *)&gInstructions[361]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_dd_mem_modrmreg = 
@@ -13134,103 +13412,103 @@ const ND_TABLE_MODRM_MOD gRootTable_root_dd_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_f4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[390]
+    (const void *)&gInstructions[400]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_69_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[396]
+    (const void *)&gInstructions[406]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[397]
+    (const void *)&gInstructions[407]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[400]
+    (const void *)&gInstructions[410]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e5_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[401]
+    (const void *)&gInstructions[411]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ec_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[402]
+    (const void *)&gInstructions[412]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ed_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[403]
+    (const void *)&gInstructions[413]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_40_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[404]
+    (const void *)&gInstructions[414]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_41_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[405]
+    (const void *)&gInstructions[415]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_42_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[406]
+    (const void *)&gInstructions[416]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_43_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[407]
+    (const void *)&gInstructions[417]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_44_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[408]
+    (const void *)&gInstructions[418]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_45_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[409]
+    (const void *)&gInstructions[419]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_46_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[410]
+    (const void *)&gInstructions[420]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_47_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[411]
+    (const void *)&gInstructions[421]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6c_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[416]
+    (const void *)&gInstructions[426]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6c_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[417]
+    (const void *)&gInstructions[427]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary = 
@@ -13249,13 +13527,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[418]
+    (const void *)&gInstructions[428]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[419]
+    (const void *)&gInstructions[429]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary = 
@@ -13274,13 +13552,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[424]
+    (const void *)&gInstructions[434]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[425]
+    (const void *)&gInstructions[435]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6d_ds16_auxiliary = 
@@ -13312,43 +13590,43 @@ const ND_TABLE_DSIZE gRootTable_root_6d_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_cd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[426]
+    (const void *)&gInstructions[436]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[427]
+    (const void *)&gInstructions[437]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cc_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[428]
+    (const void *)&gInstructions[438]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ce_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[429]
+    (const void *)&gInstructions[439]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[437]
+    (const void *)&gInstructions[447]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[438]
+    (const void *)&gInstructions[448]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[439]
+    (const void *)&gInstructions[449]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_cf_dsize = 
@@ -13367,31 +13645,31 @@ const ND_TABLE_DSIZE gRootTable_root_cf_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_76_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[441]
+    (const void *)&gInstructions[451]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_72_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[443]
+    (const void *)&gInstructions[453]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e3_as16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[444]
+    (const void *)&gInstructions[454]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e3_as32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[445]
+    (const void *)&gInstructions[455]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e3_as64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[477]
+    (const void *)&gInstructions[487]
 };
 
 const ND_TABLE_ASIZE gRootTable_root_e3_asize = 
@@ -13408,115 +13686,115 @@ const ND_TABLE_ASIZE gRootTable_root_e3_asize =
 const ND_TABLE_INSTRUCTION gRootTable_root_7c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[447]
+    (const void *)&gInstructions[457]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[449]
+    (const void *)&gInstructions[459]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[450]
+    (const void *)&gInstructions[460]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_eb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[451]
+    (const void *)&gInstructions[461]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ea_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[455]
+    (const void *)&gInstructions[465]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_77_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[458]
+    (const void *)&gInstructions[468]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_73_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[460]
+    (const void *)&gInstructions[470]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[462]
+    (const void *)&gInstructions[472]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[464]
+    (const void *)&gInstructions[474]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_71_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[466]
+    (const void *)&gInstructions[476]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[468]
+    (const void *)&gInstructions[478]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_79_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[470]
+    (const void *)&gInstructions[480]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_75_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[472]
+    (const void *)&gInstructions[482]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_70_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[474]
+    (const void *)&gInstructions[484]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[476]
+    (const void *)&gInstructions[486]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_78_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[479]
+    (const void *)&gInstructions[489]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_74_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[481]
+    (const void *)&gInstructions[491]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[551]
+    (const void *)&gInstructions[561]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c5_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[556]
+    (const void *)&gInstructions[566]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod = 
@@ -13531,7 +13809,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_8d_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[558]
+    (const void *)&gInstructions[568]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod = 
@@ -13546,13 +13824,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_c9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[559]
+    (const void *)&gInstructions[569]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c4_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[560]
+    (const void *)&gInstructions[570]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_c4_modrmmod = 
@@ -13567,13 +13845,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c4_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_ac_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[569]
+    (const void *)&gInstructions[580]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ac_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[570]
+    (const void *)&gInstructions[581]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ac_auxiliary = 
@@ -13592,13 +13870,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ac_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[571]
+    (const void *)&gInstructions[582]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[572]
+    (const void *)&gInstructions[583]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ad_ds32_auxiliary = 
@@ -13617,13 +13895,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ad_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[573]
+    (const void *)&gInstructions[584]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[574]
+    (const void *)&gInstructions[585]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ad_ds64_auxiliary = 
@@ -13642,13 +13920,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ad_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[575]
+    (const void *)&gInstructions[586]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[576]
+    (const void *)&gInstructions[587]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ad_ds16_auxiliary = 
@@ -13680,55 +13958,55 @@ const ND_TABLE_DSIZE gRootTable_root_ad_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_e2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[577]
+    (const void *)&gInstructions[588]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[578]
+    (const void *)&gInstructions[589]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[579]
+    (const void *)&gInstructions[590]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_88_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[608]
+    (const void *)&gInstructions[619]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_89_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[609]
+    (const void *)&gInstructions[620]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[610]
+    (const void *)&gInstructions[621]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[611]
+    (const void *)&gInstructions[622]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8c_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[612]
+    (const void *)&gInstructions[623]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8c_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[613]
+    (const void *)&gInstructions[624]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_8c_modrmmod = 
@@ -13743,13 +14021,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8c_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_8e_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[614]
+    (const void *)&gInstructions[625]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8e_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[615]
+    (const void *)&gInstructions[626]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_8e_modrmmod = 
@@ -13764,127 +14042,127 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8e_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_a0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[616]
+    (const void *)&gInstructions[627]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[617]
+    (const void *)&gInstructions[628]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[618]
+    (const void *)&gInstructions[629]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[619]
+    (const void *)&gInstructions[630]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[620]
+    (const void *)&gInstructions[631]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[621]
+    (const void *)&gInstructions[632]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[622]
+    (const void *)&gInstructions[633]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[623]
+    (const void *)&gInstructions[634]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[624]
+    (const void *)&gInstructions[635]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b5_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[625]
+    (const void *)&gInstructions[636]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[626]
+    (const void *)&gInstructions[637]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[627]
+    (const void *)&gInstructions[638]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[628]
+    (const void *)&gInstructions[639]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_b9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[629]
+    (const void *)&gInstructions[640]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ba_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[630]
+    (const void *)&gInstructions[641]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_bb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[631]
+    (const void *)&gInstructions[642]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_bc_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[632]
+    (const void *)&gInstructions[643]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_bd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[633]
+    (const void *)&gInstructions[644]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_be_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[634]
+    (const void *)&gInstructions[645]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_bf_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[635]
+    (const void *)&gInstructions[646]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c6_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[636]
+    (const void *)&gInstructions[647]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_c6_mem_modrmreg = 
@@ -13905,13 +14183,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_c6_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[636]
+    (const void *)&gInstructions[647]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2512]
+    (const void *)&gInstructions[2523]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_c6_reg_07_modrmrm = 
@@ -13956,7 +14234,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c6_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_c7_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[637]
+    (const void *)&gInstructions[648]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_c7_mem_modrmreg = 
@@ -13977,13 +14255,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_c7_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[637]
+    (const void *)&gInstructions[648]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2515]
+    (const void *)&gInstructions[2526]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_c7_reg_07_modrmrm = 
@@ -14028,13 +14306,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_a4_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[686]
+    (const void *)&gInstructions[697]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a4_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[687]
+    (const void *)&gInstructions[698]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_a4_auxiliary = 
@@ -14053,13 +14331,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a4_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[690]
+    (const void *)&gInstructions[701]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[691]
+    (const void *)&gInstructions[702]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_a5_ds32_auxiliary = 
@@ -14078,13 +14356,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a5_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[694]
+    (const void *)&gInstructions[705]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[695]
+    (const void *)&gInstructions[706]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_a5_ds64_auxiliary = 
@@ -14103,13 +14381,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_a5_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[698]
+    (const void *)&gInstructions[709]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[699]
+    (const void *)&gInstructions[710]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_a5_ds16_auxiliary = 
@@ -14141,19 +14419,19 @@ const ND_TABLE_DSIZE gRootTable_root_a5_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_90_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[775]
+    (const void *)&gInstructions[786]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_90_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[835]
+    (const void *)&gInstructions[846]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_90_rex_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2518]
+    (const void *)&gInstructions[2529]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary = 
@@ -14172,73 +14450,73 @@ const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_08_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[778]
+    (const void *)&gInstructions[789]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_09_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[779]
+    (const void *)&gInstructions[790]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[780]
+    (const void *)&gInstructions[791]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[781]
+    (const void *)&gInstructions[792]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[782]
+    (const void *)&gInstructions[793]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[783]
+    (const void *)&gInstructions[794]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[790]
+    (const void *)&gInstructions[801]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[791]
+    (const void *)&gInstructions[802]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ee_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[792]
+    (const void *)&gInstructions[803]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ef_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[793]
+    (const void *)&gInstructions[804]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6e_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[794]
+    (const void *)&gInstructions[805]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6e_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[795]
+    (const void *)&gInstructions[806]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6e_auxiliary = 
@@ -14257,13 +14535,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6e_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_6f_None_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[796]
+    (const void *)&gInstructions[807]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6f_None_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[797]
+    (const void *)&gInstructions[808]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6f_None_auxiliary = 
@@ -14282,13 +14560,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6f_None_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_6f_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[798]
+    (const void *)&gInstructions[809]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6f_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[799]
+    (const void *)&gInstructions[810]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6f_ds16_auxiliary = 
@@ -14320,73 +14598,73 @@ const ND_TABLE_DSIZE gRootTable_root_6f_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[967]
+    (const void *)&gInstructions[978]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_17_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[968]
+    (const void *)&gInstructions[979]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[969]
+    (const void *)&gInstructions[980]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_58_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[970]
+    (const void *)&gInstructions[981]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_59_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[971]
+    (const void *)&gInstructions[982]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[972]
+    (const void *)&gInstructions[983]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[973]
+    (const void *)&gInstructions[984]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[974]
+    (const void *)&gInstructions[985]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[975]
+    (const void *)&gInstructions[986]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[976]
+    (const void *)&gInstructions[987]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[977]
+    (const void *)&gInstructions[988]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8f_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[978]
+    (const void *)&gInstructions[989]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg = 
@@ -14407,13 +14685,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_61_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[979]
+    (const void *)&gInstructions[990]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_61_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[980]
+    (const void *)&gInstructions[991]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_61_dsize = 
@@ -14432,19 +14710,19 @@ const ND_TABLE_DSIZE gRootTable_root_61_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[982]
+    (const void *)&gInstructions[993]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9d_dds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[983]
+    (const void *)&gInstructions[994]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[984]
+    (const void *)&gInstructions[995]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_9d_dsize = 
@@ -14463,97 +14741,97 @@ const ND_TABLE_DSIZE gRootTable_root_9d_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1083]
+    (const void *)&gInstructions[1094]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1084]
+    (const void *)&gInstructions[1095]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1085]
+    (const void *)&gInstructions[1096]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1086]
+    (const void *)&gInstructions[1097]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_50_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1087]
+    (const void *)&gInstructions[1098]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_51_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1088]
+    (const void *)&gInstructions[1099]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_52_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1089]
+    (const void *)&gInstructions[1100]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_53_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1090]
+    (const void *)&gInstructions[1101]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_54_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1091]
+    (const void *)&gInstructions[1102]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_55_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1092]
+    (const void *)&gInstructions[1103]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_56_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1093]
+    (const void *)&gInstructions[1104]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_57_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1094]
+    (const void *)&gInstructions[1105]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_68_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1095]
+    (const void *)&gInstructions[1106]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1096]
+    (const void *)&gInstructions[1107]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_60_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1098]
+    (const void *)&gInstructions[1109]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_60_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1099]
+    (const void *)&gInstructions[1110]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_60_dsize = 
@@ -14572,19 +14850,19 @@ const ND_TABLE_DSIZE gRootTable_root_60_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1100]
+    (const void *)&gInstructions[1111]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9c_dds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1101]
+    (const void *)&gInstructions[1112]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1102]
+    (const void *)&gInstructions[1113]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_9c_dsize = 
@@ -14603,49 +14881,49 @@ const ND_TABLE_DSIZE gRootTable_root_9c_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1106]
+    (const void *)&gInstructions[1117]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1114]
+    (const void *)&gInstructions[1125]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1142]
+    (const void *)&gInstructions[1153]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1148]
+    (const void *)&gInstructions[1159]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1167]
+    (const void *)&gInstructions[1178]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1174]
+    (const void *)&gInstructions[1185]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1230]
+    (const void *)&gInstructions[1241]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1239]
+    (const void *)&gInstructions[1250]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg = 
@@ -14666,49 +14944,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1107]
+    (const void *)&gInstructions[1118]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1115]
+    (const void *)&gInstructions[1126]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1143]
+    (const void *)&gInstructions[1154]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1149]
+    (const void *)&gInstructions[1160]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1168]
+    (const void *)&gInstructions[1179]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1175]
+    (const void *)&gInstructions[1186]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1231]
+    (const void *)&gInstructions[1242]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1240]
+    (const void *)&gInstructions[1251]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg = 
@@ -14729,49 +15007,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1108]
+    (const void *)&gInstructions[1119]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1116]
+    (const void *)&gInstructions[1127]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1144]
+    (const void *)&gInstructions[1155]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1150]
+    (const void *)&gInstructions[1161]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1169]
+    (const void *)&gInstructions[1180]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1176]
+    (const void *)&gInstructions[1187]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1232]
+    (const void *)&gInstructions[1243]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1241]
+    (const void *)&gInstructions[1252]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg = 
@@ -14792,49 +15070,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1109]
+    (const void *)&gInstructions[1120]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1117]
+    (const void *)&gInstructions[1128]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1145]
+    (const void *)&gInstructions[1156]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1151]
+    (const void *)&gInstructions[1162]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1170]
+    (const void *)&gInstructions[1181]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1177]
+    (const void *)&gInstructions[1188]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1233]
+    (const void *)&gInstructions[1244]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1242]
+    (const void *)&gInstructions[1253]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg = 
@@ -14855,49 +15133,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1110]
+    (const void *)&gInstructions[1121]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1118]
+    (const void *)&gInstructions[1129]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1146]
+    (const void *)&gInstructions[1157]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1152]
+    (const void *)&gInstructions[1163]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1171]
+    (const void *)&gInstructions[1182]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1178]
+    (const void *)&gInstructions[1189]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1234]
+    (const void *)&gInstructions[1245]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1243]
+    (const void *)&gInstructions[1254]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg = 
@@ -14918,49 +15196,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1111]
+    (const void *)&gInstructions[1122]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1119]
+    (const void *)&gInstructions[1130]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1147]
+    (const void *)&gInstructions[1158]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1153]
+    (const void *)&gInstructions[1164]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1172]
+    (const void *)&gInstructions[1183]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1179]
+    (const void *)&gInstructions[1190]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1235]
+    (const void *)&gInstructions[1246]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1244]
+    (const void *)&gInstructions[1255]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg = 
@@ -14981,85 +15259,85 @@ const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_ca_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1136]
+    (const void *)&gInstructions[1147]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1137]
+    (const void *)&gInstructions[1148]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1138]
+    (const void *)&gInstructions[1149]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1139]
+    (const void *)&gInstructions[1150]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1166]
+    (const void *)&gInstructions[1177]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1173]
+    (const void *)&gInstructions[1184]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_18_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1182]
+    (const void *)&gInstructions[1193]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_19_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1183]
+    (const void *)&gInstructions[1194]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1184]
+    (const void *)&gInstructions[1195]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1185]
+    (const void *)&gInstructions[1196]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1186]
+    (const void *)&gInstructions[1197]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1187]
+    (const void *)&gInstructions[1198]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ae_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1192]
+    (const void *)&gInstructions[1203]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ae_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1193]
+    (const void *)&gInstructions[1204]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary = 
@@ -15078,13 +15356,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1194]
+    (const void *)&gInstructions[1205]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1195]
+    (const void *)&gInstructions[1206]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary = 
@@ -15103,13 +15381,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1196]
+    (const void *)&gInstructions[1207]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1197]
+    (const void *)&gInstructions[1208]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary = 
@@ -15128,13 +15406,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1198]
+    (const void *)&gInstructions[1209]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1199]
+    (const void *)&gInstructions[1210]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_af_ds16_auxiliary = 
@@ -15166,31 +15444,31 @@ const ND_TABLE_DSIZE gRootTable_root_af_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_f9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1264]
+    (const void *)&gInstructions[1275]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_fd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1265]
+    (const void *)&gInstructions[1276]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_fb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1267]
+    (const void *)&gInstructions[1278]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_aa_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1269]
+    (const void *)&gInstructions[1280]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_aa_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1270]
+    (const void *)&gInstructions[1281]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary = 
@@ -15209,13 +15487,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1271]
+    (const void *)&gInstructions[1282]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1272]
+    (const void *)&gInstructions[1283]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary = 
@@ -15234,13 +15512,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1273]
+    (const void *)&gInstructions[1284]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1274]
+    (const void *)&gInstructions[1285]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary = 
@@ -15259,13 +15537,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1275]
+    (const void *)&gInstructions[1286]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1276]
+    (const void *)&gInstructions[1287]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ab_ds16_auxiliary = 
@@ -15297,163 +15575,163 @@ const ND_TABLE_DSIZE gRootTable_root_ab_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_28_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1280]
+    (const void *)&gInstructions[1291]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_29_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1281]
+    (const void *)&gInstructions[1292]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1282]
+    (const void *)&gInstructions[1293]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1283]
+    (const void *)&gInstructions[1294]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1284]
+    (const void *)&gInstructions[1295]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1285]
+    (const void *)&gInstructions[1296]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_84_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1309]
+    (const void *)&gInstructions[1320]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_85_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1310]
+    (const void *)&gInstructions[1321]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1311]
+    (const void *)&gInstructions[1322]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1312]
+    (const void *)&gInstructions[1323]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2500]
+    (const void *)&gInstructions[2511]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2516]
+    (const void *)&gInstructions[2527]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2517]
+    (const void *)&gInstructions[2528]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_91_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2519]
+    (const void *)&gInstructions[2530]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_92_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2520]
+    (const void *)&gInstructions[2531]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_93_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2521]
+    (const void *)&gInstructions[2532]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_94_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2522]
+    (const void *)&gInstructions[2533]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_95_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2523]
+    (const void *)&gInstructions[2534]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2524]
+    (const void *)&gInstructions[2535]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2525]
+    (const void *)&gInstructions[2536]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2533]
+    (const void *)&gInstructions[2544]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_30_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2534]
+    (const void *)&gInstructions[2545]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_31_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2535]
+    (const void *)&gInstructions[2546]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2536]
+    (const void *)&gInstructions[2547]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_33_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2537]
+    (const void *)&gInstructions[2548]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_34_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2538]
+    (const void *)&gInstructions[2549]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_35_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2539]
+    (const void *)&gInstructions[2550]
 };
 
 const ND_TABLE_OPCODE gRootTable_root_opcode = 
diff --git a/bddisasm/include/table_vex.h b/bddisasm/include/table_vex.h
index c20bea3..98de335 100644
--- a/bddisasm/include/table_vex.h
+++ b/bddisasm/include/table_vex.h
@@ -4,7 +4,7 @@
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f2_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[49]
+    (const void *)&gInstructions[57]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f2_00_l = 
@@ -32,7 +32,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[55]
+    (const void *)&gInstructions[63]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_00_l = 
@@ -49,7 +49,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_00_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1180]
+    (const void *)&gInstructions[1191]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l = 
@@ -66,7 +66,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1238]
+    (const void *)&gInstructions[1249]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l = 
@@ -83,7 +83,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1247]
+    (const void *)&gInstructions[1258]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_03_l = 
@@ -111,7 +111,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[67]
+    (const void *)&gInstructions[75]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f3_00_03_l = 
@@ -128,7 +128,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f3_00_03_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[69]
+    (const void *)&gInstructions[77]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f3_00_02_l = 
@@ -145,7 +145,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f3_00_02_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[70]
+    (const void *)&gInstructions[78]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f3_00_01_l = 
@@ -188,7 +188,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[98]
+    (const void *)&gInstructions[106]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f5_00_l = 
@@ -205,7 +205,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f5_00_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[864]
+    (const void *)&gInstructions[875]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l = 
@@ -222,7 +222,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[865]
+    (const void *)&gInstructions[876]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f5_02_l = 
@@ -250,7 +250,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_mem_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[557]
+    (const void *)&gInstructions[567]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_00_mem_00_00_w = 
@@ -291,7 +291,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_reg_00_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1319]
+    (const void *)&gInstructions[1330]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_00_reg_00_00_00_w = 
@@ -356,7 +356,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_00_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_01_mem_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1279]
+    (const void *)&gInstructions[1290]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_01_mem_00_00_w = 
@@ -406,7 +406,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_03_reg_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1321]
+    (const void *)&gInstructions[1332]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_03_reg_00_00_w = 
@@ -467,7 +467,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_49_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f6_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[716]
+    (const void *)&gInstructions[727]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f6_03_l = 
@@ -495,7 +495,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_02_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1304]
+    (const void *)&gInstructions[1315]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5c_02_reg_00_w = 
@@ -541,7 +541,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_03_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1305]
+    (const void *)&gInstructions[1316]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_03_reg_00_w = 
@@ -576,7 +576,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_02_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1306]
+    (const void *)&gInstructions[1317]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_02_reg_00_w = 
@@ -611,7 +611,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1307]
+    (const void *)&gInstructions[1318]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_01_reg_00_w = 
@@ -646,7 +646,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1308]
+    (const void *)&gInstructions[1319]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_00_reg_00_w = 
@@ -692,7 +692,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_03_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1317]
+    (const void *)&gInstructions[1328]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_4b_03_mem_00_w = 
@@ -727,7 +727,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_01_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1318]
+    (const void *)&gInstructions[1329]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_4b_01_mem_00_w = 
@@ -762,7 +762,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_02_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1320]
+    (const void *)&gInstructions[1331]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_4b_02_mem_00_w = 
@@ -808,7 +808,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_4b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1352]
+    (const void *)&gInstructions[1363]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_de_pp = 
@@ -825,7 +825,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_de_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_df_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1354]
+    (const void *)&gInstructions[1365]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_df_pp = 
@@ -842,7 +842,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_df_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1356]
+    (const void *)&gInstructions[1367]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp = 
@@ -859,7 +859,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1358]
+    (const void *)&gInstructions[1369]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp = 
@@ -876,7 +876,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_db_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1359]
+    (const void *)&gInstructions[1370]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_db_01_l = 
@@ -904,7 +904,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_db_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1a_01_mem_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1377]
+    (const void *)&gInstructions[1388]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_1a_01_mem_01_w = 
@@ -950,7 +950,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5a_01_mem_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1383]
+    (const void *)&gInstructions[1394]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5a_01_mem_01_w = 
@@ -996,7 +996,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_19_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1390]
+    (const void *)&gInstructions[1401]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_19_01_w = 
@@ -1022,7 +1022,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_19_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_18_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1392]
+    (const void *)&gInstructions[1403]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_18_01_w = 
@@ -1048,7 +1048,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_18_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1423]
+    (const void *)&gInstructions[1434]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w = 
@@ -1063,7 +1063,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1424]
+    (const void *)&gInstructions[1435]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_13_01_01_w = 
@@ -1100,13 +1100,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_13_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1513]
+    (const void *)&gInstructions[1524]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1515]
+    (const void *)&gInstructions[1526]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_98_01_w = 
@@ -1132,13 +1132,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_98_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1517]
+    (const void *)&gInstructions[1528]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1519]
+    (const void *)&gInstructions[1530]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_99_01_w = 
@@ -1164,13 +1164,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_99_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1521]
+    (const void *)&gInstructions[1532]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1523]
+    (const void *)&gInstructions[1534]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a8_01_w = 
@@ -1196,13 +1196,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1525]
+    (const void *)&gInstructions[1536]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1527]
+    (const void *)&gInstructions[1538]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a9_01_w = 
@@ -1228,13 +1228,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1529]
+    (const void *)&gInstructions[1540]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1531]
+    (const void *)&gInstructions[1542]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b8_01_w = 
@@ -1260,13 +1260,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1533]
+    (const void *)&gInstructions[1544]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1535]
+    (const void *)&gInstructions[1546]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b9_01_w = 
@@ -1292,13 +1292,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1545]
+    (const void *)&gInstructions[1556]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1547]
+    (const void *)&gInstructions[1558]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_96_01_w = 
@@ -1324,13 +1324,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_96_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1549]
+    (const void *)&gInstructions[1560]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1551]
+    (const void *)&gInstructions[1562]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a6_01_w = 
@@ -1356,13 +1356,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1553]
+    (const void *)&gInstructions[1564]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1555]
+    (const void *)&gInstructions[1566]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b6_01_w = 
@@ -1388,13 +1388,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1561]
+    (const void *)&gInstructions[1572]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1563]
+    (const void *)&gInstructions[1574]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9a_01_w = 
@@ -1420,13 +1420,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1565]
+    (const void *)&gInstructions[1576]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1567]
+    (const void *)&gInstructions[1578]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9b_01_w = 
@@ -1452,13 +1452,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1569]
+    (const void *)&gInstructions[1580]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1571]
+    (const void *)&gInstructions[1582]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_aa_01_w = 
@@ -1484,13 +1484,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_aa_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1573]
+    (const void *)&gInstructions[1584]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1575]
+    (const void *)&gInstructions[1586]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ab_01_w = 
@@ -1516,13 +1516,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ab_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1577]
+    (const void *)&gInstructions[1588]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1579]
+    (const void *)&gInstructions[1590]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ba_01_w = 
@@ -1548,13 +1548,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ba_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1581]
+    (const void *)&gInstructions[1592]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1583]
+    (const void *)&gInstructions[1594]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bb_01_w = 
@@ -1580,13 +1580,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bb_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1585]
+    (const void *)&gInstructions[1596]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1587]
+    (const void *)&gInstructions[1598]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_97_01_w = 
@@ -1612,13 +1612,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_97_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1589]
+    (const void *)&gInstructions[1600]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1591]
+    (const void *)&gInstructions[1602]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a7_01_w = 
@@ -1644,13 +1644,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1593]
+    (const void *)&gInstructions[1604]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1595]
+    (const void *)&gInstructions[1606]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b7_01_w = 
@@ -1676,13 +1676,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1609]
+    (const void *)&gInstructions[1620]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1611]
+    (const void *)&gInstructions[1622]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9c_01_w = 
@@ -1708,13 +1708,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1613]
+    (const void *)&gInstructions[1624]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1615]
+    (const void *)&gInstructions[1626]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9d_01_w = 
@@ -1740,13 +1740,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1617]
+    (const void *)&gInstructions[1628]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1619]
+    (const void *)&gInstructions[1630]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ac_01_w = 
@@ -1772,13 +1772,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ac_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1621]
+    (const void *)&gInstructions[1632]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1623]
+    (const void *)&gInstructions[1634]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ad_01_w = 
@@ -1804,13 +1804,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ad_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1625]
+    (const void *)&gInstructions[1636]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1627]
+    (const void *)&gInstructions[1638]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bc_01_w = 
@@ -1836,13 +1836,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1629]
+    (const void *)&gInstructions[1640]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1631]
+    (const void *)&gInstructions[1642]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bd_01_w = 
@@ -1868,13 +1868,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1641]
+    (const void *)&gInstructions[1652]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1643]
+    (const void *)&gInstructions[1654]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9e_01_w = 
@@ -1900,13 +1900,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1645]
+    (const void *)&gInstructions[1656]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1647]
+    (const void *)&gInstructions[1658]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9f_01_w = 
@@ -1932,13 +1932,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1649]
+    (const void *)&gInstructions[1660]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1651]
+    (const void *)&gInstructions[1662]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ae_01_w = 
@@ -1964,13 +1964,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ae_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1653]
+    (const void *)&gInstructions[1664]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1655]
+    (const void *)&gInstructions[1666]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_af_01_w = 
@@ -1996,13 +1996,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_af_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1657]
+    (const void *)&gInstructions[1668]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1659]
+    (const void *)&gInstructions[1670]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_be_01_w = 
@@ -2028,13 +2028,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_be_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1661]
+    (const void *)&gInstructions[1672]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1663]
+    (const void *)&gInstructions[1674]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bf_01_w = 
@@ -2060,13 +2060,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bf_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1681]
+    (const void *)&gInstructions[1692]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1683]
+    (const void *)&gInstructions[1694]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_92_01_mem_w = 
@@ -2101,13 +2101,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_92_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1693]
+    (const void *)&gInstructions[1704]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1695]
+    (const void *)&gInstructions[1706]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_93_01_mem_w = 
@@ -2142,7 +2142,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_93_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_cf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1709]
+    (const void *)&gInstructions[1720]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_cf_01_w = 
@@ -2168,7 +2168,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_cf_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2d_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1731]
+    (const void *)&gInstructions[1742]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2d_01_mem_w = 
@@ -2203,7 +2203,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2f_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1732]
+    (const void *)&gInstructions[1743]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2f_01_mem_w = 
@@ -2238,7 +2238,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2c_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1733]
+    (const void *)&gInstructions[1744]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2c_01_mem_w = 
@@ -2273,7 +2273,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2e_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1734]
+    (const void *)&gInstructions[1745]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2e_01_mem_w = 
@@ -2308,7 +2308,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2a_01_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1818]
+    (const void *)&gInstructions[1829]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_02_2a_01_modrmmod = 
@@ -2334,7 +2334,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1886]
+    (const void *)&gInstructions[1897]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp = 
@@ -2351,7 +2351,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1888]
+    (const void *)&gInstructions[1899]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp = 
@@ -2368,7 +2368,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1891]
+    (const void *)&gInstructions[1902]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp = 
@@ -2385,7 +2385,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1897]
+    (const void *)&gInstructions[1908]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp = 
@@ -2402,7 +2402,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1937]
+    (const void *)&gInstructions[1948]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_78_01_w = 
@@ -2428,7 +2428,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_78_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_58_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1940]
+    (const void *)&gInstructions[1951]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_58_01_w = 
@@ -2454,7 +2454,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_58_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_59_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1945]
+    (const void *)&gInstructions[1956]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_59_01_w = 
@@ -2480,7 +2480,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_59_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1948]
+    (const void *)&gInstructions[1959]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_79_01_w = 
@@ -2506,7 +2506,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_79_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_29_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1960]
+    (const void *)&gInstructions[1971]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_29_pp = 
@@ -2523,7 +2523,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_29_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_37_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1970]
+    (const void *)&gInstructions[1981]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_37_pp = 
@@ -2540,7 +2540,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_37_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_36_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2003]
+    (const void *)&gInstructions[2014]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_36_01_01_w = 
@@ -2577,7 +2577,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_36_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2016]
+    (const void *)&gInstructions[2027]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0d_01_w = 
@@ -2603,7 +2603,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2020]
+    (const void *)&gInstructions[2031]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0c_01_w = 
@@ -2629,7 +2629,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_16_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2028]
+    (const void *)&gInstructions[2039]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_16_01_01_w = 
@@ -2666,13 +2666,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_16_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2058]
+    (const void *)&gInstructions[2069]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2060]
+    (const void *)&gInstructions[2071]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_90_01_mem_w = 
@@ -2707,13 +2707,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_90_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2062]
+    (const void *)&gInstructions[2073]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2064]
+    (const void *)&gInstructions[2075]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_91_01_mem_w = 
@@ -2748,7 +2748,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_91_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2068]
+    (const void *)&gInstructions[2079]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_02_pp = 
@@ -2765,7 +2765,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_02_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2070]
+    (const void *)&gInstructions[2081]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_03_pp = 
@@ -2782,7 +2782,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_03_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2077]
+    (const void *)&gInstructions[2088]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_01_pp = 
@@ -2799,7 +2799,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_01_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_41_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2080]
+    (const void *)&gInstructions[2091]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_41_01_l = 
@@ -2827,7 +2827,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_41_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_06_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2082]
+    (const void *)&gInstructions[2093]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_06_pp = 
@@ -2844,7 +2844,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_06_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2084]
+    (const void *)&gInstructions[2095]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_07_pp = 
@@ -2861,7 +2861,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_07_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_05_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2085]
+    (const void *)&gInstructions[2096]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_05_pp = 
@@ -2878,7 +2878,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_05_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2116]
+    (const void *)&gInstructions[2127]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_04_pp = 
@@ -2895,13 +2895,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_04_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2119]
+    (const void *)&gInstructions[2130]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2121]
+    (const void *)&gInstructions[2132]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_8c_01_mem_w = 
@@ -2936,13 +2936,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2120]
+    (const void *)&gInstructions[2131]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2122]
+    (const void *)&gInstructions[2133]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_8e_01_mem_w = 
@@ -2977,7 +2977,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2124]
+    (const void *)&gInstructions[2135]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp = 
@@ -2994,7 +2994,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2126]
+    (const void *)&gInstructions[2137]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp = 
@@ -3011,7 +3011,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2133]
+    (const void *)&gInstructions[2144]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp = 
@@ -3028,7 +3028,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2136]
+    (const void *)&gInstructions[2147]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp = 
@@ -3045,7 +3045,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_38_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2138]
+    (const void *)&gInstructions[2149]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_38_pp = 
@@ -3062,7 +3062,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_38_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_39_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2140]
+    (const void *)&gInstructions[2151]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_39_pp = 
@@ -3079,7 +3079,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_39_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2147]
+    (const void *)&gInstructions[2158]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp = 
@@ -3096,7 +3096,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2150]
+    (const void *)&gInstructions[2161]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp = 
@@ -3113,13 +3113,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2171]
+    (const void *)&gInstructions[2182]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2172]
+    (const void *)&gInstructions[2183]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_21_01_l = 
@@ -3147,13 +3147,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_21_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2174]
+    (const void *)&gInstructions[2185]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2175]
+    (const void *)&gInstructions[2186]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_22_01_l = 
@@ -3181,13 +3181,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_22_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2177]
+    (const void *)&gInstructions[2188]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2178]
+    (const void *)&gInstructions[2189]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_20_01_l = 
@@ -3215,13 +3215,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_20_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2180]
+    (const void *)&gInstructions[2191]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2181]
+    (const void *)&gInstructions[2192]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_25_01_l = 
@@ -3249,13 +3249,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_25_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2183]
+    (const void *)&gInstructions[2194]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2184]
+    (const void *)&gInstructions[2195]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_23_01_l = 
@@ -3283,13 +3283,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_23_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2186]
+    (const void *)&gInstructions[2197]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2187]
+    (const void *)&gInstructions[2198]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_24_01_l = 
@@ -3317,13 +3317,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_24_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2197]
+    (const void *)&gInstructions[2208]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2198]
+    (const void *)&gInstructions[2209]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_31_01_l = 
@@ -3351,13 +3351,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_31_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2200]
+    (const void *)&gInstructions[2211]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2201]
+    (const void *)&gInstructions[2212]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_32_01_l = 
@@ -3385,13 +3385,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_32_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2203]
+    (const void *)&gInstructions[2214]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2204]
+    (const void *)&gInstructions[2215]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_30_01_l = 
@@ -3419,13 +3419,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_30_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2206]
+    (const void *)&gInstructions[2217]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2207]
+    (const void *)&gInstructions[2218]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_35_01_l = 
@@ -3453,13 +3453,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_35_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2209]
+    (const void *)&gInstructions[2220]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2210]
+    (const void *)&gInstructions[2221]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_33_01_l = 
@@ -3487,13 +3487,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_33_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2212]
+    (const void *)&gInstructions[2223]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2213]
+    (const void *)&gInstructions[2224]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_34_01_l = 
@@ -3521,7 +3521,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_34_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_28_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2215]
+    (const void *)&gInstructions[2226]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_28_pp = 
@@ -3538,7 +3538,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_28_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2217]
+    (const void *)&gInstructions[2228]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp = 
@@ -3555,7 +3555,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_40_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2223]
+    (const void *)&gInstructions[2234]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_40_pp = 
@@ -3572,7 +3572,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_40_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2294]
+    (const void *)&gInstructions[2305]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_00_pp = 
@@ -3589,7 +3589,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_00_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_08_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2302]
+    (const void *)&gInstructions[2313]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_08_pp = 
@@ -3606,7 +3606,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_08_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2303]
+    (const void *)&gInstructions[2314]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp = 
@@ -3623,7 +3623,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_09_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2304]
+    (const void *)&gInstructions[2315]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_09_pp = 
@@ -3640,13 +3640,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_09_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2316]
+    (const void *)&gInstructions[2327]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2318]
+    (const void *)&gInstructions[2329]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_47_01_w = 
@@ -3672,7 +3672,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_47_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_46_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2331]
+    (const void *)&gInstructions[2342]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_46_01_w = 
@@ -3698,13 +3698,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_46_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2349]
+    (const void *)&gInstructions[2360]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2351]
+    (const void *)&gInstructions[2362]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_45_01_w = 
@@ -3730,7 +3730,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_45_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_17_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2375]
+    (const void *)&gInstructions[2386]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_17_pp = 
@@ -3747,7 +3747,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_17_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2480]
+    (const void *)&gInstructions[2491]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0f_01_w = 
@@ -3773,7 +3773,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2481]
+    (const void *)&gInstructions[2492]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0e_01_w = 
@@ -4062,7 +4062,7 @@ const ND_TABLE_OPCODE gVexTable_root_02_opcode =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[111]
+    (const void *)&gInstructions[119]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_mem_modrmreg = 
@@ -4083,7 +4083,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1258]
+    (const void *)&gInstructions[1269]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_reg_modrmreg = 
@@ -4113,7 +4113,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_02_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[112]
+    (const void *)&gInstructions[120]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_mem_modrmreg = 
@@ -4134,7 +4134,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_02_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[210]
+    (const void *)&gInstructions[218]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_reg_modrmreg = 
@@ -4164,13 +4164,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1729]
+    (const void *)&gInstructions[1740]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2471]
+    (const void *)&gInstructions[2482]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_ae_00_mem_modrmreg = 
@@ -4211,13 +4211,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ae_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[482]
+    (const void *)&gInstructions[492]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[483]
+    (const void *)&gInstructions[493]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_4a_01_reg_01_w = 
@@ -4252,13 +4252,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4a_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[484]
+    (const void *)&gInstructions[494]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[485]
+    (const void *)&gInstructions[495]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_4a_00_reg_01_w = 
@@ -4304,13 +4304,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_4a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[486]
+    (const void *)&gInstructions[496]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[487]
+    (const void *)&gInstructions[497]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_41_01_reg_01_w = 
@@ -4345,13 +4345,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_41_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[492]
+    (const void *)&gInstructions[502]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[493]
+    (const void *)&gInstructions[503]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_41_00_reg_01_w = 
@@ -4397,13 +4397,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_41_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[488]
+    (const void *)&gInstructions[498]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[489]
+    (const void *)&gInstructions[499]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_42_01_reg_01_w = 
@@ -4438,13 +4438,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_42_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[490]
+    (const void *)&gInstructions[500]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[491]
+    (const void *)&gInstructions[501]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_42_00_reg_01_w = 
@@ -4490,7 +4490,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_42_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_48_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[494]
+    (const void *)&gInstructions[504]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_48_00_reg_00_w = 
@@ -4536,7 +4536,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_48_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_49_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[495]
+    (const void *)&gInstructions[505]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_49_00_reg_00_w = 
@@ -4582,13 +4582,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_49_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[496]
+    (const void *)&gInstructions[506]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[501]
+    (const void *)&gInstructions[511]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_90_01_mem_00_w = 
@@ -4614,13 +4614,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[497]
+    (const void *)&gInstructions[507]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[502]
+    (const void *)&gInstructions[512]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_90_01_reg_00_w = 
@@ -4655,13 +4655,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_90_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[506]
+    (const void *)&gInstructions[516]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[511]
+    (const void *)&gInstructions[521]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_90_00_mem_00_w = 
@@ -4687,13 +4687,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_00_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[507]
+    (const void *)&gInstructions[517]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[512]
+    (const void *)&gInstructions[522]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_90_00_reg_00_w = 
@@ -4739,13 +4739,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_90_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[498]
+    (const void *)&gInstructions[508]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[503]
+    (const void *)&gInstructions[513]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_91_01_mem_00_w = 
@@ -4780,13 +4780,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_91_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[508]
+    (const void *)&gInstructions[518]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[513]
+    (const void *)&gInstructions[523]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_91_00_mem_00_w = 
@@ -4832,7 +4832,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_91_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_92_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[499]
+    (const void *)&gInstructions[509]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_92_01_reg_00_w = 
@@ -4867,13 +4867,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[504]
+    (const void *)&gInstructions[514]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[509]
+    (const void *)&gInstructions[519]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_92_03_reg_00_w = 
@@ -4908,7 +4908,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_92_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[514]
+    (const void *)&gInstructions[524]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_92_00_reg_00_w = 
@@ -4954,7 +4954,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_92_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_93_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[500]
+    (const void *)&gInstructions[510]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_93_01_reg_00_w = 
@@ -4989,13 +4989,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[505]
+    (const void *)&gInstructions[515]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[510]
+    (const void *)&gInstructions[520]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_93_03_reg_00_w = 
@@ -5030,7 +5030,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_93_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[515]
+    (const void *)&gInstructions[525]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_93_00_reg_00_w = 
@@ -5076,13 +5076,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_93_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[516]
+    (const void *)&gInstructions[526]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[517]
+    (const void *)&gInstructions[527]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_44_01_reg_00_w = 
@@ -5117,13 +5117,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_44_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[518]
+    (const void *)&gInstructions[528]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[519]
+    (const void *)&gInstructions[529]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_44_00_reg_00_w = 
@@ -5169,13 +5169,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_44_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[520]
+    (const void *)&gInstructions[530]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[521]
+    (const void *)&gInstructions[531]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_45_01_reg_01_w = 
@@ -5210,13 +5210,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_45_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[522]
+    (const void *)&gInstructions[532]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[527]
+    (const void *)&gInstructions[537]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_45_00_reg_01_w = 
@@ -5262,13 +5262,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_45_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[523]
+    (const void *)&gInstructions[533]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[524]
+    (const void *)&gInstructions[534]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_98_01_reg_00_w = 
@@ -5303,13 +5303,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_98_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[525]
+    (const void *)&gInstructions[535]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[526]
+    (const void *)&gInstructions[536]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_98_00_reg_00_w = 
@@ -5355,13 +5355,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_98_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[536]
+    (const void *)&gInstructions[546]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[537]
+    (const void *)&gInstructions[547]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_99_01_reg_00_w = 
@@ -5396,13 +5396,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_99_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[538]
+    (const void *)&gInstructions[548]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[539]
+    (const void *)&gInstructions[549]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_99_00_reg_00_w = 
@@ -5448,7 +5448,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_99_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[540]
+    (const void *)&gInstructions[550]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_4b_01_reg_01_w = 
@@ -5483,13 +5483,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[541]
+    (const void *)&gInstructions[551]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[542]
+    (const void *)&gInstructions[552]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_4b_00_reg_01_w = 
@@ -5535,13 +5535,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_4b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[543]
+    (const void *)&gInstructions[553]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[544]
+    (const void *)&gInstructions[554]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_46_01_reg_01_w = 
@@ -5576,13 +5576,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_46_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[545]
+    (const void *)&gInstructions[555]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[546]
+    (const void *)&gInstructions[556]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_46_00_reg_01_w = 
@@ -5628,13 +5628,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_46_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[547]
+    (const void *)&gInstructions[557]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[548]
+    (const void *)&gInstructions[558]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_47_01_reg_01_w = 
@@ -5669,13 +5669,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_47_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[549]
+    (const void *)&gInstructions[559]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[550]
+    (const void *)&gInstructions[560]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_47_00_reg_01_w = 
@@ -5721,25 +5721,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_47_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1342]
+    (const void *)&gInstructions[1353]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1344]
+    (const void *)&gInstructions[1355]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1346]
+    (const void *)&gInstructions[1357]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1348]
+    (const void *)&gInstructions[1359]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_58_pp = 
@@ -5756,13 +5756,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_58_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1349]
+    (const void *)&gInstructions[1360]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1350]
+    (const void *)&gInstructions[1361]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp = 
@@ -5779,13 +5779,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_55_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1364]
+    (const void *)&gInstructions[1375]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_55_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1366]
+    (const void *)&gInstructions[1377]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_55_pp = 
@@ -5802,13 +5802,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_55_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_54_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1368]
+    (const void *)&gInstructions[1379]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_54_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1370]
+    (const void *)&gInstructions[1381]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_54_pp = 
@@ -5825,25 +5825,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_54_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1394]
+    (const void *)&gInstructions[1405]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1396]
+    (const void *)&gInstructions[1407]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1398]
+    (const void *)&gInstructions[1409]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1400]
+    (const void *)&gInstructions[1411]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp = 
@@ -5860,13 +5860,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1402]
+    (const void *)&gInstructions[1413]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1404]
+    (const void *)&gInstructions[1415]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp = 
@@ -5883,13 +5883,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1408]
+    (const void *)&gInstructions[1419]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1409]
+    (const void *)&gInstructions[1420]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l = 
@@ -5906,13 +5906,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1415]
+    (const void *)&gInstructions[1426]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1454]
+    (const void *)&gInstructions[1465]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp = 
@@ -5929,19 +5929,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1411]
+    (const void *)&gInstructions[1422]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1426]
+    (const void *)&gInstructions[1437]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1459]
+    (const void *)&gInstructions[1470]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp = 
@@ -5958,13 +5958,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1417]
+    (const void *)&gInstructions[1428]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1418]
+    (const void *)&gInstructions[1429]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l = 
@@ -5981,13 +5981,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1428]
+    (const void *)&gInstructions[1439]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1429]
+    (const void *)&gInstructions[1440]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l = 
@@ -6004,13 +6004,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1441]
+    (const void *)&gInstructions[1452]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1449]
+    (const void *)&gInstructions[1460]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp = 
@@ -6027,13 +6027,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1439]
+    (const void *)&gInstructions[1450]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1451]
+    (const void *)&gInstructions[1462]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp = 
@@ -6050,13 +6050,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1445]
+    (const void *)&gInstructions[1456]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1447]
+    (const void *)&gInstructions[1458]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp = 
@@ -6073,13 +6073,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1464]
+    (const void *)&gInstructions[1475]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1467]
+    (const void *)&gInstructions[1478]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp = 
@@ -6096,25 +6096,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1478]
+    (const void *)&gInstructions[1489]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1480]
+    (const void *)&gInstructions[1491]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1482]
+    (const void *)&gInstructions[1493]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1484]
+    (const void *)&gInstructions[1495]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp = 
@@ -6131,13 +6131,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1710]
+    (const void *)&gInstructions[1721]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1711]
+    (const void *)&gInstructions[1722]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp = 
@@ -6154,13 +6154,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1712]
+    (const void *)&gInstructions[1723]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1713]
+    (const void *)&gInstructions[1724]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp = 
@@ -6177,7 +6177,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f0_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1728]
+    (const void *)&gInstructions[1739]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_f0_03_modrmmod = 
@@ -6203,7 +6203,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f7_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1730]
+    (const void *)&gInstructions[1741]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_f7_01_reg_l = 
@@ -6240,25 +6240,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1736]
+    (const void *)&gInstructions[1747]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1738]
+    (const void *)&gInstructions[1749]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1740]
+    (const void *)&gInstructions[1751]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1742]
+    (const void *)&gInstructions[1753]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp = 
@@ -6275,25 +6275,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1749]
+    (const void *)&gInstructions[1760]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1751]
+    (const void *)&gInstructions[1762]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1753]
+    (const void *)&gInstructions[1764]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1755]
+    (const void *)&gInstructions[1766]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp = 
@@ -6310,13 +6310,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_28_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1762]
+    (const void *)&gInstructions[1773]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_28_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1766]
+    (const void *)&gInstructions[1777]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_28_pp = 
@@ -6333,13 +6333,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_28_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_29_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1763]
+    (const void *)&gInstructions[1774]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_29_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1767]
+    (const void *)&gInstructions[1778]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_29_pp = 
@@ -6356,13 +6356,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_29_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1770]
+    (const void *)&gInstructions[1781]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1827]
+    (const void *)&gInstructions[1838]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_6e_01_00_w = 
@@ -6399,13 +6399,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1771]
+    (const void *)&gInstructions[1782]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1828]
+    (const void *)&gInstructions[1839]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_7e_01_00_w = 
@@ -6431,7 +6431,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_7e_01_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1829]
+    (const void *)&gInstructions[1840]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_7e_02_l = 
@@ -6459,13 +6459,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1775]
+    (const void *)&gInstructions[1786]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1776]
+    (const void *)&gInstructions[1787]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_03_l = 
@@ -6482,7 +6482,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_03_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1794]
+    (const void *)&gInstructions[1805]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l = 
@@ -6499,7 +6499,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1811]
+    (const void *)&gInstructions[1822]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_00_mem_l = 
@@ -6525,7 +6525,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_00_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1807]
+    (const void *)&gInstructions[1818]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_01_mem_l = 
@@ -6551,7 +6551,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1842]
+    (const void *)&gInstructions[1853]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_12_pp = 
@@ -6568,13 +6568,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_12_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1777]
+    (const void *)&gInstructions[1788]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1783]
+    (const void *)&gInstructions[1794]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp = 
@@ -6591,13 +6591,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1778]
+    (const void *)&gInstructions[1789]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1784]
+    (const void *)&gInstructions[1795]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp = 
@@ -6614,7 +6614,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1797]
+    (const void *)&gInstructions[1808]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_16_01_mem_l = 
@@ -6640,7 +6640,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1801]
+    (const void *)&gInstructions[1812]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l = 
@@ -6657,7 +6657,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1804]
+    (const void *)&gInstructions[1815]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_16_00_reg_l = 
@@ -6683,7 +6683,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_00_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1840]
+    (const void *)&gInstructions[1851]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_16_pp = 
@@ -6700,7 +6700,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_16_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_17_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1798]
+    (const void *)&gInstructions[1809]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_17_01_mem_l = 
@@ -6726,7 +6726,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_17_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_17_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1802]
+    (const void *)&gInstructions[1813]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_17_00_mem_l = 
@@ -6763,7 +6763,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_17_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_13_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1808]
+    (const void *)&gInstructions[1819]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_13_01_mem_l = 
@@ -6789,7 +6789,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_13_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_13_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1812]
+    (const void *)&gInstructions[1823]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_13_00_mem_l = 
@@ -6826,7 +6826,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_13_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_50_01_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1813]
+    (const void *)&gInstructions[1824]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod = 
@@ -6841,7 +6841,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_50_00_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1814]
+    (const void *)&gInstructions[1825]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_50_00_modrmmod = 
@@ -6867,7 +6867,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_50_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e7_01_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1816]
+    (const void *)&gInstructions[1827]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_e7_01_modrmmod = 
@@ -6893,7 +6893,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_01_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1820]
+    (const void *)&gInstructions[1831]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod = 
@@ -6908,7 +6908,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_00_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1822]
+    (const void *)&gInstructions[1833]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_00_modrmmod = 
@@ -6934,7 +6934,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1830]
+    (const void *)&gInstructions[1841]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_d6_01_l = 
@@ -6962,13 +6962,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1835]
+    (const void *)&gInstructions[1846]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1836]
+    (const void *)&gInstructions[1847]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod = 
@@ -6983,13 +6983,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1847]
+    (const void *)&gInstructions[1858]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1848]
+    (const void *)&gInstructions[1859]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod = 
@@ -7004,13 +7004,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1853]
+    (const void *)&gInstructions[1864]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1857]
+    (const void *)&gInstructions[1868]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_10_pp = 
@@ -7027,13 +7027,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_10_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1837]
+    (const void *)&gInstructions[1848]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1838]
+    (const void *)&gInstructions[1849]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod = 
@@ -7048,13 +7048,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1849]
+    (const void *)&gInstructions[1860]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1850]
+    (const void *)&gInstructions[1861]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod = 
@@ -7069,13 +7069,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1854]
+    (const void *)&gInstructions[1865]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1858]
+    (const void *)&gInstructions[1869]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_11_pp = 
@@ -7092,25 +7092,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_11_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1867]
+    (const void *)&gInstructions[1878]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1869]
+    (const void *)&gInstructions[1880]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1871]
+    (const void *)&gInstructions[1882]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1873]
+    (const void *)&gInstructions[1884]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_59_pp = 
@@ -7127,13 +7127,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_59_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_56_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1878]
+    (const void *)&gInstructions[1889]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_56_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1880]
+    (const void *)&gInstructions[1891]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_56_pp = 
@@ -7150,7 +7150,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_56_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1893]
+    (const void *)&gInstructions[1904]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp = 
@@ -7167,7 +7167,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_63_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1895]
+    (const void *)&gInstructions[1906]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_63_pp = 
@@ -7184,7 +7184,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_63_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_67_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1899]
+    (const void *)&gInstructions[1910]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_67_pp = 
@@ -7201,7 +7201,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_67_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1901]
+    (const void *)&gInstructions[1912]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp = 
@@ -7218,7 +7218,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fe_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1903]
+    (const void *)&gInstructions[1914]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp = 
@@ -7235,7 +7235,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1905]
+    (const void *)&gInstructions[1916]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp = 
@@ -7252,7 +7252,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ec_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1907]
+    (const void *)&gInstructions[1918]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp = 
@@ -7269,7 +7269,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ed_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1909]
+    (const void *)&gInstructions[1920]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp = 
@@ -7286,7 +7286,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1911]
+    (const void *)&gInstructions[1922]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp = 
@@ -7303,7 +7303,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1913]
+    (const void *)&gInstructions[1924]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp = 
@@ -7320,7 +7320,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1915]
+    (const void *)&gInstructions[1926]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp = 
@@ -7337,7 +7337,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_db_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1918]
+    (const void *)&gInstructions[1929]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_db_pp = 
@@ -7354,7 +7354,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_db_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_df_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1920]
+    (const void *)&gInstructions[1931]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_df_pp = 
@@ -7371,7 +7371,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_df_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1925]
+    (const void *)&gInstructions[1936]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp = 
@@ -7388,7 +7388,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1927]
+    (const void *)&gInstructions[1938]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp = 
@@ -7405,7 +7405,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_74_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1956]
+    (const void *)&gInstructions[1967]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_74_pp = 
@@ -7422,7 +7422,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_74_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_76_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1958]
+    (const void *)&gInstructions[1969]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_76_pp = 
@@ -7439,7 +7439,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_76_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_75_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1962]
+    (const void *)&gInstructions[1973]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_75_pp = 
@@ -7456,7 +7456,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_75_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_64_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1966]
+    (const void *)&gInstructions[1977]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_64_pp = 
@@ -7473,7 +7473,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_64_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_66_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1968]
+    (const void *)&gInstructions[1979]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_66_pp = 
@@ -7490,7 +7490,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_66_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_65_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1972]
+    (const void *)&gInstructions[1983]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_65_pp = 
@@ -7507,7 +7507,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_65_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c5_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2054]
+    (const void *)&gInstructions[2065]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_c5_01_reg_l = 
@@ -7544,7 +7544,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2097]
+    (const void *)&gInstructions[2108]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l = 
@@ -7561,7 +7561,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2098]
+    (const void *)&gInstructions[2109]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_c4_01_reg_l = 
@@ -7598,7 +7598,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2118]
+    (const void *)&gInstructions[2129]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp = 
@@ -7615,7 +7615,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ee_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2129]
+    (const void *)&gInstructions[2140]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp = 
@@ -7632,7 +7632,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2131]
+    (const void *)&gInstructions[2142]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_de_pp = 
@@ -7649,7 +7649,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_de_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ea_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2143]
+    (const void *)&gInstructions[2154]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp = 
@@ -7666,7 +7666,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_da_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2145]
+    (const void *)&gInstructions[2156]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_da_pp = 
@@ -7683,7 +7683,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_da_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d7_01_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2159]
+    (const void *)&gInstructions[2170]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_d7_01_modrmmod = 
@@ -7709,7 +7709,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2219]
+    (const void *)&gInstructions[2230]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp = 
@@ -7726,7 +7726,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2221]
+    (const void *)&gInstructions[2232]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp = 
@@ -7743,7 +7743,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2226]
+    (const void *)&gInstructions[2237]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp = 
@@ -7760,7 +7760,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2229]
+    (const void *)&gInstructions[2240]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp = 
@@ -7777,7 +7777,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_eb_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2234]
+    (const void *)&gInstructions[2245]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp = 
@@ -7794,7 +7794,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2260]
+    (const void *)&gInstructions[2271]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp = 
@@ -7811,19 +7811,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_70_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2297]
+    (const void *)&gInstructions[2308]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_70_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2299]
+    (const void *)&gInstructions[2310]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_70_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2301]
+    (const void *)&gInstructions[2312]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_70_pp = 
@@ -7840,19 +7840,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_70_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2307]
+    (const void *)&gInstructions[2318]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2326]
+    (const void *)&gInstructions[2337]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2340]
+    (const void *)&gInstructions[2351]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_72_01_reg_modrmreg = 
@@ -7893,7 +7893,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_72_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2308]
+    (const void *)&gInstructions[2319]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp = 
@@ -7910,25 +7910,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2310]
+    (const void *)&gInstructions[2321]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2313]
+    (const void *)&gInstructions[2324]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2343]
+    (const void *)&gInstructions[2354]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2346]
+    (const void *)&gInstructions[2357]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_73_01_reg_modrmreg = 
@@ -7969,7 +7969,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_73_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2314]
+    (const void *)&gInstructions[2325]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp = 
@@ -7986,19 +7986,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2322]
+    (const void *)&gInstructions[2333]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2336]
+    (const void *)&gInstructions[2347]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2355]
+    (const void *)&gInstructions[2366]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_71_01_reg_modrmreg = 
@@ -8039,7 +8039,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_71_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2323]
+    (const void *)&gInstructions[2334]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp = 
@@ -8056,7 +8056,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2327]
+    (const void *)&gInstructions[2338]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp = 
@@ -8073,7 +8073,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2337]
+    (const void *)&gInstructions[2348]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp = 
@@ -8090,7 +8090,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2341]
+    (const void *)&gInstructions[2352]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp = 
@@ -8107,7 +8107,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2347]
+    (const void *)&gInstructions[2358]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp = 
@@ -8124,7 +8124,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2356]
+    (const void *)&gInstructions[2367]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp = 
@@ -8141,7 +8141,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2358]
+    (const void *)&gInstructions[2369]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp = 
@@ -8158,7 +8158,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fa_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2360]
+    (const void *)&gInstructions[2371]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp = 
@@ -8175,7 +8175,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fb_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2362]
+    (const void *)&gInstructions[2373]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp = 
@@ -8192,7 +8192,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2364]
+    (const void *)&gInstructions[2375]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp = 
@@ -8209,7 +8209,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2366]
+    (const void *)&gInstructions[2377]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp = 
@@ -8226,7 +8226,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2368]
+    (const void *)&gInstructions[2379]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp = 
@@ -8243,7 +8243,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2370]
+    (const void *)&gInstructions[2381]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp = 
@@ -8260,7 +8260,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2372]
+    (const void *)&gInstructions[2383]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp = 
@@ -8277,7 +8277,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_68_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2385]
+    (const void *)&gInstructions[2396]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_68_pp = 
@@ -8294,7 +8294,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_68_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2387]
+    (const void *)&gInstructions[2398]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp = 
@@ -8311,7 +8311,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2389]
+    (const void *)&gInstructions[2400]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp = 
@@ -8328,7 +8328,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_69_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2391]
+    (const void *)&gInstructions[2402]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_69_pp = 
@@ -8345,7 +8345,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_69_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_60_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2393]
+    (const void *)&gInstructions[2404]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_60_pp = 
@@ -8362,7 +8362,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_60_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_62_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2395]
+    (const void *)&gInstructions[2406]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_62_pp = 
@@ -8379,7 +8379,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_62_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2397]
+    (const void *)&gInstructions[2408]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp = 
@@ -8396,7 +8396,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_61_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2399]
+    (const void *)&gInstructions[2410]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_61_pp = 
@@ -8413,7 +8413,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_61_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ef_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2400]
+    (const void *)&gInstructions[2411]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp = 
@@ -8430,13 +8430,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_53_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2415]
+    (const void *)&gInstructions[2426]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_53_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2416]
+    (const void *)&gInstructions[2427]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_53_pp = 
@@ -8453,13 +8453,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_53_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_52_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2437]
+    (const void *)&gInstructions[2448]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_52_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2438]
+    (const void *)&gInstructions[2449]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_52_pp = 
@@ -8476,13 +8476,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_52_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2460]
+    (const void *)&gInstructions[2471]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2462]
+    (const void *)&gInstructions[2473]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp = 
@@ -8499,25 +8499,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2464]
+    (const void *)&gInstructions[2475]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2466]
+    (const void *)&gInstructions[2477]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2468]
+    (const void *)&gInstructions[2479]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2470]
+    (const void *)&gInstructions[2481]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_51_pp = 
@@ -8534,25 +8534,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_51_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2473]
+    (const void *)&gInstructions[2484]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2475]
+    (const void *)&gInstructions[2486]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2477]
+    (const void *)&gInstructions[2488]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2479]
+    (const void *)&gInstructions[2490]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp = 
@@ -8569,13 +8569,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2483]
+    (const void *)&gInstructions[2494]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2485]
+    (const void *)&gInstructions[2496]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp = 
@@ -8592,13 +8592,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_15_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2487]
+    (const void *)&gInstructions[2498]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_15_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2489]
+    (const void *)&gInstructions[2500]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_15_pp = 
@@ -8615,13 +8615,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_15_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_14_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2491]
+    (const void *)&gInstructions[2502]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_14_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2493]
+    (const void *)&gInstructions[2504]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_14_pp = 
@@ -8638,13 +8638,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_14_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_57_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2495]
+    (const void *)&gInstructions[2506]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_57_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2497]
+    (const void *)&gInstructions[2508]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_57_pp = 
@@ -8661,13 +8661,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_57_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2498]
+    (const void *)&gInstructions[2509]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2499]
+    (const void *)&gInstructions[2510]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_77_00_l = 
@@ -8958,13 +8958,13 @@ const ND_TABLE_OPCODE gVexTable_root_01_opcode =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[528]
+    (const void *)&gInstructions[538]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[531]
+    (const void *)&gInstructions[541]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_32_01_reg_00_w = 
@@ -9010,13 +9010,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_32_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[529]
+    (const void *)&gInstructions[539]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[530]
+    (const void *)&gInstructions[540]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_33_01_reg_00_w = 
@@ -9062,13 +9062,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_33_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[532]
+    (const void *)&gInstructions[542]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[535]
+    (const void *)&gInstructions[545]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_30_01_reg_00_w = 
@@ -9114,13 +9114,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_30_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[533]
+    (const void *)&gInstructions[543]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[534]
+    (const void *)&gInstructions[544]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_31_01_reg_00_w = 
@@ -9166,7 +9166,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_31_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_f0_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1154]
+    (const void *)&gInstructions[1165]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_f0_03_l = 
@@ -9194,7 +9194,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_f0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_df_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1360]
+    (const void *)&gInstructions[1371]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_df_01_l = 
@@ -9222,7 +9222,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_df_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1373]
+    (const void *)&gInstructions[1384]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp = 
@@ -9239,7 +9239,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1374]
+    (const void *)&gInstructions[1385]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp = 
@@ -9256,7 +9256,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_4b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1375]
+    (const void *)&gInstructions[1386]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_4b_01_w = 
@@ -9282,7 +9282,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_4a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1376]
+    (const void *)&gInstructions[1387]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_4a_01_w = 
@@ -9308,7 +9308,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1431]
+    (const void *)&gInstructions[1442]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w = 
@@ -9323,7 +9323,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1432]
+    (const void *)&gInstructions[1443]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_1d_01_01_w = 
@@ -9360,7 +9360,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_1d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_41_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1486]
+    (const void *)&gInstructions[1497]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_41_01_l = 
@@ -9388,7 +9388,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_41_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_40_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1487]
+    (const void *)&gInstructions[1498]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_40_pp = 
@@ -9405,7 +9405,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_40_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_19_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1494]
+    (const void *)&gInstructions[1505]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_19_01_01_w = 
@@ -9442,7 +9442,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_19_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_39_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1499]
+    (const void *)&gInstructions[1510]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_39_01_01_w = 
@@ -9479,7 +9479,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_39_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1506]
+    (const void *)&gInstructions[1517]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l = 
@@ -9496,7 +9496,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1507]
+    (const void *)&gInstructions[1518]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_17_01_reg_l = 
@@ -9533,13 +9533,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_17_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1536]
+    (const void *)&gInstructions[1547]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1537]
+    (const void *)&gInstructions[1548]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_69_01_w = 
@@ -9565,13 +9565,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_69_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1538]
+    (const void *)&gInstructions[1549]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1539]
+    (const void *)&gInstructions[1550]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_68_01_w = 
@@ -9597,13 +9597,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_68_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1540]
+    (const void *)&gInstructions[1551]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1541]
+    (const void *)&gInstructions[1552]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6b_01_w = 
@@ -9629,13 +9629,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1542]
+    (const void *)&gInstructions[1553]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1543]
+    (const void *)&gInstructions[1554]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6a_01_w = 
@@ -9661,13 +9661,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1556]
+    (const void *)&gInstructions[1567]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1557]
+    (const void *)&gInstructions[1568]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5d_01_w = 
@@ -9693,13 +9693,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1558]
+    (const void *)&gInstructions[1569]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1559]
+    (const void *)&gInstructions[1570]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5c_01_w = 
@@ -9725,13 +9725,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1596]
+    (const void *)&gInstructions[1607]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1597]
+    (const void *)&gInstructions[1608]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5f_01_w = 
@@ -9757,13 +9757,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1598]
+    (const void *)&gInstructions[1609]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1599]
+    (const void *)&gInstructions[1610]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5e_01_w = 
@@ -9789,13 +9789,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1600]
+    (const void *)&gInstructions[1611]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1601]
+    (const void *)&gInstructions[1612]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6d_01_w = 
@@ -9821,13 +9821,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1602]
+    (const void *)&gInstructions[1613]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1603]
+    (const void *)&gInstructions[1614]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6c_01_w = 
@@ -9853,13 +9853,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1604]
+    (const void *)&gInstructions[1615]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1605]
+    (const void *)&gInstructions[1616]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6f_01_w = 
@@ -9885,13 +9885,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1606]
+    (const void *)&gInstructions[1617]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1607]
+    (const void *)&gInstructions[1618]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6e_01_w = 
@@ -9917,13 +9917,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1632]
+    (const void *)&gInstructions[1643]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1633]
+    (const void *)&gInstructions[1644]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_79_01_w = 
@@ -9949,13 +9949,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_79_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1634]
+    (const void *)&gInstructions[1645]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1635]
+    (const void *)&gInstructions[1646]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_78_01_w = 
@@ -9981,13 +9981,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_78_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1636]
+    (const void *)&gInstructions[1647]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1637]
+    (const void *)&gInstructions[1648]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7b_01_w = 
@@ -10013,13 +10013,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1638]
+    (const void *)&gInstructions[1649]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1639]
+    (const void *)&gInstructions[1650]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7a_01_w = 
@@ -10045,13 +10045,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1664]
+    (const void *)&gInstructions[1675]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1665]
+    (const void *)&gInstructions[1676]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7d_01_w = 
@@ -10077,13 +10077,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1666]
+    (const void *)&gInstructions[1677]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1667]
+    (const void *)&gInstructions[1678]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7c_01_w = 
@@ -10109,13 +10109,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1668]
+    (const void *)&gInstructions[1679]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1669]
+    (const void *)&gInstructions[1680]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7f_01_w = 
@@ -10141,13 +10141,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1670]
+    (const void *)&gInstructions[1681]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1671]
+    (const void *)&gInstructions[1682]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7e_01_w = 
@@ -10173,7 +10173,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_cf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1705]
+    (const void *)&gInstructions[1716]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_cf_01_w = 
@@ -10199,7 +10199,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_cf_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_ce_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1707]
+    (const void *)&gInstructions[1718]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_ce_01_w = 
@@ -10225,7 +10225,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_ce_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_18_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1714]
+    (const void *)&gInstructions[1725]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_18_01_01_w = 
@@ -10262,7 +10262,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_18_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_38_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1719]
+    (const void *)&gInstructions[1730]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_38_01_01_w = 
@@ -10299,7 +10299,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_38_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1726]
+    (const void *)&gInstructions[1737]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l = 
@@ -10316,7 +10316,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1727]
+    (const void *)&gInstructions[1738]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_21_01_reg_l = 
@@ -10353,7 +10353,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_21_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_42_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1859]
+    (const void *)&gInstructions[1870]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_42_pp = 
@@ -10370,7 +10370,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_42_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1917]
+    (const void *)&gInstructions[1928]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp = 
@@ -10387,7 +10387,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_02_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1928]
+    (const void *)&gInstructions[1939]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_02_01_w = 
@@ -10413,7 +10413,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_02_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_4c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1933]
+    (const void *)&gInstructions[1944]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_4c_01_w = 
@@ -10439,7 +10439,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1934]
+    (const void *)&gInstructions[1945]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp = 
@@ -10456,7 +10456,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_44_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1950]
+    (const void *)&gInstructions[1961]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_44_pp = 
@@ -10473,7 +10473,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_44_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_61_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1963]
+    (const void *)&gInstructions[1974]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_61_01_l = 
@@ -10501,7 +10501,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_61_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_60_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1964]
+    (const void *)&gInstructions[1975]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_60_01_l = 
@@ -10529,7 +10529,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_60_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_63_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1973]
+    (const void *)&gInstructions[1984]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_63_01_l = 
@@ -10557,7 +10557,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_63_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_62_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1974]
+    (const void *)&gInstructions[1985]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_62_01_l = 
@@ -10585,7 +10585,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_62_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_06_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1999]
+    (const void *)&gInstructions[2010]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_06_01_01_w = 
@@ -10622,7 +10622,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_06_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_46_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2000]
+    (const void *)&gInstructions[2011]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_46_01_01_w = 
@@ -10659,13 +10659,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_46_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2010]
+    (const void *)&gInstructions[2021]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2011]
+    (const void *)&gInstructions[2022]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_49_01_w = 
@@ -10691,13 +10691,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_49_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2012]
+    (const void *)&gInstructions[2023]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2013]
+    (const void *)&gInstructions[2024]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_48_01_w = 
@@ -10723,7 +10723,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_48_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_05_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2017]
+    (const void *)&gInstructions[2028]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_05_01_w = 
@@ -10749,7 +10749,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_05_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_04_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2021]
+    (const void *)&gInstructions[2032]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_04_01_w = 
@@ -10775,7 +10775,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_04_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_01_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2025]
+    (const void *)&gInstructions[2036]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_01_01_01_w = 
@@ -10812,7 +10812,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_01_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_00_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2031]
+    (const void *)&gInstructions[2042]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_00_01_01_w = 
@@ -10849,7 +10849,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_00_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2045]
+    (const void *)&gInstructions[2056]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l = 
@@ -10866,7 +10866,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2046]
+    (const void *)&gInstructions[2057]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_14_01_reg_l = 
@@ -10903,13 +10903,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_14_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2048]
+    (const void *)&gInstructions[2059]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2050]
+    (const void *)&gInstructions[2061]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_16_01_00_w = 
@@ -10946,7 +10946,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_16_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2055]
+    (const void *)&gInstructions[2066]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l = 
@@ -10963,7 +10963,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2056]
+    (const void *)&gInstructions[2067]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_15_01_reg_l = 
@@ -11000,7 +11000,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_15_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2089]
+    (const void *)&gInstructions[2100]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l = 
@@ -11017,7 +11017,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2090]
+    (const void *)&gInstructions[2101]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_20_01_reg_l = 
@@ -11054,13 +11054,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_20_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2092]
+    (const void *)&gInstructions[2103]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2094]
+    (const void *)&gInstructions[2105]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_22_01_00_w = 
@@ -11097,7 +11097,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_22_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_09_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2425]
+    (const void *)&gInstructions[2436]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_09_pp = 
@@ -11114,7 +11114,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_09_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_08_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2426]
+    (const void *)&gInstructions[2437]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_08_pp = 
@@ -11131,7 +11131,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_08_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2427]
+    (const void *)&gInstructions[2438]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp = 
@@ -11148,7 +11148,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2428]
+    (const void *)&gInstructions[2439]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0a_pp = 
diff --git a/bddisasm/include/table_xop.h b/bddisasm/include/table_xop.h
index d34788a..5bbe35d 100644
--- a/bddisasm/include/table_xop.h
+++ b/bddisasm/include/table_xop.h
@@ -4,19 +4,19 @@
 const ND_TABLE_INSTRUCTION gXopTable_root_0a_10_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[56]
+    (const void *)&gInstructions[64]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_0a_12_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[584]
+    (const void *)&gInstructions[595]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_0a_12_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[585]
+    (const void *)&gInstructions[596]
 };
 
 const ND_TABLE_MODRM_REG gXopTable_root_0a_12_modrmreg = 
@@ -300,43 +300,43 @@ const ND_TABLE_OPCODE gXopTable_root_0a_opcode =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[57]
+    (const void *)&gInstructions[65]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[59]
+    (const void *)&gInstructions[67]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[61]
+    (const void *)&gInstructions[69]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[66]
+    (const void *)&gInstructions[74]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[68]
+    (const void *)&gInstructions[76]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1302]
+    (const void *)&gInstructions[1313]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1325]
+    (const void *)&gInstructions[1336]
 };
 
 const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg = 
@@ -357,13 +357,13 @@ const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_02_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[58]
+    (const void *)&gInstructions[66]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[60]
+    (const void *)&gInstructions[68]
 };
 
 const ND_TABLE_MODRM_REG gXopTable_root_09_02_modrmreg = 
@@ -384,13 +384,13 @@ const ND_TABLE_MODRM_REG gXopTable_root_09_02_modrmreg =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[567]
+    (const void *)&gInstructions[577]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1254]
+    (const void *)&gInstructions[1265]
 };
 
 const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg = 
@@ -420,127 +420,127 @@ const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1676]
+    (const void *)&gInstructions[1687]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1677]
+    (const void *)&gInstructions[1688]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1678]
+    (const void *)&gInstructions[1689]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1679]
+    (const void *)&gInstructions[1690]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2065]
+    (const void *)&gInstructions[2076]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2066]
+    (const void *)&gInstructions[2077]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2067]
+    (const void *)&gInstructions[2078]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2069]
+    (const void *)&gInstructions[2080]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2071]
+    (const void *)&gInstructions[2082]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2072]
+    (const void *)&gInstructions[2083]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2073]
+    (const void *)&gInstructions[2084]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2074]
+    (const void *)&gInstructions[2085]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2075]
+    (const void *)&gInstructions[2086]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2076]
+    (const void *)&gInstructions[2087]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2078]
+    (const void *)&gInstructions[2089]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2079]
+    (const void *)&gInstructions[2090]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2081]
+    (const void *)&gInstructions[2092]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2083]
+    (const void *)&gInstructions[2094]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2086]
+    (const void *)&gInstructions[2097]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2248]
+    (const void *)&gInstructions[2259]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2249]
+    (const void *)&gInstructions[2260]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_90_w = 
@@ -555,13 +555,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_90_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2251]
+    (const void *)&gInstructions[2262]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2252]
+    (const void *)&gInstructions[2263]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_92_w = 
@@ -576,13 +576,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_92_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2254]
+    (const void *)&gInstructions[2265]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2255]
+    (const void *)&gInstructions[2266]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_93_w = 
@@ -597,13 +597,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_93_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2257]
+    (const void *)&gInstructions[2268]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2258]
+    (const void *)&gInstructions[2269]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_91_w = 
@@ -618,13 +618,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_91_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2265]
+    (const void *)&gInstructions[2276]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2266]
+    (const void *)&gInstructions[2277]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_98_w = 
@@ -639,13 +639,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_98_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2267]
+    (const void *)&gInstructions[2278]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2268]
+    (const void *)&gInstructions[2279]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_9a_w = 
@@ -660,13 +660,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2269]
+    (const void *)&gInstructions[2280]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2270]
+    (const void *)&gInstructions[2281]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_9b_w = 
@@ -681,13 +681,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2271]
+    (const void *)&gInstructions[2282]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2272]
+    (const void *)&gInstructions[2283]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_99_w = 
@@ -702,13 +702,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_99_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2273]
+    (const void *)&gInstructions[2284]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2274]
+    (const void *)&gInstructions[2285]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_94_w = 
@@ -723,13 +723,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_94_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2275]
+    (const void *)&gInstructions[2286]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2286]
+    (const void *)&gInstructions[2297]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_95_w = 
@@ -744,13 +744,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_95_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2276]
+    (const void *)&gInstructions[2287]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2277]
+    (const void *)&gInstructions[2288]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_96_w = 
@@ -765,13 +765,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_96_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2284]
+    (const void *)&gInstructions[2295]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2285]
+    (const void *)&gInstructions[2296]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_97_w = 
@@ -1049,13 +1049,13 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode =
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1951]
+    (const void *)&gInstructions[1962]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1952]
+    (const void *)&gInstructions[1963]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_08_a2_w = 
@@ -1070,133 +1070,133 @@ const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1981]
+    (const void *)&gInstructions[1992]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1982]
+    (const void *)&gInstructions[1993]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1987]
+    (const void *)&gInstructions[1998]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1988]
+    (const void *)&gInstructions[1999]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1989]
+    (const void *)&gInstructions[2000]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1990]
+    (const void *)&gInstructions[2001]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1991]
+    (const void *)&gInstructions[2002]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1992]
+    (const void *)&gInstructions[2003]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2101]
+    (const void *)&gInstructions[2112]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2102]
+    (const void *)&gInstructions[2113]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2103]
+    (const void *)&gInstructions[2114]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2104]
+    (const void *)&gInstructions[2115]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2105]
+    (const void *)&gInstructions[2116]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2106]
+    (const void *)&gInstructions[2117]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2107]
+    (const void *)&gInstructions[2118]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2108]
+    (const void *)&gInstructions[2119]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2109]
+    (const void *)&gInstructions[2120]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2110]
+    (const void *)&gInstructions[2121]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2111]
+    (const void *)&gInstructions[2122]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2112]
+    (const void *)&gInstructions[2123]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2237]
+    (const void *)&gInstructions[2248]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2238]
+    (const void *)&gInstructions[2249]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_08_a3_w = 
@@ -1211,25 +1211,25 @@ const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2247]
+    (const void *)&gInstructions[2258]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2250]
+    (const void *)&gInstructions[2261]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2253]
+    (const void *)&gInstructions[2264]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2256]
+    (const void *)&gInstructions[2267]
 };
 
 const ND_TABLE_OPCODE gXopTable_root_08_opcode = 
diff --git a/bddisasm/include/tabledefs.h b/bddisasm/include/tabledefs.h
index d28879b..d52d206 100644
--- a/bddisasm/include/tabledefs.h
+++ b/bddisasm/include/tabledefs.h
@@ -312,6 +312,8 @@ typedef enum _ND_OPERAND_SIZE_SPEC
     ND_OPS_n,
     ND_OPS_u,
     ND_OPS_t,       // Tile register size, can be up to 1K.
+    ND_OPS_384,     // 384 bit Key Locker handle.
+    ND_OPS_512,     // 512 bit Key Locker handle.
     // Stack sizes - indicates number of words. Also, hybrid sizes - sizes where from a large register (say 32 bit GPR)
     // only a smaller amount of data is used (for example, 8 bit).
     ND_OPS_v2,
@@ -425,6 +427,13 @@ typedef enum _ND_OPERAND_TYPE_SPEC
 
     // SSE registers.
     ND_OPT_SSE_XMM0,
+    ND_OPT_SSE_XMM1,
+    ND_OPT_SSE_XMM2,
+    ND_OPT_SSE_XMM3,
+    ND_OPT_SSE_XMM4,
+    ND_OPT_SSE_XMM5,
+    ND_OPT_SSE_XMM6,
+    ND_OPT_SSE_XMM7,
 
     // Implicit memory operands.
     ND_OPT_MEM_rBX_AL,
diff --git a/bddisasm_test/kl/kl_64 b/bddisasm_test/kl/kl_64
new file mode 100644
index 0000000..95dfba6
Binary files /dev/null and b/bddisasm_test/kl/kl_64 differ
diff --git a/bddisasm_test/kl/kl_64.asm b/bddisasm_test/kl/kl_64.asm
new file mode 100644
index 0000000..f687bbc
--- /dev/null
+++ b/bddisasm_test/kl/kl_64.asm
@@ -0,0 +1,13 @@
+    bits 64
+    
+    db 0xF3, 0x0F, 0x38, 0xDC, 0x01     ; AESENC128KL xmm0, m384 ptr [rcx]
+    db 0xF3, 0x0F, 0x38, 0xDD, 0x01     ; AESDEC128KL xmm0, m384 ptr [rcx]
+    db 0xF3, 0x0F, 0x38, 0xDE, 0x08     ; AESENC256KL xmm1, zmmword ptr [rax]
+    db 0xF3, 0x0F, 0x38, 0xDF, 0x08     ; AESDEC256KL xmm1, zmmword ptr [rax]
+    db 0xF3, 0x0F, 0x38, 0xD8, 0x00     ; AESENCWIDE128KL m384 ptr [rax]
+    db 0xF3, 0x0F, 0x38, 0xD8, 0x08     ; AESDECWIDE128KL m384 ptr [rax]
+    db 0xF3, 0x0F, 0x38, 0xD8, 0x10     ; AESENCWIDE256KL m384 ptr [rax]
+    db 0xF3, 0x0F, 0x38, 0xD8, 0x18     ; AESDECWIDE256KL m384 ptr [rax]
+    db 0xF3, 0x0F, 0x38, 0xFA, 0xC0     ; ENCODEKEY128 eax, eax
+    db 0xF3, 0x0F, 0x38, 0xFB, 0xCF     ; ENCODEKEY256 esi, esi
+    db 0xF3, 0x0F, 0x38, 0xDC, 0xC1     ; LOADIWKEY xmm0, xmm1
\ No newline at end of file
diff --git a/bddisasm_test/kl/kl_64.result b/bddisasm_test/kl/kl_64.result
new file mode 100644
index 0000000..76f3589
--- /dev/null
+++ b/bddisasm_test/kl/kl_64.result
@@ -0,0 +1,224 @@
+0000000000000000 f30f38dc01                      AESENC128KL xmm0, m384 ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: KL, Ins cat: AESKL, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 23
+        FLAGS access
+                CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, 
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:     Memory, Size: 48, RawSize: 48, Encoding: M, 
+                Segment: 3, Base: 1, 
+        Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
+0000000000000005 f30f38dd01                      AESDEC128KL xmm0, m384 ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: KL, Ins cat: AESKL, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 23
+        FLAGS access
+                CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, 
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:     Memory, Size: 48, RawSize: 48, Encoding: M, 
+                Segment: 3, Base: 1, 
+        Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
+000000000000000A f30f38de08                      AESENC256KL xmm1, zmmword ptr [rax]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: KL, Ins cat: AESKL, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 23
+        FLAGS access
+                CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, 
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 1, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:     Memory, Size: 64, RawSize: 64, Encoding: M, 
+                Segment: 3, Base: 0, 
+        Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
+000000000000000F f30f38df08                      AESDEC256KL xmm1, zmmword ptr [rax]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: KL, Ins cat: AESKL, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 23
+        FLAGS access
+                CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, 
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 1, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:     Memory, Size: 64, RawSize: 64, Encoding: M, 
+                Segment: 3, Base: 0, 
+        Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
+0000000000000014 f30f38d800                      AESENCWIDE128KL m384 ptr [rax]
+        DSIZE: 32, ASIZE: 64, VLEN: -
+        ISA Set: KL, Ins cat: WIDE_KL, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 23
+        FLAGS access
+                CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, 
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:     Memory, Size: 48, RawSize: 48, Encoding: M, 
+                Segment: 3, Base: 0, 
+        Operand: 1, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: S, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 8
+        Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
+0000000000000019 f30f38d808                      AESDECWIDE128KL m384 ptr [rax]
+        DSIZE: 32, ASIZE: 64, VLEN: -
+        ISA Set: KL, Ins cat: WIDE_KL, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 23
+        FLAGS access
+                CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, 
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:     Memory, Size: 48, RawSize: 48, Encoding: M, 
+                Segment: 3, Base: 0, 
+        Operand: 1, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: S, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 8
+        Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
+000000000000001E f30f38d810                      AESENCWIDE256KL zmmword ptr [rax]
+        DSIZE: 32, ASIZE: 64, VLEN: -
+        ISA Set: KL, Ins cat: WIDE_KL, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 23
+        FLAGS access
+                CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, 
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:     Memory, Size: 64, RawSize: 64, Encoding: M, 
+                Segment: 3, Base: 0, 
+        Operand: 1, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: S, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 8
+        Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
+0000000000000023 f30f38d818                      AESDECWIDE256KL zmmword ptr [rax]
+        DSIZE: 32, ASIZE: 64, VLEN: -
+        ISA Set: KL, Ins cat: WIDE_KL, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 23
+        FLAGS access
+                CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, 
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:     Memory, Size: 64, RawSize: 64, Encoding: M, 
+                Segment: 3, Base: 0, 
+        Operand: 1, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: S, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 8
+        Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
+0000000000000028 f30f38fac0                      ENCODEKEY128 eax, eax
+        DSIZE: 32, ASIZE: 64, VLEN: -
+        ISA Set: KL, Ins cat: AESKL, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 23
+        FLAGS access
+                CF: 0, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, 
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: R, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size:  4, RawSize:  4, Encoding: M, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: S, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 3, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: S, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 3
+        Operand: 4, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: S, RegType:           Vector, RegSize: 16, RegId: 4, RegCount: 3
+        Operand: 5, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
+000000000000002D f30f38fbcf                      ENCODEKEY256 ecx, edi
+        DSIZE: 32, ASIZE: 64, VLEN: -
+        ISA Set: KL, Ins cat: AESKL, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 23
+        FLAGS access
+                CF: 0, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, 
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: R, RegType:  General Purpose, RegSize:  4, RegId: 1, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size:  4, RawSize:  4, Encoding: M, RegType:  General Purpose, RegSize:  4, RegId: 7, RegCount: 1
+        Operand: 2, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: S, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 2
+        Operand: 3, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: S, RegType:           Vector, RegSize: 16, RegId: 2, RegCount: 5
+        Operand: 4, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
+0000000000000032 f30f38dcc1                      LOADIWKEY xmm0, xmm1
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: KL, Ins cat: KL, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 23
+        FLAGS access
+                CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, 
+        Valid modes
+                R0: yes, R1: no, R2: no, R3: no
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 1, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 3, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: S, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 4, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
diff --git a/disasmtool/disasmtool.c b/disasmtool/disasmtool.c
index 2030ca2..b3ca60e 100644
--- a/disasmtool/disasmtool.c
+++ b/disasmtool/disasmtool.c
@@ -143,6 +143,7 @@ const char* set_to_string(
     case ND_SET_I86:                   return "I86";
     case ND_SET_INVPCID:               return "INVPCID";
     case ND_SET_INVLPGB:               return "INVLPGB";
+    case ND_SET_KL:                    return "KL";
     case ND_SET_LONGMODE:              return "LONGMODE";
     case ND_SET_LWP:                   return "LWP";
     case ND_SET_LZCNT:                 return "LZCNT";
@@ -217,6 +218,7 @@ const char* category_to_string(
     {
     case ND_CAT_3DNOW:                return "3DNOW";
     case ND_CAT_AES:                  return "AES";
+    case ND_CAT_AESKL:                return "AESKL";
     case ND_CAT_ARITH:                return "ARITH";
     case ND_CAT_AMX:                  return "AMX";
     case ND_CAT_AVX:                  return "AVX";
@@ -252,6 +254,7 @@ const char* category_to_string(
     case ND_CAT_INTERRUPT:            return "INTERRUPT";
     case ND_CAT_IO:                   return "IO";
     case ND_CAT_IOSTRINGOP:           return "IOSTRINGOP";
+    case ND_CAT_KL:                   return "KL";
     case ND_CAT_KMASK:                return "KMASK";
     case ND_CAT_KNL:                  return "KNL";
     case ND_CAT_LOGIC:                return "LOGIC";
@@ -307,6 +310,7 @@ const char* category_to_string(
     case ND_CAT_WAITPKG:              return "WAITPKG";
     case ND_CAT_WBNOINVD:             return "WBNOINVD";
     case ND_CAT_WIDENOP:              return "WIDENOP";
+    case ND_CAT_WIDE_KL:              return "WIDE_KL";
     case ND_CAT_X87_ALU:              return "X87_ALU";
     case ND_CAT_XOP:                  return "XOP";
     case ND_CAT_XSAVE:                return "XSAVE";
diff --git a/disasmtool_lix/dumpers.cpp b/disasmtool_lix/dumpers.cpp
index 30beb6e..775e297 100644
--- a/disasmtool_lix/dumpers.cpp
+++ b/disasmtool_lix/dumpers.cpp
@@ -83,8 +83,16 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_ADDSUBPS: return "addsubps";
     case ND_INS_ADOX: return "adox";
     case ND_INS_AESDEC: return "aesdec";
+    case ND_INS_AESDEC128KL: return "aesdec128kl";
+    case ND_INS_AESDEC256KL: return "aesdec256kl";
+    case ND_INS_AESDECWIDE128KL: return "aesdecwide128kl";
+    case ND_INS_AESDECWIDE256KL: return "aesdecwide256kl";
     case ND_INS_AESDECLAST: return "aesdeclast";
     case ND_INS_AESENC: return "aesenc";
+    case ND_INS_AESENC128KL: return "aesenc128kl";
+    case ND_INS_AESENC256KL: return "aesenc256kl";
+    case ND_INS_AESENCWIDE128KL: return "aesencwide128kl";
+    case ND_INS_AESENCWIDE256KL: return "aesencwide256kl";
     case ND_INS_AESENCLAST: return "aesenclast";
     case ND_INS_AESIMC: return "aesimc";
     case ND_INS_AESKEYGENASSIST: return "aeskeygenassist";
@@ -207,6 +215,8 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_ENCLS: return "encls";
     case ND_INS_ENCLU: return "enclu";
     case ND_INS_ENCLV: return "enclv";
+    case ND_INS_ENCODEKEY128: return "encodekey128";
+    case ND_INS_ENCODEKEY256: return "encodekey256";
     case ND_INS_ENDBR: return "endbr";
     case ND_INS_ENQCMD: return "enqcmd";
     case ND_INS_ENQCMDS: return "enqcmds";
@@ -380,6 +390,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_LLDT: return "lldt";
     case ND_INS_LLWPCB: return "llwpcb";
     case ND_INS_LMSW: return "lmsw";
+    case ND_INS_LOADIWKEY: return "loadiwkey";
     case ND_INS_LODS: return "lods";
     case ND_INS_LOOP: return "loop";
     case ND_INS_LOOPNZ: return "loopnz";
@@ -1541,6 +1552,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
     case ND_CAT_INVALID: return "invalid";
     case ND_CAT_3DNOW: return "3dnow";
     case ND_CAT_AES: return "aes";
+    case ND_CAT_AESKL: return "aeskl";
     case ND_CAT_AMX: return "amx";
     case ND_CAT_ARITH: return "arith";
     case ND_CAT_AVX: return "avx";
@@ -1576,6 +1588,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
     case ND_CAT_INTERRUPT: return "interrupt";
     case ND_CAT_IO: return "io";
     case ND_CAT_IOSTRINGOP: return "iostringop";
+    case ND_CAT_KL: return "kl";
     case ND_CAT_KMASK: return "kmask";
     case ND_CAT_KNL: return "knl";
     case ND_CAT_LOGIC: return "logic";
@@ -1630,6 +1643,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
     case ND_CAT_VTX: return "vtx";
     case ND_CAT_WAITPKG: return "waitpkg";
     case ND_CAT_WBNOINVD: return "wbnoinvd";
+    case ND_CAT_WIDE_KL: return "wide_kl";
     case ND_CAT_WIDENOP: return "widenop";
     case ND_CAT_X87_ALU: return "x87_alu";
     case ND_CAT_XOP: return "xop";
@@ -1698,6 +1712,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_I64: return "i64";
     case ND_SET_I86: return "i86";
     case ND_SET_INVPCID: return "invpcid";
+    case ND_SET_KL: return "kl";
     case ND_SET_LONGMODE: return "longmode";
     case ND_SET_LWP: return "lwp";
     case ND_SET_LZCNT: return "lzcnt";
diff --git a/inc/bddisasm.h b/inc/bddisasm.h
index 15c9f8d..5cfc477 100644
--- a/inc/bddisasm.h
+++ b/inc/bddisasm.h
@@ -110,7 +110,8 @@
 #define ND_SIZE_128BIT              16          // 1 xmm word or 16 bytes.
 #define ND_SIZE_224BIT              28          // FPU environment, 28 bytes.
 #define ND_SIZE_256BIT              32          // 1 ymm word or 32 bytes.
-#define ND_SIZE_512BIT              64          // 1 zmm word or 64 bytes.
+#define ND_SIZE_384BIT              48          // 48 bytes, used for Key Locker handles.
+#define ND_SIZE_512BIT              64          // 1 zmm word or 64 bytes. Used also for Key Locker handles.
 #define ND_SIZE_752BIT              94          // FPU state, 94 bytes.
 #define ND_SIZE_864BIT              108         // FPU state, 108 bytes.
 #define ND_SIZE_4096BIT             512         // Extended state, 512 bytes.
diff --git a/inc/constants.h b/inc/constants.h
index 2e19f1d..c93171d 100644
--- a/inc/constants.h
+++ b/inc/constants.h
@@ -24,9 +24,17 @@ typedef enum _ND_INS_CLASS
     ND_INS_ADDSUBPS,
     ND_INS_ADOX,
     ND_INS_AESDEC,
+    ND_INS_AESDEC128KL,
+    ND_INS_AESDEC256KL,
     ND_INS_AESDECLAST,
+    ND_INS_AESDECWIDE128KL,
+    ND_INS_AESDECWIDE256KL,
     ND_INS_AESENC,
+    ND_INS_AESENC128KL,
+    ND_INS_AESENC256KL,
     ND_INS_AESENCLAST,
+    ND_INS_AESENCWIDE128KL,
+    ND_INS_AESENCWIDE256KL,
     ND_INS_AESIMC,
     ND_INS_AESKEYGENASSIST,
     ND_INS_ALTINST,
@@ -148,6 +156,8 @@ typedef enum _ND_INS_CLASS
     ND_INS_ENCLS,
     ND_INS_ENCLU,
     ND_INS_ENCLV,
+    ND_INS_ENCODEKEY128,
+    ND_INS_ENCODEKEY256,
     ND_INS_ENDBR,
     ND_INS_ENQCMD,
     ND_INS_ENQCMDS,
@@ -321,6 +331,7 @@ typedef enum _ND_INS_CLASS
     ND_INS_LLDT,
     ND_INS_LLWPCB,
     ND_INS_LMSW,
+    ND_INS_LOADIWKEY,
     ND_INS_LODS,
     ND_INS_LOOP,
     ND_INS_LOOPNZ,
@@ -1531,6 +1542,7 @@ typedef enum _ND_INS_SET
     ND_SET_I86,
     ND_SET_INVLPGB,
     ND_SET_INVPCID,
+    ND_SET_KL,
     ND_SET_LONGMODE,
     ND_SET_LWP,
     ND_SET_LZCNT,
@@ -1598,6 +1610,7 @@ typedef enum _ND_INS_TYPE
     ND_CAT_INVALID = 0,
     ND_CAT_3DNOW,
     ND_CAT_AES,
+    ND_CAT_AESKL,
     ND_CAT_AMX,
     ND_CAT_ARITH,
     ND_CAT_AVX,
@@ -1633,6 +1646,7 @@ typedef enum _ND_INS_TYPE
     ND_CAT_INTERRUPT,
     ND_CAT_IO,
     ND_CAT_IOSTRINGOP,
+    ND_CAT_KL,
     ND_CAT_KMASK,
     ND_CAT_KNL,
     ND_CAT_LOGIC,
@@ -1688,6 +1702,7 @@ typedef enum _ND_INS_TYPE
     ND_CAT_WAITPKG,
     ND_CAT_WBNOINVD,
     ND_CAT_WIDENOP,
+    ND_CAT_WIDE_KL,
     ND_CAT_X87_ALU,
     ND_CAT_XOP,
     ND_CAT_XSAVE,
diff --git a/inc/cpuidflags.h b/inc/cpuidflags.h
index bd1cbf9..810095f 100644
--- a/inc/cpuidflags.h
+++ b/inc/cpuidflags.h
@@ -69,6 +69,7 @@
 #define ND_CFF_AVX512BITALG             ND_CFF(0x00000007, 0x00000000, NDR_ECX, 12)
 #define ND_CFF_AVX512VPOPCNTDQ          ND_CFF(0x00000007, 0x00000000, NDR_ECX, 14)
 #define ND_CFF_RDPID                    ND_CFF(0x00000007, 0x00000000, NDR_ECX, 22)
+#define ND_CFF_KL                       ND_CFF(0x00000007, 0x00000000, NDR_ECX, 23)
 #define ND_CFF_CLDEMOTE                 ND_CFF(0x00000007, 0x00000000, NDR_ECX, 25)
 #define ND_CFF_MOVDIRI                  ND_CFF(0x00000007, 0x00000000, NDR_ECX, 27)
 #define ND_CFF_MOVDIR64B                ND_CFF(0x00000007, 0x00000000, NDR_ECX, 28)
diff --git a/inc/version.h b/inc/version.h
index dbb68db..94d7bcf 100644
--- a/inc/version.h
+++ b/inc/version.h
@@ -6,7 +6,7 @@
 #define DISASM_VER_H
 
 #define DISASM_VERSION_MAJOR        1
-#define DISASM_VERSION_MINOR        29
+#define DISASM_VERSION_MINOR        30
 #define DISASM_VERSION_REVISION     0
 
 #endif // DISASM_VER_H
diff --git a/isagenerator/disasmlib.py b/isagenerator/disasmlib.py
index 81ff54d..d25c256 100644
--- a/isagenerator/disasmlib.py
+++ b/isagenerator/disasmlib.py
@@ -202,6 +202,9 @@ valid_opsize = [
     'cl',           # 32/64/128 bytes - the size of one cache line.
     '12',           # 4 bytes (0) + 8 bytes (old SSP), used by SAVEPREVSSP.
     't',            # A tile register. The size varies dependning on execution environment, but can be as high as 1K.
+
+    '384',          # 384 bits representing a Key Locker handle.
+    '512',          # 512 bits representing a Key Locker handle.
 ]
 
 # Implicit/fixed operands. Self explanatory.
@@ -244,6 +247,13 @@ valid_impops = {# register      size
     'yIP'      : ('rIP',        'yf'),  # EIP in 16/32 bit mode, or RIP in 64 bit mode.
     '1'        : ('1',          'b'),   # Constant 1.
     'XMM0'     : ('XMM0',       'dq'),  # XMM0 register.
+    'XMM1'     : ('XMM1',       'dq'),  # XMM1 register.
+    'XMM2'     : ('XMM2',       'dq'),  # XMM2 register.
+    'XMM3'     : ('XMM3',       'dq'),  # XMM3 register.
+    'XMM4'     : ('XMM4',       'dq'),  # XMM4 register.
+    'XMM5'     : ('XMM5',       'dq'),  # XMM5 register.
+    'XMM6'     : ('XMM6',       'dq'),  # XMM6 register.
+    'XMM7'     : ('XMM7',       'dq'),  # XMM7 register.
     'ST(0)'    : ('ST(0)',      'ft'),  # ST(0) register.
     'ST(i)'    : ('ST(i)',      'ft'),  # ST(1) register.
     'CS'       : ('CS',         'v'),   # CS register.
@@ -550,6 +560,13 @@ class Operand():
         elif op.endswith('+1'):
             self.Block = 2
             op = op.replace('+1', '')
+        else:
+            m = re.match(r'XMM(\d)-(\d)', op)
+            if m:
+                start = m.group(1)
+                end = m.group(2)
+                self.Block = int(end) - int(start) + 1
+                op = 'XMM' + start
 
         # Handle the decorators.
         for dec in valid_decorators:
diff --git a/isagenerator/generate_tables.py b/isagenerator/generate_tables.py
index f63bd4f..48da078 100644
--- a/isagenerator/generate_tables.py
+++ b/isagenerator/generate_tables.py
@@ -136,6 +136,13 @@ optype = {
     'ST(0)'    : 'ND_OPT_FPU_ST0',
     'ST(i)'    : 'ND_OPT_FPU_STX',
     'XMM0'     : 'ND_OPT_SSE_XMM0',
+    'XMM1'     : 'ND_OPT_SSE_XMM1',
+    'XMM2'     : 'ND_OPT_SSE_XMM2',
+    'XMM3'     : 'ND_OPT_SSE_XMM3',
+    'XMM4'     : 'ND_OPT_SSE_XMM4',
+    'XMM5'     : 'ND_OPT_SSE_XMM5',
+    'XMM6'     : 'ND_OPT_SSE_XMM6',
+    'XMM7'     : 'ND_OPT_SSE_XMM7',
 
     # Memory operands
     'pBXAL'    : 'ND_OPT_MEM_rBX_AL',
@@ -233,6 +240,8 @@ opsize = {
     'cl'       : 'ND_OPS_cl',
     '12'       : 'ND_OPS_12',
     't'        : 'ND_OPS_t',
+    '384'      : 'ND_OPS_384',
+    '512'      : 'ND_OPS_512',
 }
 
 opdecorators = {
diff --git a/isagenerator/instructions/cpuid.dat b/isagenerator/instructions/cpuid.dat
index e8312e3..aad5cac 100644
--- a/isagenerator/instructions/cpuid.dat
+++ b/isagenerator/instructions/cpuid.dat
@@ -69,6 +69,7 @@ AVX512VNNI              : 0x00000007, 0x00000000, ECX, 11
 AVX512BITALG            : 0x00000007, 0x00000000, ECX, 12
 AVX512VPOPCNTDQ         : 0x00000007, 0x00000000, ECX, 14
 RDPID                   : 0x00000007, 0x00000000, ECX, 22
+KL                      : 0x00000007, 0x00000000, ECX, 23
 CLDEMOTE                : 0x00000007, 0x00000000, ECX, 25
 MOVDIRI                 : 0x00000007, 0x00000000, ECX, 27
 MOVDIR64B               : 0x00000007, 0x00000000, ECX, 28
diff --git a/isagenerator/instructions/flags.dat b/isagenerator/instructions/flags.dat
index ec45fa3..a5f66a6 100644
--- a/isagenerator/instructions/flags.dat
+++ b/isagenerator/instructions/flags.dat
@@ -99,3 +99,9 @@ CL          : SF=t|OF=t
 CNL         : SF=t|OF=t     
 CLE         : SF=t|ZF=t|OF=t
 CNLE        : SF=t|ZF=t|OF=t
+
+# AES Key Locker instructions. ZF set to 0 or 1, depending on success. All other flags are cleared to 0.
+AESKL       : CF=0|PF=0|AF=0|ZF=m|SF=0|OF=0
+
+# All flags are zeroed.
+ZERO        : CF=0|PF=0|AF=0|ZF=0|SF=0|OF=0
diff --git a/isagenerator/instructions/table_0F_38.dat b/isagenerator/instructions/table_0F_38.dat
index cc2ebdd..275658d 100644
--- a/isagenerator/instructions/table_0F_38.dat
+++ b/isagenerator/instructions/table_0F_38.dat
@@ -99,11 +99,20 @@ SHA256MSG2          Vdq,Wdq               nil               [         NP 0x0F 0x
 GF2P8MULB           Vdq,Wdq               nil               [       0x66 0x0F 0x38 0xCF /r]         s:GFNI, t:GFNI, w:RW|R, e:4
 
 # 0xD0 - 0xDF
+AESENCWIDE128KL     M384                  XMM0-7,Fv         [       0xF3 0x0F 0x38 0xD8 /0:mem]     s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL
+AESDECWIDE128KL     M384                  XMM0-7,Fv         [       0xF3 0x0F 0x38 0xD8 /1:mem]     s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL
+AESENCWIDE256KL     M512                  XMM0-7,Fv         [       0xF3 0x0F 0x38 0xD8 /2:mem]     s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL
+AESDECWIDE256KL     M512                  XMM0-7,Fv         [       0xF3 0x0F 0x38 0xD8 /3:mem]     s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL
 AESIMC              Vdq,Wdq               nil               [       0x66 0x0F 0x38 0xDB /r]         s:AES, t:AES, w:W|R, e:4
 AESENC              Vdq,Wdq               nil               [       0x66 0x0F 0x38 0xDC /r]         s:AES, t:AES, w:RW|R, e:4
+AESENC128KL         Vdq,M384              Fv                [       0xF3 0x0F 0x38 0xDC /r:mem]     s:KL, t:AESKL, w:RW|R|W, f:AESKL
+LOADIWKEY           Vdq,Udq               EAX,XMM0,Fv       [       0xF3 0x0F 0x38 0xDC /r:reg]     s:KL, t:KL, w:R|R|R|R|W, f:AESKL, m:KERNEL
 AESENCLAST          Vdq,Wdq               nil               [       0x66 0x0F 0x38 0xDD /r]         s:AES, t:AES, w:RW|R, e:4
+AESDEC128KL         Vdq,M384              Fv                [       0xF3 0x0F 0x38 0xDD /r:mem]     s:KL, t:AESKL, w:RW|R|W, f:AESKL
 AESDEC              Vdq,Wdq               nil               [       0x66 0x0F 0x38 0xDE /r]         s:AES, t:AES, w:RW|R, e:4
+AESENC256KL         Vdq,M512              Fv                [       0xF3 0x0F 0x38 0xDE /r:mem]     s:KL, t:AESKL, w:RW|R|W, f:AESKL
 AESDECLAST          Vdq,Wdq               nil               [       0x66 0x0F 0x38 0xDF /r]         s:AES, t:AES, w:RW|R, e:4
+AESDEC256KL         Vdq,M512              Fv                [       0xF3 0x0F 0x38 0xDF /r:mem]     s:KL, t:AESKL, w:RW|R|W, f:AESKL
 
 # 0xE0 - 0xEF
 
@@ -126,3 +135,6 @@ MOVDIR64B           rMoq,Moq              nil               [       0x66 0x0F 0x
 ENQCMD              rM?,Moq               Fv                [       0xF2 0x0F 0x38 0xF8 /r:mem]     s:ENQCMD, t:ENQCMD, w:W|R|W, f:ENQCMD
 ENQCMDS             rM?,Moq               Fv                [       0xF3 0x0F 0x38 0xF8 /r:mem]     s:ENQCMD, t:ENQCMD, w:W|R|W, f:ENQCMD
 MOVDIRI             My,Gy                 nil               [         NP 0x0F 0x38 0xF9 /r:mem]     s:MOVDIRI, t:MOVDIRI, w:W|R
+
+ENCODEKEY128        Gd,Rd                 XMM0,XMM0-2,XMM4-6,Fv [   0xF3 0x0F 0x38 0xFA /r:reg]     s:KL, t:AESKL, w:W|R|R|W|W|W, f:ZERO
+ENCODEKEY256        Gd,Rd                 XMM0-1,XMM2-6,Fv  [       0xF3 0x0F 0x38 0xFB /r:reg]     s:KL, t:AESKL, w:W|R|RW|W|W, f:ZERO
diff --git a/pybddisasm/setup.py b/pybddisasm/setup.py
index 380f4b9..16118f7 100644
--- a/pybddisasm/setup.py
+++ b/pybddisasm/setup.py
@@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution
 from codecs import open
 
 VERSION = (0, 1, 3)
-LIBRARY_VERSION = (1, 29, 0)
+LIBRARY_VERSION = (1, 30, 0)
 LIBRARY_INSTRUX_SIZE = 864
 
 packages = ['pybddisasm']