Implemented a reverse oprand lookup table. It holds pointers to relevant operands inside INSTRUX, for quick lookup.
Moved helper functions in bdhelpers.c. Added a dedicated BranchInfo field inside INSTRUX, containing the most relevant branch information.pull/53/head
BITDEFENDER\vlutas
2 years ago
parent
def76f8633
commit
433e723e07
@ -0,0 +1,321 @@
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#include "include/nd_crt.h"
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#include "../inc/bddisasm.h"
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//
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// NdIsInstruxRipRelative
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//
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bool
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NdIsInstruxRipRelative(
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const INSTRUX *Instrux
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)
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//
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// Provided for backwards compatibility with existing code that uses disasm 1.0
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//
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{
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if (NULL == Instrux)
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{
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return false;
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}
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else
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{
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return Instrux->IsRipRelative;
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}
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}
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//
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// NdGetFullAccessMap
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//
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NDSTATUS
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NdGetFullAccessMap(
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const INSTRUX *Instrux,
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ND_ACCESS_MAP *AccessMap
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)
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{
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uint32_t i;
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const ND_OPERAND *pOp;
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// pre-init
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i = 0;
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pOp = NULL;
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// validate
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if (NULL == Instrux)
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{
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return ND_STATUS_INVALID_PARAMETER;
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}
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if (NULL == AccessMap)
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{
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return ND_STATUS_INVALID_PARAMETER;
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}
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for (i = 0; i < Instrux->OperandsCount; i++)
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{
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pOp = &Instrux->Operands[i];
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if (ND_OP_MEM == pOp->Type)
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{
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if (pOp->Info.Memory.IsStack)
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{
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AccessMap->StackAccess |= pOp->Access.Access;
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AccessMap->GprAccess[NDR_RSP] |= ND_ACCESS_READ|ND_ACCESS_WRITE;
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AccessMap->SegAccess[NDR_SS] |= ND_ACCESS_READ;
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}
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else
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{
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AccessMap->MemAccess |= pOp->Access.Access;
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if (pOp->Info.Memory.HasSeg)
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{
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AccessMap->SegAccess[pOp->Info.Memory.Seg] |= ND_ACCESS_READ;
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}
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if (pOp->Info.Memory.HasBase)
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{
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AccessMap->GprAccess[pOp->Info.Memory.Base] |= ND_ACCESS_READ;
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}
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if (pOp->Info.Memory.HasIndex)
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{
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if (pOp->Info.Memory.IsVsib)
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{
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AccessMap->SseAccess[pOp->Info.Memory.Index] |= ND_ACCESS_READ;
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}
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else
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{
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AccessMap->GprAccess[pOp->Info.Memory.Index] |= ND_ACCESS_READ;
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}
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}
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}
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}
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else if (ND_OP_REG == pOp->Type)
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{
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switch (pOp->Info.Register.Type)
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{
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case ND_REG_GPR:
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{
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uint32_t k;
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for (k = 0; k < pOp->Info.Register.Count; k++)
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{
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AccessMap->GprAccess[pOp->Info.Register.Reg + k] |= pOp->Access.Access;
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}
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}
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break;
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case ND_REG_SEG:
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AccessMap->SegAccess[pOp->Info.Register.Reg] |= pOp->Access.Access;
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break;
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case ND_REG_FPU:
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AccessMap->FpuAccess[pOp->Info.Register.Reg] |= pOp->Access.Access;
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break;
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case ND_REG_MMX:
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AccessMap->MmxAccess[pOp->Info.Register.Reg] |= pOp->Access.Access;
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break;
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case ND_REG_SSE:
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{
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uint32_t k;
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for (k = 0; k < pOp->Info.Register.Count; k++)
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{
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AccessMap->SseAccess[pOp->Info.Register.Reg + k] |= pOp->Access.Access;
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}
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}
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break;
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case ND_REG_CR:
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AccessMap->CrAccess[pOp->Info.Register.Reg] |= pOp->Access.Access;
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break;
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case ND_REG_DR:
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AccessMap->DrAccess[pOp->Info.Register.Reg] |= pOp->Access.Access;
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break;
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case ND_REG_TR:
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AccessMap->TrAccess[pOp->Info.Register.Reg] |= pOp->Access.Access;
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break;
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case ND_REG_BND:
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AccessMap->BndAccess[pOp->Info.Register.Reg] |= pOp->Access.Access;
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break;
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case ND_REG_MSK:
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AccessMap->MskAccess[pOp->Info.Register.Reg] |= pOp->Access.Access;
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break;
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case ND_REG_SYS:
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AccessMap->SysAccess[pOp->Info.Register.Reg] |= pOp->Access.Access;
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break;
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case ND_REG_X87:
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AccessMap->X87Access[pOp->Info.Register.Reg] |= pOp->Access.Access;
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break;
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case ND_REG_FLG:
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AccessMap->FlagsAccess |= pOp->Access.Access;
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break;
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case ND_REG_RIP:
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AccessMap->RipAccess |= pOp->Access.Access;
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break;
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case ND_REG_MXCSR:
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AccessMap->MxcsrAccess |= pOp->Access.Access;
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break;
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case ND_REG_PKRU:
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AccessMap->PkruAccess |= pOp->Access.Access;
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break;
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case ND_REG_SSP:
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AccessMap->SspAccess |= pOp->Access.Access;
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break;
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case ND_REG_TILE:
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AccessMap->TmmAccess[pOp->Info.Register.Reg] |= pOp->Access.Access;
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break;
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default:
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break;
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}
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}
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else if (ND_OP_BANK == Instrux->Operands[i].Type)
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{
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uint8_t j;
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// Bank registers access. This needs special handling. Note that LOADALL/LOADALLD is not supported, as
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// it is too old and it's not valid since the good old 486.
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if (ND_INS_FNSAVE == Instrux->Instruction)
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{
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for (j = 0; j < ND_MAX_FPU_REGS; j++)
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{
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AccessMap->FpuAccess[j] |= ND_ACCESS_READ;
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}
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}
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else if (ND_INS_FRSTOR == Instrux->Instruction)
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{
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for (j = 0; j < ND_MAX_FPU_REGS; j++)
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{
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AccessMap->FpuAccess[j] |= ND_ACCESS_WRITE;
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}
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}
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if ((ND_INS_XSAVE == Instrux->Instruction) || (ND_INS_XSAVEOPT == Instrux->Instruction) ||
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(ND_INS_XSAVES == Instrux->Instruction) || (ND_INS_XSAVEC == Instrux->Instruction))
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{
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for (j = 0; j < ND_MAX_SSE_REGS; j++)
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{
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AccessMap->SseAccess[j] |= ND_ACCESS_READ;
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}
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}
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else if ((ND_INS_XRSTOR == Instrux->Instruction) || (ND_INS_XRSTORS == Instrux->Instruction))
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{
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for (j = 0; j < ND_MAX_SSE_REGS; j++)
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{
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AccessMap->SseAccess[j] |= ND_ACCESS_WRITE;
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}
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}
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}
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}
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return ND_STATUS_SUCCESS;
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}
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//
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// NdGetOperandRlut
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//
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NDSTATUS
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NdGetOperandRlut(
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INSTRUX *Instrux,
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ND_OPERAND_RLUT *Rlut
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)
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{
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if (NULL == Instrux)
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{
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return ND_STATUS_INVALID_PARAMETER;
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}
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if (NULL == Rlut)
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{
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return ND_STATUS_INVALID_PARAMETER;
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}
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// Initialize the RLUT.
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nd_memset(Rlut, 0, sizeof(*Rlut));
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for (uint8_t i = 0; i < Instrux->OperandsCount; i++)
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{
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if (!!(Instrux->Operands[i].Access.Access & ND_ACCESS_ANY_WRITE))
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{
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// We only care about the first 2 destination operands.
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if (Rlut->Dst1 == NULL)
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{
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Rlut->Dst1 = &Instrux->Operands[i];
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}
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else if (Rlut->Dst2 == NULL)
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{
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Rlut->Dst2 = &Instrux->Operands[i];
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}
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}
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if (!!(Instrux->Operands[i].Access.Access & ND_ACCESS_ANY_READ))
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{
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// We only care about the first 4 source operands.
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if (Rlut->Src1 == NULL)
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{
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Rlut->Src1 = &Instrux->Operands[i];
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}
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else if (Rlut->Src2 == NULL)
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{
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Rlut->Src2 = &Instrux->Operands[i];
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}
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else if (Rlut->Src3 == NULL)
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{
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Rlut->Src3 = &Instrux->Operands[i];
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}
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else if (Rlut->Src4 == NULL)
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{
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Rlut->Src4 = &Instrux->Operands[i];
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}
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}
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if (Instrux->Operands[i].Type == ND_OP_MEM)
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{
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// We only care about the first 2 memory operands.
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if (Rlut->Mem1 == NULL)
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{
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Rlut->Mem1 = &Instrux->Operands[i];
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}
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else if (Rlut->Mem2 == NULL)
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{
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Rlut->Mem2 = &Instrux->Operands[i];
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}
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if (Instrux->Operands[i].Info.Memory.IsStack)
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{
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Rlut->Stack = &Instrux->Operands[i];
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}
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}
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if (Instrux->Operands[i].Type == ND_OP_REG && Instrux->Operands->Flags.IsDefault)
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{
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switch (Instrux->Operands[i].Info.Register.Type)
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{
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case ND_REG_FLG:
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Rlut->Flags = &Instrux->Operands[i];
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break;
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case ND_REG_RIP:
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Rlut->Rip = &Instrux->Operands[i];;
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break;
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case ND_REG_SEG:
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if (Instrux->Operands[i].Info.Register.Reg == NDR_CS)
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{
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Rlut->Cs = &Instrux->Operands[i];
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}
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else if (Instrux->Operands[i].Info.Register.Reg == NDR_SS)
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{
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Rlut->Ss = &Instrux->Operands[i];
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}
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break;
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case ND_REG_GPR:
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if (Instrux->Operands[i].Info.Register.Reg < 8)
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{
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*(&Rlut->Rax + Instrux->Operands[i].Info.Register.Reg) = &Instrux->Operands[i];
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}
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break;
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default:
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break;
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}
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}
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}
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return ND_STATUS_SUCCESS;
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}
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